Display Devices

Abstract

The display device includes a substrate including a display area and a peripheral area outside the display area. The circuit unit is arranged in the display area and includes a semiconductor layer. The insulating layer is on the semiconductor layer. The conductive layer is connected to the semiconductor layer through a contact hole in the insulating layer. The conductive layer includes a lower layer, the lower layer includes a metal nitride, and the metal nitride includes a first metal. The display element is arranged on the circuit unit and includes a pixel electrode electrically connected to the conductive layer. The connecting layer is arranged below the conductive layer. The connecting layer corresponds to the contact hole and includes a second metal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2017-0170509 filed on December 12, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] An exemplary embodiment of the present invention relates to a display device. Background Art

[0004] The display device may include a display element and an electronic element that controls an electrical signal applied to the display element. The electronic element may include a thin film transistor (TFT), a capacitor, and a plurality of wirings. The electronic elements may be electrically insulated from each other by an insulating layer therebetween, or may be electrically connected to each other by contact holes formed in the insulating layer. Summary of the invention

[0005] The insulating layer between the electronic components of the display device may react with the conductive layer of the electronic components to form an unintended layer (eg, depending on the material of the insulating layer). Such an unintended layer may appear as a stain to the user.

[0006] The display device according to the exemplary embodiment of the present invention can prevent a layer from being formed between the conductive layer and the insulating layer, which can improve the quality of a generated image.

[0007] According to an exemplary embodiment of the present invention, a display device includes a substrate including a display area and a peripheral area outside the display area. A circuit unit is arranged in the display area and includes a semiconductor layer. An insulating layer is on the semiconductor layer. A conductive layer is connected to the semiconductor layer through a contact hole in the insulating layer. The conductive layer includes a lower layer, the lower layer includes a metal nitride, and the metal nitride includes a first metal. A display element is arranged on the circuit unit and includes a pixel electrode electrically connected to the conductive layer. A connecting layer is arranged below the conductive layer to correspond to the contact hole. The connecting layer includes a second metal.

[0008] The insulating layer may include an organic insulating layer.

[0009] A portion of the lower surface of the conductive layer may be in direct contact with the upper surface of the insulating layer.

[0010] The display device may include a side layer located on at least a portion of an inner wall of the contact hole. The side layer may include a second metal.

[0011] The lower layer may include at least one of titanium nitride, tantalum nitride, niobium nitride, and tungsten nitride.

[0012] The conductive layer may include a metal layer disposed on the lower layer.

[0013] The metal layer may include at least one of Mo, Al, Cu, and Ti.

[0014] The thickness of the metal layer may be greater than the thickness of the underlying layer.

[0015] The thickness of the lower layer may be about or larger.

[0016] The connection layer may be a metal silicide layer including a second metal.

[0017] The display element may include an organic light emitting diode.

[0018] According to an exemplary embodiment of the present invention, a display device includes a substrate, the substrate including a display area and a surrounding area outside the display area. A circuit unit is arranged in the display area. The circuit unit includes a semiconductor layer, a conductive layer and an organic insulating layer. The lower part of the conductive layer is in direct contact with the organic insulating layer. The lower part of the conductive layer includes a metal nitride. A display element is arranged on the circuit unit and includes a pixel electrode electrically connected to the conductive layer.

[0019] A portion of a lower surface of the conductive layer may be in direct contact with the organic insulating layer.

[0020] The conductive layer may include a metal nitride layer and a metal layer disposed on the metal nitride layer.

[0021] The metal nitride layer may include at least one of titanium nitride, tantalum nitride, niobium nitride, and tungsten nitride.

[0022] The metal layer may include at least one of Mo, Al, Cu, and Ti.

[0023] The conductive layer may include a capping layer on the metal layer.

[0024] The thickness of the metal nitride layer may be about or larger.

[0025] The thickness of the metal layer may be greater than the thickness of the metal nitride layer.

[0026] The conductive layer may be connected to the semiconductor layer through a contact hole in the organic insulating layer.

[0027] The display device may include a metal silicide layer disposed under a lower portion of the conductive layer.

[0028] The display device may include a side layer covering at least a portion of an inner wall of the contact hole. A metal included in the side layer is the same as a metal included in the metal silicide layer.

[0029] The conductive layer may contact a metal element disposed under the organic insulating layer through a contact hole in the organic insulating layer.

[0030] The circuit unit may include a storage capacitor. The metal element may be an electrode of the storage capacitor.

[0031] The circuit unit may include a thin film transistor. The data line and the driving voltage line may be electrically connected to the thin film transistor. The conductive layer may be one of the data line and the driving voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] A more complete understanding of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present invention;

[0034] Figure 2 is an equivalent circuit diagram of one pixel located in a display area of ​​a display device according to an exemplary embodiment of the present invention;

[0035] Figure 3 is a cross-sectional view of a display area of ​​a display device according to an exemplary embodiment of the present invention;

[0036] Figures 4 to 9 is a cross-sectional view of a process of forming a data line in a conductive layer in a manufacturing process of a display device according to an exemplary embodiment of the present invention;

[0037] Fig.10 is a cross-sectional view of a display area of ​​a display device according to an exemplary embodiment of the present invention; and

[0038] Fig.11 is a cross-sectional view of a display region of a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In this regard, exemplary embodiments may have different forms and should not be construed as limited to the exemplary embodiments of the present invention described herein.

[0040] Like reference numerals may refer to like elements throughout the specification and drawings.

[0041] It should be understood that, although the terms "first" and "second" may be used herein to describe various components, these components should not be limited by these terms.

[0042] As used herein, the singular forms "a", "an", and "the" may include the plural forms as well, unless the context clearly indicates otherwise.

[0043] It will be understood that when a component such as a layer, film, region, or panel is referred to as being “on” another component, it can be directly on the other component or intervening components may be present.

[0044] The sizes of elements in the drawings may be exaggerated for clarity of description.

[0045] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order (or in other ways different from the described order).

[0046] It will be understood that when a layer, region or component is referred to as being “connected to” another layer, region or component, it may be directly connected to the other layer, region or component or may be indirectly connected to the other layer, region or component with other layers, regions or components disposed therebetween.

[0047] The display device can display an image. Examples of the display device may include a liquid crystal display, an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display, or a cathode ray display.

[0048] An organic light emitting display is mainly described below as an example. However, the display device according to the exemplary embodiment of the present invention is not limited thereto, and various types of display devices may be used.

[0049] Figure 1 is a plan view of a display device according to an exemplary embodiment of the present invention.

[0050] refer to Figure 1 , the display device may include a substrate 100. The substrate 100 may include a display area DA and a peripheral area PA outside the display area DA. As an example, the peripheral area PA may surround the display area DA (for example, when viewed in a plan view along a direction orthogonal to the upper surface of the substrate 100). The peripheral area PA may have a substantially uniform width around the display area DA; however, exemplary embodiments of the present invention are not limited thereto. A display element such as an organic light emitting diode (OLED) may be disposed in the display area DA of the substrate 100. The peripheral area PA of the substrate 100 may be a non-display area where an image is not displayed. Wiring for transmitting an electrical signal to be applied to the display area DA may be located in the peripheral area PA. As an example, a display device including an OLED as a display element is described in more detail below. However, exemplary embodiments of the present invention are not limited thereto.

[0051] Figure 2 2 is an equivalent circuit diagram of one pixel P located in a display area of ​​a display device according to an exemplary embodiment of the present invention. Figure 2 An example in which the pixel P includes an OLED is illustrated.

[0052] refer to Figure 2 , the pixel P may include a first thin film transistor (TFT) T1, a second TFT T2, a storage capacitor Cst, and an OLED.

[0053] The second TFT T2 may be a switching TFT and may be connected to the scan line SL and the data line DL. The second TFT T2 may transfer a data voltage input from the data line DL to the first TFT T1 in response to a switching voltage input from the scan line SL.

[0054] The storage capacitor Cst may be connected to the second TFT T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transferred from the second TFT T2 and a voltage ELVDD supplied through the driving voltage line PL.

[0055] The first TFT T1 may be a driving TFT, may be connected to the driving voltage line PL and the storage capacitor Cst, and may control the driving current Id flowing from the driving voltage line PL through the OLED in response to the voltage stored in the storage capacitor Cst. The OLED may emit light having a preset brightness by using the driving current Id. For example, the OLED may emit red light, green light, blue light, or white light.

[0056] As an example, refer to Figure 2 A circuit unit of a pixel P including two TFTs and one storage capacitor is described; however, the exemplary embodiment of the present invention is not limited thereto. Therefore, a high-quality image can be displayed by a display device having a circuit unit connected to an OLED of a pixel P with a different design according to an exemplary embodiment of the present invention. For example, a pixel P may include three or more TFTs and / or two or more storage capacitors.

[0057] Figure 3 is a cross-sectional view of a display region of a display device according to an exemplary embodiment of the present invention. Figure 3 For along Figure 1 A cross-sectional view of the display area taken along line II'.

[0058] refer to Figure 3 , the buffer layer 101 may be disposed on the substrate 100. The substrate 100 may include various flexible, rollable and bendable materials (eg, polymer resins). For example, the substrate 100 may include a polymer such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyimide.

[0059] The buffer layer 101 may block foreign matter or moisture from penetrating the substrate 100. For example, the buffer layer 101 may include an inorganic insulating material such as SiO x (x>0), SiN x (x>0) and / or SiON. The buffer layer 101 may have a single-layer structure or a multi-layer structure.

[0060] The first TFT 210 and the second TFT 220 may include first and second semiconductor layers 211 and 221 and first and second gate electrodes 215 and 225 , respectively.

[0061] The first semiconductor layer 211 and the second semiconductor layer 221 may be disposed on the buffer layer 101 and may include amorphous silicon or polycrystalline silicon. The first semiconductor layer 211 may include a first channel region 211a, and a first source region 211b and a first drain region 211c, respectively located on opposite sides of the first channel region 211a. The second semiconductor layer 221 may include a second channel region 221a, and a second source region 221b and a second drain region 221c, respectively located on opposite sides of the second channel region 221a. The first source region 211b and the second source region 221b, and the first drain region 211c and the second drain region 221c may be doped with impurities having a higher impurity concentration than the first channel region 211a and the second channel region 221a, respectively. The impurities may include N-type impurities or P-type impurities.

[0062] The first gate electrode 215 and the second gate electrode 225 may overlap the first semiconductor layer 211 and the second semiconductor layer 221, respectively, with the gate insulating layer 103 interposed therebetween. The first gate electrode 215 and the second gate electrode 225 may overlap the first semiconductor layer 211 and the second semiconductor layer 221, respectively, along a direction orthogonal to the upper surface of the substrate 100. For example, the first gate electrode 215 may overlap the first channel region 211a of the first semiconductor layer 211, and the second gate electrode 225 may overlap the second channel region 221a of the second semiconductor layer 221. The gate insulating layer 103 may include an inorganic insulating layer, such as SiO x (x>0), SiN x (x>0) and / or SiON. The gate insulating layer 103 may have a single-layer structure or a multi-layer structure.

[0063] The storage capacitor 230 may include a first electrode 231 and a second electrode 232. In an exemplary embodiment of the present invention, the first electrode 231 may include the same material as the first and second semiconductor layers 211 and 221, and the second electrode 232 may include the same material as the first and second gate electrodes 215 and 225.

[0064] As an example, the gate insulating layer 103 may substantially completely cover the substrate 100; however, exemplary embodiments of the present invention are not limited thereto. The gate insulating layer 103 may be formed during the same mask process as the first and second gate electrodes 215, 225, and the second electrode 232. Therefore, the gate insulating layer 103 may be patterned to overlap the first and second gate electrodes 215, 225, and the second electrode 232.

[0065] According to an exemplary embodiment of the present invention, each of the first semiconductor layer 211, the second semiconductor layer 221, and the first electrode 231 may be disposed on the substrate 100 (e.g., the buffer layer 101 is disposed therebetween). The gate insulating layer 103 may be conformally disposed on the upper surface of the buffer layer 101 and the upper surface of each of the first semiconductor layer 211, the second semiconductor layer 221, and the first electrode 231. The first gate electrode 215 and the second gate electrode 225 may be disposed on the gate insulating layer 103. Therefore, the first gate electrode 215 and the second gate electrode 225 may be in direct contact with the gate insulating layer 103.

[0066] According to an exemplary embodiment of the present invention, the first gate electrode 215 may be aligned with the first channel region 211a above the substrate 100 (e.g., along a direction orthogonal to the upper surface of the substrate 100). The second gate electrode 225 may be aligned with the second channel region 221a (e.g., along a direction orthogonal to the upper surface of the substrate 100).

[0067] According to an exemplary embodiment of the present invention, the first gate electrode 215 may be spaced apart from the third contact hole 107H3 adjacent thereto, and the second gate electrode 225 may be spaced apart from the first contact hole 107H1 adjacent thereto.

[0068] The first TFT 210 and the second TFT 220 may be covered by the first insulating layer 107. The first insulating layer 107 may be an organic insulating layer. The first insulating layer 107 may be an organic insulating layer that may substantially completely cover the display area DA (see, for example, Figure 1 ) insulating layer. Compared with the inorganic insulating layer, the first insulating layer 107 including the organic insulating layer may be relatively flexible (eg, the first insulating layer 107 may be relatively strong against stress), and thus the display area DA (see, for example Figure 1) may be rolled, bent or curved. As an example, the display area DA may be substantially fixed in a bent state. The first insulating layer 107 may include a general polymer such as an imide-based polymer, polymethyl methacrylate (PMMA) or polystyrene (PS), or a polymer derivative having a phenol-based group, an acrylic acid-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof. In an exemplary embodiment of the present invention, the first insulating layer 107 may include polyimide.

[0069] The data line 310 may be disposed on the first insulating layer 107 and may be electrically connected to the second TFT 220. For example, the data line 310 may be connected to a portion of the second semiconductor layer 221, for example, the second source region 221b, through a first contact hole 107H1 defined in the first insulating layer 107. The data line 310 connected to the second source region 221b of the second semiconductor layer 221 may be a portion of a source electrode of the second TFT 220.

[0070] The driving voltage line 330 may be disposed on the first insulating layer 107. The driving voltage line 330 may be connected to the second electrode 232 of the storage capacitor 230 through a second contact hole 107H2 formed in the first insulating layer 107. The driving voltage line 330 may provide a voltage of a preset level, for example, a driving voltage ELVDD (see, for example Figure 2 ).

[0071] The connection conductor 350 may be disposed on the first insulating layer 107, and may electrically connect the first TFT 210 to the pixel electrode 510. The connection conductor 350 may be referred to as a conductive layer. For example, the connection conductor 350 may be connected to a semiconductor layer, for example, the first drain region 211 c of the first semiconductor layer 211, through a third contact hole 107H3 defined in the first insulating layer 107. The pixel electrode 510 may be connected to the connection conductor 350 through a contact hole 109H formed in the second insulating layer 109. The connection conductor 350 connected to the first drain region 211 c of the first semiconductor layer 211 may be a portion of the drain electrode of the first TFT 210.

[0072] The conductive layers such as the data line 310, the driving voltage line 330, and the connection conductor 350 may be substantially covered by the second insulating layer 109. The second insulating layer 109 may be an organic insulating layer, and may include, for example, a general polymer such as an imide-based polymer, PMMA, or PS, or a polymer derivative having a phenol-based group, an acrylic-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0073] The pixel electrode 510 may be disposed on the second insulating layer 109 (e.g., on the upper surface of the second insulating layer 109), and may be electrically connected to a circuit unit including the above-mentioned conductive layer disposed on the substrate 100. A pixel defining layer 130 including an opening exposing the pixel electrode 510 may be disposed on the pixel electrode 510. The pixel defining layer 130 may prevent an arc from occurring between the pixel electrode 510 and the counter electrode 530 by increasing a distance between an edge of the pixel electrode 510 and the counter electrode 530. The pixel defining layer 130 may include, for example, an organic insulating material such as polyimide or hexamethyldisiloxane (HMDSO).

[0074] The intermediate layer 520 may include a relatively low molecular weight material or a polymer material. When the intermediate layer 520 includes a relatively low molecular weight material, the intermediate layer 520 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML1), an electron transport layer (ETL), and / or an electron injection layer (EIL) are stacked. When the intermediate layer 520 includes a polymer material, the intermediate layer 520 may generally have a structure including an HTL and an EML1. The structure of the intermediate layer 520 is not limited to the above structure, and may have various structures. For example, at least one layer of the intermediate layer 520 may have a body to substantially completely cover the display area DA (see, for example, Figure 1 ). For example, at least one layer of the intermediate layer 520 may substantially cover the upper surface of the pixel defining layer 130 .

[0075] The counter electrode 530 may be disposed on the intermediate layer 520 and may substantially completely cover the display area DA (see, for example, Figure 1 ). In an exemplary embodiment of the present invention, light emitted from the OLED 500 including the pixel electrode 510, the intermediate layer 520, and the counter electrode 530 may be observed in a direction away from the substrate 100 (e.g., in a plan view), for example, from the outside having light transmittance through the counter electrode 530. However, the exemplary embodiment of the present invention is not limited thereto. In an exemplary embodiment of the present invention, light emitted from the OLED 500 may be observed from the outside through the substrate 100.

[0076] The lower portion of the conductive layer on the first insulating layer 107 may include a metal nitride. For example, the lower portions of each of the data line 310, the driving voltage line 330, and the connecting conductor 350 may be the lowest layer including the metal nitride. The conductive layers such as the data line 310, the driving voltage line 330, and the connecting conductor 350 may each have a multi-layer structure, and the lowest layer of the multi-layer structure may be a metal nitride layer. For example, the data line 310, the driving voltage line 330, and the connecting conductor 350 may each include the lowest layer as the lower layer UL1.

[0077] The lower layer UL1 of the conductive layer such as the data line 310, the driving voltage line 330, and the connecting conductor 350 may include a metal nitride layer, and the metal layer ML1 may be disposed on the lower layer UL1. The metal layer ML1 may be substantially covered by the cover layer CL1. The lower layer UL1, the metal layer ML1, and the cover layer CL1 may each include a first portion corresponding to the upper surface of the first insulating layer 107, a second portion corresponding to the bottom of the contact hole, and a third portion corresponding to the side surface of the contact hole.

[0078] The lower layer UL1 may be a metal nitride layer including a first metal. The first metal may include at least one of Ti, Ta, Nb, or W, and thus the lower layer UL1 may include at least one of titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride. The metal layer ML1 may include a metal having a relatively small resistance, such as Mo, Al, Cu, or Ti. The cover layer CL1 may include a metal different from the metal included in the metal layer ML1, and may prevent the metal layer ML1 from being damaged or oxidized. In an exemplary embodiment of the present invention, the lower layer UL1, the metal layer ML1, and the cover layer CL1 may be TiN / Al / Ti, however, the exemplary embodiment of the present invention is not limited thereto.

[0079] The lower layer UL1 of the conductive layer may be in direct contact with the first insulating layer 107 (for example, the first insulating layer 107 may include an organic insulating layer) disposed therebelow. The bottom surface of the lower layer UL1 may be in direct contact with the upper surface of the first insulating layer 107. When the lower layer UL1 includes a metal nitride layer, it may prevent the metal from coupling with oxygen included in the organic insulating layer, and may prevent the formation of an oxide layer. As a comparative example, in the case where the lower layer of the conductive layer is a titanium layer, titanium may couple with oxygen of the first insulating layer 107 as an organic insulating layer, and may form a titanium oxide layer. The titanium oxide layer may remain on the first insulating layer 107 and may be viewed as a stain by the user. According to an exemplary embodiment of the present invention, the lower layer UL1 including the metal nitride layer may prevent or minimize the formation of an oxide layer by forming the lower layer UL1 of the conductive layer in direct contact with the first insulating layer 107.

[0080] The thickness of the lower layer UL1 may be about or greater. The thickness of the lower layer UL1 is less than In the case of , stains can be observed from the outside. The thickness of the lower layer UL1 is about When the thickness of the metal layer ML1 is greater than 1000 Å, the stain can be prevented from being observed from the outside (see, for example, Table 1 below). The thickness of the metal layer ML1 and the cover layer CL1 can be greater than the thickness of the lower layer UL1, and the thickness of the metal layer ML1 can be greater than the thickness of the cover layer CL1. The thickness of the metal layer ML1 can be several thousand Å. And the thickness of the cover layer CL1 can be hundreds of

[0081] Table 1

[0082]

[0083] The driving voltage line 330 in the conductive layer may be connected to a conductor under the first insulating layer 107, for example, the second electrode 232, through the second contact hole 107H2 of the first insulating layer 107. For example, the lower layer UL1 of the driving voltage line 330 may directly contact the second electrode 232 of the storage capacitor 230 through the second contact hole 107H2.

[0084] At least one of the above conductive layers, for example, the data line 310 and the connection conductor 350 may be connected to the semiconductor layer. Figure 3 The data line 310 may be connected to the second semiconductor layer 221 through the first contact hole 107H1 of the first insulating layer 107, and the connection conductor 350 may be connected to the first semiconductor layer 211 through the third contact hole 107H3 of the first insulating layer 107. A contact layer 361 may be disposed in the connection region.

[0085] The contact layer (connection layer) 361 can reduce the resistance between the lower layer UL1 and the semiconductor layer (e.g., the first semiconductor layer 211 and the second semiconductor layer 221). The contact layer 361 may include a metal silicide layer. The metal silicide layer includes a second metal. For example, the second metal of the silicide layer includes a metal such as Ti, Ta, W, Co, or Ni.

[0086] The contact layer 361 may be disposed on a region of the first semiconductor layer 211 exposed through the contact hole. The contact layer 361 may overlap the contact hole along a direction orthogonal to the upper surface of the substrate 100. Figure 3 As shown, each contact layer 361 may overlap with each of the first contact hole 107H1 and the third contact hole 107H3 .

[0087] The contact layer 361 may be disposed in a contact hole (e.g., the first contact hole 107H1 or the third contact hole 107H3). For example, the width of the contact layer 361 under the data line 310 may be substantially the same as the width of the region of the second semiconductor layer 221 exposed through the first contact hole 107H1. The width of the contact layer 361 under the connection conductor 350 may be substantially the same as the width of the region of the first semiconductor layer 211 exposed through the third contact hole 107H3. The lower layer UL1 of each of the data line 310 and the connection conductor 350 may be in direct contact with the contact layer 361.

[0088] The contact layer 361 may be formed in the bottom of the first contact hole 107H1 and the third contact hole 107H3, respectively. The side layer 362 may be formed on the inner wall of the first contact hole 107H1 and the third contact hole 107H3, respectively. The metal included in the side layer 362 may be the same as the metal included in the contact layer 361, and each of the side layers 362 may substantially completely cover or partially cover the inner wall depending on the inclination angle of each inner wall of the first contact hole 107H1 and the third contact hole 107H3.

[0089] Figures 4 to 9 FIG. 1 is a cross-sectional view of a process of forming a data line in a conductive layer in a manufacturing process of a display device according to an exemplary embodiment of the present invention.

[0090] refer to Figure 4 , a buffer layer 101 may be formed on the substrate 100, and a second semiconductor layer 221 may be formed on the buffer layer 101. A gate insulating layer 103 may be formed, and a second gate electrode 225 may be formed. A second channel region 221a, a second source region 221b, and a second drain region 221c may be formed by doping the second semiconductor layer 221 with impurities using the second gate electrode 225 as a self-aligned mask.

[0091] A first insulating layer 107 may be formed, and a first contact hole 107H1 exposing a portion (or region) of the second semiconductor layer 221 (e.g., the second source region 221 b) may be formed in the first insulating layer 107. The materials of the substrate 100, the buffer layer 101, the second semiconductor layer 221, the second gate electrode 225, and the first insulating layer 107 may be the same as those described above with reference to Figure 3 The same as those described in more detail.

[0092] refer to Figure 5 , a photoresist 600 including a hole 600H at a position corresponding to the position of the first contact hole 107H1 may be formed on the first insulating layer 107. The photoresist 600 including the hole 600H may be formed through an exposure process and a development process.

[0093] refer to Figure 6 , a layer 360 including a second metal may be formed over the substrate 100. The second metal of the layer 360 may include Ti, Ta, W, Co, or Ni.

[0094] The first region 360A of the layer 360 may be formed in the hole 600H of the photoresist 600, and the second semiconductor layer 221 may be exposed through the first contact hole 107H1. Depending on the inclination angle α of the inner wall 107IS of the first contact hole 107H1, the second region 360B of the layer 360 may be substantially completely or partially formed on the inner wall 107IS. For example, when the inclination angle α of the inner wall 107IS is relatively large, the second region 360B of the layer 360 may partially cover the inner wall 107IS, and when the inclination angle α of the inner wall 107IS is relatively small, the second region 360B of the layer 360 may substantially completely cover the inner wall 107IS. Depending on the exemplary embodiment of the present invention, the first contact hole 107H1 may be formed to a relatively small size, and the inclination angle α of the inner wall 107IS may be relatively large (e.g., about 70° to about 90°).

[0095] Since the inner wall of the hole 600H of the photoresist 600 may be formed at a relatively large inclination angle, the layer 360 does not need to be formed on the inner wall of the hole 600H of the photoresist 600 .

[0096] The photoresist 600 may be removed. While removing the photoresist 600, the layer 360 (see, e.g., Figure 7 ).

[0097] The contact layer 361 may be formed by performing annealing. By annealing, Figure 6 The metal included in the described first region 360A of the layer 360 may react with silicon included in the second semiconductor layer 221 and may form a contact layer 361 including metal silicide. The second region 360B of the layer 360 may remain on the inner wall 107IS of the first contact hole 107H1 to form a side layer 362.

[0098] refer to Figure 8 , a conductive material layer 300 including a lower layer UL1, a metal layer ML1, and a capping layer CL1 may be formed, and a data line 310 may be formed by etching the conductive material layer 300 (see, for example Fig. 9 ). In an exemplary embodiment of the present invention, the conductive material layer 300 may be formed by a sputtering process, and the etching process for forming the data line 310 may be a dry etching process.

[0099] Although referenced Figures 4 to 9 An exemplary process for forming the data line 310 is described, but exemplary embodiments of the present invention are not limited thereto. The connecting conductor 350 (see, for example, Figure 3 ) may be formed by the same process as the process of forming the data line 310, and may be formed by using the same mask as the mask used to form the data line 310. The driving voltage line 330 (see, for example, Figure 3) may be formed substantially simultaneously with the data line 310 and may be formed by the same process as the process for forming the data line 310. However, since the driving voltage line 330 may be in direct contact with the second electrode 232, the second contact hole 107H2 exposing the second electrode 232 may be covered with the photoresist 600 during the process described in Figure 5 and Figure 6 .

[0100] In an exemplary embodiment of the present invention, by forming the lower layer UL1 of the conductive material layer 300 having a metal nitride layer, it is possible to prevent stains that may occur when the lower layer UL1 is a metal layer including a metal such as Ti from being observed by the user. In an exemplary embodiment of the present invention, the molar ratio of nitrogen to metal (N / M, where N is nitrogen and M is metal) included in the lower layer UL1 may be greater than 0.8. For example, when the metal is titanium, 0.8 < N / Ti ≤ 1.15. When N / Ti deviates from the lower limit of the above conditions, silicon may diffuse into the lower layer UL1 of the data line 310 or the driving voltage line 330 during the annealing process, and the resistance may increase.

[0101] Although in the exemplary embodiment of the present invention described in Figures 4 to 9 , the annealing process may be performed before the formation of the conductive material layer 300, the exemplary embodiment of the present invention is not limited thereto. In an exemplary embodiment of the present invention, the annealing process may be performed after the formation of the conductive material layer 300. In an exemplary embodiment of the present invention, the annealing process may be performed after the formation of the conductive material layer 300 and before the process of forming the pixel electrode 510.

[0102] The technical features of the first contact hole 107H1 are also applicable to other contact holes described herein (e.g., the third contact hole 107H3). For example, the technical features described herein with reference to Figures 4 to 9 may be applicable to the third contact hole 107H3.

[0103] Fig.10 is a cross-sectional view of a display area of a display device according to an exemplary embodiment of the present invention. Fig.10 is a cross-sectional view of the display area taken along the line Figure 1 I-I'.

[0104] Referring to Fig.10 , a display device according to an exemplary embodiment of the present invention may include conductive layers such as a data line 310, a driving voltage line 330, and a connection conductor 350. The data line 310, the driving voltage line 330, and the connection conductor 350 may each have a multilayer structure including a lower layer UL1, and the lower layer UL1 may include a metal nitride layer (see, for example Figure 3). The data line 310 and the driving voltage line 330 may be connected to the semiconductor layer, for example, the second semiconductor layer 221 and the first semiconductor layer 211, respectively. A contact layer 361 and a side layer 362 may be formed around the contact hole for connecting the data line 310 and the driving voltage line 330 to the semiconductor layer. Figures 1 to 3 ) has the same or substantially the same technical features as those described in the preceding paragraph.

[0105] refer to Fig.10 , the storage capacitor 230' connected to the driving voltage line 330 may overlap the first TFT 210. The storage capacitor 230' may include a first electrode 231' and a second electrode 232', and the first electrode 231' may serve as a first gate electrode 215 of the first TFT 210. The second electrode 232' may overlap the first gate electrode 215 and the first electrode 231' with the interlayer insulating layer 105 interposed therebetween. The interlayer insulating layer 105 may include an inorganic insulating layer.

[0106] Fig.11 is a cross-sectional view of a display region of a display device according to an exemplary embodiment of the present invention. Fig.11 For along Figure 1 A cross-sectional view of the display area taken along line II'.

[0107] refer to Fig.11 , the display device according to the exemplary embodiment of the present invention may include a conductive layer such as a data line 310, a driving voltage line 330, and a connecting conductor 350 (see, for example Figure 3 and Fig.10 ). Fig.11 The display device may further include a third insulating layer 108, and a driving voltage line 430 and a connecting conductor 450 disposed on the third insulating layer 108. Figures 1 to 3 and Fig.10 ) has the same or substantially the same technical features as those described in the preceding paragraph.

[0108] Similar to the driving voltage line 330 under the third insulating layer 108, the driving voltage line 430 on the third insulating layer 108 can provide the circuit unit with the driving voltage ELVDD. In order to distinguish the driving voltage line 430 on the third insulating layer 108 (e.g., on the upper surface of the third insulating layer 108) from the driving voltage line 330 disposed under the third insulating layer 108 (e.g., on the bottom surface of the third insulating layer 108), the driving voltage line 430 on the third insulating layer 108 can be referred to as an upper driving voltage line 430. Similarly, the connecting conductor 450 on the third insulating layer 108 can be referred to as an upper connecting conductor 450.

[0109] The data line 310, the driving voltage line 330, and the connecting conductor 350 may be substantially covered by the third insulating layer 108. The stacked structure of the conductive layers such as the data line 310, the driving voltage line 330, and the connecting conductor 350, for example, the lower layer UL1, the metal layer ML1, and the cover layer CL1 may be connected to the reference layer 108. Figures 3 to 10 The same as those described in more detail.

[0110] The upper driving voltage line 430 and the upper connecting conductor 450 may be disposed on the third insulating layer 108. The third insulating layer 108 may include an organic insulating layer, and may include, for example, a general polymer such as an imide-based polymer, PMMA, or PS, or a polymer derivative having a phenol-based group, an acrylic-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof.

[0111] The upper driving voltage line 430 may be directly disposed on the third insulating layer 108 to directly contact the upper surface of the third insulating layer 108, and may be connected to the driving voltage line 330 disposed below the third insulating layer 108. For example, a portion of the upper driving voltage line 430 may directly contact the upper surface of the driving voltage line 330 exposed through the fourth contact hole 108H1.

[0112] The upper connection conductor 450 may be directly disposed on the third insulating layer 108 to directly contact the upper surface of the third insulating layer 108, and may be connected to the connection conductor 350 disposed under the third insulating layer 108. For example, a portion of the upper connection conductor 450 may directly contact the upper surface of the connection conductor 350 exposed through the fifth contact hole 108H2. The upper connection conductor 450 may connect the connection conductor 350 to the pixel electrode 510.

[0113] The lower layer UL2 of the upper conductive layer such as the upper driving voltage line 430 and the upper connecting conductor 450 may include a metal nitride layer, and the metal layer ML2 may be disposed on the lower layer UL2. The metal layer ML2 may be substantially covered by the cover layer CL2.

[0114] The lower layer UL2 may be a metal nitride layer, and may include at least one of titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride. The metal layer ML2 may include a metal having a small resistance, such as Mo, Al, Cu, or Ti. The cover layer CL2 may include a metal different from the metal included in the metal layer ML2, and may prevent the metal layer ML2 from being damaged or oxidized during a process (during a manufacturing process). In an exemplary embodiment of the present invention, although the lower layer UL2 of the upper conductive layer, the metal layer ML2, and the cover layer CL2 may be TiN / Al / Ti, the exemplary embodiment of the present invention is not limited thereto.

[0115] The lower layer UL2 of the upper conductive layer may directly contact the third insulating layer 108. When the lower layer UL2 includes a metal nitride layer, the lower layer UL2 may prevent the metal nitride from coupling with oxygen included in the organic insulating layer and prevent the formation of an oxide layer, as described above in more detail.

[0116] The lower layer UL2 may have a or greater, and stains may be prevented from being viewed from the outside, and the metal layer ML2 and the cover layer CL2 may be formed to have a thickness greater than that of the underlayer UL2, as described above.

[0117] refer to Figures 3 to 11 , the connection conductor 350 and the upper connection conductor 450 may be connected to the first TFT 210, but the exemplary embodiment of the present invention is not limited thereto. Figure 2 , the circuit unit may further include a TFT connected to the first TFT 210 and the OLED. In this case, the added TFT may be electrically connected to the pixel electrode 510 through the connection conductor 350 and the upper connection conductor 450.

[0118] While the present invention has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display device, comprising: a substrate, the substrate comprising a display area and a surrounding area outside the display area; a circuit unit, the circuit unit being disposed in the display area and comprising a semiconductor layer, a first insulating layer on the semiconductor layer, and a conductive layer connected to the semiconductor layer through a first contact hole in the first insulating layer, wherein the conductive layer comprises a capping layer, a metal layer and a lower layer, the lower layer comprises a metal nitride, and the metal nitride comprises a first metal; a second insulating layer on the conductive layer and having a second contact hole, wherein the conductive layer includes: a first region portion overlapped by the second contact hole, wherein the first region portion includes a portion of the cover layer, a portion of the metal layer, and a portion of the lower layer, all of which overlap with a bottom surface of the second contact hole; A display element disposed on the circuit unit and including a pixel electrode electrically connected to the conductive layer; and a connecting layer, the connecting layer being disposed below the conductive layer, wherein the connecting layer corresponds to the first contact hole and comprises a second metal, Wherein, a portion of the lower surface of the conductive layer is in direct contact with the upper surface of the first insulating layer. 2 . The display device according to claim 1 , wherein the first insulating layer comprises an organic insulating layer.

3. The display device according to claim 1, further comprising: A side layer is located on at least a portion of an inner wall of the first contact hole and includes the second metal. 4 . The display device according to claim 1 , wherein the lower layer comprises at least one of titanium nitride, tantalum nitride, niobium nitride, and tungsten nitride. The display device according to claim 1 , wherein the metal layer is provided on the lower layer. 6 . The display device according to claim 5 , wherein the metal layer includes at least one of Mo, Al, Cu, and Ti. 7 . The display device according to claim 5 , wherein a thickness of the metal layer is greater than a thickness of the lower layer.

8. The display device according to claim 1, wherein the thickness of the lower layer is or larger. 9 . The display device according to claim 1 , wherein the connection layer comprises a metal silicide layer, and the metal silicide layer comprises the second metal.

10. The display device of claim 1, wherein the display element comprises an organic light emitting diode.

11. A display device, comprising: a substrate, the substrate comprising a display area and a surrounding area outside the display area; A circuit unit, the circuit unit is arranged in the display area and includes a semiconductor layer, a conductive layer and an organic insulating layer, wherein the conductive layer includes a cover layer, a metal layer and a lower layer, the lower layer includes a metal nitride, and the lower layer is in direct contact with the organic insulating layer; an insulating layer on the conductive layer, wherein the conductive layer includes: a first region portion overlapped by the contact hole in the insulating layer, wherein the first region portion includes a portion of the cover layer, a portion of the metal layer, and a portion of the lower layer, each overlapping a bottom surface of the contact hole in the insulating layer; and a display element, the display element being disposed on the circuit unit and comprising a pixel electrode electrically connected to the conductive layer, Wherein, a portion of the lower surface of the conductive layer is in direct contact with the upper surface of the organic insulating layer. 12 . The display device according to claim 11 , wherein the conductive layer comprises a metal nitride layer, and the metal layer is disposed on the metal nitride layer. 13 . The display device of claim 12 , wherein the metal nitride layer comprises at least one of titanium nitride, tantalum nitride, niobium nitride, and tungsten nitride. 14 . The display device according to claim 12 , wherein the metal layer comprises at least one of Mo, Al, Cu, and Ti.

15. The display device according to claim 12, wherein the cover layer is disposed on the metal layer.

16. The display device according to claim 12, wherein the thickness of the metal nitride layer is or larger. 17 . The display device according to claim 12 , wherein a thickness of the metal layer is greater than a thickness of the metal nitride layer.

18. The display device according to claim 11, wherein the conductive layer is connected to the semiconductor layer through a contact hole in the organic insulating layer.

19. The display device according to claim 18, further comprising: A metal silicide layer is disposed below the lower layer of the conductive layer.

20. The display device according to claim 19, further comprising: a side layer covering at least a portion of an inner wall of the contact hole in the organic insulating layer, The metal contained in the side layer is the same as the metal contained in the metal silicide layer.

21. The display device according to claim 11, further comprising: a metal element disposed below the organic insulating layer, and The conductive layer directly contacts the metal element through a contact hole in the organic insulating layer. 22 . The display device according to claim 21 , wherein the circuit unit further includes a storage capacitor, and the metal element is an electrode of the storage capacitor.

23. The display device according to claim 11, wherein the circuit unit further comprises a thin film transistor, and a data line and a driving voltage line electrically connected to the thin film transistor, and the conductive layer is one of the data line and the driving voltage line.

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