Display device for driving and compensating low latency virtual reality

Abstract

A display device for driving and compensating low latency virtual reality. The present disclosure relates to a display device for driving virtual reality with low latency and compensating for reduced luminance. According to the present disclosure, a display device is provided, and the display device includes a timing controller for receiving a data signal and a timing signal from a host system, a data driving unit for receiving a driving signal from the timing controller, a gate driving unit for receiving a driving signal from the timing controller, a display panel having a plurality of sub-pixels and displaying a video based on signals received from the data driving unit and the gate driving unit, and a power supply unit for supplying power to the data driving unit, the gate driving unit, and the display panel, and the timing controller receives an addressing reset signal from the host system.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display apparatus for driving and compensating virtual reality, and more particularly, to a display apparatus for driving virtual reality with low latency and compensating for reduced brightness. BACKGROUND

[0002] As information technology develops, the market for display apparatuses, which are a medium for connecting users and information, is expanding. Accordingly, the use of display apparatuses such as organic light emitting diode (OLED) display apparatuses, quantum dot displays (ODD), liquid crystal displays (LCD), and plasma display panels (PDP) is increasing.

[0003] Display apparatuses are implemented as small, medium, or large displays such as televisions, set-top boxes, navigations, video players, Blu-ray players, personal computers, wearable devices, mobile phones, and virtual reality displays.

[0004] In addition, virtual reality display apparatuses enable users to immerse in an environment that imitates and reproduces reality as it is. For this purpose, users of virtual reality display apparatuses wear devices such as goggles, headsets, gloves, and special clothes to exchange information and are exposed to a virtual environment created by a system (e.g., a computer, etc.).

[0005] However, there is a problem in that users experience so-called virtual reality sickness (VR sickness) when viewing virtual reality display apparatuses. Virtual reality is closer to a person's eyeball than a conventional display apparatus, so that the person's visual acceptance of a picture becomes very large. When a person's motion is not consistent with a change in a picture corresponding to the motion, virtual reality sickness occurs. There is a problem in that virtual reality sickness is a major discomfort for virtual reality users and limits the use time of virtual reality. SUMMARY

[0006] The disclosure aims to solve these problems, and one object of the disclosure is to provide a display apparatus for driving low-latency virtual reality.

[0007] In addition, the disclosure aims to solve these problems, and another object of the disclosure is to provide a display apparatus for compensating for brightness while driving low-latency virtual reality.

[0008] According to this disclosure, a display device is provided, comprising: a timing controller for receiving data signals and timing signals from a host system; a data driving unit for receiving driving signals from the timing controller; a gating driving unit for receiving driving signals from the timing controller; a display panel having a plurality of sub-pixels and displaying video based on signals received from the data driving unit and the gating driving unit; and a power supply unit for supplying power to the data driving unit, the gating driving unit, and the display panel; and the timing controller receiving an address reset signal from the host system.

[0009] The timing controller receives the address reset signal when motion occurs.

[0010] When the addressing reset signal is received, the timing controller sends a strobe reset signal to the strobe drive unit.

[0011] The address reset bit is assigned to any one of a plurality of irrelevant bits in the Low Voltage Differential Signaling (LVDS) transmission format transmitted between the host system and the timing controller.

[0012] The address reset signal is received by referring to a recovery table indicating the combination of VSYNC and HSYNC bits in the LVDS transmission format transmitted between the host system and the timing controller.

[0013] In the built-in clock interface between the host system and the timing controller, a first horizontal blanking packet with address reset start data, a dummy packet following the first horizontal blanking packet, and a second horizontal blanking packet with address reset end data following the dummy packet are sent / received.

[0014] The display device adjusts the pulse width of the address reset signal by adjusting the length of the dummy group.

[0015] The timing controller sends the compensation light emission signal to the gating drive unit.

[0016] The compensation illumination is controlled by the compensation illumination period based on the compensation illumination signal in the display device, and the compensation illumination period is controlled by the pulse width of the address reset signal.

[0017] The compensation illumination based on the compensation illumination signal in the display device is controlled by the illumination brightness.

[0018] The gating drive unit performs control to reduce the brightness of the light emitted to display video data reflecting motion.

[0019] The reduced luminance in the display device is calculated based on the compensation ratio, and the compensation ratio is calculated as the ratio between the ideal luminance and the actual luminance.

[0020] According to this disclosure, low latency can be achieved when driving virtual reality.

[0021] Furthermore, according to this disclosure, it is possible to remove virtual reality syndromes (VR syndromes) from virtual reality users.

[0022] In addition, according to this disclosure, the reduction in brightness can be compensated because the transmit hold time of the previous frame becomes longer due to the gating address reset and the new frame configuration in response to changes in user motion. Attached Figure Description

[0023] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0024] Figure 2 This is an illustrative example. Figure 1 The diagram illustrates the arrangement of subpixels in a display device.

[0025] Figure 3 This is a diagram illustrating a portion of a virtual reality display device.

[0026] Figure 4 This is a diagram used to illustrate the definition of delay in virtual reality display devices.

[0027] Figure 5A This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0028] Figure 5B This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0029] Figure 5C This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0030] Figure 6 This is a schematic example used to implement the reference. Figure 5C A block diagram of an example display device.

[0031] Figure 7 This is an example used to implement the reference. Figure 5C The illustration shows a diagram of the data structure of the display device.

[0032] Figure 8 This is an example used to implement the reference. Figure 5C The illustration shows a diagram of the grouping structure of the display device.

[0033] Figure 9A It is used to illustrate the implementation of the reference. Figure 5C The diagram illustrates the brightness compensation during the delay configuration.

[0034] Figure 9B It is used to illustrate the implementation of the reference. Figure 5C The diagram illustrates the brightness compensation during the delay configuration.

[0035] Figure 9C It is used to illustrate the implementation of the reference. Figure 5C The diagram illustrates the brightness compensation during the delay configuration. Detailed Implementation

[0036] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0038] Figure 2 This is an illustrative example. Figure 1 The diagram illustrates the arrangement of subpixels in a display device.

[0039] like Figure 1 As illustrated, the display device includes a host system 100, a timing controller 170, a data drive unit 130, a power supply unit 140, a gating drive unit 150, and a display panel 110.

[0040] The host system 100 includes a system-on-chip (SoC) with a built-in scaler, and converts the digital video data of the input video into a data signal in a format suitable for display on the display panel 110 and outputs the data signal. The host system 100 provides various timing signals along with the data signals to the timing controller 170.

[0041] The timing controller 170 receives video data from the host system 100. The timing controller 170 controls the operation timing of the data drive unit 130 and the strobe drive unit 150 based on timing signals such as the vertical synchronization signal (V_Sync), the horizontal synchronization signal (H_Sync), the data enable signal (DE), and the master clock signal (Pixel Clock) input from the host system 100.

[0042] The timing controller 170 processes the data signal input from the host system 100 into video and supplies it to the data drive unit 130. For example, the timing controller 170 compensates for the data signal input from the host system 100 and supplies it to the data drive unit 130.

[0043] The data drive unit 130 performs operations in response to signals supplied from the timing controller 170. For example, the data drive unit 130 operates in response to a first drive signal (DDC) provided from the timing controller 170. The data drive unit 130 converts the digital data signal (DATA) provided from the timing controller 170 into an analog data signal and outputs the analog data signal.

[0044] Specifically, the data driving unit 130 converts the digital data signal (DATA) into an analog data signal in response to a gamma voltage in gamma units provided internally or externally. The data driving unit 130 provides the data signal to the data lines (DL1 to DLn) of the display panel 110.

[0045] The gating drive unit 150 operates in response to a signal supplied from the timing controller 170. For example, the gating drive unit 150 operates in response to a second drive signal (GDC) provided from the timing controller 170. The gating drive unit 150 outputs a gating signal that selects a high voltage or a low voltage. The gating signal may also be referred to as a scan signal.

[0046] The gating drive unit 150 can sequentially output gating signals in the forward direction or sequentially output gating signals in the reverse direction. Alternatively, the gating drive unit 150 can output gating signals simultaneously. The gating drive unit 150 provides the gating signals to the gating lines (GL1 to GLm) of the display panel 110.

[0047] The power supply unit 140 provides a first voltage source (VCC, GND) for driving the data drive unit 130, etc., and a second voltage source (EVDD, EVSS) for driving the display panel 110. In addition, the power supply unit 140 generates the voltages required to drive the display device, such as the gating high voltage or gating low voltage to be transmitted to the gating drive unit 150.

[0048] Display panel 110 includes a plurality of sub-pixels (SPs), data lines (DL1 to DLn) connected to the sub-pixels (SPs), and gating lines (GL1 to GLm) connected to the sub-pixels (SPs). Display panel 110 displays video in response to a gating signal output from gating drive unit 150 and a data signal output from data drive unit 130. Display panel 110 includes a lower substrate and an upper substrate. Sub-pixels (SPs) can be interposed between the lower substrate and the upper substrate.

[0049] like Figure 2As illustrated, a sub-pixel includes a switching thin-film transistor (SW) connected to (or formed at the intersection of) a gate line (GL1) and a data line (DL1) and a pixel circuit (PC) that operates in response to a data signal supplied through the switching thin-film transistor (SW).

[0050] Depending on the configuration of the pixel circuits (PCs) of the sub-pixels (SPs), the display panel 110 can be implemented as a liquid crystal display panel or an organic light-emitting display panel, etc. For example, when the display panel 110 is implemented as a liquid crystal display panel, it operates in twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, edge field switching (FFS) mode, or electrically controlled birefringence (ECB) mode.

[0051] As another example, when the display panel 110 is implemented as an organic light-emitting display panel, it operates in either a top-emitting mode or a bottom-emitting mode.

[0052] The display panel of the aforementioned display device can be selected from liquid crystal display panels, organic light-emitting display panels, electrophoretic display panels, plasma display panels, etc. However, it should be understood that this disclosure is not limited to any one of them.

[0053] Furthermore, the aforementioned display devices can be implemented as small, medium, or large displays such as televisions, set-top boxes, navigation systems, video players, Blu-ray players, personal computers, wearable devices, home theaters, mobile phones, and virtual reality (VR) display devices. When implementing virtual reality based on display devices with organic light-emitting display panels, the following display devices offer greater advantages and will be described as examples. However, it should be understood that this disclosure is not limited to any of them.

[0054] Furthermore, in the display panel implementing virtual reality, it can be achieved through either a scroll shutter mode or a global shutter mode. When implemented in global shutter mode, the following display device has greater advantages, and will be described as an example. However, it should be understood that this disclosure is not limited to either of them.

[0055] Figure 3 This is a diagram illustrating a portion of a virtual reality display device.

[0056] like Figure 3 As illustrated, the virtual reality display device includes a left-eye display driver unit (180L, 150L, ​​LAA) for displaying video in the left-eye direction and a right-eye display driver unit (180R, 150R, RAA) for displaying video in the right-eye direction.

[0057] The left eye display driving unit (180L, 150L, ​​LAA) and the right eye display driving unit (180R, 150R, RAA) include a panel driving unit (180L, 180R), a gating driving unit (150L, ​​150R), and a display unit (LAA and RAA).

[0058] The panel driving units (180L, 180R) control the gating driving units (150L, ​​150R) and supply data signals to the display units (LAA, RAA). The panel driving units (180L, 180R) integrate... Figure 1 The timing controller 170 and data drive unit 130 are integrated circuits (ICs). The panel drive units (180L, 180R) may also include... Figure 1 The power supply unit 140 in the middle.

[0059] also, Figure 3 Examples of separate left-eye display driver units (180L, 150L, ​​LAA) for displaying video in the left-eye display direction and right-eye display driver units (180R, 150R, RAA) for displaying video in the right-eye display direction are illustrated, but it should be understood that this is merely an example and this disclosure is not limited thereto.

[0060] Virtual reality display devices, as described above, enable users to immerse themselves in an environment that faithfully mimics and reproduces reality. For this purpose, users wear devices such as goggles, headsets, gloves, and special clothing to exchange information and are exposed to a virtual environment created by a system (e.g., a computer).

[0061] In the following text, in order to improve virtual reality symptoms (VR symptoms) that occur in virtual reality display devices, a display device for driving and compensating for virtual reality with low latency will be described.

[0062] Figure 4 This is a diagram used to illustrate the definition of delay in virtual reality display devices.

[0063] Reference Figure 4In virtual reality (VR) display devices, latency is defined as the time interval from the moment motion occurs to the moment the first photon is generated. Specifically, motion refers to a change in the video displayed to the user. For example, when a user experiencing VR turns their head, this signifies a change in field of view. Since the display should show an omnidirectional view in a physically constrained environment, the display device should display the changed field of view on the panel according to the change in field of view. Displaying an image on the display device means that the organic light-emitting elements in the organic light-emitting display device emit light, that is, generate the first photon. Therefore, latency in VR display devices is defined as the time interval from the moment motion occurs to the moment the first photon is generated to display the video reflecting the changed motion. When the latency becomes longer, the user will experience VR sickness. That is, despite the change in field of view, the user feels uncomfortable when the changed field of view is delayed and displayed on the display device, and this delay occurs continuously. As another example, changes can occur in the displayed video even if the user does not take any action. For example, changes in the video due to a specific event are also included in motion.

[0064] also, Figure 4 The addressing period illustrated refers to the period during which the host system 100 provides signals (V_Sync, H_Sync, data enable signal, master clock signal, etc.) to the timing controller 170 in response to motion, for displaying video corresponding to the motion, and the timing controller 170 provides drive signals (DATA, DDC, GDC, etc.) to the data drive unit and the strobe drive unit. Additionally, Figure 4 The emission period illustrated herein refers to the period during which the organic light-emitting element emits light. However, it should be understood that this disclosure is not limited to these meanings and may also include equivalent periods.

[0065] As a result, the latency in a virtual reality display device is defined as the time interval from the moment motion occurs to the moment the first photon is generated. That is, the latency is preferably the addressing time interval (T_addr).

[0066] Figure 5A This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0067] Reference Figure 5AThe example illustrates three frame periods (T_frame1, T_frame2, and T_frame3), each including an addressing period and an emission period. Specifically, frame period 1 (T_frame1) includes addressing period 1 (T_addr1) and emission period 1 (T_emit1), frame period 2 (T_frame2) includes addressing period 2 (T_addr2) and emission period 2 (T_emit2), and frame period 3 (T_frame3) includes addressing period 3 (T_addr3) and emission period 3 (T_emit3).

[0068] For example, in a display device operating in 120Hz 20% global shutter mode, the frame duration (T_frame) can be 8.33ms, the addressing duration (T_addr) can be 6.66ms, and the emission duration (T_emit) can be 1.67ms.

[0069] Assume that motion occurs during addressing period 2 (T_addr2). In this case, emission for displaying video reflecting the motion can be performed during emission period 3 (T_emit3). As previously defined, the delay in a virtual reality display device is defined as the time interval from the moment motion occurs to the moment the first photon is generated for displaying video reflecting the changed motion. Therefore, Figure 5A The delay in this case is T_extra + T_frame. In other words, the delay in this case is T_extra + T_emit2 + T_addr3.

[0070] As mentioned above, the preferred option is that the delay is the addressing time period (T_addr). (Refer to...) Figure 5A In the example, the latency has been further increased by T_extra + T_emit compared to the addressing period (T_addr). That is, the user has already experienced motion from his / her perspective, but will see the video reflecting that motion later than ideally. Therefore, virtual reality syndrome (VR syndrome) experienced by the user is unavoidable.

[0071] Figure 5B This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0072] Reference Figure 5BThe example illustrates four frame periods (T_frame1, T_frame2, T_frame3, T_frame4), and each frame period includes an addressing period and an emission period. That is, frame period 1 (T_frame1) includes addressing period 1 (T_addr1) and emission period 1 (T_emit1), frame period 2 (T_frame2) includes addressing period 2 (T_addr2) and emission period 2 (T_emit2), frame period 3 (T_frame3) includes addressing period 3 (T_addr3) and emission period 3 (T_emit3), and frame period 4 (T_frame4) includes addressing period 4 (T_addr4) and emission period 4 (T_emit4).

[0073] For example, in a display device operating in 120Hz 20% global shutter mode, the frame duration (T_frame) can be 8.33ms, the addressing duration (T_addr) can be 6.66ms, and the emission duration (T_emit) can be 1.67ms.

[0074] Assume motion occurs during addressing period 2 (T_addr2). In this case, the SoC (included in the host system 100) processes two data sets within one addressing period. That is, the SoC processes video data prior to the motion and video data reflecting the motion within one addressing period (T_addr2,3). In other words, it mixes and processes the video data prior to the motion and the video data reflecting the motion. The display device receiving data from the SoC generates photons for displaying the two video data sets (i.e., the video data prior to the motion and the video data reflecting the motion) within one emission period (T_emit2,3). As previously defined, the latency in the virtual reality display device is defined as the period from the moment motion occurs to the moment the first photon for displaying the video reflecting the motion is generated. Therefore, Figure 5B The delay in the time interval is shorter than the ideal time interval (T_addr).

[0075] As mentioned above, the preferred option is that the delay is the addressing time period (T_addr). (Refer to...) Figure 5B In the example, the latency is further reduced compared to the addressing period (T_addr). That is, the user has already experienced motion from his / her perspective and can immediately see the video reflecting that motion. Therefore, the virtual reality syndrome (VR syndrome) experienced by the user can be minimized. However, as... Figure 5B As illustrated, since both the emission of the video before the motion (T_emit2) and the emission of the video reflecting the motion (T_emit3) are performed simultaneously, the resulting mixed video will ultimately be displayed to the user at the same time.

[0076] Figure 5C This is a diagram illustrating an example of a delay configuration when motion occurs during the addressing period.

[0077] Reference Figure 5C The example illustrates four frame periods (T_frame1, T_frame2, T_frame3, T_frame4), and each frame period includes an addressing period and an emission period. That is, frame period 1 (T_frame1) includes addressing period 1 (T_addr1) and emission period 1 (T_emit1), frame period 2 (T_frame2) includes addressing period 2 (T_addr2) and emission period 2 (T_emit2), frame period 3 (T_frame3) includes addressing period 3 (T_addr3) and emission period 3 (T_emit3), and frame period 4 (T_frame4) includes addressing period 4 (T_addr4) and emission period 4 (T_emit4).

[0078] For example, in a display device operating in 120Hz 20% global shutter mode, the frame duration (T_frame) can be 8.33ms, the addressing duration (T_addr) can be 6.66ms, and the emission duration (T_emit) can be 1.67ms.

[0079] Motion occurs during addressing period 2 (T_addr2). In this case, the SoC (included in the host system 100) generates an addressing reset signal. Additionally, the SoC processes the video data reflecting the motion. When the display device receives the addressing reset signal, it begins a new frame period (T_frame3). That is, the display device addresses the video data reflecting the motion during the T_addr3 period and generates photons for displaying the motion-reflecting video data during the T_emit3 period. As previously defined, the latency in a virtual reality display device is defined as the period from the moment motion occurs to the moment the first photon for displaying the motion-reflecting video is generated. Therefore, Figure 5C The delay in the time interval is the same as the ideal time interval (T_addr).

[0080] As mentioned above, the preferred option is that the delay is the addressing time period (T_addr). (Refer to...) Figure 5C In the example, the latency can be made the same as the addressing time (T_addr). That is, the user has already experienced motion from his / her perspective and can view the video reflecting the motion at the optimal moment. Therefore, the virtual reality syndrome (VR syndrome) experienced by the user can be minimized.

[0081] Figure 6 This is a schematic example used to implement the reference. Figure 5C A block diagram of the display device described in the example.

[0082] like Figure 6 As illustrated, the display device includes a host system 100, a timing controller 170, a data drive unit 130, a power supply unit 140, a gating drive unit 150, and a display panel 110.

[0083] The host system 100 includes a system-on-chip (SoC) with a built-in scaler, and converts the digital data of the input video into a data signal in a format suitable for display on the display panel 110 and outputs the data signal. The host system 100 provides various timing signals along with the data signals to the timing controller 170.

[0084] Additionally, the host system 100 provides an addressing reset signal to the timing controller 170. Specifically, when motion occurs, the host system 100 provides an addressing reset signal to the timing controller 170.

[0085] The timing controller 170 receives video data from the host system 100. Additionally, the timing controller 170 controls the operation timing of the data drive unit 130 and the strobe drive unit 150 based on timing signals input from the host system 100, such as the vertical sync signal (V_Sync), the horizontal sync signal (H_Sync), the data enable signal (DE), and the master clock signal (Pixel Clock).

[0086] The timing controller 170 processes the data signal input from the host system 100 into video and supplies it to the data drive unit 130. For example, the timing controller 170 compensates for the data signal input from the host system 100 and supplies it to the data drive unit 130.

[0087] Additionally, the timing controller 170 receives an addressing reset signal from the host system 100. Specifically, when motion occurs, the host system 100 provides an addressing reset signal to the timing controller 170.

[0088] When the timing controller 170 receives an addressing reset signal from the host system 100, it provides a gate reset signal to the gate driver unit 150. At this time, the gate reset can be configured differently depending on the type and operation of the gate driver unit. For example, the gate driver unit can be reset by keeping the GCLK signal repeatedly input to the on-board gate-type gate driver unit digitally low or digitally high.

[0089] The data drive unit 130 performs operations in response to signals supplied from the timing controller 170. For example, the data drive unit 130 operates in response to a first drive signal (DDC) provided from the timing controller 170. The data drive unit 130 converts the digital data signal (DATA) provided from the timing controller 170 into an analog data signal and outputs the analog data signal.

[0090] Specifically, the data driving unit 130 converts the digital data signal (DATA) into an analog data signal in response to a gamma voltage in gamma units provided internally or externally. The data driving unit 130 provides the data signal to the data lines (DL1 to DLn) of the display panel 110.

[0091] The gating drive unit 150 operates in response to a signal supplied from the timing controller 170. For example, the gating drive unit 150 operates in response to a second drive signal (GDC) provided from the timing controller 170. The gating drive unit 150 outputs a gating signal that selects a high voltage or a low voltage. The gating signal may also be referred to as a scan signal.

[0092] The gating drive unit 150 outputs gating signals sequentially in the forward direction or sequentially in the reverse direction. Alternatively, the gating drive unit 150 can output gating signals simultaneously. The gating drive unit 150 provides the gating signals to the gating lines (GL1 to GLm) of the display panel 110.

[0093] When the gate drive unit 150 receives a gate reset signal from the timing controller 170, the gate drive unit 150 resets the gate drive process. As a result, the display device addresses the video data reflecting the motion. Figure 5C In T_addr3), and generate photons for displaying the video reflecting the motion ( Figure 5C(T_emit3 in the original text). As a result, the delay (the time interval from the moment motion occurs to the moment the first photon reflecting the motion is used to display the video) can be maintained at T_addr, which is the ideal time interval. Therefore, the user has already experienced motion from his / her perspective and can watch the video reflecting the motion at the most ideal moment. Thus, the virtual reality syndrome (VR syndrome) experienced by the user can be minimized.

[0094] The power supply unit 140 provides a first voltage source (VCC, GND) for driving the data drive unit 130, etc., and a second voltage source (EVDD, EVSS) for driving the display panel 110. In addition, the power supply unit 140 generates the voltages required to drive the display device, such as the gating high voltage or gating low voltage to be transmitted to the gating drive unit 150.

[0095] Display panel 110 includes a plurality of sub-pixels (SPs), data lines (DL1 to DLn) connected to the sub-pixels (SPs), and gating lines (GL1 to GLm) connected to the sub-pixels (SPs). Display panel 110 displays video in response to a gating signal output from gating drive unit 150 and a data signal output from data drive unit 130. Display panel 110 includes a lower substrate and an upper substrate. Sub-pixels (SPs) can be interposed between the lower substrate and the upper substrate.

[0096] Figure 7 This is an example used to implement the reference. Figure 5C The diagram describes the data structure of the display device as an example.

[0097] Specifically, Figure 7 This diagram illustrates the communication between the host system 100 and the timing controller 170 via low-voltage differential signaling (LVDS).

[0098] Reference Figure 7 Examples of LVDS transfer format 710 and LVDS recovery table 720 are shown.

[0099] Transmit LVDS transmission format 710 between host system 100 and timer controller 170.

[0100] The LVDS transmission format 710 includes multiple bits. For example, bits R0 to R7 are used to represent red video, bits G0 to G7 are used to represent green video, and bits B0 to B7 are used to represent blue video. Bit VSYNC 712 is used to indicate the vertical sync signal, and bit HSYNC 713 is used to indicate the horizontal sync signal.

[0101] According to this disclosure, any one of the uninteresting bits (so-called irrelevant bits) is assigned to bit 711, which is used to indicate the addressing reset signal. That is, when the addressing reset bit 711 is high (H), the timing controller 170 receiving the corresponding LVDS transmission format 710 receives a command to perform an addressing reset. When the addressing reset bit 711 is low (L), the timing controller 170 receiving the corresponding LVDS transmission format 710 receives a command not to perform an addressing reset.

[0102] According to this disclosure, VSYNC bit 712, HSYNC bit 713, and recovery table 720 can be utilized. For example, when VSYNC bit 712 is low and HSYNC bit 713 is high in LVDS transmission format 710, the timing controller 170 corresponding to LVDS transmission format 710 receives an HSYNC synchronization command with reference to recovery table 720 721. For example, when VSYNC bit 712 is high and HSYNC bit 713 is low in LVDS transmission format 710, the timing controller 170 corresponding to LVDS transmission format 710 receives an HSYNC synchronization command with reference to recovery table 720 722. For example, when VSYNC bit 712 is high and HSYNC bit 713 is high in LVDS transmission format 710, the timing controller 170 corresponding to LVDS transmission format 710 receives a command to perform address reset with reference to recovery table 720 723. For example, when VSYNC bit 712 is low and HSYNC bit 713 is low in LVDS transmission format 710, the timing controller 170 receiving the corresponding LVDS transmission format 710 receives a command to perform no operation by referring to recovery tables 720 and 724.

[0103] Figure 8 This is an example used to implement the reference. Figure 5C The diagram illustrates the grouping structure of the example display device.

[0104] Specifically, Figure 8 This diagram illustrates the communication between the host system 100 and the timing controller 170 via a built-in clock interface.

[0105] Reference Figure 8 This illustrates multiple packets being sent and received between the host system 100 and the timing controller 170. For example, these multiple packets include video data packets 811 and horizontal blanking packets 812.

[0106] When motion occurs during the transmission of video data packet 821, the horizontal blanking packet 822 following the corresponding video data packet 821 includes data indicating the start of addressing reset (ARESET_START). Subsequently, a dummy packet 823 is sent, followed by a horizontal blanking packet 824 including data indicating the end of addressing reset (ARESET_STOP). The length of the dummy packet 823 can be adjusted to control the timing of the addressing reset.

[0107] In other words, addressing reset is indicated by a first horizontal blanking packet 822 including addressing reset start data (ARESET_START), a dummy packet 823 sent and received after the first horizontal blanking packet 822, and a second horizontal blanking packet 824 sent and received after the dummy packet 823 including addressing reset end data (ARESET_STOP), and the dummy packet 823 can be used to control the period during which addressing reset is performed.

[0108] Figure 9A It is used to illustrate the implementation of the reference. Figure 5C A diagram illustrating brightness compensation during the described delay configuration.

[0109] For ease of illustration, a 120 Hz 20% global shutter mode will be described. However, it should be understood that this disclosure is for illustrative purposes only and is not intended to be limiting. In the 120 Hz 20% global shutter mode, the addressing period (T_addr) is 6.66 ms, the emission period (T_emit) is 1.67 ms, and the frame period (T_frame) is 8.33 ms.

[0110] First, I will explain why brightness compensation is needed.

[0111] Reference Figure 9A The example illustrates interval 1 (ideal). Interval 1 (ideal) is the general case where no movement occurs during the second addressing period (T_addr2). The time interval from the emission in the first emission period (T_emit1) to the start of the second emission period (T_emit2) is T_emit1 + T_addr2 = 8.33ms. That is, it is the same as the frame period (T_frame). Since the emission period (T_emit1) is 1.67ms, the brightness perceived by the user is considered to be the average brightness of (emission period) / (frame period). That is, (1.67ms / 8.33ms) = 0.2, resulting in the reception of 20% brightness. For example, when light with a brightness of 100 nits has been emitted during the emission period (T_emit1), the brightness perceived by the user during interval 1 (ideal) is 20 nits, or 20%.

[0112] ReferenceFigure 9B The example illustrates interval 2 (actual). Interval 2 (actual) represents the situation where movement occurs during the second addressing period (T_addr2). In this paper, T_extra is assumed to be 3.33 ms. The emission period (T_emit1) is 1.67 ms, and the period before the second emission is T_emit1 + T_extra + T_addr3 = 11.66 ms. Therefore, since the brightness perceived by the user is (1.67 ms) / (11.66 ms) = 0.143, the perceived brightness is 14.3%. For example, if a light with a brightness of 100 nits has already been emitted during the emission period (T_emit1), the brightness perceived by the user during interval 2 (actual) is 14.3 nits, or 14.3%.

[0113] In other words, according to the reference Figure 5C The delayed configuration resulted in a decrease in brightness that was perceived by the user, leading to the proposal of brightness compensation for the reduced brightness.

[0114] Figure 9B It is used to illustrate the implementation of the reference. Figure 5C A diagram illustrating brightness compensation during the described delay configuration.

[0115] In this embodiment, a compensation emission is proposed to generate brightness compensation for reduced brightness.

[0116] Specifically, preferably, compensation emission occurs between the occurrence of motion and the start of the frame reflecting the motion (T_frame3). (Referring to...) Figure 9A In the description, the reduced brightness is 5.7%. It is possible to control the operation to perform compensating illumination according to the amount of brightness reduction. Specifically, compensating illumination can be performed by controlling the duration of the compensating illumination. For example, as the amount of brightness reduction becomes greater, it is possible to control the duration of the compensating illumination to be longer. As one implementation, the duration of the compensating illumination can be controlled by addressing the pulse width 910 of the reset signal. As another implementation, compensating illumination can be performed by controlling the brightness of the compensating illumination. For example, as the amount of brightness reduction becomes greater, it is possible to control the brightness of the compensating illumination to be greater.

[0117] Compensation emission can be referred to as short global emission or global compensation emission.

[0118] Because of the aforementioned compensatory illumination, virtual reality sickness (VR sickness) experienced by users can be reduced. In other words, without compensatory illumination, motion would cause large brightness deviations in each frame, resulting in visual flickering for the user. However, the brightness deviations can be reduced through the aforementioned compensatory illumination.

[0119] Figure 9C It is used to illustrate the implementation of the reference. Figure 5C A diagram illustrating brightness compensation during the described delay configuration.

[0120] In this embodiment, it is proposed to reduce the amount of light emitted to display video data reflecting motion in order to compensate for the reduced brightness.

[0121] Specifically, in reference Figure 9A In the implementation, the ideal brightness (L_ideal) is 20%, but the actual brightness (L_actual) is 14.3%, a reduction of 5.7%. In this case, when the emission (T_emit3) used to display video data reflecting motion is performed without compensation, the user will experience glare due to the large visual change in brightness. Therefore, this implementation proposes reducing the amount of emission (T_emit3) used to display video data reflecting motion.

[0122] Specifically, the reduction rate of the amount of light emitted (T_emit3) used to display video data reflecting motion can be as follows.

[0123] Compensation ratio = (L_actual) / (L_ideal)

[0124] In other words, in reference Figure 9A In this embodiment, (L_actual) / (L_ideal) = (0.143) / (0.2) = 0.715. Therefore, the amount of light emitted (T_emit3) used to display video data reflecting motion can be reduced by 71.5%. For example, when the intention is to emit 200 nits of light at T_emit3, it can be controlled to emit 143 nits of light as 71.5% according to this embodiment. As another example, when the intention is to emit 300 nits of light at T_emit3, it can be controlled to emit 214.5 nits of light according to this embodiment.

[0125] The reduction in light emission reduces virtual reality sickness (VR sickness) experienced by users. In other words, without compensation lighting, motion causes significant brightness variations per frame, resulting in visual flickering for the user. However, the reduced light emission minimizes these brightness variations.

[0126] As described above, although this disclosure has been described in conjunction with the embodiments illustrated in the figures, those skilled in the art to which this disclosure pertains should understand that other specific forms may be formed without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

[0127] Cross-references to related applications

[0128] This application claims priority to Korean Patent Application No. 10-2017-0183566, filed on December 29, 2017, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising: A timing controller, which receives data signals and timing signals from the host system; A data driving unit, which is used to receive driving signals from the timing controller; A gating drive unit is used to receive drive signals from the timing controller; A display panel having multiple sub-pixels and displaying video based on signals received from the data driving unit and the gating driving unit; as well as A power supply unit is used to supply power to the data driving unit, the gating driving unit, and the display panel. The timing controller receives an address reset signal from the host system. The timing controller receives the address reset signal when motion occurs. In response to receiving the address reset signal, the display device addresses and displays video data mixed with video data reflecting the motion and video data prior to the motion occurring within the current frame period, or immediately starts a new frame period and addresses and displays the video data reflecting the motion within the new frame period. The display device is a virtual reality display device.

2. The display device according to claim 1, wherein, When the addressing reset signal is received, the timing controller sends a strobe reset signal to the strobe drive unit.

3. The display device according to claim 1, wherein, The address reset bit is assigned to any one of a plurality of irrelevant bits in the Low Voltage Differential Signaling (LVDS) transmission format transmitted between the host system and the timing controller.

4. The display device according to claim 1, wherein, The address reset signal is received by referring to a recovery table indicating the combination of VSYNC and HSYNC bits in the LVDS transmission format transmitted between the host system and the timing controller.

5. The display device according to claim 1, wherein, In the built-in clock interface between the host system and the timing controller, a first horizontal blanking packet with address reset start data, a dummy packet following the first horizontal blanking packet, and a second horizontal blanking packet with address reset end data following the dummy packet are sent / received.

6. The display device according to claim 5, wherein, The pulse width of the address reset signal is adjusted by adjusting the length of the dummy group.

7. The display device according to claim 1, wherein, The timing controller sends the compensation light emission signal to the gating drive unit.

8. The display device according to claim 7, wherein, The compensation illumination based on the compensation illumination signal is controlled by the compensation illumination period, and the compensation illumination period is controlled by the pulse width of the address reset signal.

9. The display device according to claim 7, wherein, The compensation illumination based on the compensation illumination signal is controlled by the illumination brightness.

10. The display device according to claim 1, wherein, The gating drive unit performs control to reduce the brightness of the light source used to display video data reflecting motion.

11. The display device according to claim 10, in, The reduction in luminous intensity is calculated based on the compensation ratio, and The compensation ratio is calculated using the ratio between the ideal brightness and the actual brightness.

12. The display device according to claim 1, wherein, The display device is driven in global shutter mode.

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