Image sensor, imaging device and image sensor chip package manufacturing method

Abstract

An image sensor, an imaging device, and a method for manufacturing an image sensor chip package are provided. The image sensor comprises: a pixel array, the pixel array comprising an active area and a dummy area, a plurality of active pixels are located in the active area, and a plurality of dummy pixels are located in the dummy area; and at least one test element group (TEG), which is located in the dummy area and has a test shading pattern formed on the at least one test element group that is different from the shading pattern formed on the active area to detect the degree of misalignment between the shading pattern and the active area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0003350 filed on January 10, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus, device, method and product according to the present disclosure relate to an image sensor, and more particularly, to an image sensor, an imaging device and a method for manufacturing an image sensor chip package. Background Art

[0004] Examples of image sensors as devices for converting optical images into electrical signals include charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors use multiple transistors, and in each pixel, the signal charge generated in the photodiode is converted into a voltage and then output. Since the CMOS image sensor converts light into an electrical signal, image distortion may occur even when the external light changes slightly. Specifically, when the shading structure formed around the photodiode for converting light into an electrical signal is misaligned, the output value of the CMOS image sensor may change, resulting in various defects. Research is underway to solve these problems of CMOS image sensors. Summary of the invention

[0005] One aspect of the present disclosure is to provide an image sensor, an imaging device, and a method of manufacturing an image sensor chip package, which can improve the mass production yield of the image sensor and the performance of the image sensor.

[0006] According to one aspect of an exemplary embodiment, an image sensor is provided, comprising: a pixel array, the pixel array comprising an active area and a dummy area, a plurality of active pixels being located in the active area, and a plurality of dummy pixels being located in the dummy area; and at least one test element group (TEG), which is located in the dummy area and on which a test shading pattern different from a shading pattern formed on the active area is formed to detect a degree of misalignment between the shading pattern and the active area.

[0007] According to another aspect of the exemplary embodiment, there is provided an imaging device including: an image sensor including a pixel array, the pixel array including at least one test element group (TEG), a test shading pattern different from a shading pattern formed on a plurality of active pixels being formed on the at least one test element group to detect a degree of misalignment between the shading pattern and the plurality of active pixels; and an image signal processor configured to receive a plurality of accumulated charges from a plurality of photodiodes of the plurality of active pixels and perform image processing on the plurality of accumulated charges.

[0008] According to another aspect of an exemplary embodiment, a method for manufacturing an image sensor chip package is provided, the method comprising: providing a wafer having a plurality of semiconductor chips formed thereon, wherein each semiconductor chip comprises at least one test element group (TEG) having a plurality of dummy pixels; forming a shading pattern on a plurality of active pixels of each semiconductor chip among the plurality of semiconductor chips, and forming a test shading pattern on the at least one TEG of each semiconductor chip among the plurality of semiconductor chips; testing whether the shading pattern of each semiconductor chip among the plurality of semiconductor chips is aligned based on a plurality of pixel signals generated from the at least one TEG of each semiconductor chip among the plurality of semiconductor chips; for any semiconductor chip among the plurality of semiconductor chips whose shading pattern is not aligned, reforming the shading pattern of the semiconductor chip according to the test result; providing a separate image sensor chip by separating the plurality of semiconductor chips from the wafer; and packaging the separate image sensor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an imaging device according to an example embodiment;

[0011] Figure 2 yes Figure 1 A block diagram of an image sensor;

[0012] Figure 3 is a detailed block diagram of an image sensor according to an example embodiment;

[0013] FIG. 4A to FIG. 4C is a circuit diagram illustrating a unit pixel according to some example embodiments;

[0014] Figure 5 is a diagram of a wafer having image sensor chips arranged thereon according to example embodiments;

[0015] Fig. 6A and Figure 6Bis a plan view of an image sensor chip according to example embodiments;

[0016] Fig. 7A is a plan view showing a state in which a light shielding pattern is aligned with an active region;

[0017] Figure 7B yes Fig. 7A A cross-sectional view of an image sensor in a state of

[0018] Figure 7C is a plan view showing a state where a light shielding pattern is not aligned with an active region;

[0019] FIG. 8A to FIG. 8C is a diagram illustrating a test light shielding pattern formed on a first test element group (TEG) and a second TEG in a step of manufacturing an image sensor according to an example embodiment;

[0020] Fig.9A is a flow chart of a method of manufacturing an image sensor chip package according to an example embodiment;

[0021] Fig. 9B and Fig. 9C It is used to illustrate Fig.9A Schematic diagram of operations S120 and S130;

[0022] FIG. 10A to FIG. 10C is a diagram for explaining various test light shielding patterns according to example embodiments;

[0023] Fig.11A and Fig. 11B is a diagram for explaining steps of forming and reforming a light shielding pattern during a process of manufacturing an image sensor chip package according to example embodiments;

[0024] Fig.12 is a block diagram of a system including an image sensor according to an example embodiment; and Fig.13 is a block diagram illustrating an electronic system including an image sensor and an interface according to example embodiments. DETAILED DESCRIPTION

[0025] Various example embodiments will now be described more fully with reference to the accompanying drawings in which example embodiments are shown.It should be noted that in this specification, the phrase "at least one of A and B" includes "only A", "only B" and "both A and B".

[0026] Figure 1 is a block diagram of an imaging device 1 according to an exemplary embodiment.

[0027] See also Figure 1, the imaging device 1 may include an image sensor 10, an image signal processor 20, and a display 30. The imaging device 1 may be a digital camera or a portable electronic device with a digital camera attached, such as a mobile phone, a smart phone, or a tablet personal computer (PC).

[0028] The image sensor 10, which is a semiconductor device for converting an optical image into an electrical signal, may be, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The image sensor 10 generates image data of the object 50 according to light incident through the lens 40, and outputs the generated image data to the image signal processor 20. The image signal processor 20 processes the image signal output from the image sensor 10, and transmits the processed image signal to the display 30.

[0029] Each of the image sensor 10 and the image signal processor 20 may be a printed circuit board (PCB) such as a motherboard, an integrated circuit (IC), or a system on chip (SoC). In example embodiments, the image sensor 10 and the image signal processor 20 may be implemented by using a single package, such as a multi-chip package (MCP) or a system-in-package (SiP). In example embodiments, the image sensor 10 may be implemented as a separate chip, such as a CMOS image sensor chip.

[0030] The image sensor 10 according to the example embodiment may include a test element group (TEG) 15. A light shielding pattern may be formed on an active area of ​​the image sensor 10, in which active pixels of the image sensor 10 that generate image signals are located. The TEG 15 may be used to detect the degree of misalignment between the light shielding pattern and the active area (or active pixels). The light shielding pattern may prevent areas other than the photodiode area of ​​each active pixel from being exposed to light. The light shielding pattern may include a light shielding structure (or a light shielding member or a light shielding film) formed on each active pixel. The light shielding pattern may be formed of a light blocking material (e.g., tungsten or polysilicon). The TEG 15 may be used in the steps of manufacturing the image sensor 10 and / or the steps of using the image sensor 10.

[0031] First, in the step of manufacturing the image sensor 10, whether the shading pattern is aligned with the active area and the degree of misalignment between the shading pattern and the active area can be detected by using TEG15, and the shading pattern can be re-formed on the active area based on the detected degree of misalignment. TEG15 may include a plurality of dummy pixels, and in the step of manufacturing the image sensor 10, a test shading pattern different from the shading pattern formed on the active pixel can be formed on the dummy pixel of TEG15. In an exemplary embodiment, the test shading pattern may include a test shading structure, and the area of ​​each test shading structure is the same or different from each other according to the dummy pixel, so as to detect the degree of misalignment between the shading pattern and the active area, as described in detail below.

[0032] Since misalignment may occur between the light shielding pattern and the active area due to various factors after the step of manufacturing the image sensor 10, in the step of using the manufactured image sensor 10, whether the light shielding pattern and the active area are aligned with each other and the degree of misalignment between the light shielding pattern and the active area (or the state of the active pixel) can be detected by using the TEG 15. The image signal processor 20 can process the image signal output from the image sensor 10 based on the detected degree of misalignment (or the state of the active pixel). For example, considering the detected degree of misalignment, the image signal processor 20 can apply different processing methods to the image signal.

[0033] The display 30 displays image data received from the image signal processor 20. The display 30 may be a thin film transistor liquid crystal display (TFT-LCD), a light emitting diode (LED) display, an organic LED (OLED) display, or an active matrix OLED (AMOLED) display.

[0034] The image sensor 10 according to the example embodiment can quickly and accurately detect whether the active area where the active pixel is located and the light shielding pattern are aligned with each other by using the TEG 15 on which the test light shielding pattern is formed, and in the case of misalignment, the degree of misalignment between the active area and the light shielding pattern can be detected. In addition, the detected degree of misalignment can be reflected in the steps of manufacturing the image sensor 10 and / or the steps of using the image sensor 10, thereby improving the mass production yield of the image sensor 10 and / or the performance of the image sensor 10.

[0035] Figure 2 yes Figure 1 10 is a block diagram of an image sensor 10.

[0036] See also Figure 2, the image sensor 10 may include a pixel array 100 and a peripheral circuit 200. The pixel array 100 may include an active area 120 and a TEG area 140. A plurality of active pixels may be located in the active area 120, and a plurality of dummy pixels may be located in the TEG area 140. Figure 2 140 , but the inventive concept is not limited thereto, and the pixel array 100 may further include one or more TEG regions. A light shielding pattern may be formed on the active region 120 , and a test light shielding pattern may be formed on the TEG region 140 .

[0037] The peripheral circuit 200 may include at least one logic block. A logic block is a logic circuit including a plurality of logic elements configured to receive a power signal or a control signal and perform a logic operation according to the received power signal or control signal. A logic block as a predefined functional block may be referred to as a digital block or an intelligent property (IP) block.

[0038] Figure 3 is a detailed block diagram of an image sensor 10 a according to example embodiments.

[0039] See also Figure 3 , the image sensor 10a may include a pixel array 100 and a peripheral circuit 200. The pixel array 100 and the peripheral circuit 200 may correspond to Figure 2 The pixel array 100 and the peripheral circuit 200 are shown in FIG. The peripheral circuit 200 may include a control register block 210, a timing generator 220, a row driver 230, a correlated double sampling (CDS) block 240, a comparator block 250, an analog-to-digital conversion (ADC) block 260, a ramp signal generator 270, and a buffer 280. In this case, the CDS block 240, the comparator block 250, the ADC block 260, the ramp signal generator 270, and the buffer 280 may constitute a readout circuit RDC.

[0040] The pixel array 100 may include a plurality of pixels PX arranged in a matrix. The pixel array 100 may include an active area 120, Figure 3 The plurality of pixels PX may be referred to as active pixels located in the active region 120. Each pixel PX may be connected between a row line and a column line, and may output a pixel signal according to incident light. In an example embodiment, each pixel PX may have a multilayer structure including an organic photoelectric conversion unit or an inorganic photoelectric conversion unit. In an example embodiment, each pixel PX may have a multilayer structure in which only an organic photoelectric conversion unit is stacked.

[0041] The timing generator 220 may generate a control signal for controlling the operation timing of the image sensor 10a. Specifically, under the control of the control register block 210, the timing generator 220 may control the operations of the row driver 230, the CDS block 240, the ADC block 260, and the ramp signal generator 270.

[0042] Under the control of the timing generator 220, the row driver 230 may drive at least one of the plurality of row lines of the pixel array 100. Specifically, the row driver 230 may apply a row signal to each of the plurality of row lines of the pixel array 100. The row signal may include a plurality of control signals for controlling a plurality of transistors included in a unit pixel.

[0043] The CDS block 240 receives pixel signals P1 to Pm (where m is a natural number) from a plurality of column lines included in the pixel array 100, and performs CDS on each of the pixel signals P1 to Pm. Specifically, the CDS block 240 may perform double sampling on a noise level and a signal level corresponding to the pixel signal, and may output a difference level corresponding to a difference between the noise level and the signal level.

[0044] The comparator block 250 compares each CDS pixel signal output from the CDS block 240 with the ramp signal output from the ramp signal generator 270 and outputs a comparison signal. In this example embodiment, the peripheral circuit 200 may further include at least one redundant comparator block that may replace the comparator block 250.

[0045] The ADC block 260 counts the comparison signals according to the clock signal, converts the plurality of comparison signals output from the comparator block 250 into a plurality of digital data, and outputs the plurality of digital data to the buffer 280 .

[0046] The ramp signal generator (ramp generator) 270 generates a ramp signal under the control of the timing generator 220. By using a current-based digital-to-analog converter (DAC) or a voltage-to-current (VI) converter, the ramp signal generator 270 can change the voltage level of the ramp signal when the current changes over time. The ramp signal can be generated as a voltage with a single slope, the ramp signal can be applied to the comparator block 250, and can be compared with the pixel signal output from the pixel array 100.

[0047] In the image signal processor 20 (see Figure 1 ), the control register block 210 can control the operations of the timing generator 220, the ramp signal generator 270 and the buffer 280.

[0048] The buffer 280 can store the digital data output from the ADC block 260 in units of frames, and thus can be referred to as a frame memory or a buffer memory. The buffer 280 can output the digital data stored in units of frames to the image signal processor 20 (see Figure 1 ).

[0049] FIG. 4A to FIG. 4C is a circuit diagram of a unit pixel according to some example embodiments.

[0050] See also Figure 4A The unit pixel PXa includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a drive transistor DX, and a selection transistor SX. The unit pixel PXa according to this example embodiment may correspond to Figure 3 Pixel PX.

[0051] The unit pixel PXa can be driven from the outside (eg, the row driver 230 (see Figure 3 )) receives a row signal. The row signal may include a reset signal RG applied to the gate of the reset transistor RX, a transfer signal TG applied to the gate of the transfer transistor TX, and a selection signal SEL applied to the gate of the selection transistor SX. In addition, the unit pixel PXa may generate a pixel signal according to the detected light intensity, and may output the generated pixel signal to the outside, for example, the CDS block 240 (see Figure 3 ). The unit pixel PXa may receive a power supply voltage VDD and may be electrically connected to a column line COL.

[0052] The photodiode PD can receive light and generate photocharges, and can be referred to as a light detection element. The photodiode PD may include at least one of a phototransistor, a photogate, a pinned photodiode (PPD), and a combination thereof. The transfer transistor TX transfers the photocharges generated by the photodiode PD to the floating diffusion area FD. In addition, the reset transistor RX periodically resets the photocharges stored in the floating diffusion area FD, the drive transistor DX serves as a source follower buffer amplifier, and buffers the signal according to the photocharges filled in the floating diffusion area FD, and the selection transistor SX serves as a switch and addressing element for selecting the unit pixel PXa.

[0053] although Figure 4A , a 4-transistor (4T) unit pixel including one photodiode PD and four MOS transistors (ie, TX, RX, DX, and SX) is shown, but the inventive concept is not limited thereto and may be applied to any circuit including a photodiode PD and at least three transistors including a drive transistor DX and a select transistor SX. Figure 4B and Figure 4C Other unit pixels are shown in .

[0054] Reference Figure 4B , a unit pixel PXb as a 3-transistor (3T) unit pixel may include a photodiode PD, a reset transistor RX, a drive transistor DX, and a selection transistor SX. Figure 4C , a unit pixel PXc as a 5-transistor (5T) unit pixel may include a photodiode PD, a reset transistor RX, a drive transistor DX, and a selection transistor SX, and may further include one transistor GX.

[0055] Figure 5 is a diagram of a wafer WF on which image sensor chips CH are arranged according to example embodiments.

[0056] Reference Figure 5 , a plurality of image sensor chips CH may be arranged in a two-dimensional (2D) manner on one surface of the wafer WF. The image sensor chip CH may be referred to as a semiconductor chip. Each image sensor chip CH may include a pixel array PX_array, and the pixel array PX_array may include an active area A_active where a plurality of active pixels are located and a TEG area A_TEG where a plurality of dummy pixels are located.

[0057] In the step of manufacturing the image sensor chip CH, a light shielding pattern may be formed on the active area A_active, and a test light shielding pattern may be formed on the TEG area A_TEG. Next, whether the active area A_active and the light shielding pattern are aligned with each other and the degree of misalignment between the active area A_active and the light shielding pattern in the case of misalignment may be detected based on a pixel signal generated from a dummy pixel located in the TEG area A_TEG.

[0058] Although not in Figure 5 As shown in FIG. 1 , the image sensor chip CH may further include a peripheral circuit 200 (see FIG. Figure 2 ).

[0059] Fig. 6A and Figure 6B 2 are plan views respectively illustrating image sensor chips CHa and CHb according to example embodiments.

[0060] Reference Fig. 6A , the image sensor chip CHa may include a sensor array region SAR, a logic region LR, and a pad region PR formed on a semiconductor substrate SUB. In addition to the sensor array region SAR, the logic region LR and the pad region PR may be collectively referred to as a peripheral circuit region PCR, and the peripheral circuit region PCR refers to a region on the substrate SUB of the image sensor chip CHa except for the sensor array region SAR. The image sensor chip CHa according to example embodiments may be Figure 5However, the image sensor chip CHa is not limited to Fig. 6A In some example embodiments, the logic region LR may be omitted.

[0061] The semiconductor substrate SUB may include, for example, silicon (Si). Alternatively, the semiconductor substrate SUB may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, the semiconductor substrate SUB may include a silicon-on-insulator (SOI) structure or a buried oxide (BOX) layer. The semiconductor substrate SUB may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. In addition, the semiconductor substrate SUB may have any of a variety of device isolation structures, for example, a shallow trench isolation (STI) structure.

[0062] The sensor array region SAR formed with a pixel array may include a plurality of active pixels PX_active and a first TEG (TEG1a) and a second TEG (TEG2a). Fig. 6A The sensor array area SAR is only an example, and the present inventive concept is not limited thereto. In some example embodiments, the sensor array area SAR may include any one of the first TEG TEG1a and the second TEG TEG2a, or may further include one or more additional TEGs in addition to the first TEG TEG1a and the second TEG TEG2a. That is, the number of TEGs is not particularly limited. Consistent with the above description, the first TEG TEG1a may include a plurality of dummy pixels PX_d1, and the second TEG TEG2a may include a plurality of dummy pixels PX_d2.

[0063] In example embodiments, the first TEG TEG1a may be positioned adjacent to at least one of the left and right sides of the active region where the active pixel PX_active is located. Fig. 6A As shown, the first TEG TEG1a may be located on the right side of the active region. A test light shielding pattern may be formed on the first TEG TEG1a, the test light shielding pattern being used to detect whether there is left / right alignment between the active region and the light shielding pattern, and the degree of left / right misalignment between the active region and the light shielding pattern in the case of misalignment. Fig. 8A The test light shielding pattern formed on the first TEG TEG1a is described in detail.

[0064] In example embodiments, the second TEG TEG2a may be positioned adjacent to at least one of the upper side and the lower side of the active region. Fig. 6AAs shown, the second TEG TEG2a may be located on the upper side of the active region. A test light shielding pattern may be formed on the second TEG TEG2a, and the test light shielding pattern is used to detect whether there is an up / down alignment between the active region and the light shielding pattern, and the degree of up / down misalignment between the active region and the light shielding pattern in the case of misalignment. Figure 8B The test light shielding pattern formed on the second TEG TEG2a is described in detail.

[0065] The first TEG TEG1a and the second TEG TEG2a may be spaced apart from each other by a predetermined distance. The number of dummy pixels included in the first TEG TEG1a and the number of dummy pixels included in the second TEG TEG2a may be the same as or different from each other. Fig. 6A The arrangement of the first TEG TEG1a and the second TEG TEG2a is merely exemplary, and the inventive concept is not limited thereto. In some example embodiments, the first TEG TEG1a and the second TEG TEG2a may be located in various positions.

[0066] The logic region LR may be located along the edge of the sensor array region SAR. Fig. 6A In the example of FIG. 1 , the logic region LR is located along all four edges of the sensor array region SAR, but the inventive concept is not limited thereto. In some example embodiments, the logic region LR may be located along only two edges or three edges of the sensor array region SAR.

[0067] The logic area LR may include an electronic component having a plurality of transistors, and may control an output signal, or may apply a predetermined signal to an active pixel PX_active or dummy pixels PX_d1 and PX_d2 of the sensor array area SAR. The pad area PR includes a plurality of pads for sending an electrical signal to an external device or a package base substrate / for receiving an electrical signal from an external device or a package base substrate. The pad area PR is located around the sensor array area SAR. Specifically, a plurality of pads PAD formed on the pad area PR are electrically connected to the active pixel PX_active or the dummy pixels PX_d1 and PX_d2, and a plurality of pads PAD are located around the sensor array area SAR. Although the image sensor chip CHa according to the example embodiment includes the pad area PR, the inventive concept is not limited thereto, and in another example embodiment, the image sensor chip CHa may not include the pad area PR and the pad, or the connector may be located under the sensor array area SAR or the logic area LR.

[0068] Each of the plurality of pads PAD may be formed of, for example, a metal, a metal nitride, or a combination thereof. Conductive wires and conductive plugs for electrically connecting a plurality of active pixels PX_active or dummy pixels PX_d1 and PX_d2 included in the sensor array region SAR, electronic components included in the logic region LR, and the plurality of pads PAD may be formed on the substrate SUB. Each of the conductive wires and conductive plugs may be formed of, for example, a metal, a metal nitride, or a combination thereof.

[0069] See also Figure 6B ,and Fig. 6A Differently, the first TEG and the second TEG may contact each other. Figure 6B As shown, the first TEG TEG1b and the second TEG TEG2b may contact each other. In example embodiments, the first TEG TEG1b and the second TEG TEG2b may contact each other in a diagonal direction of the active region. That is, at least one dummy pixel included in the first TEG TEG1b and at least one dummy pixel included in the second TEG TEG2b may contact each other.

[0070] Fig. 7A is a plan view showing a state of alignment of a light shielding pattern with an active region A_active. Figure 7B is in Fig. 7A sectional view of the image sensor 10 in the state of FIG. Figure 7C is a plan view showing a state where the light shielding pattern and the active region A_active are not aligned.

[0071] Reference Fig. 7A In the step of manufacturing the image sensor 10, a light shielding pattern SP may be formed on the active area A_active of the image sensor 10. The light shielding pattern SP may be formed to prevent an area other than the photodiode area A_PD, in which the photodiode of each active pixel PX_active is formed, from being exposed to light. The light shielding pattern SP may include a light shielding structure formed on each active pixel PX_active.

[0072] Reference Figure 7B , the image sensor 10 may include a microlens ML, a color filter CF, a light shielding structure SS, and an active pixel PX_active. The active pixel PX_active may include a photodiode PD and a storage diode SD. The photodiode PD converts incident light into electric charge and accumulates the electric charge, and the accumulated electric charge is stored in the storage diode SD. In this case, a light shielding structure SS may be formed on the active pixel PX_active so that light is incident on the photodiode PD and is blocked by the storage diode SD.

[0073] See also Figure 7C Due to various factors during or after the steps of manufacturing the image sensor 10, the light shielding pattern SP may be formed offset in a predetermined direction (e.g., to the left) and may be misaligned with the active area A_active. Therefore, the light shielding pattern SP may be formed on a portion of the photodiode area A_PD, so that a portion of light incident on the photodiode may be blocked, and the storage diode of the active pixel PX_active may be exposed, so the output value of the active pixel PX_active may not be the expected value. In the steps of manufacturing the image sensor 10, in order to align the light shielding pattern SP with the active area A_active, such as Fig. 7A As shown, TEG may be used. A test light shielding pattern formed on TEG will be described in detail below.

[0074] FIG. 8A to FIG. 8C is a diagram showing a test light shielding pattern formed on the first TEG TEG1 and the second TEG TEG2 in the step of manufacturing the image sensor. FIG. 8A to FIG. 8C The test light shielding pattern is configured to accurately determine the degree of misalignment between the active area of ​​the image sensor and the light shielding pattern. Although in the step of manufacturing the image sensor, the first TEG TEG1 and the second TEG TEG2 are formed FIG. 8A to FIG. 8C The test shading pattern, but due to Fig. 9B Due to various factors of the environment of the manufacturing process shown, the test light shielding pattern may be misaligned. The misalignment trend between the active region and the light shielding pattern may be the same as or similar to the misalignment trend between the TEG and the test light shielding pattern.

[0075] Fig. 8A The first TEG TEG1a in can correspond to Fig. 6A The first TEG TEG1a or Figure 6B The first TEG TEG1b. The first TEG TEG1 may include a plurality of dummy pixels PXa_d11, PXa_d21, PXa_d31, PXa_d41, PXa_d51, PXa_d12, PXa_d22, PXa_d32, PXa_d42, and PXa_d52, and the plurality of dummy pixels PXa_d11 to PXa_d52 may be divided into a first group of dummy pixels and a second group of dummy pixels. However, Fig. 8A The first TEG TEG1 is exemplary, and the present inventive concept is not limited thereto, and the first TEG TEG1 may include Fig. 8A More or fewer dummy pixels are shown in .

[0076] In example embodiments, a first group of dummy pixels for detecting a left misalignment degree between an active area and a light shielding pattern may include a vertically aligned dummy pixel PXa_d11, a dummy pixel PXa_d21, a dummy pixel PXa_d31, a dummy pixel PXa_d41, and a dummy pixel PXa_d51. A second group of dummy pixels for detecting a right misalignment degree between an active area and a light shielding pattern may include a vertically aligned dummy pixel PXa_d12, a dummy pixel PXa_d22, a dummy pixel PXa_d32, a dummy pixel PXa_d42, and a dummy pixel PXa_d52.

[0077] In an example embodiment, a test light shielding pattern may be formed on the first TEG TEG1 in the step of manufacturing the image sensor. The test light shielding pattern may include a first test pattern TP1, a second test pattern TP2, a third test pattern TP3, a fourth test pattern TP4, and a fifth test pattern TP5. The first test pattern TP1 may include a test light shielding structure SS_1a formed on a dummy pixel PXa_d11 and a test light shielding structure SS_1b formed on a dummy pixel PXa_d12. The second test pattern TP2 may include a test light shielding structure SS_2a formed on a dummy pixel PXa_d21 and a test light shielding structure SS_2b formed on a dummy pixel PXa_d22. The third test pattern TP3 may include a test light shielding structure SS_3a formed on a dummy pixel PXa_d31 and a test light shielding structure SS_3b formed on a dummy pixel PXa_d32. The fourth test pattern TP4 may include a test light shielding structure SS_4a formed on the dummy pixel PXa_d41 and a test light shielding structure SS_4b formed on the dummy pixel PXa_d42. The fifth test pattern TP5 may include a test light shielding structure SS_5a formed on the dummy pixel PXa_d51 and a test light shielding structure SS_5b formed on the dummy pixel PXa_d52.

[0078] When checking the test light shielding pattern formed on the first group of dummy pixels PXa_d11 to PXa_d51, the test light shielding structure SS_1a can be formed on the entire dummy pixel PXa_d11, and the test light shielding structures SS_2a to SS_5a can be formed to be spaced apart from the starting line L1 of the test light shielding structure SS_1a by distances Da, Db, Dc and Dd, respectively. In an example embodiment, the differences between the distances Da, Db, Dc and Dd may be the same or different from each other. Specifically, the difference between the distances Db and Da, the difference between the distances Dc and Db, and the difference between the distances Dd and Dc may be the same or different from each other. That is, the test light shielding pattern formed on the first group of dummy pixels PXa_d11 to PXa_d51 may have a downward stepped shape in the downward direction. In another example embodiment, the test light shielding pattern formed on the first group of dummy pixels PXa_d11 to PXa_d51 may include a test light shielding structure having an area different according to the first group of dummy pixels PXa_d11 to PXa_d51 .

[0079] When checking the test light shielding pattern formed on the second group of dummy pixels PXa_d12 to PXa_d52, the test light shielding structure SS_1b can be formed on the entire dummy pixel PXa_d12, and the test light shielding structures SS_2b to SS_5b can be formed to be spaced apart from the starting line L2 of the test light shielding structure SS_1b by distances Da, Db, Dc and Dd, respectively. In an example embodiment, the differences between the distances Da, Db, Dc and Dd may be the same or different from each other. Specifically, the difference between the distances Db and Da, the difference between the distances Dc and Db, and the difference between the distances Dd and Dc may be the same or different from each other. That is, the test light shielding pattern formed on the second group of dummy pixels PXa_d12 to PXa_d52 may have a downward stepped shape in the downward direction. In another example embodiment, the test light shielding pattern formed on the second group of dummy pixels PXa_d12 to PXa_d52 may include a test light shielding structure having different areas according to the second group of dummy pixels PXa_d12 to PXa_d52 .

[0080] In addition, the test light shielding pattern formed on the first group of dummy pixels PXa_d11 to PXa_d51 and the test light shielding pattern formed on the second group of dummy pixels PXa_d12 to PXa_d52 may be symmetrical to each other about a line L3 contacting the first group of dummy pixels PXa_d11 to PXa_d51 and the second group of dummy pixels PXa_d12 to PXa_d52.

[0081] However, Fig. 8AThe test light shielding pattern is exemplary, and the present inventive concept is not limited thereto. In some example embodiments, the test light shielding pattern may have any of various shapes according to the number of dummy pixels included in the first TEG TEG1. For example, the test light shielding pattern may have a shape formed by vertically inverting Fig. 8A Or the test light shielding pattern formed on the first group of dummy pixels PXa_d11 to PXa_d51 and the test light shielding pattern formed on the second group of dummy pixels PXa_d12 to PXa_d52 may be asymmetrical.

[0082] See also Figure 8B , the second TEG TEG2 can correspond to Fig. 6A The second TEG TEG2a or Figure 6B The second TEG TEG2b. The second TEG TEG2 may include a plurality of dummy pixels PXb_d11, PXb_d21, PXb_d31, PXb_d41, PXb_d51, PXb_d12, PXb_d22, PXb_d32, PXb_d42, and PXb_d52, and the plurality of dummy pixels PXb_d11 to PXb_d52 may be divided into a first group of dummy pixels and a second group of dummy pixels. However, Figure 8B The second TEG TEG2 is exemplary, and the inventive concept is not limited thereto. In some example embodiments, the second TEG TEG2 may include Figure 8B More or fewer dummy pixels are shown in .

[0083] In example embodiments, a first group of dummy pixels for detecting an upper misalignment between an active area and a light shielding pattern may include horizontally aligned dummy pixels PXb_d11, PXb_d21, PXb_d31, PXb_d41, and PXb_d51. In addition, a second group of dummy pixels for detecting a lower misalignment between an active area and a light shielding pattern may include dummy pixels PXb_d12, PXb_d22, PXb_d32, PXb_d42, and PXb_d52.

[0084] In an example embodiment, in the step of manufacturing the image sensor, a test light shielding pattern may be formed on the second TEG TEG2. The test light shielding pattern may include a first test pattern TP1' to a fifth test pattern TP5'. The first test pattern TP1' may include a test light shielding structure SS_1a' formed on a dummy pixel PXb_d11 and a test light shielding structure SS_1b' formed on a dummy pixel PXb_d12. The second test pattern TP2' may include a test light shielding structure SS_2a' formed on a dummy pixel PXb_d21 and a test light shielding structure SS_2b' formed on a dummy pixel PXb_d22. The third test pattern TP3' may include a test light shielding structure SS_3a' formed on a dummy pixel PXb_d31 and a test light shielding structure SS_3b' formed on a dummy pixel PXb_d32. The fourth test pattern TP4' may include a test light shielding structure SS_4a' formed on the dummy pixel PXb_d41 and a test light shielding structure SS_4b' formed on the dummy pixel PXb_d42. The fifth test pattern TP5' may include a test light shielding structure SS_5a' formed on the dummy pixel PXb_d51 and a test light shielding structure SS_5b' formed on the dummy pixel PXb_d52.

[0085] When checking the test light shielding pattern formed on the first group of dummy pixels PXb_d11 to PXb_d51, the test light shielding structure SS_1a' can be formed on the entire dummy pixel PXb_d11, and the test light shielding structures SS_2a' to SS_5a' can be formed to be spaced apart from the starting line L1' of the test light shielding structure SS_1a' by distances Da', Db', Dc' and Dd', respectively. In an example embodiment, the differences between the distances Da', Db', Dc' and Dd' may be the same or different from each other. Specifically, the difference between the distances Db' and Da', the difference between the distances Dc' and Db', and the difference between the distances Dd' and Dc' may be the same or different from each other. That is, the test light shielding pattern formed on the first group of dummy pixels PXb_d11 to PXb_d51 may have a downward stepped shape in the right direction.

[0086] When inspecting the test light shielding pattern formed on the second group of dummy pixels PXb_d12 to PXb_d52, the test light shielding structure SS_1b' may be formed on the entire dummy pixel PXb_d12, and the test light shielding structures SS_2b' to SS_5b' may be formed to be spaced apart from the starting line L2' of the test light shielding structure SS_1b' by distances Da', Db', Dc', and Dd', respectively. That is, the test light shielding pattern formed on the second group of dummy pixels PXb_d12 to PXb_d52 may have a downward stepped shape in the right direction.

[0087] In addition, the test light shielding pattern formed on the first group of dummy pixels PXb_d11 to PXb_d51 and the test light shielding pattern formed on the second group of dummy pixels PXb_d12 to PXb_d52 may be symmetrical to each other about a line L3 ′ contacting the first group of dummy pixels PXb_d11 to PXb_d51 and the second group of dummy pixels PXb_d12 to PXb_d52.

[0088] However, Figure 8B The test light shielding pattern is exemplary, and the present inventive concept is not limited thereto. In some example embodiments, the test light shielding pattern may have any of various shapes according to the number of dummy pixels included in the second TEG TEG2. For example, the test light shielding pattern may have a shape that is formed by horizontally inverting Figure 8B Or the test light shielding pattern formed on the first group of dummy pixels PXb_d11 to PXb_d51 and the test light shielding pattern formed on the second group of dummy pixels PXb_d12 to PXb_d52 may be asymmetrical.

[0089] See also Figure 8C ,and Fig. 8A Compared with the first TEG TEG1, the test light shielding patterns formed on the first group of dummy pixels PXa_d11 to PXa_d51 may be the same, while the test light shielding patterns formed on the second group of dummy pixels PXa_d12 to PXa_d52 may be different. Specifically, when inspecting the test light shielding patterns formed on Figure 8C When the test light shading pattern is formed on the second group of dummy pixels PXa_d12 to PXa_d52, the test light shading structure SS_5b" can be formed on the entire dummy pixel PXa_d52, and the test light shading structures SS_4b" to SS_1b" can be formed to be spaced apart from the starting line L2 of the test light shading structure SS_5b" by distances Da, Db, Dc and Dd, respectively. As a result, the test light shading pattern formed on the first TEG TEG1 may include first to fifth test patterns TP1 to TP5 having the same width.

[0090] Fig.9A is a flowchart of a method of manufacturing an image sensor chip package according to example embodiments. Fig. 9B and 9C It is used to illustrate Fig.9A FIG. 1 is a diagram of operations S120 and S130 of FIG.

[0091] Reference Fig.9AIn operation S100, a wafer having semiconductor chips formed thereon is provided, wherein each semiconductor chip includes at least one TEG having a plurality of dummy pixels. In operation S110, a light shielding pattern is formed on the active pixels of each semiconductor chip, and a test light shielding pattern according to an example embodiment is also formed on the TEG of each semiconductor chip. Next, in operation S120, whether the light shielding pattern of each semiconductor chip is aligned is tested based on a pixel signal generated from the TEG of each semiconductor chip.

[0092] In operation S110, Fig. 8A When the test light shielding pattern shown is formed on the first TEG TEG1 of a semiconductor chip, the test light shielding pattern may be misaligned with the first TEG TEG1, such as Fig. 9B Although the test light shielding pattern formed on the first TEGTEG1 is Fig. 9B In some example embodiments, the test light shielding pattern formed on the first TEG TEG1 may be moved rightward, upward, or downward.

[0093] With further reference to 9B, in operation S120, whether the active area of ​​the semiconductor chip is aligned with the light-shielding pattern may be tested based on the dummy pixel signal generated from the TEG TEG1. Specifically, whether the active area of ​​the semiconductor chip is aligned with the light-shielding pattern, and the degree of misalignment between the active area and the light-shielding pattern in the case of misalignment may be detected based on the dummy pixel signals PX11 to PX51 generated from the first group of dummy pixels PXa_d11 to PXa_d51, respectively. When light is detected, each dummy pixel signal may have a "1" or a logic high value, and when light is not detected, each dummy pixel signal may have a "0" or a logic low value. For example, it can be found that when the dummy pixel signals PX11 to PX51 sequentially have '00111' due to the misalignment of the test light-shielding pattern, the entire dummy pixel PXa_d21 is covered by the test light-shielding structure SS_2a. That is, despite the Fig. 8A As shown, the test light shielding structure SS_2a should be spaced apart from the line L1 by a distance Da, but the test light shielding structure SS_2a is actually as Fig. 9B As shown, the test light shielding structure is shifted to the left by any distance between the distance "Da" and the distance "Db". Since the misalignment trend of the test light shielding pattern is the same or similar to the misalignment trend of the light shielding pattern, the misalignment degree of the light shielding pattern can be obtained by using the misalignment degree of the test light shielding pattern.

[0094] Fig. 9CThe table shows the degree of misalignment between the light shielding pattern and the active area (or between the test light shielding pattern and the TEG) of the semiconductor chip corresponding to each dummy pixel signal value. In operation S120, the degree of misalignment according to the dummy pixel signal value can be detected by referring to the table. In addition, in operation S120, when the degree of misalignment is equal to or greater than the threshold value, it can be determined that the active area of ​​the semiconductor chip and the light shielding pattern are not aligned with each other. For example, when the threshold is a distance Da and the degree of misalignment is equal to or greater than the distance Da, it can be determined that the active area of ​​the semiconductor chip and the light shielding pattern are not aligned with each other.

[0095] Return to reference Fig.9A In operation S130, it may be determined whether to reform the light shielding pattern according to each semiconductor chip based on the test result. When it is determined in operation S130 that the light shielding pattern is to be reformed, the method may return to operation S110, in which the light shielding pattern for the semiconductor chip is reformed by adjusting the light shielding pattern formation parameters (e.g., the position of the light shielding pattern) based on the misalignment degree of the light shielding pattern detected according to each semiconductor chip (or the misalignment degree of the test light shielding pattern). When it is determined in operation S130 that the light shielding pattern is not to be reformed, the method may proceed to operation S140. In operation S140, the remaining processes may be performed on the semiconductor chip, and the semiconductor chip may be separated. Next, in operation S150, an image sensor chip package may be produced by packaging each of the separated semiconductor chips.

[0096] Figures 10A to 10C 2 is a diagram for explaining various test light-shielding patterns according to example embodiments.

[0097] Reference Fig. 10A , a test light shielding structure may be omitted (ie, not formed) on a region corresponding to at least one dummy pixel included in the TEG TEGa according to example embodiments. Fig. 8A Compared with the first TEG TEG1, the TEG TEGa may further include dummy pixels PXc_d11, PXc_d21, PXc_d31, PXc_d41, PXc_d12, PXc_d22, PXc_d32, and PXc_d42 on which the test light shielding structure is not formed.

[0098] Reference Fig. 10B , the test light shielding structure may be formed on the entire area corresponding to at least one dummy pixel included in the TEG TEGb according to the example embodiment. Fig. 8AWhen compared with the first TEG TEG1, TEGTEGb may further include dummy pixels PXc_d1, PXc_d2, PXc_d3, PXc_d4, and PXc_d5 on which a test light shielding structure is integrally formed.

[0099] Reference Fig. 10C , the test light shielding structure may be formed on the entire area corresponding to at least one dummy pixel included in the TEG TEGc according to the example embodiment. Figure 8C Compared with the first TEG TEG1, TEGTEGc may further include dummy pixels PXc_d1 to PXc_d5 on which a test light shielding structure is integrally formed.

[0100] Figures 10A to 10C In some example embodiments, a test light shielding pattern having any of various shapes may be configured to quickly and accurately detect a degree of misalignment between an active region and a light shielding pattern.

[0101] Fig.11A and Fig. 11B is a diagram for explaining steps of forming and reforming a light shielding pattern during a process of manufacturing an image sensor chip package according to example embodiments.

[0102] See also Fig.9A and 11A , a plurality of semiconductor chips CH may be arranged on one surface of the wafer WF in a 2D manner, and operation S110 may be performed on any one of the first chipset unit CH_Ga, the second chipset unit CH_Gb, and the third chipset unit CH_Gc. For example, operation S110 may be performed on the first semiconductor chip and the second semiconductor chip included in the first chipset unit CH_Ga based on the same light shielding pattern formation parameters.

[0103] Operations S120 and S130 may be performed on any one of the first chipset unit CH_Ga, the second chipset unit CH_Gb, and the third chipset unit CH_Gc. For example, the first chipset unit CH_Ga may be tested for alignment of the light shielding pattern by using a dummy pixel signal of a TEG formed on each of the first semiconductor chip and the second semiconductor chip included in the first chipset unit CH_Ga, and it may be determined whether to reform the light shielding pattern based on the test result. In addition, the step of reforming the light shielding pattern may be performed by using a dummy pixel signal of a TEG formed on each of the first semiconductor chip and the second semiconductor chip. However, Fig.11AThe first chipset unit CH_Ga, the second chipset unit CH_Gb, and the third chipset unit CH_Gc are exemplary, and the inventive concept is not limited thereto, and operations S110 to S130 may be performed on more kinds of chipset units.

[0104] See also Fig. 11B , the semiconductor chip CH arranged on one surface of the wafer WF may be divided into an external semiconductor chip CH_ex located outside and an internal semiconductor chip CH_in located inside. When operations S110 to S130 are performed on the external semiconductor chip CH_ex according to the example embodiment, operations S110 to S130 may be performed according to each semiconductor chip unit CH_G1; when operations S110 to S130 are performed on the internal semiconductor chip CH_in, operations S110 to S130 may be performed according to each chipset unit CH_G2 including a predetermined number of semiconductor chips.

[0105] Fig.12 is a block diagram of a system 1000 including an image sensor 1300 according to example embodiments.

[0106] See also Fig.12 , system 1000 may be any of a computing system, camera system, scanner, vehicle navigation system, video phone, security system, and motion detection system requiring image data.

[0107] Reference Fig.12 , the system 1000 may include a central processing unit (CPU) (or processor) 1100, a nonvolatile memory 1200, an image sensor 1300, an input-output device 1400, and a random access memory (RAM) 1500. The CPU 1100 may communicate with the nonvolatile memory 1200, the image sensor 1300, the input-output device 1400, and the RAM 1500 via a bus 1600. The image sensor 1300 may be implemented as an independent semiconductor chip, or may be implemented as one semiconductor chip by being combined with the CPU 1100. The image sensor 1300 may be implemented as a semiconductor chip. Figures 1 to 11B This is implemented in accordance with an exemplary embodiment of the present invention.

[0108] The CPU 1100 may control the system 1000 and may transmit / receive data to / from other elements through the bus 1600. For example, the CPU 1100 may receive data generated by the image sensor 1300 according to an example embodiment. The nonvolatile memory 1200 that keeps storing data even when the power is turned off may store data generated by the image sensor 1300 or data obtained after processing the generated data. The RAM 1500 may be used as a data storage of the CPU 1100 and may be a volatile memory device. The input-output device 1400 may receive a command from a user or may output video and / or audio to the user.

[0109] Fig.13 is a block diagram illustrating an electronic system 2000 including an image sensor 2040 and an interface according to example embodiments.

[0110] Reference Fig.13 , the electronic system 2000 may be a data processing device that can use or support the MIPI interface, such as a mobile phone, a personal digital assistant (PDA), a personal media player (PMP), or a smart phone. The electronic system 2000 may include an application processor 2010, an image sensor 2040, and a display 2050. The image sensor 2040 may be configured according to Figures 1 to 11B This is implemented in accordance with an exemplary embodiment of the present invention.

[0111] A camera serial interface (CSI) host 2012 in the application processor 2010 may sequentially communicate with a CSI device 2041 of the image sensor 2040 through the CSI. In this case, an optical deserializer may be implemented in the CSI host 2012, and an optical serializer may be implemented in the CSI device 2041.

[0112] A display serial interface (DSI) host 2011 in the application processor 2010 may sequentially communicate with a DSI device 2051 of the display 2050 through DSI. In this case, for example, an optical serializer may be implemented in the DSI host 2011, and an optical deserializer may be implemented in the DSI device 2051.

[0113] The electronic system 2000 may further include a radio frequency (RF) chip 2060 that may communicate with the application processor 2010. The PHY (physical layer protocol) interface 2013 of the electronic system 2000 and the PHY interface 2061 of the RF chip 2060 may transmit / receive data according to MIP IgRF. The electronic system 2000 may further include a global positioning system (GPS) 2020, a memory 2070, a microphone 2080, a dynamic random access memory (DRAM) 2085, and a speaker 2090, and may communicate by using a worldwide interoperability for microwave access (WiMAX) 2030, a wireless local area network (WLAN) 2100, and an ultra-wideband (UWB) 2110.

[0114] The image sensor and stacked image sensor according to one or more example embodiments may be implemented in any of a variety of packages. For example, at least some elements of the integrated circuit may be mounted by using a package such as a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic lead chip carrier (PLCC), a plastic dual in-line package (PDIP), a waffle package die, a wafer form die, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic encapsulated quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a reduced outline package (SSOP), a thin small outline package (TSOP), a thin quad flat package (TQFP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0115] Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, it should be understood that various changes can be made in form and detail without departing from the spirit and scope of the appended claims. Therefore, the true technical scope of the present invention is defined by the technical spirit of the appended claims.

Claims

1. An image sensor, comprising: A pixel array, comprising an active area and a dummy area, wherein a plurality of active pixels are located in the active area and a plurality of dummy pixels are located in the dummy area; as well as at least one test element group located in the dummy area, and a test light shielding pattern different from the light shielding pattern formed on the active area is formed on the at least one test element group, Wherein, the at least one test element group is adjacent to at least one of the left and right sides of the active area, and the at least one test element group includes a plurality of first groups of dummy pixels among the plurality of dummy pixels, wherein a first test shading pattern having a stepped shape in an upward direction or a downward direction of the at least one test element group is formed on the plurality of first groups of dummy pixels.

2. The image sensor according to claim 1, wherein: The plurality of first groups of dummy pixels include first dummy pixels, second dummy pixels, and third dummy pixels adjacent to an upper side or a lower side of the at least one test element group, The first test light shielding pattern includes a first test light shielding structure formed on the first dummy pixel, a second test light shielding structure formed on the second dummy pixel, and a third test light shielding structure formed on the third dummy pixel. Wherein, the second test light shading structure is spaced apart from a first starting line of the first test light shading structure by a first distance in the left direction or the right direction of the at least one test element group, and the third test light shading structure is spaced apart from a second starting line of the second test light shading structure by a second distance in the left direction or the right direction of the at least one test element group.

3. The image sensor according to claim 2, wherein: The first distance and the second distance are the same as or different from each other.

4. The image sensor according to claim 1, wherein: The at least one test element group further includes a plurality of second groups of dummy pixels among the plurality of dummy pixels, the plurality of second groups of dummy pixels being adjacent to the plurality of first groups of dummy pixels in a left direction or a right direction of the at least one test element group, A second test light shielding pattern is formed on the plurality of second group dummy pixels, and the second test light shielding pattern is symmetrical to the first test light shielding pattern about a line contacting the plurality of first group dummy pixels.

5. The image sensor according to claim 1, wherein: The at least one test element group includes a first test element group and a second test element group, and The first test element group is adjacent to at least one of a left side and a right side of the active region, and the second test element group is adjacent to at least one of an upper side and a lower side of the active region.

6. The image sensor according to claim 5, wherein: The first test element group and the second test element group are adjacent to each other.

7. The image sensor according to claim 5, wherein: A first number of dummy pixels included in the first test element group and a second number of dummy pixels included in the second test element group are the same as or different from each other.

8. The image sensor according to claim 1, wherein: The test light shielding pattern is not formed on a region corresponding to at least one dummy pixel included in the at least one test element group.

9. The image sensor according to claim 1, wherein: The test light shielding pattern is formed on an entire region corresponding to at least one dummy pixel included in the at least one test element group.

10. An image sensor, comprising: A pixel array, comprising an active area and a dummy area, wherein a plurality of active pixels are located in the active area and a plurality of dummy pixels are located in the dummy area; as well as at least one test element group located in the dummy area, and a test light shielding pattern different from the light shielding pattern formed on the active area is formed on the at least one test element group, wherein the at least one test element group is adjacent to at least one of the upper side and the lower side of the active area, The at least one test element group includes a plurality of groups of dummy pixels among the plurality of dummy pixels. The test light shielding pattern has a step shape in a left direction or a right direction of the at least one test element group and is formed on the plurality of groups of dummy pixels.

11. An imaging device, comprising: An image sensor comprising a pixel array, the pixel array comprising at least one test element group on which a test light shielding pattern different from a light shielding pattern formed on a plurality of active pixels is formed, and an image signal processor configured to receive a plurality of accumulated charges from a plurality of photodiodes of the plurality of active pixels and perform image processing on the plurality of accumulated charges, Wherein, the at least one test element group is adjacent to at least one of the left and right sides of the active area of ​​the pixel array, and the at least one test element group includes a plurality of first groups of dummy pixels among a plurality of dummy pixels, wherein a first test shading pattern having a stepped shape in an upward direction or a downward direction of the at least one test element group is formed on the plurality of first groups of dummy pixels.

12. The imaging device according to claim 11, wherein: The at least one test element group includes a plurality of groups of dummy pixels, The test light-shielding pattern includes a plurality of test light-shielding structures, and the areas of the plurality of test light-shielding structures are different according to the plurality of groups of dummy pixels.

13. The imaging device according to claim 11, wherein: The image signal processor is further configured to receive a plurality of pixel signals from the at least one test element group, detect a plurality of states of the plurality of active pixels based on the plurality of pixel signals, and perform image processing based on the detected plurality of states.

14. A method for manufacturing an image sensor chip package, the method comprising: providing a wafer having a plurality of semiconductor chips formed thereon, wherein each semiconductor chip includes at least one test element group having a plurality of dummy pixels; forming a light shielding pattern on a plurality of active pixels of each of the plurality of semiconductor chips, and forming a test light shielding pattern on the at least one test element group of each of the plurality of semiconductor chips; testing whether the light shielding pattern of each semiconductor chip is aligned based on a plurality of pixel signals generated from the at least one test element group of each semiconductor chip of the plurality of semiconductor chips; For any semiconductor chip among the plurality of semiconductor chips whose light shielding pattern is not aligned, reforming the light shielding pattern of the semiconductor chip according to the test result; providing individual image sensor chips by separating the plurality of semiconductor chips from the wafer; as well as packaging the individual image sensor chips, Wherein, the at least one test element group is adjacent to at least one of the left and right sides of the active area in which the multiple active pixels are formed, and the at least one test element group includes a first plurality of dummy pixels among the multiple dummy pixels, wherein a first test shading pattern having a stepped shape in an upward direction or a downward direction of the at least one test element group is formed on the first plurality of dummy pixels.

15. The method according to claim 14, wherein: The at least one test element group includes a plurality of first dummy pixels and a plurality of second dummy pixels, wherein the plurality of first dummy pixels are used to detect a first misalignment degree of the light shielding pattern relative to the first side, and the plurality of second dummy pixels are used to detect a second misalignment degree of the light shielding pattern relative to the second side, The test light-shielding pattern includes a plurality of first test light-shielding structures and a plurality of second test light-shielding structures, the areas of the plurality of first test light-shielding structures are different according to the plurality of first groups of dummy pixels, and the areas of the plurality of second test light-shielding structures are different according to the plurality of second groups of dummy pixels.

16. The method according to claim 14, wherein: Testing whether the light shielding pattern is aligned includes detecting a misalignment degree of the light shielding pattern of each of the plurality of semiconductor chips based on a plurality of pixel signals generated from the at least one test element group of each of the plurality of semiconductor chips.

17. The method according to claim 16, wherein: The light shielding patterns are reformed by adjusting positions of the light shielding patterns of the plurality of semiconductor chips based on the degree of misalignment.

Images