Internal copy for handling NAND program failures

Abstract

An embodiment of a semiconductor packaging device may include techniques for: attempting to program data in a first portion of a non-volatile memory; determining whether the attempt was successful; and if the attempt was determined to be unsuccessful, restoring the data to a second portion of the non-volatile memory using an internal data move operation. Other embodiments are disclosed and claimed.

Description

Technical Field

[0001] In general, embodiments relate to memory systems and, more particularly, to internal copy for handling NAND program failures. Background Art

[0002] Multi-level non-volatile memory stores more than one bit per cell. Multi-level NAND memory with four (4) possible voltage levels per cell can represent two (2) bits of data per cell. NAND memory with eight (8) voltage levels per cell can be referred to as triple-level cell (TLC) memory and can represent three (3) bits of data per cell. NAND memory with sixteen (16) voltage levels per cell can be referred to as quad-level cell (QLC) memory and can represent four (4) bits of data per cell. With some NAND flash devices, erasing a block can set all bit values to 1. Programming can refer to the process of changing a bit from a bit value of 1 to a bit value of 0. Various techniques such as error correction coding (ECC) and exclusive-OR (XOR) parity can be used to correct various memory errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art upon reading the following description and appended claims, and by referring to the following drawings, in which:

[0004] Figure 1 is a block diagram of an example of an electronic processing system according to an embodiment;

[0005] Figure 2 is a block diagram of an example of a semiconductor packaging device according to an embodiment;

[0006] Figures 3A to 3C is a flowchart of an example of a method of restoring data according to an embodiment;

[0007] Figure 4 is a block diagram of an example of a memory controller according to an embodiment;

[0008] Figure 5 is a flowchart of another example of a method for restoring data according to an embodiment;

[0009] Figure 6 is an illustrative diagram of examples of various command queues according to an embodiment; and

[0010] Figure 7 is an explanatory diagram of an example of data movement according to an embodiment. DETAILED DESCRIPTION

[0011] Various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or non-volatile memory. Non-volatile memory may be a storage medium that does not require power to maintain the state of the data stored by the medium. In one embodiment, the memory device may include a block-addressable memory device, such as a memory device based on NAND or NOR technology. The memory device may also include future generation non-volatile devices, such as a three-dimensional cross-point memory device or other byte-addressable write-in-place non-volatile memory device. In one embodiment, the memory device may be or may include: a memory device using chalcogenide glass, multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) memory incorporating memristor technology, resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), or spin transfer torque (STT)-MRAM, a device based on spintronic magnetic junction memory, a device based on magnetic tunneling junction (MTJ), a device based on DW (domain wall) and SOT (spin-orbit transfer), a thyristor-based memory device, or any of the above memories or other combinations thereof. The memory device may refer to the die itself and / or a packaged memory product. In particular embodiments, memory components having non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standards (JEDEC standards referenced herein are available at jedec.org).

[0012] Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of RAM, such as dynamic random access memory (DRAM) or static random access memory (SRAM). One specific type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In a particular embodiment, the DRAM of the memory component may comply with standards published by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards, and the communication interfaces of storage devices that implement such standards may be referred to as DDR-based interfaces.

[0013] Now go to Figure 1An embodiment of an electronic processing system 10 may include a processor 11, a non-volatile memory 12 communicatively coupled to the processor 11, and logic 13 communicatively coupled to the processor 11 and the non-volatile memory 12, the logic 13 configured to: attempt to program data in a first portion of the non-volatile memory 12; determine whether the attempt was successful; and if the attempt was determined to be unsuccessful, restore the data to a second portion of the non-volatile memory 12 using an internal data move operation. In some embodiments, the logic 13 may be configured to store the data in a cache of the non-volatile memory 12 before the attempt, and if the attempt was determined to be unsuccessful, restore the data from the cache of the non-volatile memory 12 to the second portion of the non-volatile memory 12 using an internal data move operation. For example, the logic 13 may also be configured to determine whether the data stored in the cache of the non-volatile memory is valid before restoring the data. In some embodiments, logic 13 may also be configured to utilize an internal data move operation to move data from a cache in non-volatile memory 12 to a temporary location in non-volatile memory 12, and to utilize an internal data move operation to restore data from the temporary location in non-volatile memory 12 to a second portion of non-volatile memory 12. In some embodiments, logic 13 may also be configured to utilize an internal data move operation to move previously programmed data from the first portion of non-volatile memory 12 to the second portion of non-volatile memory 12 if the attempt is determined to be unsuccessful. For example, non-volatile memory 12 may include NAND memory. In some embodiments, logic 13 may be located in various components including processor 11 or co-located with various components including processor 11 (e.g., on the same die).

[0014] The embodiments of each of the above processor 11, non-volatile memory 12, logic 13, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, a hardware implementation may include configurable logic, such as, for example, a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or fixed-functionality logic hardware using circuit technology such as, for example, an application-specific integrated circuit (ASIC), a complementary metal oxide semiconductor (CMOS), or a transistor-transistor logic (TTL) technology, or any combination thereof.

[0015] Alternatively or additionally, all or part of these components may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium, such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., for execution by a processor or computing device. For example, computer program code for performing the operations of these components may be written in any combination of programming languages suitable for one or more operating systems (OSs), including object-oriented programming languages such as Python, Perl, Java, SmallTalk, C++, C#, and conventional procedural programming languages such as the "C" programming language or similar programming languages. For example, non-volatile memory 12, a permanent storage medium, or other system memory may store a set of instructions that, when executed by processor 11, causes system 10 to implement one or more components, features, or aspects of system 10 (e.g., logic 13 attempts to program data in a first portion of non-volatile memory, determines whether the attempt was successful, and if the attempt is determined to be unsuccessful, utilizes internal data movement operations to restore the data to a second portion of non-volatile memory, etc.).

[0016] Now go to Figure 2 , an embodiment of the semiconductor package device 20 may include one or more substrates 21 and logic 22 coupled to the one or more substrates 21, wherein the logic 22 is at least partially implemented in one or more of configurable logic and fixed-functionality hardware logic. The logic 22 coupled to the one or more substrates may be configured to attempt to program data in a first portion of a non-volatile memory, determine whether the attempt was successful, and if it is determined that the attempt was unsuccessful, then restore the data to a second portion of the non-volatile memory using an internal data move operation. In some embodiments, the logic 22 may be configured to store the data in a cache of the non-volatile memory before the attempt, and if it is determined that the attempt was unsuccessful, then restore the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using an internal data move operation. For example, the logic 22 may also be configured to determine whether the data stored in the cache of the non-volatile memory is valid before restoring the data. In some embodiments, the logic 22 may further be configured to utilize an internal data move operation to move data from a cache in the non-volatile memory to a temporary location in the non-volatile memory, and to utilize an internal data move operation to restore the data from the temporary location in the non-volatile memory to the second portion of the non-volatile memory. In some embodiments, the logic 22 may further be configured to utilize an internal data move operation to move previously programmed data from the first portion of the non-volatile memory to the second portion of the non-volatile memory if the attempt is determined to be unsuccessful. For example, the non-volatile memory may include NAND memory.

[0017] Embodiments of the logic 22 and other components of the device 20 may be implemented using hardware, software, or any combination thereof, including at least partial implementations using hardware. For example, a hardware implementation may include configurable logic, such as, for example, a PLA, FPGA, or CPLD, or fixed-function logic hardware utilizing circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Additionally, portions of these components may be implemented in one or more modules as a collection of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, or the like for execution by a processor or computing device. For example, the computer program code for performing the operations of these components may be written in any combination of one or more OS-appropriate / suitable programming languages, including object-oriented programming languages such as Python, Perl, Java, SmallTalk, C++, C#, and conventional procedural programming languages such as the "C" programming language or similar programming languages.

[0018] Now go to Figures 3A to 3C , an embodiment of a method 30 for recovering data may include: at block 31, attempting to program data in a first portion of non-volatile memory; at block 32, determining whether the attempt was successful; and at block 33, if the attempt was determined to be unsuccessful, recovering the data to a second portion of non-volatile memory using an internal data move operation. Some embodiments of method 30 may include: at block 34, before the attempt, storing the data in a cache of the non-volatile memory; and at block 35, if the attempt was determined to be unsuccessful, recovering the data from the cache of the non-volatile memory to the second portion of non-volatile memory using an internal data move operation. For example, method 30 may also include: at block 36, before recovering the data, determining whether the data stored in the cache of the non-volatile memory is valid. Some embodiments of method 30 may further include, at block 37, moving the data from the cache of the nonvolatile memory to a temporary location in the nonvolatile memory using an internal data move operation; and, at block 38, restoring the data from the temporary location in the nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation. Some embodiments of method 30 may further include, at block 39, if it is determined that the attempt was unsuccessful, moving the previously programmed data from the first portion of the nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation. For example, at block 40, the nonvolatile memory may include NAND memory.

[0019] Embodiments of method 30 may be implemented in, for example, systems, devices, computers, and apparatuses such as those described herein. More particularly, a hardware implementation of method 30 may include configurable logic, such as, for example, PLA, FPGA, CPLD, or fixed-functionality logic hardware utilizing circuit technology such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively or additionally, method 30 may be implemented in one or more modules as a collection of logic instructions stored in a machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. for execution by a processor or computing device. For example, computer program code for performing the operations of these components may be written in any combination of one or more OS-appropriate / suitable programming languages (including object-oriented programming languages such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, and conventional procedural programming languages such as "C" or similar programming languages).

[0020] For example, method 30 may be implemented on a computer-readable medium as described in connection with the following Examples 19 to 24. Embodiments or portions of method 30 may be implemented in firmware, an application (e.g., via an application programming interface (API)), or driver software running on an operating system (OS).

[0021] Now go to Figure 4, an embodiment of the memory controller 42 may include a NAND programmer 43 and a program fault handler 44. The NAND programmer 43 may include technology for programming data in a first block of NAND memory. The program fault handler 44 may include technology for performing the following operations: determining whether programming of the first block has failed; and if programming of the first block has failed, recovering the data to a second block of the NAND memory using internal data move commands. In some embodiments, the NAND programmer 43 may be configured to store the data in a cache of the NAND memory before attempting to program the first block, and if programming of the first block has failed, the program fault handler 44 may recover the data from the cache of the NAND memory to the second block of the NAND memory using internal data move commands. For example, the program fault handler 44 may also be configured to determine whether the data stored in the cache of the NAND memory is valid before recovering the data. In some embodiments, the program failure handler 44 may be further configured to use an internal data move command to move data from a cache memory of the NAND memory to a single-level cell (SLC) block of the NAND memory, and to use an internal data move command to restore data from the SLC block to a second block of the NAND memory. In some embodiments, the program failure handler 44 may be further configured to use an internal data move command to move previously programmed data from a first block of the NAND memory to a second block of the NAND memory if programming of the first block fails.

[0022] Embodiments of the NAND programmer 43, program fault handler 44, and other components of the memory controller 42 may be implemented in hardware, software, or any combination thereof (including at least partial hardware implementations). For example, a hardware implementation may include configurable logic, such as, for example, a PLA, FPGA, or CPLD, or fixed-function logic hardware utilizing circuit technology, such as, for example, ASIC, CMOS, or TTL technology, or any combination thereof. Additionally, portions of these components may be implemented in one or more modules as a collection of logic instructions stored in a machine- or computer-readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, or the like, for execution by a processor or computing device. For example, the computer program code for performing the operations of these components may be written in any combination of one or more OS-appropriate / suitable programming languages, including object-oriented programming languages such as Python, Perl, Java, SmallTalk, C++, C#, and conventional procedural programming languages such as the "C" programming language or similar programming languages.

[0023] Some embodiments may advantageously provide program failure handling for DRAM-less and / or fire-and-forget systems. After writing data to the SSD write buffer (e.g., the DRAM or SRAM memory components within the SSD), some high-performance SSDs may return a completion status to the host. Waiting for the SSD's NAND to return to a pass-through program status can slow SSD write performance. Firmware can handle NAND program failures to recover user data with little or no impact on SSD write performance. For example, after a program failure, the firmware may reprogram the data to another NAND block. To achieve high or maximum write performance, some SSDs may implement what may be referred to as a so-called fire-and-forget strategy. For example, a fire-and-forget implementation may remove data from the SSD write buffer after writing it to the NAND buffer. With a fire-and-forget implementation, the firmware cannot retrieve the data from the SSD write buffer for reprogramming to another NAND block (e.g., in the event of a NAND program failure). Some SSDs may not have DRAM or SRAM components to store data to handle NAND program failures, or some SSDs may not have sufficient additional DRAM or SRAM capacity to handle NAND program failures. Some SSDs can utilize XOR technology to recover data after a NAND program failure. However, not all program failures can be recovered using XOR technology (e.g., and not all SSDs have such XOR support).

[0024] Some embodiments may advantageously provide an efficient technique for recovering from some NAND program failures through internal NAND data movement. In some embodiments, no SRAM / DRAM buffer sharing may be involved in data recovery. Some embodiments may be scalable and extendable for SLC, multi-level cell, triple-level cell (TLC), and / or quad-level cell (QLC) NAND program failures. In some embodiments, system implementations may include firmware techniques for moving the failed page data and all previously programmed data from the failed block to a new block through internal NAND copying. Some embodiments may provide a comprehensive technique for recovering from program failures that supports most or all failure types, including, for example, single-die group failures (4K), multi-die group or single-plane failures (16K), and / or multi-plane failures (e.g., x2, x3, x4). Some embodiments may be compatible with fire-and-forget implementations, where the system may release data from faster volatile caches once the data is committed to the NAND. Some embodiments may also provide a faster technique for recovering data and completing the recovery process and may not involve SRAM / DRAM resource sharing during program failure handling.

[0025] An example NAND device architectural layout may include one or more cache registers, one or more data registers, and an associated NAND array. For example, the NAND array may be logically or physically arranged into one or more planes. Each plane of the NAND array may also be logically or physically arranged into one or more blocks. In some embodiments, when data to be programmed is sent to a NAND memory, the data may first be staged in a cache register. From the cache register, the data may be moved to the NAND array. When a program failure occurs, the failure generally refers to a NAND array write failure. In some cases, unless new data is written to the cache register, a copy of the data may still be available in the cache register. For example, for a non-cached program command, the data in the cache register may not be overwritten until the next program command is issued. According to some embodiments, the NAND controller may detect a program state failure before issuing the next program command and may recover the data by reading the data from the cache register. For example, internal "copy back read" and "copy back program" commands may allow the NAND controller to read data from the array into the cache register and / or move data from the cache register to the NAND array. Some embodiments may advantageously leverage NAND architecture and internal data movement commands to provide recovery from some NAND program failures (eg, and may be applicable to most or all NAND types including TLC and QLC).

[0026] Now go to Figure 5 An embodiment of a method 50 for recovering data may include processing a command queue at block 51. For example, a NAND controller may maintain a hardware (HW) command queue, and NAND commands from the HW queue may be executed in a first-in, first-out (FIFO) order. When a NAND program command is in the HW queue, method 50 may be followed by a determination of whether a program failure occurred at block 52 following the NAND program command. For example, the NAND controller may read status information to check for program completion. If the program succeeded at block 52, method 50 may continue processing the command queue at block 51. If a program failure occurred at block 52, method 50 may then determine whether the data stored in the cache is still valid at block 53. The program data may be retained in a cache register within the NAND die until the data is overwritten by the next program command. For example, the NAND controller may check a status bit indicating whether the controller is ready to accept new commands (e.g., which may correspond to potential overwrites of cached data). If the cached data is invalid at block 53, the data may be recovered using any suitable external recovery process at block 54. If it is determined at block 54 that the cache data is valid, then recovery of the failed page from within the NAND device may proceed.

[0027] Method 50 may pause the HW command queue at block 55 and copy data from the cache to the SLC block at block 56. For example, some embodiments may utilize a "Copy Back to Program" command (e.g., command codes 85-10h) to write cache register data to the SLC block (e.g., which may be specifically reserved for program failure handling). Then, at block 57, method 50 may populate the auxiliary (AUX) command queue with a suitable sequence of page recovery commands to copy data from the failed block to the new destination block. For example, the recovery command sequence may include internal data move commands for copying valid pages from the failed block up to the failed page to the new destination block. Firmware (FW) may populate the AUX queue commands. For example, in some embodiments, the AUX queue may be populated with suitable "Copy Back Read" commands (e.g., command codes 00-35h) and "Copy Back to Program" commands (e.g., command codes 00-85h) from page 0 to the last valid page (e.g., n-1, where n corresponds to the failed page). A read can be performed from the failed block, and the program can go to the new destination block.

[0028] Then, at block 58, method 50 may add the appropriate command to the AUX queue to copy the data from the SLC block to the new destination block. For example, for the originally failed page data, some embodiments may utilize a "copy read back" command to retrieve the data from the SLC block that retains the failed page data, and a "copy back program" command that points to the new destination block. Then, method 50 may process the AUX command queue at block 59, set the HW command queue restart position at block 60, and continue processing the HW command queue at block 51 (e.g., after recovery is complete, the NAND command queue will restart). For example, after the copy back process is complete, the FW may track the last command successfully executed by the HW command queue and restart from the next command.

[0029] Now go to Figure 6 An illustrative embodiment of command queue management for recovering from program failures may include a FW command queue 61 (e.g., across the die), a HW command queue 62 (e.g., across the die), and an AUX command queue 63 (e.g., across the die). The FW command queue 61 may include an example command sequence including the following program commands: a program command for Page A (e.g., command code 80-10h), followed by a read status command for Page A (e.g., command code 70h), followed by a program command for Page B, followed by a read status command for Page B, followed by a program command for Page C, followed by a read status command for Page C, and so on. The FW command queue 61 may cause a similar command sequence to be populated in the HW command queue 62.

[0030] The program command for Page A may complete successfully, causing the Read Status command for Page A to indicate successful completion. The program command for Page B may fail, causing the Read Status command to indicate a program failure. The HW queue may be paused, and the AUX command queue 63 may be filled with a command sequence for recovering the page data. The recovery command sequence may include: a Copy Back Program command (e.g., command code 00-85h) for moving Page B data to the SLC block, followed by a Read Status command for Page B, followed by a Copy Read Back command (e.g., command code 00-35h) for reading Page A data, followed by a Copy Back Program command for moving Page A data to a new destination block, followed by a Read Status command for Page A, followed by a Copy Read Back command for reading Page B data from the SLC block, followed by a Copy Back Program command for moving Page B data to the destination block, followed by a Read Status command for Page B data. After the AUX command queue 63 is completed, the HW command queue 62 may be restarted with the next command for programming Page C. Some embodiments may advantageously provide system management of the AUX command queue 63 to facilitate recovery from program failures.

[0031] Now go to Figure 7 , an illustrative data movement embodiment for data recovery may include an SLC block usage model. For example, an SLC block may be utilized as a temporary block primarily for program failure recovery. The SLC block reserved for program failure recovery may be any block from the SLC pool. Portion 71 of the NAND memory may include blocks 0 to 11 having corresponding block types. For example, blocks 0 to 5 may be SLC blocks, while blocks 6 to 11 may be TLC or QLC blocks. Block 4 may be reserved as a temporary block for program failure recovery. In an illustrative operational example, an attempt to program block 8 may fail. In some embodiments, the NAND controller may determine that the attempt was unsuccessful and internally move the failed page data to the temporary SLC block 4, as indicated by arrow 72. The NAND controller may then internally copy the block 8 pages from zero (0) to the failed page -1 to the new destination block 11 (e.g., copying valid pages from the failed block up to the failed page), as indicated by arrow 73. The NAND controller may then internally move the failed page data from the temporary SLC block 4 to the destination block 11 , as indicated by arrow 74 .

[0032] In some embodiments, internal block copies may present some ECC risk. For example, there may be some risk in moving data internally within a NAND block because the data is not read out through the ECC engine. In some embodiments, ECC risk can be mitigated through stricter raw bit error rate (RBER) masking at the NAND components. Because SLC utilizes a single-stage arrangement, programming of failed page data can be performed by applying a single pulse to a selected write line without a verify step. This type of SLC programming can be very fast (e.g., executing in 250 μs or less) and advantageously may not require external error correction. In some embodiments, the size of the available SLC memory reserved for program failure recovery can be preconfigured or dynamically configured.

[0033] Additional notes and examples:

[0034] Example 1 may include an electronic processing system comprising: a processor; a nonvolatile memory communicatively coupled to the processor; and logic communicatively coupled to the processor and the nonvolatile memory, the logic to: attempt to program data in a first portion of the nonvolatile memory; determine whether the attempt was successful; and if it is determined that the attempt was unsuccessful, restore the data to a second portion of the nonvolatile memory using an internal data move operation.

[0035] Example 2 may include the system of Example 1, wherein the logic is further configured to: store the data in a cache of the non-volatile memory prior to the attempt; and if the attempt is determined to be unsuccessful, restore the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0036] Example 3 may include the system of Example 2, wherein the logic is further configured to: determine whether the data stored in the cache of the non-volatile memory is valid prior to the restoring of the data.

[0037] Example 4 may include the system of Example 3, wherein the logic is further configured to: move the data from the cache of the non-volatile memory to a temporary location in the non-volatile memory using the internal data move operation; and restore the data from the temporary location in the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0038] Example 5 may include the system of Example 4, wherein the logic is further configured to: if it is determined that the attempt was unsuccessful, move the previously programmed data from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0039] Example 6 may include the system of any of Examples 1 to 5, wherein the non-volatile memory comprises NAND memory.

[0040] Example 7 may include a semiconductor packaging device comprising: one or more substrates; and logic coupled to the one or more substrates, wherein the logic is at least partially implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates being configured to: attempt to program data in a first portion of a non-volatile memory; determine whether the attempt is successful; and if it is determined that the attempt is unsuccessful, restore the data to a second portion of the non-volatile memory using an internal data move operation.

[0041] Example 8 may include the apparatus of Example 7, wherein the logic is further configured to: store the data in a cache of the non-volatile memory prior to the attempt; and if the attempt is determined to be unsuccessful, restore the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0042] Example 9 may include the apparatus of Example 8, wherein the logic is further configured to determine whether the data stored in the cache of the nonvolatile memory is valid prior to the restoring of the data.

[0043] Example 10 may include the apparatus of Example 9, wherein the logic is further configured to: move the data from the cache of the non-volatile memory to a temporary location of the non-volatile memory using the internal data move operation; and restore the data from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0044] Example 11 may include the apparatus of Example 10, wherein the logic is further configured to, if it is determined that the attempt was unsuccessful, move previously programmed data from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0045] Example 12 may include the device of any of Examples 7 to 11, wherein the non-volatile memory comprises a NAND memory.

[0046] Example 13 may include a method of recovering data, the method comprising: attempting to program data in a first portion of a non-volatile memory; determining whether the attempt is successful; and if it is determined that the attempt is unsuccessful, recovering the data to a second portion of the non-volatile memory using an internal data move operation.

[0047] Example 14 may include the method of Example 13, further comprising: storing the data in a cache of the non-volatile memory before the attempt; and if it is determined that the attempt is unsuccessful, restoring the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0048] Example 15 may include the method of Example 14, further comprising, prior to the restoring of the data, determining whether the data stored in the cache of the nonvolatile memory is valid.

[0049] Example 16 may include the method of Example 15, further comprising: moving the data from the cache of the non-volatile memory to a temporary location of the non-volatile memory using the internal data move operation; and restoring the data from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0050] Example 17 may include the method of Example 16, further comprising: if it is determined that the attempt is unsuccessful, moving the previously programmed data from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0051] Example 18 may include the method of any of Examples 13 to 17, wherein the non-volatile memory comprises a NAND memory.

[0052] Example 19 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to perform the following operations: attempt to program data in a first portion of a non-volatile memory; determine whether the attempt is successful; and if it is determined that the attempt is unsuccessful, restore the data to a second portion of the non-volatile memory using an internal data move operation.

[0053] Example 20 may include at least one computer-readable medium of Example 19, comprising a further set of instructions that, when executed by the computing device, causes the computing device to: store the data in a cache of the non-volatile memory before the attempt; and if the attempt is determined to be unsuccessful, restore the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0054] Example 21 may include at least one computer-readable medium as described in Example 20, comprising a further set of instructions that, when executed by the computing device, causes the computing device to perform the following operations: determining whether the data stored in the cache of the non-volatile memory is valid before the restoration of the data.

[0055] Example 22 may include at least one computer-readable medium of Example 21, comprising a further set of instructions that, when executed by the computing device, causes the computing device to: move the data from the cache of the non-volatile memory to a temporary location of the non-volatile memory using the internal data move operation; and restore the data from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0056] Example 23 may include at least one computer-readable medium of Example 22, comprising a further set of instructions that, when executed by the computing device, causes the computing device to perform the following operations: if it is determined that the attempt is unsuccessful, then using the internal data move operation to move the previously programmed data from the first portion of the non-volatile memory to the second portion of the non-volatile memory.

[0057] Example 24 may include the at least one computer-readable medium of any one of Examples 19 to 23, wherein the nonvolatile memory comprises a NAND memory.

[0058] Example 25 may include a memory controller device comprising: means for attempting to program data in a first portion of a non-volatile memory; means for determining whether the attempt is successful; and means for restoring the data to a second portion of the non-volatile memory using an internal data move operation if the attempt is determined to be unsuccessful.

[0059] Example 26 may include the apparatus of Example 25, further comprising: a component for storing the data in a cache of the non-volatile memory prior to the attempt; and a component for restoring the data from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation if it is determined that the attempt is unsuccessful.

[0060] Example 27 may include the apparatus of Example 26, further comprising means for determining whether the data stored in the cache of the non-volatile memory is valid before restoring the data.

[0061] Example 28 may include the apparatus of Example 27, further comprising: a component for moving the data from the cache of the non-volatile memory to a temporary location of the non-volatile memory using the internal data move operation; and a component for restoring the data from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0062] Example 29 may include the apparatus of Example 28, further comprising means for moving previously programmed data from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation if the attempt is determined to be unsuccessful.

[0063] Example 30 may include the apparatus of any of Examples 25 to 29, wherein the non-volatile memory comprises NAND memory.

[0064] This disclosure / application provides the following technical solutions:

[0065] 1. An electronic processing system, comprising:

[0066] processor;

[0067] a nonvolatile memory communicatively coupled to the processor; and

[0068] Logic communicatively coupled to the processor and the non-volatile memory, the logic being configured to:

[0069] attempting to program data in a first portion of the nonvolatile memory,

[0070] determining whether the attempt was successful, and

[0071] If the attempt is determined to be unsuccessful, the data is restored to a second portion of the non-volatile memory using an internal data move operation.

[0072] 2. The system of claim 1, wherein the logic is further configured to:

[0073] prior to said attempting, storing said data in a cache of said non-volatile memory; and

[0074] If the attempt is determined to be unsuccessful, the data is restored from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0075] 3. The system of claim 2, wherein the logic is further configured to:

[0076] Prior to the restoration of the data, it is determined whether the data stored in the cache of the nonvolatile memory is valid.

[0077] 4. The system of claim 3, wherein the logic is further configured to:

[0078] moving the data from the cache of the non-volatile memory to a temporary location in the non-volatile memory using the internal data move operation; and

[0079] The data is restored from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0080] 5. The system of claim 4, wherein the logic is further configured to:

[0081] If the attempt is determined to be unsuccessful, the previously programmed data is moved from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0082] 6. A system as described in technical solution 1, wherein the non-volatile memory includes a NAND memory.

[0083] 7. A semiconductor packaging device, comprising:

[0084] one or more substrates; and

[0085] Logic coupled to the one or more substrates, wherein the logic is implemented at least in part in one or more of configurable logic and fixed functionality hardware logic, the logic coupled to the one or more substrates to:

[0086] Attempt to program the data in the first portion of the nonvolatile memory,

[0087] determining whether the attempt was successful, and

[0088] If the attempt is determined to be unsuccessful, the data is restored to a second portion of the non-volatile memory using an internal data move operation.

[0089] 8. The device of claim 7, wherein the logic is further configured to:

[0090] prior to said attempting, storing said data in a cache of said non-volatile memory; and

[0091] If the attempt is determined to be unsuccessful, the data is restored from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0092] 9. The device of claim 8, wherein the logic is further configured to:

[0093] Prior to the restoration of the data, it is determined whether the data stored in the cache of the nonvolatile memory is valid.

[0094] 10. The device of claim 9, wherein the logic is further configured to:

[0095] moving the data from the cache of the non-volatile memory to a temporary location in the non-volatile memory using the internal data move operation; and

[0096] The data is restored from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0097] 11. The device of claim 10, wherein the logic is further configured to:

[0098] If the attempt is determined to be unsuccessful, the previously programmed data is moved from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0099] 12. A device as described in technical solution 7, wherein the non-volatile memory includes a NAND memory.

[0100] 13. A method for recovering data, the method comprising:

[0101] attempting to program data in a first portion of the nonvolatile memory;

[0102] determining whether the attempt was successful; and

[0103] If the attempt is determined to be unsuccessful, the data is restored to a second portion of the non-volatile memory using an internal data move operation.

[0104] 14. The method according to technical solution 13 further includes:

[0105] prior to said attempting, storing said data in a cache of said non-volatile memory; and

[0106] If the attempt is determined to be unsuccessful, the data is restored from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0107] 15. The method according to technical solution 14 further includes:

[0108] Prior to the restoration of the data, it is determined whether the data stored in the cache of the nonvolatile memory is valid.

[0109] 16. The method according to technical solution 15 further includes:

[0110] moving the data from the cache of the non-volatile memory to a temporary location in the non-volatile memory using the internal data move operation; and

[0111] The data is restored from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0112] 17. The method according to technical solution 16 further includes:

[0113] If the attempt is determined to be unsuccessful, the previously programmed data is moved from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0114] 18. A method as described in technical solution 13, wherein the non-volatile memory includes a NAND memory.

[0115] 19. At least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to:

[0116] attempting to program data in a first portion of the nonvolatile memory;

[0117] determining whether the attempt was successful; and

[0118] If the attempt is determined to be unsuccessful, the data is restored to a second portion of the non-volatile memory using an internal data move operation.

[0119] 20. The at least one computer-readable medium of technical solution 19, comprising a further set of instructions, which, when executed by the computing device, causes the computing device to perform the following operations:

[0120] prior to said attempting, storing said data in a cache of said non-volatile memory; and

[0121] If the attempt is determined to be unsuccessful, the data is restored from the cache of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0122] 21. The at least one computer-readable medium of technical solution 20, comprising a further set of instructions, which, when executed by the computing device, causes the computing device to perform the following operations:

[0123] Prior to the restoration of the data, it is determined whether the data stored in the cache of the nonvolatile memory is valid.

[0124] 22. The at least one computer-readable medium of technical solution 21, comprising a further set of instructions, which, when executed by the computing device, causes the computing device to perform the following operations:

[0125] moving the data from the cache of the non-volatile memory to a temporary location in the non-volatile memory using the internal data move operation; and

[0126] The data is restored from the temporary location of the non-volatile memory to the second portion of the non-volatile memory using the internal data move operation.

[0127] 23. The at least one computer-readable medium of technical solution 22, comprising a further set of instructions, which, when executed by the computing device, causes the computing device to perform the following operations:

[0128] If the attempt is determined to be unsuccessful, the previously programmed data is moved from the first portion of nonvolatile memory to the second portion of the nonvolatile memory using the internal data move operation.

[0129] 24. At least one computer-readable medium as described in technical solution 19, wherein the non-volatile memory includes a NAND memory.

[0130] The embodiments are applicable for use with all types of semiconductor integrated circuit ("IC") chips. Examples of such IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, systems-on-chips (SoCs), SSD / NAND controller ASICs, and the like. However, in some figures, signal lines are represented by lines. Some may be different to indicate more component signal paths, some may have numbered labels to indicate multiple component signal paths, and / or some may have arrows at one or more ends to indicate the primary direction of information flow. However, this should not be construed as limiting. Rather, such added detail may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuits. Regardless of the additional information, any depicted signal line may actually include one or more signals that can propagate in multiple directions and may be implemented using any suitable type of signaling scheme, such as digital or analog lines implemented using differential pairs, fiber optic lines, and / or single-ended lines.

[0131] Example sizes / models / values / ranges may be provided, but the embodiments are not limited thereto. As manufacturing techniques (e.g., photolithography) mature over time, it is expected that devices of smaller sizes will be fabricated. Furthermore, to simplify the description and discussion, and to avoid obscuring certain aspects of the embodiments, the figures may or may not show commonly known power / ground connections to the IC chip and other components. Furthermore, the arrangements may be shown in block diagram form to avoid obscuring the embodiments, and in view of the fact that the details regarding the implementation of such block diagram arrangements are highly dependent on the platform within which the embodiments are implemented, i.e., such details should be within the purview of those skilled in the art. Where specific details (e.g., circuits) are set forth to describe example embodiments, it should be apparent to those skilled in the art that the embodiments can be practiced without or with variations from these specific details. Therefore, this description is to be considered illustrative rather than restrictive.

[0132] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. Additionally, the terms "first," "second," etc., may be used herein only for ease of discussion, and unless otherwise indicated, these terms do not carry a specific temporal or sequential meaning.

[0133] As used in this application and in the claims, a list of items linked by the term "one or more of" may mean any combination of the listed items. For example, the phrase "one or more of A, B, and C" and the phrase "one or more of A, B, or C" may both mean: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0134] From the foregoing description, those skilled in the art will appreciate that the broad technology of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in conjunction with specific examples thereof, the true scope of the embodiments should not be so limited, as other modifications will become apparent to those skilled in the art upon a study of the drawings, the specification, and the appended claims.

Claims

1. An electronic processing system, comprising: processor; a nonvolatile memory communicatively coupled to the processor; as well as Logic communicatively coupled to the processor and the non-volatile memory, the logic being configured to: attempting to program data in a first block of the nonvolatile memory, wherein the nonvolatile memory is a NAND memory, prior to said attempting, storing said data in a cache of said non-volatile memory, determining whether the attempt was successful, If it is determined that the attempt was unsuccessful: determining whether the data stored in the cache of the non-volatile memory is valid; The device is characterized in that the logic coupled to the processor and the non-volatile memory is further configured to: moving the data from the cache to a second block of the non-volatile memory using an internal data move operation, wherein the second block is specifically reserved for program fault handling; moving previously programmed valid pages until a failed page from the first block of the nonvolatile memory to a new destination block of the nonvolatile memory using the internal data move operation; and The internal data move operation is used to restore the failed page data included in the data from the second block of the non-volatile memory to the new destination block of the non-volatile memory.

2. A semiconductor packaging device, comprising: one or more substrates; as well as Logic coupled to the one or more substrates, wherein the logic is implemented at least in part in one or more of configurable logic and fixed functionality hardware logic, the logic coupled to the one or more substrates to: attempting to program data in a first block of a non-volatile memory, wherein the non-volatile memory is a NAND memory, prior to said attempting, storing said data in a cache of said non-volatile memory, determining whether the attempt was successful, If it is determined that the attempt was unsuccessful: determining whether the data stored in the cache of the non-volatile memory is valid; characterised in that the logic coupled to the one or more substrates is further configured to: moving the data from the cache to a second block of the non-volatile memory using an internal data move operation, wherein the second block is specifically reserved for program fault handling; moving previously programmed valid pages until a failed page from the first block of the nonvolatile memory to a new destination block of the nonvolatile memory using the internal data move operation; and The internal data move operation is used to restore the failed page data included in the data from the second block of the non-volatile memory to the new destination block of the non-volatile memory.

3. A method for recovering data, the method comprising: attempting to program data in a first block of a non-volatile memory, wherein the non-volatile memory is a NAND memory, prior to said attempting, storing said data in a cache of said non-volatile memory; determining whether the attempt was successful; If it is determined that the attempt was unsuccessful: determining whether the data stored in the cache of the non-volatile memory is valid; Its characteristics are: moving the data from the cache of the non-volatile memory to a second block of the non-volatile memory using an internal data move operation, wherein the second block is specifically reserved for program fault handling; moving previously programmed valid pages until a failed page from the first block of the nonvolatile memory to a new destination block of the nonvolatile memory using the internal data move operation; and The internal data move operation is used to restore the failed page data included in the data from the second block of the non-volatile memory to the new destination block of the non-volatile memory.

4. A memory controller device, comprising: means for attempting to program data in a first block of a non-volatile memory, wherein the non-volatile memory is a NAND memory, means for storing said data in a cache of said non-volatile memory prior to said attempting; means for determining whether said attempt was successful; If it is determined that the attempt is unsuccessful, the method further comprises: means for determining whether said data stored in said cache of said non-volatile memory is valid; It is characterized by also including: means for moving the data from the cache of the non-volatile memory to a second block of the non-volatile memory using an internal data move operation, wherein the second block is specifically reserved for program fault handling; means for moving previously programmed valid pages, up to a failed page, from the first block of the nonvolatile memory to a new destination block of the nonvolatile memory using the internal data move operation; and Means for restoring the failed page data comprised by the data from the second block of the non-volatile memory to the new destination block of the non-volatile memory using the internal data move operation. 5 . A computer-readable medium having instructions stored thereon, which, when executed by a computing device, cause the computing device to perform the method according to claim 3 .

6. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method of claim 3.

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