An fpga and opencl-based fpga algorithm for large-capacity data

A data computing and data technology, applied in the field of data computing, can solve problems such as large time resources, limited algorithm performance, complex DDR hardware, etc., and achieve the effect of acceleration

CN110188066BActive Publication Date: 2021-02-02FASII INFORMATION TECH SHANGHAI
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2021-02-02

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Abstract

The invention provides an FPGA aimed at large-capacity data and an opencl-based FPGA algorithm, belonging to the technical field of data calculation. The FPGA includes an FPGA controller, a pcie interface, a Flash controller, a DDR controller and an algorithm module for command communication with the FPGA controller; it also includes a Flash memory controlled by the Flash controller and a DDR controlled by the DDR controller memory; the Flash controller communicates with the DDR controller instruction, the DDR controller communicates with the algorithm module instruction; the data transmission between the pcie interface and the Flash controller, the data between the Flash controller and the DDR controller Transmission, data transmission between the DDR controller and the algorithm module. By setting the Flash controller and the Flash memory on the original FPGA, the method enables the host to move a large amount of data to be calculated to the Flash memory through the pcie interface, and then move each data to be calculated to the DDR memory, avoiding multiple Move data through the pcie interface to achieve algorithm acceleration.
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Description

Technical field

[0001] The invention belongs to the technical field of data computing, and in particular relates to an FPGA for large-capacity data and an opencl-based FPGA algorithm.Background technique

[0002] In the current opencl-based algorithm architecture, the host transfers data to the DDR external to the FPGA through the pcie interface. The kernel algorithm module fetches the data from the DDR, performs the algorithm logic operation, and sends the calculated data back to the DDR after the calculation, and then the host takes out the calculated data from the DDR through the pcie interface. In this prior art, due to the use of DDR as a cache, storage resources are limited, and the hardware of DDR is more complex, increasing the number of DDRs requires higher hardware requirements for FPGAs, and because each time the host sends and receives data, the pcie interface link consumes The time resources are relatively large, which reduces the utilization rate of the kernel algorithm modu...

Examples

Embodiment Construction

[0039]Such asfigure 1 withfigure 2 As shown, an FPGA for large-capacity data includes an FPGA controller, a pcie interface for command communication with the FPGA controller, a Flash controller, a DDR controller, and an algorithm module; it also includes a Flash memory controlled by the Flash controller And the DDR memory controlled by the DDR controller; the Flash controller communicates with the DDR controller command communication, the DDR controller communicates with the algorithm module command communication; the pcie interface and the Flash controller communicate data between the Data transmission between the Flash controller and the DDR controller, and data transmission between the DDR controller and the algorithm module.

[0040]In this embodiment, the Flash controller 2 includes a Flash array group A controller and a Flash array group B controller; there are 96 Flash memories 5, of which 48 pieces of Flash memories 5 are connected to 12 of the Flash array group A controllers F...