Clock signal generator, phase-locked loop circuit, operation method, and wireless communication device

Abstract

The present application provides a clock signal generator, a phase-locked loop circuit, an operation method, and a wireless communication device, wherein the clock signal generator is configured to generate a target output clock signal based on a reference clock signal. The clock signal generator includes: a digital time converter (DTC), which is configured to delay a reference clock signal based on an input code to generate a delayed clock signal and output the delayed clock signal; a DTC controller, which is configured to determine an initial gain value of the DTC based on a result obtained by comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and to generate an input code based on the initial gain value; and a phase-locked loop, which is configured to generate a target output clock signal based on a frequency-divided clock signal of the delayed clock signal and the previously generated output clock signal, and the target output clock signal is locked to the delayed clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0040602 filed on April 6, 2018 in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The inventive concept relates to a semiconductor circuit including a digital-to-time converter (DTC) circuit, and more particularly to a phase-locked loop circuit, a clock signal generator including the DTC circuit, a method of operating the phase-locked loop circuit and the clock signal generator, and a wireless communication device. Background Art

[0004] The DTC generates a delayed clock signal by delaying the input reference clock signal according to the received digital code. The DTC can be used in an oscilloscope, a fractional-N phase-locked loop (PLL), a time-interleaved analog-to-digital converter (ADC), etc. The DTC included in the fractional-N PLL circuit can delay the reference clock signal in advance by a delay amount corresponding to the quantization error, and provide the delayed reference clock signal as the input clock of the phase-locked loop, so that the quantization error of the fractional-N PLL circuit can be removed in advance. For the effective operation of the DTC, it is desirable to quickly derive a gain value of the DTC that satisfies the operating conditions of the clock signal generator including the DTC. Summary of the invention

[0005] The inventive concept provides a phase-locked loop circuit, a clock signal generator, and a method of operating the phase-locked loop circuit and the clock signal generator capable of reducing a time taken to derive a gain value for operating a digital-to-time converter (DTC).

[0006] According to some example embodiments, a clock signal generator configured to generate a target output clock signal based on a reference clock signal is provided. The clock signal generator includes a digital time converter (DTC), the DTC being configured to delay the reference clock signal based on an input code to generate a delayed clock signal and output the delayed clock signal. The clock signal generator also includes a DTC controller, the DTC controller being configured to determine an initial gain value of the DTC based on a result obtained by comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and to generate the input code based on the initial gain value. The clock signal generator also includes a phase-locked loop, the phase-locked loop being configured to generate the target output clock signal based on the delayed clock signal and a frequency-divided clock signal of the previously generated output clock signal, the target output clock signal being locked to the delayed clock signal.

[0007] According to some example embodiments, a phase-locked loop circuit is provided, the phase-locked loop circuit comprising: a phase-locked loop, the phase-locked loop being configured to generate a target output clock signal based on a divided clock signal of an input clock signal and a previously generated output clock signal, the target output clock signal being locked to the input clock signal; a modulator, the modulator being configured to change a division ratio of the phase-locked loop and output an error value generated according to the changed division ratio; a digital-to-time converter (DTC), the digital-to-time converter being configured to delay a reference clock signal based on an input code to generate the input clock signal and provide the input clock signal to the phase-locked loop; and a DTC controller, the DTC controller being configured to determine an initial gain value of the DTC based on a result obtained by comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and to generate the input code based on the initial gain value.

[0008] According to some example embodiments, a method of operating a phase-locked loop circuit is provided, the phase-locked loop circuit including a digital time converter (DTC) configured to provide an input clock signal of a delayed reference clock signal. The method includes: generating a target output clock signal having a target frequency by locking the frequency of a divided clock signal of a previously generated output clock signal to the frequency of the input clock signal. The method also includes: determining an initial gain value of the DTC based on a result obtained by comparing at least one time difference between the reference clock signal and at least one previously generated input clock signal and a period of the previously generated output clock signal. In addition, the method includes: locking the phase of the target output clock signal to the phase of the reference clock signal by calibrating a delay amount of the DTC based on the initial gain value.

[0009] According to some example embodiments, there is provided a wireless communication device, the wireless communication device comprising: a signal processor configured to process a reception signal and a transmission signal in a baseband and output a frequency control signal; a transceiver configured to perform a transmission operation and a reception operation continuously in time; and a clock signal generator configured to generate a target output clock signal for providing a frequency for sampling the transmission signal and the reception signal in response to the frequency control signal, wherein the clock signal generator comprises: a phase-locked loop configured to generate a frequency-divided clock signal of a previously generated output clock signal and an input clock based on the frequency control signal. a signal to generate a target output clock signal, the target output clock signal being locked to the input clock signal and changing a frequency division ratio for generating the divided clock signal based on the frequency control signal; a digital time converter (DTC) configured to delay a reference clock signal based on an input code to generate the input clock signal and provide the input clock signal to the phase-locked loop; and a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC and a period of the previously generated output clock signal, and to generate the input code based on the initial gain value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Some exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a clock signal generator according to some example embodiments;

[0012] Figure 2 is a block diagram of a phase-locked loop circuit according to some example embodiments;

[0013] Figure 3 is a block diagram of an example of a gain calibration circuit according to some example embodiments;

[0014] Figure 4A and 4B yes Figure 3 A timing diagram of the operation of the pulse generator and logic circuit;

[0015] Figure 5 An example of a binary search operation is shown;

[0016] Figure 6 is a block diagram of an example of a DTC calibration circuit according to some example embodiments;

[0017] Figure 7 yes Figure 2A circuit diagram of an example of an output control circuit included in a DTC controller;

[0018] Fig. 8A and 8B It is used to illustrate Figure 2 A block diagram of an output path of a DTC controller in a phase-locked loop circuit;

[0019] Fig.9A is a timing diagram illustrating a locking time of a phase locked loop circuit according to some example embodiments;

[0020] Fig. 9B is a timing chart showing a locking time according to a comparative example;

[0021] Fig.10 is a block diagram of a phase-locked loop circuit in which a phase detector is implemented as a time-to-digital converter according to some example embodiments;

[0022] Fig.11 is a flow chart of a method of operating a phase locked loop circuit according to some example embodiments;

[0023] Fig.12 It is derived Fig.11 A flowchart of the operation of determining the initial gain value of the DTC; and

[0024] Fig.13 is a block diagram of a wireless communication device including a phase-locked loop circuit, according to some example embodiments. DETAILED DESCRIPTION

[0025] Hereinafter, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram of a clock signal generator 10 according to some example embodiments. The clock signal generator 10 may be included in a receiving and / or transmitting circuit of a wireless communication device, a system on a chip (SoC), an interface circuit for receiving a signal from a device (e.g., a wireless communication device) and / or transmitting a signal to a device (e.g., a wireless communication device), etc.

[0027] refer to Figure 1 The clock signal generator 10 can be based on the received reference clock signal CLK REF Generates the output clock signal CLK OUT The reference clock signal CLK may include a locked loop 11, a digital time converter 12 (hereinafter referred to as DTC), and a DTC controller 13. REFThe output clock signal CLK may be provided from a reference clock signal generator (eg, an oscillator, a periodic signal generator, etc.) in a device (or circuit) including the clock signal generator 10, or provided from outside the device. OUT The frequency of the reference clock signal CLK REF N times the frequency of (where N is a real number equal to or greater than 1). Any one or all of the locked loop 11, DTC 12, and DTC controller 13 may be implemented by, for example, a circuit or line, or alternatively by at least one processor that executes a program code including instructions corresponding to any or all operations described herein performed by the locked loop 11, DTC 12, and DTC controller 13. The instructions may be stored in a memory. The term "processor" used in the present disclosure may refer to, for example, a hardware-implemented data processing device having a circuit physically structured to perform desired operations including, for example, operations represented by codes and / or instructions included in a program. In at least some example embodiments, the above-mentioned hardware-implemented data processing device may include, but is not limited to, a microprocessor, a central processing unit (CPU), a processor core, a multi-core processor, a multiprocessor, an application-specific integrated circuit (ASIC), and a field-programmable gate array (FPGA).

[0028] DTC 12 can generate a delayed clock signal CLK D , the delayed clock signal will receive the reference clock signal CLK REF The delay is a time period corresponding to the input of the DTC 12 (ie, the input code ICD). In other words, the DTC 12 may generate a delayed clock signal CLK having a delay amount (eg, delay time or phase shift) corresponding to the input code ICD. D . The DTC 12 may generate the delay amount in various ways. For example, the DTC 12 may generate the delay time by selecting a plurality of delay units corresponding to the input code ICD from among the delay units included in the DTC 12. In addition, the DTC 12 may generate the delay amount using a passive element that is charged or discharged based on a current corresponding to the input code ICD. However, one or more example embodiments are not limited thereto. The DTC 12 may operate in various ways.

[0029] The locked loop 11 may receive the delayed clock signal CLK provided by the DTC 12 as an input clock signal. D and can be based on the delayed clock signal CLK D Generate and delay the clock signal CLK D Synchronous output clock signal CLK OUT The locked loop 11 can provide the output clock signal CLK OUTOr the output clock signal CLK OUT The feedback signal of the divided clock signal is divided, and the delayed clock signal CLK D and feedback signal to generate the output clock signal CLK OUT , for example, with a delayed clock signal CLK D The same phase as the output clock signal CLK OUT In some example embodiments, the locked loop 11 may include a phase-locked loop PLL, a delay-locked loop DLL, a phase / frequency locked loop, etc. However, one or more example embodiments are not limited thereto. The locked loop 11 may be implemented as at least one of various locked loops.

[0030] The DTC controller 13 can control the delay amount of the DTC 12 by providing the input code ICD to the DTC 12. The DTC controller 13 can calibrate the input code ICD and can change the delay amount. The DTC controller 13 can derive a gain value for driving the DTC 12 and can calibrate the input code ICD based on the derived gain value. In this case, the gain value can be adjusted according to the output clock signal CLK OUT The DTC controller 13 may include a gain calibration circuit 14 for quickly acquiring an initial value (hereinafter referred to as an initial gain value) of a gain value used to drive the DTC 12. The DTC controller 13 may be implemented by, for example, a circuit or line, or alternatively by at least one processor that executes a program code including instructions corresponding to any or all operations performed by the DTC controller 13 described herein.

[0031] The gain calibration circuit 14 can be based on the reference clock signal CLK REF With the delayed clock signal CLK D The time difference between (i.e., the delay amount of DTC 12) and the output clock signal CLK OUT A cycle of the output clock signal CLK OUT The gain calibration circuit 14 can compare the delay amount of the DTC 12 with the output clock signal CLK OUT The gain calibration circuit 14 can use a time-to-digital converter to convert the delay amount of the DTC 12 and the output clock signal CLK into a binary search operation based on the comparison result, thereby quickly deriving the initial gain value. OUT One cycle of is converted into a digital code value, and the digital code values ​​can be compared with each other to output a comparison result.

[0032] It is desirable to be able to quickly derive an initial gain value for driving the DTC 12 to reduce the time required for the clock signal generator 10 to generate an output clock signal CLK having a target frequency and a target phase. OUT (For example, the output clock signal CLK in the locked state OUT As described above, the gain calibration circuit 14 compares the delay amount of the DTC 12 with the output clock signal CLK OUT When performing a binary search operation based on the result obtained in one cycle of , the clock signal generator 10 according to some example embodiments can quickly derive an initial gain value. Therefore, the locking time of the clock signal generator 10 according to some example embodiments can be reduced compared to a conventional clock signal generator.

[0033] Figure 1 shows the reference clock signal CLK REF , delay clock signal CLK D And the output clock signal CLK OUT The DTC controller 13 is operated. However, Figure 1 The illustration is an example for convenience of explanation, and thus one or more example embodiments are not limited thereto. As described below, the DTC controller 13 may operate in response to various signals.

[0034] Figure 2 is a block diagram of a phase-locked loop circuit 1000 according to some example embodiments.

[0035] The phase-locked loop circuit 1000 may be included in a transmission and / or reception circuit of a wireless communication device, a SoC, an interface circuit that can exchange signals between devices (e.g., a wireless communication device, a base station, etc.), etc. The phase-locked loop circuit 1000 may be included in various devices that operate in response to a clock signal and may provide a clock signal.

[0036] refer to Figure 2 The phase-locked loop circuit 1000 may include a phase-locked loop 100, a DTC 200, a DTC controller 300, and a modulator (DSM) 400. The phase-locked loop 100 may be a fractional-N phase-locked loop, and the phase-locked loop circuit 1000 may generate a reference clock signal CLK having a frequency of REF The output clock signal CLK is N times the frequency (where N is a real number equal to or greater than 1) of OUT .

[0037] DTC 200 can generate a delayed clock signal CLK D , the delayed clock signal can receive the reference clock signal CLK REF Delay for a period of time corresponding to the input code ICD. Figure 1 The DTC 200 may be implemented by, for example, a circuit or line, or alternatively by at least one processor executing program code corresponding to instructions including any or all operations performed by the DTC 200 as described herein.

[0038] The phase-locked loop 100 may include a frequency detector (FD) 110, a phase detector (PD) 120, a charge pump (CP) 130, a loop filter (LF) 140, an oscillator 150, and a multi-mode frequency divider (MMDIV) 160. In some example embodiments, the frequency detector 110 and the phase detector 120 may be formed as one body. Any one or all of the frequency detector 110, the phase detector 120, the charge pump 130, the loop filter 140, the oscillator 150, and the multi-mode frequency divider 160 may be implemented by, for example, a circuit or line, or alternatively by at least one processor executing a program code including instructions corresponding to any or all operations performed by the phase-locked loop 100, the frequency detector 110, the phase detector 120, the charge pump 130, the loop filter 140, the oscillator 150, and the multi-mode frequency divider 160 as described herein.

[0039] The frequency detector 110 can detect (eg, determine) the frequency-divided clock signal CLK DIV and delay the clock signal CLK D The frequency difference between the divided clock signal and the output clock signal CLK OUT When the divided clock signal CLK DIV and delay the clock signal CLK D When the frequencies of are equal or similar, the frequency detector 110 may generate a frequency lock signal LOCK F For example, when the divided clock signal CLK DIV and delay the clock signal CLK D When the frequency of the input signal is different from that of the input signal, the frequency detector 110 may generate a frequency lock signal LOCK having a logic low (ie, an invalid level). F ; When the divided clock signal CLK DIV and delay the clock signal CLK D When the frequencies of the two signals are equal or similar, the frequency detector 110 may generate a frequency lock signal LOCK having a logic high (ie, an active level). F In some example embodiments, the frequency detector 110 may be based on the divided clock signal CLK DIV and delay the clock signal CLK D A control signal (eg, a current signal) for controlling the loop filter 140 is generated based on the frequency difference between the two.

[0040] The phase detector 120 may detect (eg, determine) the delayed clock signal CLK D And the divided clock signal CLK DIV The phase difference between the two clock signals can be detected by the phase detector 120, and a phase difference signal UD corresponding to the phase difference can be generated. In some example embodiments, the phase detector 120 can detect the phase difference between the two clock signals by delaying the clock signal CLK based on certain clock signals. D and delay the clock signal CLK D The phase difference is sampled to generate a sampled voltage as a phase difference signal UD.

[0041] The charge pump 130 may generate a pump output current corresponding to the phase difference signal UD, that is, a control current CO. The loop filter 140 may generate an oscillation control voltage VC by integrating the control current CO, and the oscillator 150 may generate an output clock signal CLK having a certain target frequency and oscillating in response to the oscillation control voltage VC. OUT .

[0042] The multi-mode frequency divider 160 can output the clock signal CLK based on the set frequency division ratio. OUT Divide the frequency to generate the divided clock signal CL DIV The average frequency division ratio of the phase-locked loop 100 during a certain period of time can be expressed as a fraction rather than an integer. The multi-mode frequency divider 160 can output the clock signal CLK according to the integer frequency division ratio. OUT The multi-mode divider 160 can perform frequency division and change the integer division ratio to meet the fractional division ratio. The multi-mode divider 160 can output the clock signal CLK in each feedback loop based on the integer division ratio set according to the control signal MCS provided by the modulator (DSM) 400. OUT Perform frequency division.

[0043] The modulator 400 may receive a frequency control command FCW and may generate a control signal MCS for the multi-mode frequency divider 160 according to the frequency control command FCW. The frequency control command FCW may be generated from a device including the phase-locked loop 100 or based on the output clock signal CLK OUT The frequency control command FCW can be based on the reference clock signal CLK REF and output clock signal CLK OUT For example, the frequency control command FCW may include a fractional portion of the average frequency division ratio set for the phase-locked loop 100. The modulator 400 may be implemented as a delta-sigma modulator. The modulator 400 may be implemented by, for example, a circuit or line, or alternatively by at least one processor executing a program code including instructions corresponding to any or all operations performed by the modulator 400 as described herein.

[0044] The modulator 400 can provide an integer division ratio to the multi-mode divider 160. For example, when the multi-mode divider 160 is configured to output the clock signal CLK based on a division ratio among K-1, K, and K+1 (where K is a positive integer), OUT When performing frequency division, the modulator 400 can select one of the integer division ratios K-1, K and K+1 in each cycle in such a way that the average division ratio has a desired value (for example, a target value), and can provide the selected integer division ratio (or a coefficient indicating the selected integer division ratio) as a control signal MCS to the multi-mode divider 160.

[0045] For example, assume that the multi-mode frequency divider 160 is configured to output the clock signal CLK based on a frequency division ratio of K and K+1. OUT The default frequency division ratio K is 2, and the average frequency division ratio is 2.25. The modulator 400 can receive the fractional part 0.25 as the frequency control command FCW. The modulator 400 can divide the output clock signal CLK by 2 three times in four times on average. OUT And divide the output clock signal CLK by 3 once in 4 times on average OUT , so that the average division ratio becomes 2.25 based on the respectively set integer division ratios 2 and 3. Therefore, the modulator 400 can output a control signal MCS indicating the value added to the default division ratio to the multi-mode divider 160. For example, the control signal MCS can be '0' or '1'. In this case, '0' or '1' can be randomly selected, '0' can be selected 3 times out of 4 times on average, and '1' can be selected 1 time out of 4 times on average. The multi-mode divider 160 can change the division ratio based on the received control signal MCS.

[0046] As described above, when the integer division ratio changes, a quantization error (QE) may occur. In the phase-locked loop 100, the QE may occur due to the difference between the integer division ratio (i.e., the real division ratio) and the fractional-N division ratio (i.e., the average division ratio). Therefore, the modulator 400 may provide the QE (e.g., a QE value representing the QE) to the DTC controller 300, and the DTC controller 300 may calibrate (e.g., generate) the input code ICD in such a manner that the delay amount of the DTC 200 corresponds to the QE.

[0047] The DTC controller 300 may include a gain calibration circuit 310 and a DTC calibration circuit 320 , and may further include an output control circuit 330 .

[0048] When the phase-locked loop 100 is in a frequency locked state, in other words, when the phase-locked loop 100 outputs a frequency locked signal LCOK of logic high FWhen the gain calibration circuit 310 can respond to the frequency lock signal LOCK F Derived initial gain value CD of DTC 200 IG .

[0049] When the output clock signal CLK OUT When the target frequency of the phase-locked loop circuit 1000 changes due to the frequency control signal FCW, the phase-locked loop circuit 1000 can perform a rough lock, and accordingly, the output clock signal CLK OUT The frequency can reach the target frequency. When the output clock signal CLK OUT When the frequency reaches the target frequency, the gain calibration circuit 310 may respond to the frequency lock signal LOCK of logic high F Be driven.

[0050] The gain calibration circuit 310 can be based on the reference clock signal CLK REF and delay the clock signal CLK D The delay amount of the DTC 200 is obtained, and the delay amount can be compared with the output clock signal CLK OUT The initial gain value CD is derived according to the binary search algorithm. IG .

[0051] The gain calibration circuit 310 can provide the set initial gain value CD to the DTC 200 via the output control circuit 330. IG and / or an initial gain value CD calibrated according to a binary search operation IG , as the input code ICD. When the initial gain value CD IG When calibrated, the delay amount of the DTC 200 may be changed. The gain calibration circuit 310 may derive a target initial gain value CD based on the delay amount changed according to the binary search operation. IG .

[0052] When the output clock signal CLK OUT When the target frequency is reached, the DTC 200 should be delayed by a delay amount D DTC It can be expressed by equation 1 to output the clock signal CLK OUT The phase is locked to the delayed clock signal CLK D phase.

[0053] [Equation 1]

[0054] D DTC =T OUT *QE=K D *G DTC *QE

[0055] Among them, T OUTRefers to the output clock signal CLK with the target frequency OUT One cycle of K D Refers to a time period that can be delayed for one digital code as a unit resolution (or unit delay amount) of the DTC 200, G DTC Refers to the gain value of DTC 200.

[0056] As calculated according to Equation 2, the gain value G of the DTC 200 is DTC Corresponding to the unit resolution K D In addition to the output clock signal CLK OUT One cycle T OUT The obtained value and the gain value G based on the DTC 200 according to Equation 1 DTC Generate delay D DTC .

[0057] [Equation 2]

[0058] G DTC =T OUT / K D

[0059] According to Equation 2, the gain value G DTC Indicates that the reference clock signal CLK REF Delay and output clock signal CLK OUT One cycle T OUT The code value corresponding to the time period.

[0060] The gain calibration circuit 310 can compare the delay amount of the DTC 200 with the output clock signal CLK OUT One cycle T OUT , and the initial gain value CD can be calibrated by performing a binary search operation based on the comparison result IG , thus deriving the reference clock signal CLK REF Delay and output clock signal CLK OUT One cycle T OUT The code value of the corresponding time period (ie, the initial gain value CD IG ). The binary search operation can be performed with the reference clock signal CLK REF The gain calibration circuit 310 is executed during a time period corresponding to M cycles of the input code ICD (where M is the number of bits of the input code ICD). When the binary search operation is completed, the gain calibration circuit 310 may output an indication that the binary search operation is completed (ie, indicating that the initial gain value CD IG is the target value) of the completion signal DONE (for example, an operation completion signal).

[0061] When the completion signal DONE is output from the gain calibration circuit 310, the DTC calibration circuit 320 may be configured based on the initial gain value CD provided together with the completion signal DONE. IG To generate the control code value CD CAL The DTC calibration circuit 320 may receive a phase difference signal UD from the phase-locked loop 100 and may be based on the initial gain value CD IG , phase difference signal UD and QE generated control code value CD received from modulator 400 CAL , and finally the output clock signal CLK OUT The phase is locked to the reference clock signal CLK REF In other words, the DTC calibration circuit 320 can perform a background fine lock operation. The DTC calibration circuit 320 can perform a background fine lock operation by accumulating the correlation value of the code of the QE and the phase difference signal UD to the initial gain value CD IG To generate the gain value G DTC and can be obtained by combining QE with the gain value G DTC Multiply to generate control code value CD CAL The following will refer to Figure 6 The detailed structure and detailed operation of the DTC calibration circuit 320 are described.

[0062] As described above, the DTC calibration circuit 320 can be configured to calculate the initial gain value CD by accumulating the correlation value of the code of the QE and the phase difference signal UD. IG To generate the gain value G DTC , when the initial gain value CD IG When set to '0', the gain value G DTC The delay in reaching the target gain value may be too large. For example, if the output clock signal CLK OUT One cycle is 500 picoseconds (ps) and the unit resolution is K D When the initial gain value CD is 1ps, the target gain value can be 500. IG is set to '0', it will take time for the reference clock signal CLK REF The gain value G is corresponding to the period of hundreds of cycles. DTC Reach '500'. In addition, when calculating the gain value G DTC Previously, the output clock signal CLK was implemented OUT The frequency of the output clock signal CLK reaches the target frequency (i.e., the frequency locked state). OUT The delay in reaching the phase lock state may be too large. In addition, due to the gain value G of DTC 200 DTC The output clock signal CLK OUT The frequency changes, so when the target frequency changes, the gain value G of DTC 200DTC The derivation of is repeated.

[0063] However, in the DTC controller 300 according to some example embodiments, the gain calibration circuit 310 may deduce that the reference clock signal CLK REF Delay and output clock signal CLK OUT One cycle T OUT The corresponding initial gain value CD IG , and the DTC calibration circuit 320 can be based on the initial gain value CD IG Fine locking is performed. Therefore, the locking time of the phase-locked loop circuit 1000 can be reduced.

[0064] The DTC controller 300 may further include an output control circuit 330. The output control circuit 330 may select an initial gain value CD outputted from the gain calibration circuit 310. IG and the control code CD output from the DTC calibration circuit 320 CAL The output control circuit 330 may provide an initial gain value CD output from the gain calibration circuit 310 when the gain calibration circuit 310 performs a binary search operation. IG As the input code ICD of the DTC 200. When the completion signal DONE is outputted with the completion of the binary search operation, the output control circuit 330 may provide the control code value CD outputted from the DTC calibration circuit 320. CAL As the input code ICD of DTC200. Figure 3 To further discuss the gain calibration circuit 310, the following Figure 6 The DTC calibration circuit 320 is further discussed below in conjunction with Figure 7 The output control circuit 330 is discussed further.

[0065] Figure 3 is a block diagram of an example of a gain calibration circuit 310 according to some example embodiments. Figure 4A and 4B yes Figure 3 A timing diagram of the operations of the logic circuit 31 and the pulse generator 33.

[0066] Figure 3 The gain calibration circuit 310 can be used as Figure 2 The gain calibration circuit 310 and the reference Figure 2 The description of the gain calibration circuit 310 provided can be applied to reference Figure 3 A gain calibration circuit 310 is provided.

[0067] refer to Figure 3 The gain calibration circuit 310 may include a first time-to-digital conversion circuit 311, a second time-to-digital conversion circuit 312, a comparator 313, and a decoder 314. The first time-to-digital conversion circuit 311 and the second time-to-digital conversion circuit 312 may include time-to-digital converters 32 and 34, respectively.

[0068] The first time-to-digital conversion circuit 311 may include a logic circuit 31 and a first time-to-digital converter 32, wherein the logic circuit 31 extracts the reference clock signal CLK REF and delay the clock signal CLK D The time difference (or phase difference) between them. Figure 3 The logic circuit 31 implemented as an XOR logic gate is shown. However, one or more example embodiments are not limited thereto.

[0069] The logic circuit 31 can receive the reference clock signal CLK REF and delay the clock signal CLK D , and can generate a reference clock signal CLK indicating REF and delay the clock signal CLK D The time difference between the time difference signals T DIFF . Time difference signal T DIFF Can be used with DTC (e.g. Figure 2 The delay amount of DTC 200) is similar or equal.

[0070] refer to Figure 4A , the logic circuit 31 can respond to the reference clock signal CLK at time point t1 REF The rising edge (or falling edge) and the delayed clock signal CLK D The rising edge (or falling edge) of the reference clock signal CLK is generated. REF and delay the clock signal CLK D The time difference between the time difference signals T DIFF As shown in the figure, the reference clock signal CLK REF The rising edge of the time point t1 and the delayed clock signal CLK D The interval between the time points t2 when the rising edge of the reference clock signal CLK REF and delay the clock signal CLK D The time difference between.

[0071] Return to reference Figure 3 , the first time-to-digital converter 32 may be based on the reference clock signal CLK REF and delay the clock signal CLK D The time difference between the time difference signals T DIFF Generate the first digital code DCDLY . First digital code DC DLY The reference clock signal CLK REF and delay the clock signal CLK D The digital value corresponding to the time difference between

[0072] The second time-to-digital conversion circuit 312 may include a pulse generator 33 and a second time-to-digital converter 34. F When the pulse generator 33 is logic high, it can output the clock signal CLK OUT Generates the output clock signal CLK OUT One cycle of the pulse signal T VCO .

[0073] refer to Figure 4B , when the frequency lock signal LOCK F When the time point t1 becomes logic high, the pulse generator 33 can output the clock signal CLK OUT The rising edge (or falling edge) generates a pulse signal T VCO . Accordingly, the pulse signal T VCO The clock signal CLK may be generated and output at the interval between the time point t2 and the time point t3. OUT The rising edge of occurs at this interval.

[0074] return Figure 3 The second time-to-digital converter 34 may respond to the pulse signal T VCO Generate the second digital code DC OFP . Second digital code DC OFP The output clock signal CLK OUT The digital value corresponding to one cycle of

[0075] The comparator 313 can compare the first digital code DC DLY and the second digital code DC OFP To output the comparison result. For example, when the first digital code DC DLY Greater than the second digital code DC OFP When the first digital code DC DLY Less than the second digital code DC OFP , the comparator 313 may output data '0'. In some example embodiments, when the first digital code DC DLY With the second digital code DC OFP At the same time, the comparator 313 can provide the decoder 314 with a first digital code DC indicating DLY With the second digital code DC OFP Same single signal.

[0076] The decoder 314 may perform a binary search operation by executing a binary search algorithm based on the comparison result, and may calibrate the initial gain value CD IG The binary search operation of decoder 314 will refer to Figure 5 Any or all of the comparator 313, the decoder 314, the first time-to-digital converter 32, the second time-to-digital converter 34, the logic circuit 31, and the pulse generator 33 may be implemented by, for example, a circuit or line, or may alternatively be implemented by at least one processor executing a program code including instructions corresponding to any or all operations performed by the gain calibration circuit 310, the first time-to-digital conversion circuit 311, the second time-to-digital conversion circuit 312, the comparator 313, the decoder 314, the first time-to-digital converter 32, the second time-to-digital converter 34, the logic circuit 31, and the pulse generator 33 as described herein.

[0077] Figure 5 An example of a binary search operation is shown. The horizontal axis indicates time and the vertical axis indicates the initial gain value CD IG .

[0078] Figure 5 The example is based on Figure 2 The input code ICD of DTC 200 is 4 digits and the initial gain value CD IG Assumption of '1000' as the median of input code ICD.

[0079] Initial gain value CD IG The default value may be set to '1000' which is the median of the input code ICD. Initial gain value CD IG The default value of ICD may be provided to DTC 200 as input code ICD, and DTC 200 may generate a reference clock signal CLK REF The clock signal CLK is delayed by a period corresponding to '1000'. D .

[0080] Figure 3 The comparator 313 can compare the reference clock signal CLK REF and delay the clock signal CLK D The time difference between the first digital code DC DLY The output clock signal CLK indicates OUT The second digital code of one cycle DC OFP , and the comparison result can be provided to the decoder 314. When the first digital code DC DLY Greater than the second digital code DC OFP When the reference clock signal CLKREF and delayed clock signal CL KD , that is, the delay amount of the DTC 200 corresponding to the input code ICD'1000' is greater than the output clock signal CLK OUT In one cycle of IG Calibrated (eg, changed and / or determined) to '0100'. The initial gain value CD after calibration IG , that is, '0100' is provided as the input code ICD to the DTC 200, and the DTC 200 can generate the reference clock signal CLK REF The delayed clock signal CLK is delayed for a period corresponding to '0100' D When the delay amount of DTC200 corresponding to the input code ICD'0100' is less than the output clock signal CLK OUT In one cycle of IG Calibrate (eg, change) to '0110'.

[0081] Initial gain value after calibration CD IG , that is, '0110' is provided as the input code ICD to the DTC 200, and the DTC 200 can generate the reference clock signal CLK REF The delayed clock signal CLK is delayed for a period corresponding to '0110' D When the delay amount of the DTC 200 corresponding to the input code ICD'0110' is greater than the output clock signal CLK OUT In one cycle of IG The initial gain value CD can be derived as IG As described above, the decoder 314 may perform a binary search algorithm until the initial gain value CD IG until the last digit of is changed.

[0082] Accordingly, the output clock signal CLK OUT One cycle can be in with CD as the initial gain value IG Between the delay amount corresponding to '0110' and the delay amount corresponding to '0100', '0101' can be derived as the initial gain value CDIG.

[0083] The initial gain value CD according to the binary search algorithm IG The calibration, that is, Figure 3The operation of the gain calibration circuit 310 can be performed in conjunction with the reference clock signal CLK REF The execution is performed during a period corresponding to the value obtained by multiplying the number of bits of the input code ICD by one cycle. Figure 5 As shown in the figure, when the number of bits of the input code ICD is equal to 4, the initial gain value CD IG The calibration can be performed with the reference clock signal CLK REF The time periods corresponding to the four cycles.

[0084] Figure 6 is a block diagram of an example of a DTC calibration circuit 320 according to some example embodiments. Figure 6 The DTC calibration circuit 320 can be used as Figure 2 The DTC calibration circuit 320 and the reference Figure 2 The description of the DTC calibration circuit 320 provided can be applied to Figure 6 The DTC calibration circuit 320 is provided.

[0085] refer to Figure 6 , the DTC calibration circuit 320 may include a correlation circuit 321, an integrator 322, and a multiplier 26, and may represent a calibration circuit driven in a sign-sign least mean square (LMS) manner. In the correlation circuit 321, the first circuit 21 may detect and output the sign of the phase difference signal UD and the second circuit 22 may detect and output the sign of QE, and the correlator 23 may output the correlation value of the sign of the phase difference signal UD and the sign of QE. For example, the correlator 23 may be implemented as an exclusive OR (XOR) gate.

[0086] Integrator 322 may include an adder 24 that receives the correlation value and a storage device 25 (e.g., a flip-flop) that receives the output of adder 24. The output of storage device 25 may be returned as an input to adder 24. Storage device 25 may be responsive to the output of Figure 2 The gain calibration circuit 310 provides a completion signal DONE that is enabled and can receive an initial gain value CD IG As the initial value. The integrator 322 can be based on the initial gain value CD IG The gain value G is generated by integrating (eg, accumulating) the correlation value DTC .

[0087] The multiplier 26 can be operated by adding the gain value G DTC Multiply by QE to generate control code value CD CALAny or all of the first circuit 21, the second circuit 22, the correlator 23, the adder 24, the storage device 25, and the multiplier 26 may be implemented by, for example, circuits or lines, or alternatively by at least one processor executing program code including instructions corresponding to any or all operations performed by the DTC calibration circuit 320, the correlation circuit 321, the integrator 322, the first circuit 21, the second circuit 22, the correlator 23, the adder 24, the storage device 25, and the multiplier 26 as described herein.

[0088] Figure 7 yes Figure 2 2 is a circuit diagram of an example of an output control circuit 330 included in the DTC controller 300 .

[0089] refer to Figure 7 , the output control circuit 330 may include a selection signal generator 331 and a selector 332. Any or all of the selection signal generator 331 and the selector 332 may be implemented by, for example, a circuit or line, or may alternatively be implemented by at least one processor executing a program code including instructions corresponding to any or all operations performed by the output control circuit 330, the selection signal generator 331, and the selector 332 as described herein.

[0090] The selection signal generator 331 may be based on Figure 2 The gain calibration circuit 310 provides a completion signal DONE and a frequency lock signal LOCK F Generate a selection signal SEL. For example, when the frequency lock signal LOCK F When the frequency lock signal LOCK is logic low or when the completion signal DONE is logic high, the selection signal SEL can be logic low; F When the select signal SEL is logic high and the completion signal DONE is logic low, the select signal SEL may be logic high.

[0091] The selector 332 may select the Figure 2 The initial gain value CD output by the gain calibration circuit 310 is IG and the control code value CD output from the DTC calibration circuit 320 CAL and can provide the selected value as Figure 2 For example, when the selection signal SEL is logic high, the initial gain value CD may be selected. IG ; When the selection signal SEL is logic low, the control code value CD can be selected CAL Therefore, when Figure 2 The phase-locked loop circuit 1000 is based on the initial gain value CD for frequency locking operation IGWhen performing a coarse locking operation or a fine locking operation, the control code value CD CAL may be provided as an input code ICD of the DTC 200, and when the gain calibration circuit 310 calibrates the initial gain value CD by performing a binary search operation IG When the initial gain value CD IG may be provided as an input code ICD of the DTC 200 .

[0092] Fig. 8A and 8B It is used to illustrate Figure 2 1 is a block diagram of an output path of the DTC controller 300 in the phase-locked loop circuit 1000.

[0093] refer to Fig. 8A , the gain calibration circuit 310 may respond to the activated frequency lock signal LOCK F To perform a binary search operation. Accordingly, the gain calibration circuit 310 can calibrate the initial gain value CD IG , and can provide an initial gain value CD under the control of the output control circuit 330 IG As the input code ICD of the DTC 200. In this case, the DTC calibration circuit 320 may be disabled and not driven.

[0094] refer to Figure 8B , the DTC calibration circuit 320 may be driven in response to the completion signal DONE output from the gain calibration circuit 310. In this case, the phase-locked loop circuit 1000 may perform a fine locking operation, and the DTC calibration circuit 320 may generate a control code value CD for calibrating the delay amount of the DTC 200 to correspond to the QE CAL , and can provide a control code value CD under the control of the output control circuit 330 CAL As the input code ICD of DTC 200. In this case, after setting the initial gain value CD IG After the completion signal DONE is provided to the DTC calibration circuit 320, the gain calibration circuit 310 may be disabled and may not be driven. In addition, as further discussed above, when the phase-locked loop circuit 1000 performs a coarse lock operation for frequency locking, the gain calibration circuit 310 may not be driven, such as Figure 8B shown.

[0095] Fig.9A is a timing diagram illustrating a locking time of a phase locked loop circuit according to some example embodiments. Fig. 9B is a timing chart showing a locking time according to a comparative example.

[0096] refer to Fig.9A, in a phase-locked loop circuit (eg, Figure 2 In the phase-locked loop circuit 1000), when the frequency F of the output clock signal OUT Close to the target frequency F TV When the frequency lock signal LOCK F For example, the frequency lock signal LOCK F Can go from logic low to logic high. Figure 2 The gain calibration circuit 310 can respond to the frequency lock signal LOCK F is driven, and the initial gain value CD can be calibrated by performing a binary search operation based on a binary search algorithm IG The gain calibration circuit 310 may be driven in a foreground manner. A binary search operation is performed in the interval TP1, and when the binary search operation is completed, the initial gain value CD IG Can be used as gain value G DTC Therefore, the gain value G DTC Becoming close to the target gain value G TV . Figure 2 The DTC calibration circuit 320 is based on the gain value G DTC A fine locking operation is performed. The DTC calibration circuit 320 may be driven in a background manner.

[0097] refer to Fig. 9B The phase-locked loop circuit according to the comparative example does not include the gain calibration circuit 310, and may not generate the initial gain value CD separately. IG .

[0098] The phase-locked loop circuit according to the comparative example may be driven in a background manner to allow the gain value G DTC At the output clock signal frequency F OUT Becoming close to frequency F TV The target gain value G is reached when TV For example, the DTC calibration circuit can generate the gain value G by accumulating the code of QE and the correlation value of the phase difference signal UD. DTC Since the correlation value between the QE code and the phase difference signal UD is +1 or -1, when the gain value G DTC When the initial value is '0', the gain value G DTC Achieve Target G TV The delay may be too large. As shown in the figure, the gain value G DTC can gradually increase in the interval TP2, and thus can reach the target gain value G TV In comparison Fig.9A and Fig. 9B When compared with the combination Fig. 9B The phase-locked loop circuit of the comparative example discussed, according to some example embodiments Figure 2 The phase-locked loop circuit 1000 enables the operation of the DTC 200 with a gain value G DTC Reach the target gain value G TV The period taken is relatively short, so the locking time of the phase-locked loop circuit 1000 can be reduced relative to the phase-locked loop circuit of the comparative example.

[0099] Fig.10 is a block diagram of a phase-locked loop circuit 2000 in which a phase detector is implemented as a time-to-digital converter according to some example embodiments.

[0100] refer to Fig.10 The phase-locked loop circuit 2000 may include a phase-locked loop 100a, a DTC 200, a DTC controller 300a, and a modulator 400. The phase-locked loop 100a may be a fractional-N digital phase-locked loop, and the phase-locked loop circuit 2000 may generate a received reference clock signal CLK having a frequency of REF The output clock signal CLK is N times the frequency (where N is a real number equal to or greater than 1) of OUT The DTC 200, the DTC controller 300a and the modulator 400 may be combined with Figure 2 The DTC 200, DTC controller 300, and modulator discussed are similar or identical.

[0101] The phase-locked loop 100a may include a frequency detector 110a, a phase detector 120a, a digital loop filter (D-LPF) 140a, an oscillator 150a, and a multi-mode frequency divider 160a. Any or all of the frequency detector 110a, the phase detector 120a, the digital loop filter 140a, the oscillator 150a, and the multi-mode frequency divider 160a may be implemented by, for example, a circuit or line, or alternatively by at least one processor executing program code including instructions corresponding to any or all operations performed by the phase-locked loop 100a, the frequency detector 110a, the phase detector 120a, the digital loop filter 140a, the oscillator 150a, and the multi-mode frequency divider 160a as described herein.

[0102] The frequency detector 110a can detect (eg, determine) the frequency-divided clock signal CLK DIV and delay the clock signal CLK D The frequency difference between the two, and when the divided clock signal CLK DIV and delay the clock signal CLK D When the frequencies are equal or similar, a frequency lock signal LOCK with an effective level can be generated. F .

[0103] The phase detector 120a may be implemented as a time-to-digital converter. The phase detector 120a may detect (eg, determine) the delay lock signal CLK D And the divided clock signal CLK DIV and a phase difference data value DV corresponding to the phase difference can be generated.

[0104] The digital loop filter 140a may perform low-pass filtering on the phase difference data value DV, and may generate a control value CV by filtering out noise and high-frequency signals from the phase difference data value DV. The oscillator 150a may generate an output clock signal CLK based on the control value CV. OUT .

[0105] The operation of the multi-mode frequency divider 160a and the modulator 400 is identical or similar to that of the reference Figure 2 The operations of the multi-mode frequency divider 160 and the modulator 400 of the phase-locked loop circuit 1000 are described above, and thus repeated description will be omitted here.

[0106] The gain calibration circuit 310 can be based on the reference clock signal CLK REF and delay the clock signal CLK D The delay amount of DTC 200 is obtained, and the initial gain value CD can be derived based on the binary search algorithm according to the result obtained by comparing the delay amount with one cycle of the output clock signal. IG .

[0107] When the initial gain value CD is derived from the gain calibration circuit 310 IG When the completion signal DONE is output, the DTC calibration circuit 320a may be based on the initial gain value CD provided together with the completion signal DONE. IG Generate control code value CD CAL The DTC calibration circuit 320a may receive the phase difference data value DV from the phase-locked loop 100a and QE from the modulator 400, and may be based on the initial gain value CD IG , phase difference data value DV and QE generate control code value CD CAL , so the output clock signal CLK OUT The phase can be locked to the reference clock signal CLK REF .

[0108] Fig.11 is a flow chart of a method of operating a phase locked loop circuit according to some example embodiments. Fig.11 The method is a method of operating a phase-locked loop circuit including a DTC and a DTC controller. The method can be applied to Figure 2 and Fig.10 The phase-locked loop circuits 1000 and 2000, and reference Figure 2and Fig.10 The description provided can be applied to Fig.11 .

[0109] refer to Figure 2 and Fig.11 In operation S10, the phase-locked loop circuit may generate an output clock signal having a target frequency. The phase-locked loop circuit may perform a coarse locking operation, and accordingly, the frequency of the output clock signal may reach the target frequency.

[0110] In operation S20, the phase-locked loop circuit (specifically, Figure 2 The gain calibration circuit 310 of the DTC may compare the delay amount of the DTC with one cycle of the output clock signal, and may derive (e.g., determine) an initial gain value of the DTC based on the comparison result. The gain calibration circuit 310 may perform a binary search operation based on the comparison result, and may calibrate the initial gain value of the DTC. The gain calibration circuit 310 may derive a code value for controlling the DTC to delay the reference clock signal for a period of time corresponding to one cycle of the output clock signal as the initial gain value.

[0111] In operation S30, the phase-locked loop circuit can lock the phase of the output clock signal by calibrating the delay amount of the DTC based on the initial gain value. In other words, the phase-locked loop circuit can perform a fine locking operation based on the initial gain value, and accordingly, the phase of the output clock signal can become similar to or equal to the phase of the reference clock signal (the output signal having a target frequency and a phase identical or similar to the reference clock signal is also referred to herein as a "target output clock signal").

[0112] Fig.12 is the operation of deriving the initial gain value of the DTC (for example, Fig.11 Flow chart of operation S20). Fig.12 The method shown can be Figure 2 The gain calibration circuit 310 performs.

[0113] refer to Figure 2 and Fig.11 In operation S21, the gain calibration circuit 310 may control the DTC based on a default value of the initial gain value (eg, Figure 2 DTC 200 of the present invention). In some example embodiments, the default value of the initial gain value may be the median of the input code. For example, when the input code is a 5-bit signal, the default value of the initial gain value may be '10000'. The default value of the initial gain value may be provided as the input code. Accordingly, the DTC 200 may generate a delayed clock signal that delays the reference clock signal by a delay amount corresponding to the default value of the initial gain value. The gain calibration circuit 310 may set the current bit of the initial gain value to the most significant bit of the initial gain value.

[0114] In operation S22, the gain calibration circuit 310 may compare one cycle of the output clock signal with the delay amount of the DTC 200. For example, the gain calibration circuit 310 may obtain the delay amount of the DTC 200, that is, the time difference between the reference clock signal and the delayed clock signal, and may obtain a pulse signal corresponding to one cycle of the output clock signal. The gain calibration circuit 310 may convert the time difference and the pulse signal into a first digital code and a second digital code, respectively, and may compare the first digital code with the second digital code.

[0115] In operation S23, the gain calibration circuit 310 may calibrate the current bit of the initial gain value based on the comparison result and the binary search algorithm. The gain calibration circuit 310 may perform a binary search operation based on the comparison result and may calibrate the current bit of the initial gain value.

[0116] In operation S24, the gain calibration circuit 310 may check whether the least significant bit of the initial gain value is calibrated. When the least significant bit of the initial gain value is not calibrated, the gain calibration circuit 310 may shift the current bit to the next most significant bit in operation S25, may determine that the binary search operation has not been completed, and may control the DTC based on the calibrated initial gain value. Then, the gain calibration circuit 310 may perform operations S22 and S23, and may calibrate the initial gain value.

[0117] When the least significant bit of the initial gain value is calibrated, the gain calibration circuit 310 may determine in operation S26 that the binary search operation has been completed and may output a completion signal indicating the completion of the binary search operation.

[0118] Fig.13 is a block diagram of a wireless communication device 3000 including a phase-locked loop circuit, according to some example embodiments.

[0119] The wireless communication device 3000 may include an antenna 3400 and may send and / or receive signals via the antenna 3400 so that the wireless communication device 3000 may communicate with other devices (eg, other wireless communication devices, base stations, etc.).

[0120] The wireless communication system in which the wireless communication device 3000 communicates with other devices is a non-limiting example, and may be a wireless communication system using a cellular network, such as a fifth generation (5G) wireless system, a long term evolution (LTE) system, an LTE advanced system, a code division multiple access (CDMA) system, a global system for mobile communications (GSM) system, a wireless local area network (WLAN) system, or other wireless communication systems.

[0121] like Fig.13As shown, the wireless communication device 3000 may include a signal processor 3100, a transceiver 3200, a transmit / receive duplexer (TX / RX DPX) 3300, and an antenna 3400. The transmit / receive duplexer 3300 may provide a signal received via the antenna 3400 as a radio frequency (RF) input signal RFin to the transceiver 3200, and / or provide an RF output signal RFout received from the transceiver 3200 to the antenna 3400.

[0122] The signal processor 3100 may process a transmission signal and / or a reception signal in a baseband. The signal processor 3100 may include a controller 3110, and the controller 3110 may control the transceiver 3200. In some example embodiments, the controller 3110 may output a frequency control signal.

[0123] The transceiver 3200 may include a transmitter 3210, a receiver 3220, and a phase-locked loop circuit (PLL) 3230. The transmitter 3210 may process a transmit input signal TXin received from the signal processor 3100, and may generate an RF output signal RFout. As shown, the transmitter 3210 may include a variable gain amplifier (VGA) 3211, a TX filter 3212, a TX mixer 3213, and a power amplifier (PA) 3214 to process the transmit input signal TXin.

[0124] The receiver 3220 may process the RF input signal RFin and may generate a reception input signal RXin, thereby providing the generated reception input signal RXin to the signal processor 3100. The receiver 3220 may include a low noise amplifier (LNA) 3221, an RX mixer 3222, a variable gain amplifier (VGA) 3223, and an RX filter 3224 to process the RF input signal RFin. Any one or all of the signal processor 3100, the RX controller 3110, the variable gain amplifier 3211, the TX filter 3212, the TX mixer 3213, the power amplifier 3214, the low noise amplifier 3221, the RX mixer 3222, the variable gain amplifier 3223, the RX filter 3224, and the transmit / receive duplexer 3300 may be implemented by, for example, a circuit or line, or alternatively by at least one processor executing program code including instructions corresponding to any or all operations performed by the wireless communication device 3000, the signal processor 3100, the RX controller 3110, the transceiver 3200, the transmitter 3210, the receiver 3220, the variable gain amplifier 3211, the TX filter 3212, the TX mixer 3213, the power amplifier 3214, the low noise amplifier 3221, the RX mixer 3222, the variable gain amplifier 3223, the RX filter 3224, and the transmit / receive duplexer 3300 as described herein.

[0125] The phase-locked loop circuit 3230 can generate a local oscillation signal, i.e., a clock signal, which provides a frequency for sampling the transmit input signal TXin and the RF input signal RFin. The output clock signal of the phase-locked loop circuit 3230 can be provided to the TX mixer 3213 of the transmitter 3210 and the RF mixer 3222 of the receiver 3220.

[0126] According to reference Figures 1 to 12 The clock signal generator 10 and the phase-locked loop circuits 1000 and 2000 of some example embodiments described may be applied to Fig.13The phase-locked loop circuit 3230. The phase-locked loop circuit 3230 may include a DTC and a DTC controller, the DTC generating a delayed clock signal by delaying a reference clock signal by a delay amount corresponding to an input code, and the DTC controller being used to control the delay amount of the DTC. The phase-locked loop circuit 3230 may generate an output clock signal based on the delayed clock signal. The phase-locked loop circuit 3230 may change the frequency of the output clock signal in response to a received frequency control signal. The DTC controller may quickly derive an initial gain value for setting the delay amount to be similar to or equal to one cycle of the output clock signal based on a binary search algorithm and a result obtained by comparing the delay amount of the DTC with one cycle of the output clock signal. The DTC controller may control the delay amount of the DTC based on the initial gain value. Therefore, when the frequency of the output clock signal changes, the locking time of the phase-locked loop circuit 3230 may be reduced.

[0127] The transceiver 3200 may allow the transmitter 3210 and the receiver 3220 to process the transmission signal and / or the reception signal in time continuously according to the duplex mode of the time sequence. In this case, the frequencies of the transmission signal and the reception signal, that is, the RF output signal RFout and the RF input signal RFin may be different. Since the locking time of the phase-locked loop circuit 3230 according to some example embodiments is short, the frequency of the output clock signal may be quickly changed to the target frequency. For example, the phase-locked loop circuit 3230 may quickly change the frequency of the output clock signal from the transmission frequency to the reception frequency, or from the reception frequency to the transmission frequency.

[0128] While the inventive concept has been particularly shown and described with reference to certain example embodiments, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A clock signal generator, the clock signal generator being configured to generate a target output clock signal based on a reference clock signal, the clock signal generator comprising: A digital time converter, i.e., DTC, is configured to: delaying the reference clock signal based on an input code to generate a delayed clock signal, and Outputting the delayed clock signal; A DTC controller, the DTC controller being configured to: determining an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generating the input code based on the initial gain value; as well as a phase-locked loop configured to generate the target output clock signal based on the delayed clock signal and a divided clock signal of the previously generated output clock signal, the target output clock signal being locked to the delayed clock signal, Wherein, the DTC controller includes a gain calibration circuit, and the gain calibration circuit is configured as follows: determining the at least one delay amount of the DTC based on the reference clock signal and at least one previously generated delayed clock signal; and determining the initial gain value by performing a binary search operation based on a result of comparing the at least one delay amount of the DTC and a period of the previously generated output clock signal, Wherein, the gain calibration circuit comprises: a first time-to-digital converter configured to convert the at least one delay amount into at least one first digital code; a second time-to-digital converter configured to convert a period of the previously generated output clock signal into a second digital code; a comparator configured to compare a corresponding value of the at least one first digital code with a corresponding value of the second digital code to generate at least one comparison result; and A decoder is configured to determine the initial gain value based on the at least one comparison result of the comparator.

2. The clock signal generator according to claim 1, wherein: The initial gain value includes a code value corresponding to a ratio of a period of the previously generated output clock signal to a unit delay amount of the DTC.

3. The clock signal generator according to claim 1, wherein: The gain calibration circuit is further configured to complete the binary search operation within a time period equal to a product of a number of bits of the input code and a period of the reference clock signal.

4. The clock signal generator according to claim 1, wherein: The gain calibration circuit is activated in response to a frequency lock signal indicating that the previously generated output clock signal has a target frequency.

5. The clock signal generator according to claim 1, wherein: The phase-locked loop comprises: a phase detector configured to determine a phase difference between the delayed clock signal and the divided clock signal; a frequency detector configured to determine a frequency difference between the delayed clock signal and the divided clock signal; an oscillator configured to generate the target output clock signal based on the phase difference and the frequency difference; a frequency divider configured to generate the divided clock signal by dividing the frequency of the previously generated output clock signal; and A modulator, the modulator being configured to: changing the integer division ratio of the frequency divider so that the average division ratio of the frequency divider has a target value, and A quantization error value is provided to the DTC, the quantization error value indicating a quantization error occurring according to the changed integer division ratio.

6. The clock signal generator according to claim 5, wherein: The DTC controller includes a DTC calibration circuit configured to generate a control code value based on at least one phase difference between at least one previously generated delayed clock signal and the divided clock signal, the quantization error value of the phase locked loop, and the initial gain value.

7. The clock signal generator according to claim 6, wherein: The DTC calibration circuit comprises: a correlation circuit configured to output a correlation value of the at least one phase difference and a code of the quantization error value; an integrator configured to generate a calibrated gain value by accumulating the correlation value and the initial gain value; and A multiplier is configured to generate the control code value by multiplying the quantization error value and the calibrated gain value.

8. The clock signal generator according to claim 7, wherein: The DTC controller is further configured to: providing the initial gain value as the input code to the DTC when the previously generated output clock signal has a target frequency; as well as When the initial gain value is a target gain value, the control code value is provided to the DTC as the input code.

9. A phase-locked loop circuit, comprising: a phase-locked loop configured to generate a target output clock signal based on a divided clock signal of a previously generated output clock signal and an input clock signal, the target output clock signal being locked to the input clock signal; A modulator, the modulator being configured to: changing the division ratio of the phase-locked loop, and Output the error value according to the changed frequency division ratio; A digital time converter, i.e., DTC, is configured to: delaying a reference clock signal based on an input code to generate the input clock signal, providing the input clock signal to the phase locked loop; as well as A DTC controller, the DTC controller being configured to: determining an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generating the input code based on the initial gain value, wherein the DTC controller includes a gain calibration circuit configured to determine the initial gain value by performing a binary search operation based on a result obtained by comparing the at least one delay amount of the DTC with a period of the previously generated output clock signal, Wherein, the gain calibration circuit comprises: a first time-to-digital converter configured to convert the at least one delay amount into at least one first digital code; a second time-to-digital converter configured to convert a period of the previously generated output clock signal into a second digital code; a comparator configured to compare a corresponding value of the at least one first digital code with a corresponding value of the second digital code to generate at least one comparison result; and A decoder is configured to determine the initial gain value based on the at least one comparison result of the comparator.

10. The phase-locked loop circuit according to claim 9, wherein: The DTC controller also includes a DTC calibration circuit configured to output a control code value based on at least one phase difference between at least one previously generated first input clock signal and the divided clock signal, the error value, and the initial gain value.

11. The phase-locked loop circuit according to claim 10, wherein: The gain calibration circuit further includes: a logic gate configured to determine the at least one delay amount based on the reference clock signal and at least one previously generated second input clock signal; a pulse generator configured to generate a pulse signal indicative of a period of the previously generated output clock signal; and A time-to-digital converter is configured to convert the at least one delay amount and the pulse signal into a digital code.

12. The phase-locked loop circuit according to claim 10, wherein: The DTC controller further includes an output control circuit, wherein the output control circuit is configured to: selecting one of the initial gain value or the control code value based on a frequency lock signal output from the phase-locked loop and an operation completion signal output from the gain calibration circuit; as well as A selected one of the initial gain value or the control code value is provided to the DTC as the input code.

13. The phase-locked loop circuit according to claim 12, wherein: The output control circuit is configured as: When the frequency lock signal is in a valid state and the operation completion signal is in an invalid state, selecting the initial gain value; as well as The control code value is selected when the frequency lock signal is in an invalid state or the operation completion signal is in a valid state.

14. The phase-locked loop circuit according to claim 9, wherein: The phase-locked loop comprises: a phase detector configured to determine a phase difference between the input clock signal and the divided clock signal; A frequency detector, the frequency detector being configured to: determining a frequency difference between the input clock signal and the divided clock signal, and generating a frequency lock signal based on the determined frequency difference; a charge pump configured to generate a current signal corresponding to the phase difference; a loop filter configured to generate an oscillating control voltage by integrating the current signal; an oscillator configured to generate the target output clock signal based on the oscillation control voltage; and A frequency divider is configured to generate the divided clock signal by dividing the frequency of the previously generated output clock signal.

15. The phase-locked loop circuit according to claim 9, wherein: The phase-locked loop comprises: A time-to-digital converter, the time-to-digital converter being configured to: determining a phase difference between the input clock signal and the divided clock signal, and converting the phase difference into a digital value; a digital loop filter configured to generate an oscillation control signal by integrating the digital value received from the time-to-digital converter; an oscillator configured to generate the target output clock signal based on the oscillation control signal; and A frequency divider is configured to generate the divided clock signal by dividing the frequency of the previously generated output clock signal.

16. A method of operating a phase locked loop circuit, the phase locked loop circuit comprising a digital time converter (DTC) configured to delay a reference clock signal to provide an input clock signal, the method comprising: generating a target output clock signal having a target frequency by locking the frequency of a divided clock signal of a previously generated output clock signal to the frequency of the input clock signal; determining an initial gain value of the DTC by performing a binary search operation based on a result of comparing at least one time difference between the reference clock signal and at least one previously generated input clock signal and a period of the previously generated output clock signal; as well as Based on the initial gain value, the phase of the target output clock signal is locked to the phase of the reference clock signal by calibrating the delay amount of the DTC, Wherein, determining the initial gain value comprises: obtaining the at least one time difference between the reference clock signal and the at least one previously generated input clock signal; Acquire a pulse signal corresponding to the period of the previously generated output clock signal; converting the at least one time difference and the pulse signal into at least one first digital code and a second digital code, respectively; comparing a corresponding value of the at least one first digital code with a corresponding value of the second digital code; and By performing the binary search operation based on the comparing the corresponding values, the initial gain value is calibrated.

17. The method according to claim 16, wherein When the last bit of the initial gain value is not calibrated, the acquiring of the at least one time difference is performed based on the calibrated initial gain value; and Determining the initial gain value comprises: When the last bit of the initial gain value is calibrated, a binary search completion signal is output.

18. The method according to claim 17, wherein: Locking the phase of the target output clock signal to the phase of the reference clock signal is performed in response to the binary search complete signal.

19. A wireless communication device, comprising: A signal processor, the signal processor being configured to: Processes receive and transmit signals in baseband, and Output frequency control signal; a transceiver configured to perform a transmitting operation and a receiving operation successively in time; as well as a clock signal generator configured to generate a target output clock signal for providing a frequency for sampling the transmission signal and the reception signal in response to the frequency control signal, Wherein, the clock signal generator comprises: A phase-locked loop, the phase-locked loop being configured as: generating the target output clock signal based on a divided clock signal of a previously generated output clock signal and an input clock signal, the target output clock signal being locked to the input clock signal, and changing a frequency division ratio for generating the frequency-divided clock signal based on the frequency control signal; A digital time converter, namely DTC, is configured to: delaying a reference clock signal based on an input code to generate the input clock signal, and providing the input clock signal to the phase locked loop; and A DTC controller, the DTC controller being configured to: determining an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of the previously generated output clock signal, and generating the input code based on the initial gain value, Wherein, the DTC controller includes a gain calibration circuit, and the gain calibration circuit is configured as follows: comparing the at least one delay amount of the DTC with a period of the previously generated output clock signal, and determining the initial gain value by performing a binary search operation based on the comparison, Wherein, the gain calibration circuit comprises: a first time-to-digital converter configured to convert the at least one delay amount into at least one first digital code; a second time-to-digital converter configured to convert a period of the previously generated output clock signal into a second digital code; a comparator configured to compare a corresponding value of the at least one first digital code with a corresponding value of the second digital code to generate at least one comparison result; and A decoder is configured to determine the initial gain value based on the at least one comparison result of the comparator.

20. The wireless communication device according to claim 19, wherein: The DTC controller further includes a DTC calibration circuit configured to output a control code value based on at least one phase difference between at least one previously generated input clock signal and the divided clock signal, an error value according to a change in the division ratio, and the initial gain value.

21. The wireless communication device according to claim 19, wherein: The phase-locked loop comprises a fractional-N phase-locked loop.

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