Memory and signal processing method

Abstract

This application discloses a memory and a signal processing method. The memory includes: a latch circuit, a decoding circuit, a memory array, a read circuit, and a write circuit. The memory array includes M rows and N columns of bit cells, each of which is used to store 1 bit of data, and the bit cell includes a first port and a second port. The latch circuit is used to receive a first address and a second address. The decoding circuit is used to determine a first bit cell based on the first address and a second bit cell based on the second address. The write circuit is used to receive data and write data to the first bit cell through the first port of the first bit cell. The read circuit is used to read data stored in the first bit cell through the first port of the first bit cell and also to read data stored in the second bit cell through the second port of the second bit cell. Implementing this application can achieve a 1R1RW function.

Description

Technical Field

[0001] The present application relates to the field of communication and storage technology, and in particular to a memory and a signal processing method. Background Art

[0002] Static random access memory (SRAM) is a widely used semiconductor memory that can be used in various scenarios. For example, it can be used to design Ethernet switch chips to provide cache and table storage functions.

[0003] The data in SRAM is stored in a memory array composed of bit cells, where each bit cell stores one bit of data. Depending on the bit cell structure, the basic SRAM provided by memory vendors includes the following:

[0004] (1) Single-port SRAM (SP SRAM) provides one port that can perform read or write operations, also known as 1 read or 1 write (1RW) SRAM.

[0005] (2) Two-port SRAM (TP SRAM) provides one port for write operations and one port for read operations, also known as 1 read and 1 write (1R1W) SRAM.

[0006] (3) Dual-port SRAM (DP SRAM) provides two ports that can perform read or write operations, also known as 2read and 2write (2R2W) SRAM.

[0007] When memory vendors only provide the above-mentioned basic SRAMs, multi-port SRAMs need to be constructed based on the above-mentioned basic SRAMs, such as 2R1W (supporting 2 read ports and 1 write port) SRAM, 1R2W SRAM, 2R2W SRAM, etc., to meet actual needs.

[0008] Currently, 2R1W SRAM is being used in increasingly diverse scenarios. For example, it is used in system-on-chip (SOC) to provide flexible and efficient storage access. Many network chips require 2R1W SRAM. Therefore, how to construct or design a usable 2R1W SRAM based on basic SRAM is an urgent problem that needs to be solved. Summary of the Invention

[0009] The present application provides a memory and a signal processing method, which can realize the 1R1RW function and avoid waste of area and power consumption.

[0010] In a first aspect, the present application provides a memory comprising: a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit, wherein the latch circuit is connected to the decoding circuit, and the storage array is connected to the decoding circuit, the read circuit, and the write circuit, wherein:

[0011] The storage array includes M rows and N columns of bit cells, each bit cell is used to store 1 bit of data, and the bit cell includes a first port and a second port;

[0012] The latch circuit is used for receiving the first address and the second address;

[0013] The decoding circuit is used to determine a first bit unit among the M*N bit units according to the first address, and is also used to determine a second bit unit among the M*N bit units according to the second address;

[0014] The write circuit is used to receive data and write the received data into the first bit unit through the first port of the first bit unit;

[0015] The read circuit is used to read out data stored in the first bit unit through the first port of the first bit unit, and the read circuit is also used to read out data stored in the second bit unit through the second port of the second bit unit.

[0016] As can be seen from the above, the memory of the first aspect provides two ports, one of which can be used to perform a read operation, and the other port can be used to perform a read operation or a write operation (perform a read operation or a write operation at one point in time), thereby realizing the 1R1RW function.

[0017] In an optional embodiment, the connection relationship of the M rows and N columns of the storage array of the present application is as follows: each bit cell in the i-th row of bit cells is connected to the i-th positive bit line, the i-th inverted bit line, and the i-th read bit line; each bit cell in the j-th column of bit cells is connected to the j-th read / write word line and the j-th read word line; wherein, 1≤i≤M, 1≤j≤N, i and j are positive integers; the i-th positive bit line, the i-th inverted bit line, and the j-th read / write word line constitute the first port, and the i-th read bit line and the j-th read word line constitute the second port.

[0018] In an alternative embodiment, each bit cell in the memory array has the same structure. The bit cell in row i, column j is used as an example for description. The bit cell in row i, column j includes eight MOS transistors M1-M8, where M1, M3, M5, M6, M7, and M8 are N-MOS transistors, and M2 and M4 are P-MOS transistors. Among them, the source of M2 and the source of M4 are connected to a high level, and the source of M1 and the source of M3 are connected to a low level; the source of M6, the gate of M2, the gate of M1, the drain of M4 and the drain of M3 are connected; the source of M5, the gate of M4, the gate of M3, the drain of M2 and the drain of M1 are connected; the gate of M5 and the gate of M6 are connected to the jth read / write word line; the drain of M5 is connected to the i-th positive bit line, and the drain of M6 is connected to the i-th inverted bit line; the gate of M8 is connected to the j-th read word line, and the drain of M8 is connected to the i-th read bit line; the source of M8 is connected to the drain of M7, and the source of M7 is connected to a low level.

[0019] As can be seen from the structure of the storage array in the above optional implementation, the present application fully utilizes the structure of the bit unit, using one port of the bit unit to perform a read operation and the other port to perform a read operation or a write operation, thereby realizing the 1R1RW function.

[0020] In an optional embodiment, the read circuit includes: a first sense amplifier and a second sense amplifier, wherein the first sense amplifier is SA and the second sense amplifier is ASA. The first input of the first sense amplifier is connected to the i-th positive bit line, and the second input is connected to the i-th inverted bit line; the input of the second sense amplifier is connected to the i-th read bit line. The read circuit is configured to read the data stored in the first bit unit through the first port of the first bit unit, specifically including: the read circuit is configured to amplify the difference between the voltages received at the first input and the second input via the first sense amplifier, and then output the difference through the output of the first sense amplifier. The read circuit is also configured to read the data stored in the second bit unit through the second port of the second bit unit, specifically including: the read circuit is configured to amplify the voltage received at the input of the second sense amplifier via the second sense amplifier, and then output the difference through the output of the second sense amplifier.

[0021] Here, a second sense amplifier is used in the read circuit to amplify the voltage signal on the read word line, ensuring sufficient driving force for subsequent circuits when reading the signal. This allows one port in the bit cell of the present application to implement a write function while also adding a read function, thereby achieving a 1R1RW function. In other words, the memory of the present application can achieve a 1R1RW function while fully utilizing the read and write functions of the bit cell and rationally planning the area and power consumption.

[0022] In an optional embodiment, the two ports of the bit unit of the present application are respectively configured with corresponding peripheral circuits, specifically as follows:

[0023] The latch circuit includes: a first address latch circuit and a second address latch circuit; the first address latch circuit is used to receive a first address, and the second address latch circuit is used to receive a second address;

[0024] The decoding circuit includes: a first decoding circuit and a second decoding circuit; the first decoding circuit is used to determine the first bit unit among the M*N bit units according to the first address, and the second decoding circuit is used to determine the second bit unit among the M*N bit units according to the second address;

[0025] The first latch circuit is connected to the first decoding circuit, the second latch circuit is connected to the second decoding circuit, the first decoding circuit is connected to the storage array through the first port, and the second decoding circuit is connected to the storage array through the second port;

[0026] The read circuit includes: a first read circuit and a second read circuit; the first read circuit is used to read the data stored in the first bit unit through the first port of the first bit unit, and the second read circuit is used to read the data stored in the second bit unit through the second port of the second bit unit;

[0027] The first read circuit is connected to the memory array through a first port, and the second read circuit is connected to the memory array through a second port.

[0028] In an optional embodiment, the core circuit of the memory provided herein may include, in addition to the latch circuit, decoding circuit, memory array, read circuit, and write circuit, a control circuit for providing memory operation power. The control circuit is connected to the latch circuit, decoding circuit, write circuit, and read circuit; the control circuit is configured to receive a first signal and a second signal, the first signal being configured to instruct the memory to perform a read operation or a write operation via the first port, and the second signal being configured to instruct the memory to perform a read operation via the second port.

[0029] In an optional embodiment, the latch circuit is also used to receive a read / write enable signal. When the read / write enable signal takes a first value, the first signal is specifically used to instruct the memory to perform a write operation through the first port; when the read / write enable signal takes a second value, the first signal is specifically used to instruct the memory to perform a read operation through the first port.

[0030] In an optional embodiment, the first signal includes a first port enable signal and a first port clock signal; the control circuit is further configured to provide a clock signal to the latch circuit, the decoding circuit, and the write circuit, or to provide a clock signal to the latch circuit, the decoding circuit, and the read circuit, upon receiving the first signal. The second signal includes a second port enable signal and a second port clock signal; the control circuit is further configured to provide a clock signal to the latch circuit, the decoding circuit, and the read circuit, upon receiving the second signal.

[0031] In a second aspect, the present application provides a signal processing method, comprising: a memory receiving an instruction, the instruction including at least one of a first instruction or a second instruction; the memory is the memory provided by the first aspect and any one of the embodiments of the first aspect; wherein the first instruction carries a first address, or the first instruction carries the first address and data; and the second instruction carries a second address;

[0032] In the case where the instruction includes a first instruction and the first instruction carries a first address, the memory reads data stored in a first bit unit corresponding to the first address through the first port according to the first instruction; or

[0033] When the instruction includes a first instruction and the first instruction carries a first address and data, the memory writes data to the first bit unit through the first port according to the first instruction;

[0034] In a case where the instruction includes a second instruction, the memory reads data stored in a second bit unit corresponding to the second address through a second port according to the second instruction.

[0035] By implementing the present application, the 1R1RW function can be realized while fully utilizing the read and write functions of the bit unit and rationally planning the area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1A Schematic diagram of the structure of the bit unit of SP SRAM;

[0037] Figure 1B Another structural diagram of a bit cell of SP SRAM;

[0038] Figure 2 Schematic diagram of the structure of the bit unit of TP SRAM;

[0039] Figure 3 Schematic diagram of the structure of the bit unit of DP SRAM;

[0040] Figure 4 Schematic diagram of a 1R1W SRAM module in the prior art;

[0041] Figure 5 To utilize Figure 2 Schematic diagram of the module of 1R1RW SRAM implemented by the bit cell shown;

[0042] Figure 6 This is a module diagram of the 1R1RW SRAM of this application;

[0043] Figure 7 Schematic diagram of the structure of the 1R1RW SRAM provided in this application;

[0044] Figure 8Another structural diagram of the 1R1RW SRAM provided in this application;

[0045] Figure 9 A schematic diagram of the structure of the latch circuit provided in this application;

[0046] Figure 10 A schematic diagram of the structure of the writing circuit provided in this application;

[0047] Figure 11 A schematic diagram of the structure of the storage array in the 1R1RW SRAM provided in this application;

[0048] Figure 12 This is a schematic diagram of the structure of the 1R1RW SRAM mid-bit unit provided by this application;

[0049] Figure 13 A schematic diagram of the structure of the ASA provided for this application;

[0050] Figure 14 Schematic diagram of the waveform of the ASA working signal provided in this application;

[0051] Figure 15 This is a flowchart of the signal processing method provided in this application. DETAILED DESCRIPTION

[0052] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0053] In order to better describe the present application, several basic bitcell structures and their working principles are first introduced in detail.

[0054] (1) SP SRAM bitcell

[0055] See also Figure 1A The bit cell in the SP SRAM storage array consists of six metal oxide semiconductor (MOS) field effect transistors, namely six MOS tubes, including two P-channel MOS tubes and four N-channel MOS tubes.

[0056] Figure 1A In the 6T bitcell shown, the four middle MOS transistors are used to store bits, and the other two MOS transistors form control switches from the bitcell to the positive bit line BL and the negative bit line BLB used for reading and writing.

[0057] For simplicity of expression, Figure 1A Simplified to Figure 1BThe four MOS tubes in the middle are simplified into two cross-coupled inverters, with the Q point storing the true value of the bit cell and the QB point storing the inverse value of the bit cell.

[0058] When reading data, the positive and negative bit lines BL and BLB are precharged to a certain voltage (e.g., precharged high). Then, the word line WL is pulled high, turning on M5 and M6. M5 on the left outputs the stored true value, such as "0," to bit line BL, while M6 on the right outputs the stored inverse value, such as "1," to bit line BLB. The connected differential sense amplifier (SA) senses the true value "0" stored in the bit cell, outputting the sensed "0" value.

[0059] When writing data, the written value is loaded onto the bit line. For example, when writing data "1" into the bit cell, the positive bit line BL inputs the true value "1" and the negative bit line BLB inputs the negative value "0", forming complementary inputs. Then, the word line WL is loaded with a high level, M5 and M6 are turned on, and the true value stored in the bit cell is forced to be changed to "1" and the negative value is forced to be changed to "0". Then, the word line WL is loaded with a low level, M5 and M6 are turned off, and the value is saved in the bit cell.

[0060] As can be seen above, the SP SRAM's word line WL, positive bit line BL, and negative bit line BLB form a port that can perform either a read or write operation. Read and write operations cannot be performed simultaneously. Therefore, SP SRAM can also be called 1RW SRAM.

[0061] (2) TP SRAM bitcell

[0062] like Figure 2 As shown in the figure, the bitcell in the TP SRAM memory array consists of eight MOS transistors. Compared to the SP SRAM bitcell, it has two more MOS transistors on the right (M7 and M8). The true value of this bitcell is stored at point Q, and the inverted value is stored at point QB. WWL (write word line) is the write word line, RWL (read word line) is the read word line, WBL (write bitline) and WBLB are the positive and negative write bit lines, and RBL is the read bit line.

[0063] When reading data, the read word line RWL is pulled high, turning on M8. If the true value stored in the bit cell is "0," M7 turns on, and the read bit line RBL reads "0." If the true value stored in the bit cell is "1," QB turns off, and the read bit line RBL reads the pre-charged value "1" of the read / write (IO) circuit connected to the bit cell, achieving the purpose of reading the stored value "1." The pre-charged value for the IO circuit is provided by the memory's control circuit (also called the clock generation circuit).

[0064] When writing data, similar to the above-mentioned SP SRAM, the write word line WWL is increased to a high level to open the write path, and the value enters the feedback circuit composed of M1, M2, M3, and M4 through the forward and reverse write bit lines WBL and WBLB. Then the write word line WWL is increased to a low level to close the write path, and the value is stored in the bit cell.

[0065] As can be seen above, the write word line WWL, forward and reverse write bit lines WBL, and WBLB of a TP SRAM form a port for performing write operations, while the read word line RWL and read bit line RBL form a port for performing read operations. Read and write operations can be performed simultaneously. Therefore, TP SRAM can also be called 1R1W SRAM.

[0066] (3) DP SRAM bitcell

[0067] like Figure 3 As shown, the bitcell in the DP SRAM storage array is also composed of 8 MOS transistors, including two word lines and two sets of positive and negative bit lines. The process of reading and writing data in the bitcell is similar to that of the SP SRAM. Please refer to the previous description and will not be repeated here.

[0068] DP SRAM includes two ports. Word line WL-1, positive and negative bit lines BL-1 and BLB-1 form one port that can perform read or write operations. Word line WL-2, positive and negative bit lines BL-2 and BLB-2 form another port that can perform read or write operations. Read and write operations can be performed simultaneously. Therefore, DP SRAM can also be called 1RW1RWSRAM.

[0069] Several basic bit cells have been introduced above. The following briefly describes how to implement a 2R1W SRAM based on the basic bit cells in the prior art.

[0070] 2R1W SRAM includes two ports, one port can perform read operations, and the other port can perform read operations or write operations. In order to better reflect the correspondence between the ports and read and write functions of the SRAM, in the subsequent description of this application, the 2R1W SRAM is referred to as 1R1RW SRAM, that is, "1R" corresponds to one port, and "1RW" corresponds to the other port. It is understandable that the two ports of 1R1RWSRAM can work separately at the same time without affecting each other, that is, at the same time, one port can perform read operations, and the other port can perform read operations or write operations. It is understandable that when performing read operations and write operations on the same bit unit at the same time through two ports, generally only the accuracy of the write data can be guaranteed, but the accuracy of the read data cannot be guaranteed.

[0071] In the prior art, DP SRAM is used to implement the 1R1RW function. Specifically, the write (W) function of one of the two ports of the DP SRAM is disabled to achieve 1R1RW. Obviously, this design approach, while able to achieve the 1R1RW function, wastes circuit area and power consumption.

[0072] This application proposes a memory that can be used to implement 1R1RW function and avoid waste of circuit area and power consumption. The memory of this application utilizes the above-mentioned (2) basic bitcell, namely Figure 2 The 8-tube (8T) bitcell shown in the figure constitutes a memory array. The memory of the present application includes two ports, one of which can be used to perform a read operation and the other port can be used to perform a read or write operation.

[0073] According to the above Figure 2 As can be seen from the description of the 8T bitcell, the 8T bitcell is usually used to construct TP SRAM, including one port that can perform read operations and one port that can perform write operations. In fact, from the structure of the 8T bitcell, the 8T bitcell can be used to construct one port that can perform read operations and one port that can perform read or write operations (that is, the 6 tubes on the left can be used to implement read or write functions, and the 2 tubes on the right can be used to implement read functions). However, in the existing technology, this type of 8T bitcell structure is not used to construct a 1R1RW memory. The following is a detailed step-by-step explanation of the reasons:

[0074] 1. In the prior art, Figure 2 The array constructed with the 8T bitcell shown has limited capacity.

[0075] Normally, the signal of the stored data read directly from the memory is relatively weak, and a differential sense amplifier (SA) is needed to amplify the read value and output a stronger signal to provide sufficient driving force for the subsequent circuit that uses the stored data, thereby completing the memory access data function.

[0076] The SA used to amplify the signal in the prior art has two input terminals and one output terminal, which is used to amplify the difference between the two input voltages and output it. For example, Figure 1A or Figure 1B The two positive and negative bit lines BL and BLB in the circuit are used to output the read value. The two input terminals of SA can be connected to the positive and negative bit lines BL and BLB respectively. The voltage difference between the positive and negative bit lines BL and BLB input is amplified and output through the output terminal, that is, the value stored in point Q is output.

[0077] However, and Figure 1A or Figure 1B The 6T bitcell shown is different. Figure 2 The two MOS transistors on the right of the 8T bitcell shown are used to read data, and the read data is output through only one read bitline RBL. Since there is only one read bitline RBL, the output signal of the read bitline RBL cannot be amplified using SA. The weak signal output by the read bitline RBL can only be used directly to drive the subsequent circuits. In order to ensure sufficient driving force, the number of bitcells connected to the same bitline is usually limited to 32 or less, resulting in Figure 2 The storage capacity of the array composed of 8T bitcells shown is very limited.

[0078] Specifically, the array includes multiple bitcells in an array configuration. The bitcells in each row share a wordline, and the bitcells in each column share a bitline. Alternatively, the bitcells in each row share a bitline, and the bitcells in each column share a wordline. If the number of bitcells connected to a bitline is limited to 32 or less, then the number of wordlines in the array is also limited to 32 or less, thus limiting the array's storage capacity.

[0079] Due to the limited array capacity, use Figure 2 The layout area of ​​the memory with 8T bitcell structure shown in FIG is relatively large. Figure 4 As shown, in use Figure 2When constructing a large-capacity 1R1W SRAM with a depth of 256, for example, using the 8T bitcell shown, eight arrays need to be spliced ​​together. Each array needs to be configured with corresponding peripheral circuits (such as latch circuits, decoding circuits, and amplifier circuits). The layout area of ​​the 1R1RW SRAM is relatively large.

[0080] 2. If using Figure 2 The 8T bitcell structure 1R1RW SRAM shown in the figure will increase the area of ​​the peripheral circuit.

[0081] Specifically, if you want to use Figure 2 To implement the 1R1RW function in the 8T bitcell shown, Figure 2 The six MOS transistors on the left in the middle must implement not only the write function but also the read function. Therefore, the peripheral circuit must include more related circuits (such as read address decoding circuit, read address latch circuit, etc.) to support the read function, and the area of ​​each peripheral circuit will be greatly increased.

[0082] See also Figure 5 ,use Figure 2 When the 8T bitcell shown is used to implement a 1R1RW SRAM with a depth of 256, the area of ​​each peripheral circuit is greatly increased, resulting in serious waste. No customer is willing to use this construction solution.

[0083] 3. This application uses Figure 2 The 8T bitcell shown implements the 1R1RW function, which can greatly reduce the area of ​​the peripheral circuit.

[0084] In the array of this application, the number of bitcells that can be connected to one bit line is Figure 4 and Figure 5 Therefore, the storage capacity of the array is relatively large. Figure 4 and Figure 5 CUHK. Figure 6 As shown, this application uses Figure 2 When constructing a large capacity 1R1RW SRAM with a depth of 256, for example, the 8T bitcell shown above does not require multiple arrays to be connected together. Instead, only one or a few arrays can be used. Accordingly, only one or a few peripheral circuits need to be configured. Figure 2 The read function of the six MOS transistors on the left side of the 8T bitcell results in an increase in the area of ​​a single peripheral circuit. However, since the number of peripheral circuits is reduced, the layout area of ​​the entire memory is still greatly reduced.

[0085] The structure and implementation principle of the 1R1RW memory of the present application are described in detail below.

[0086] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of the 1R1RW memory provided by this application. Figure 7 As shown, the 1R1RW memory of the present application includes at least the following parts: a latch circuit 101, a decoding circuit 102, a storage array 103, a read circuit 104 and a write circuit 105, wherein the latch circuit 101 is connected to the decoding circuit 102, and the storage array 103 is connected to the decoding circuit 102, the read circuit 104 and the write circuit 105.

[0087] In the present application, the memory array 103 includes M rows and N columns of bit cells, each bit cell is used to store 1 bit of data, and the bit cell includes a first port and a second port;

[0088] The latch circuit 101 is used to receive a first address and a second address;

[0089] The decoding circuit 102 is configured to determine a first bit unit among the M*N bit units according to a first address, and further configured to determine a second bit unit among the M*N bit units according to a second address;

[0090] The write circuit 105 is used to receive data and write the received data into the first bit unit through the first port of the first bit unit;

[0091] The read circuit 104 is used to read data stored in the first bit unit through the first port of the first bit unit. The read circuit 104 is also used to read data stored in the second bit unit through the second port of the second bit unit.

[0092] As can be seen from the above, the 1R1RW memory in this application provides two ports, one of which can be used to perform a read operation, and the other port can be used to perform a read operation or a write operation, thereby realizing the 1R1RW function.

[0093] above Figure 7 The related description briefly explains the structure of the 1R1RW memory of the present application. The following describes the internal structure of each circuit, the connection relationship between each circuit, and the working principle.

[0094] 1. Latch circuit, decoding circuit

[0095] In this application, a latch circuit is used to receive a first address and a second address. Here, the latch circuit can latch the received addresses for use by subsequent circuits. The first address is for the first port, and the second address is for the second port. The first port is the port on which the memory performs read or write operations, and the second port is the port on which the memory performs read operations. The meaning and structure of the first port and the second port can be referred to the subsequent description of the memory array and will not be repeated here.

[0096] In an alternative embodiment, see Figure 8 The latch circuit of the present application includes a first address latch circuit (AA_latch) and a second address latch circuit (AB_latch), the first address latch circuit is used to receive a first address (AA), and the second address latch circuit is used to receive a second address (AB).

[0097] See also Figure 9 , Figure 9 A possible implementation of the latch circuit is shown. The first address latch circuit and the second address latch circuit can be implemented as Figure 9 The latch circuit of the structure shown can also be implemented as a latch circuit of other structures, and this application does not impose any restrictions. Optionally, taking the first address latch circuit as an example, when Figure 9 When the latch circuit is a negative latch, when ICKA (the clock signal with large driving capability generated by the memory clock control signal CLK after passing through the buffer) is at a low level, the first address AA is transmitted from D1 to O1 output, and is inverted and transmitted to ON1 output; when ICKA is at a high level, the latch is in hold mode, maintaining the values ​​at O1 and ON1.

[0098] In the present application, a decoding circuit is configured to determine a first bit cell among the M*N bit cells based on a first address, and further configured to determine a second bit cell among the M*N bit cells based on a second address. It is understood that the first bit cell may be any one of the M*N bit cells of the memory array, and the second bit cell may also be any one of the M*N bit cells of the array. The first bit cell and the second bit cell may be the same bit cell or different bit cells.

[0099] In an alternative embodiment, see Figure 8The decoding circuit of the present application includes a first decoding circuit (W_DEC / R_DEC) and a second decoding circuit (R_DEC). The first decoding circuit is used to determine a first bit unit among M*N bit units based on a first address (AA), and the second decoding circuit is used to determine a second bit unit among M*N bit units based on a second address (AB). A first latch circuit (AA_latch) is connected to the first decoding circuit, and a second latch circuit (AB_latch) is connected to the second decoding circuit. The first decoding circuit is connected to a memory array via a first port, and the second decoding circuit is connected to the memory array via a second port.

[0100] Taking the first decoding circuit as an example, the first decoding circuit is configured to determine a unique bit cell among M rows and N columns of bit cells based on a first address. Optionally, the first decoding circuit may specifically include a row decoder and a column decoder, where the row decoder is configured to determine the row and the column decoder is configured to determine the column. It is understood that the second decoding circuit and the first decoding circuit share the same implementation principles.

[0101] 2. Write the circuit

[0102] In this application, the write circuit is used to receive data and write the received data to the first bit unit through the first port of the first bit unit. Figure 8 ,The write circuit can also be regarded as a data latch circuit (D_latch), that is, a write IO circuit (Write_IO), which can latch the received data (D) for use by subsequent circuits.

[0103] The write circuit is connected to the memory array via the first port. Data received by the write circuit is destined for the first port, which is the only port on the memory that performs write operations. The meaning and structure of the first port can be found in the subsequent description of the memory array and are not detailed here.

[0104] See also Figure 10 , Figure 10 A possible implementation of a data latch circuit is shown. As shown in the figure, the data latch circuit is similar to the address latch circuit. When ICKA is high, the data latch circuit is turned on, and data is transmitted from port D2 to port O2. When ICKA is low, the values ​​of O2 and ON2 are maintained, that is, the values ​​of the positive bit line BL and the negative bit line BLB connected to the data latch circuit remain unchanged.

[0105] It is understandable that the reading circuit of the present application can be implemented as Figure 10 The latch circuit of the structure shown can also be implemented as a latch circuit of other structures, and this application does not impose any limitation.

[0106] 3. Storage array

[0107] In the present application, the storage array array is composed of M rows and N columns of bit cells, each bit cell is used to store 1 bit of data, and the bit cell includes a first port and a second port.

[0108] See also Figure 11 , Figure 11 A possible layout of the storage array is shown in FIG. Figure 11 As shown, the bitcells in the array are connected by 3*M bitlines and 2*N wordlines. The N bitcells in each row share 3 bitlines (including 1 positive bitline BL, 1 reverse bitline BLB and 1 read bitline RBL), and the M bitcells in each column share 2 wordlines (including 1 read / write wordline WLA and 1 read wordline WLB). Figure 11 In the example, M=160 and N=256 are used for explanation.

[0109] Specifically, each bit cell in the i-th row of bit cells is connected to the i-th positive bit line BL <i-1>, the i-th bit bar line BLB <i-1>, i-th read bit line RBL <i-1>Each bit cell in the j-th column of bit cells is connected to the j-th read / write word line WLA <j-1>, j-th read word line WLB <j-1>Here, 1≤i≤M, 1≤j≤N, and i and j are positive integers.

[0110] Among them, the i-th positive line BL <i-1>, the i-th bit bar line BLB <i-1>and the jth read / write word line WLA <j-1>The first port of the bitcell in row i and column j, the i-th read bit line RBL <i-1>and the jth read word line WLB <j-1>The second port of the bitcell at row i and column j.

[0111] See also Figure 12 , Figure 12 The internal structure diagram of the bitcell in the i-th row and j-th column of the array of this application is shown. As shown in the figure, this application adopts and Figure 2 The 8T bitcell with the same structure as shown is used as the bit unit of the storage array. However, the six MOS transistors on the left not only realize the write function, but also the read function.

[0112] The following takes the bitcell in row i and column j in the array as an example to illustrate the internal structure and connection relationship of the bitcell of the present application. Figure 12 As shown, the bitcell includes eight MOS transistors M1-M8. M1, M3, M5, M6, M7, and M8 are N-MOS transistors, and M2 and M4 are P-MOS transistors. Both N-MOS and P-MOS transistors include three electrodes: a gate, a source, and a drain. The N-MOS transistor conducts when the gate potential is higher than the source potential by an N-MOS threshold voltage, while the P-MOS transistor conducts when the gate potential is lower than the source potential by a P-MOS threshold voltage.

[0113] like Figure 12 As shown, the internal connection relationship of the bitcell is as follows: the source of M2 and the source of M4 are connected to a high level, the source of M1 and the source of M3 are connected to a low level; the source of M6, the gate of M2, the gate of M1, the drain of M4 and the drain of M3 are connected; the source of M5, the gate of M4, the gate of M3, the drain of M2 and the drain of M1 are connected; the gate of M5 and the gate of M6 are connected to the jth read / write word line WLA <j-1>The drain of M5 is connected to the i-th positive bit line BL <i-1>The drain of M6 is connected to the i-th inverted bit line BLB <i-1>The gate of M8 is connected to the j-th read word line WLB <j-1>, the drain of M8 is connected to the i-th read bit line RBL <i-1>; The source of M8 and the drain of M7 are connected to a low level, and the source of M7 is connected to a low level.

[0114] here, Figure 12 The structure of the 6 MOS tubes on the left side of the 8T bitcell shown Figure 1A or Figure 1B The bitcells shown are the same. The port formed by the six bitcells on the left can be used to perform read or write operations on the bitcell. The process of performing read and write operations is the same as Figure 1A or Figure 1B Same as in Figure 1A or Figure 1B And related descriptions are not repeated here.

[0115] here, Figure 12 The two MOS transistors on the right side of the 8T bitcell shown in the figure form a port that can be used to perform a read operation on the bitcell. The process of performing a read operation is similar to Figure 2 The two MOS tubes on the right side of the bitcell have the same read operation process, which can be referred to Figure 2 And related descriptions are not repeated here.

[0116] In an optional embodiment, the 1R1RW memory of the present application may include multiple Figure 11 As can be understood, when a memory includes multiple arrays, corresponding peripheral circuits, such as a read circuit, a write circuit, and a decoding circuit, need to be configured separately.

[0117] 4. Read circuit

[0118] First, the structures of SA and asymmetric sense amplifier (ASA) are briefly introduced.

[0119] (1) SA is a sensitive amplifier commonly used in the prior art. It reads a small-amplitude potential difference through two input terminals, amplifies the potential difference to a full-amplitude logic value potential, and then outputs it.

[0120] (2) ASA is a new type of sensitive amplifier that can read a small-amplitude potential through one input terminal and amplify the potential to a logic value potential before outputting it.

[0121] See also Figure 13 , Figure 13 A structural diagram of an ASA provided for this application. As shown in the figure, the sensitive amplifier is based on a voltage-type SA, and the symmetrically amplified NM1 and NM2 are changed into an asymmetric structure. One comparison signal of the SA comes from the point port bit line (ie, RBL) of the bitcell in the array, and the other comes from the power supply voltage, and the sense function is realized by using an asymmetric SA. Among them, NSAPCH is the pre-charge signal of the ASA (provided by the clock control circuit), and VREF is connected to the power supply of the ASA through PM4 as the reference comparison signal of the sensitive amplifier. When RBL = "1", when SACLK is turned on, the VREF and RBL_SA voltages are both VDD, but NM3 and NM4 will help NM2 pull down VREF, and eventually pull VREF to "0", and RBL_SA is pulled to "1"; when RBL = "0", that is, when RBL drops, when the voltage on RBL drops to a large enough level to offset the influence of NM3 and NM4, SACLK is turned on, and RBL_SA is pulled to "0", as shown in FIG. Figure 14 As shown in the waveform.

[0122] As can be seen from the above, ASA can receive an input voltage through an input terminal, amplify the voltage value and output it through the output terminal. Figure 13 The structure shown may also be an ASA of other structures with the same function, and this application does not impose any limitation.

[0123] In this application, the read circuit includes a first sense amplifier and a second sense amplifier. The first sense amplifier is SA, and the second sense amplifier is ASA. The first input of the first sense amplifier is connected to the i-th positive bit line, the second input of the first sense amplifier is connected to the i-th inverted bit line, and the input of the second sense amplifier is connected to the i-th read bit line.

[0124] The read circuit can read the data stored in the first bit unit through the first port of the first bit unit. Specifically, the read circuit amplifies the difference between the voltages received at the first input terminal and the second input terminal of the first sense amplifier through a first sense amplifier, and then outputs the difference through the output terminal of the first sensor. Here, the logic value output by the output terminal of the first sensor indicates the data stored in the first bit unit.

[0125] The read circuit can also read the data stored in the second bit cell through the second port of the second bit cell. Specifically, the read circuit amplifies the voltage received at the input of the second sense amplifier through a second sense amplifier and outputs the amplified voltage through the output of the second sense amplifier. Here, the logic value output by the output of the second sense amplifier indicates the data stored in the second bit cell.

[0126] In an alternative embodiment, see Figure 8 The read circuit includes a first read circuit (PortA 10) and a second read circuit (PortB 10). The first read circuit is used to read data stored in the first bit unit through the first port of the first bit unit, and the second read circuit is used to read data stored in the second bit unit through the second port of the second bit unit. The first read circuit is connected to the memory array through the first port, and the second read circuit is connected to the memory array through the second port. Optionally, the first read circuit includes the above-mentioned first sense amplifier, and the second read circuit includes the above-mentioned second sense amplifier.

[0127] As can be seen from the above description of the memory array and read circuit, the voltage signal on the read word line of the 8T bitcell in the array of this application can be amplified by the second sense amplifier (ASA), ensuring sufficient driving force for the subsequent circuit when reading the signal. Therefore, in this application, the number of bitcells that can be connected to each bit line in an array can be large, such as 256, that is, the number of word lines in an array can be large, that is, the storage capacity of an array in this application is increased.

[0128] When the storage capacity of the array increases, when implementing the memory, there is no need to splice multiple arrays. Only one or a few arrays can meet the storage capacity requirements, and the number of corresponding peripheral circuits in the memory is reduced. Therefore, in this application, after enabling the read function of the 6 MOS tubes on the left side of the 8T bitcell, and Figure 4 Compared with the 1R1RW SRAM in the present invention, even if the area of ​​a single peripheral circuit increases, the layout area of ​​the entire memory is still greatly reduced due to the reduction in the number of peripheral circuits. Figure 2 The ASA is used on the basis of the 8T bitcell shown, thereby fully utilizing the read and write functions of the 8T bitcell (ie, one port can perform a read function, and the other port can perform a read function or a write function).

[0129] In general, the memory of this application can achieve 1R1RW functionality while fully utilizing the read and write functions of the bitcells and rationally planning the area and power consumption. Compared with the existing solution of using DP SRAM to implement 1R1RW SRAM, this application avoids the waste of area and power consumption.

[0130] The above describes in detail the structure and implementation principle of the 1R1RW memory of the present application. In addition to the core circuit latch circuit, decoding circuit, storage array, read circuit and write circuit described above, the 1R1RW memory of the present application may also include a control circuit for providing memory operation power.

[0131] In an alternative embodiment, the control circuit is connected Figure 7 The latch circuit, decoding circuit, reading circuit and writing circuit in the memory shown. In this application, the control circuit is used to receive the first signal and the second signal. Figure 8 The control circuit may include a first control circuit (PortA TIMER) and a second control circuit (PortB TIMER), wherein the first control circuit is configured to receive the first signal and the second control circuit is configured to receive the second signal. The first signal is configured to instruct the memory to perform a read operation or a write operation via the first port, and the second signal is configured to instruct the memory to perform a read operation via the second port.

[0132] Optionally, the first signal includes a first port enable signal (CENA) and a first port clock signal (CLKA). The control circuit is further configured to, upon receiving the first signal, enable the latch circuit (eg Figure 8 AA_latch shown), decoding circuit (eg Figure 8 D_DEC / R_DEC) and write circuits (e.g. Figure 8 D_latch) provides a clock signal (ICKA) with greater driving force, or provides a clock signal (ICKA) for the latch circuit, decoding circuit and reading circuit (such as Figure 8 Here, the memory can only perform a write operation or a read operation through the first port when receiving the first port enable signal, and the first port clock signal provides operating power for the operation performed by the memory through the first port.

[0133] Optionally, the second signal includes a second port enable signal (CENB) and a second port clock signal (CLKB). The control circuit is further configured to, upon receiving the second signal, enable the latch circuit (eg Figure 8 AB_latch shown), decoding circuit (eg Figure 8 R_DEC shown) and read circuit (e.g. Figure 8 PortB 10) shown in FIG. 1 provides a clock signal (ICKB) with greater driving force. The clock signal (ICKB) is used for read operations on the second port. The memory can only perform a read operation through the second port upon receiving a second port enable signal. The second clock signal provides operating power for the memory to perform operations through the second port.

[0134] Optional, see Figure 8 In the 1R1RW memory of the present application, the latch circuit is further configured to receive a read / write enable signal (WEN). When the read / write enable signal takes a first value (e.g., 1), the first signal is specifically configured to instruct the memory to perform a write operation through the first port; when the read / write enable signal takes a second value (e.g., 0), the first signal is specifically configured to instruct the memory to perform a read operation through the first port.

[0135] For example, assume that all enable signals involved are active at low level and inactive at high level. Figure 8 If the memory receives a first port enable signal (CENA) (logical value 0), a first port clock signal (CLKA), a read / write enable signal (WEN) (logical value 0), a first address (AA), and data (D), the memory writes data (D) to the bitcell corresponding to the first address in the memory array array. If the memory receives a first port enable signal (CENA) (logical value 0), a first port clock signal (CLKA), a read / write enable signal (WEN) (logical value 1), and a first address (AA), the memory reads data stored in the bitcell corresponding to the first address in the memory array array. If the memory receives a second port enable signal (CENB) (logical value 0), a second port clock signal (CLKB), and a second address (AB), the memory reads data stored in the bitcell corresponding to the second address in the memory array array.

[0136] The following describes a method for storing or reading data using the 1R1RW memory provided by this application. Figure 15 , Figure 15 The following is a flow chart of a signal processing method of the present application. As shown in the figure, the method may include the following steps:

[0137] S110. The memory receives an instruction, which includes at least one of a first instruction and a second instruction; wherein the first instruction carries a first address, or the first instruction carries the first address and data; and the second instruction carries a second address.

[0138] Here, the memory is the 1R1RW memory provided by any possible implementation manner in the above-mentioned application.

[0139] The first instruction and the second instruction are introduced below.

[0140] 1. First Instruction

[0141] In this application, the first instruction is for the first port of the memory, and the memory can perform a write operation or a read operation through the first port according to the first instruction. The first instruction can carry different information, including the following two types:

[0142] (1) The first instruction carries the first address.

[0143] Here, the first address is the first address mentioned in the above description of the memory structure, for example Figure 8 AA in the memory, the process of receiving the first instruction can refer to the relevant description above. In an optional embodiment, the first instruction of type (1) can also include a first signal, and the first signal includes a first port enable signal (CENA) and a first clock signal (CLKA). For details, refer to the relevant description of the memory structure above.

[0144] (2) The first instruction carries the first address and data.

[0145] Here, the first address and data are the first address and data mentioned in the above description of the memory structure, for example Figure 8 AA and D in the memory, the process of the memory receiving the first instruction can refer to the relevant description above. In an optional embodiment, the first instruction of type (2) can also include a first signal, and the first signal includes a first port enable signal (CENA) and a first clock signal (CLKA). For details, refer to the relevant description of the memory structure above.

[0146] In an optional embodiment, when determining which of the above (1) and (2) the first instruction received by the memory belongs to, it can be determined not only by the information carried by the first instruction, but also by the value of the read / write enable signal (WEN) received by the memory latch circuit. For example, when the value of the read / write enable signal (WEN) is "1", it can be determined that the memory has received the first instruction of type (1); when the value of the read / write enable signal (WEN) is "0", it can be determined that the memory has received the first instruction of type (2).

[0147] 2. Second Instruction

[0148] In the present application, the second instruction is directed to the second port of the memory, and the memory can perform a read operation through the second port according to the second instruction.

[0149] In this application, the second instruction carries the second address. Here, the second address is the second address mentioned in the above description of the memory structure, for example Figure 8 AB in the memory, the process of receiving the second instruction can refer to the relevant description above. In an optional embodiment, the second instruction may further include a second signal, and the second signal includes a second port enable signal (CENB) and a second clock signal (CLKB). For details, refer to the relevant description of the memory structure above.

[0150] S120: When the instruction includes a first instruction and the first instruction carries a first address, the memory reads data stored in a first bit cell corresponding to the first address through a first port according to the first instruction; or

[0151] In a case where the instruction includes a first instruction and the first instruction carries a first address and data, the memory writes data to the first bit unit through the first port according to the first instruction;

[0152] In a case where the instruction includes a second instruction, the memory reads data stored in a second bit unit corresponding to a second address through a second port according to the second instruction.

[0153] Specifically, in this application, the memory performs corresponding operations according to the received instructions. The operations performed by the memory are different depending on the instructions received. The following describes the following situations:

[0154] 1. The instructions received by the memory include only the first instruction.

[0155] If the memory receives the first instruction of type (1) above, the decoding circuit in the memory determines the first bit unit among the M*N bit units of the storage array array according to the first address, and uses the read circuit to read the data stored in the first bit unit through the first port of the first bit unit.

[0156] If the memory receives the first instruction of type (2) above, the decoding circuit in the memory determines the first bit unit among the M*N bit units of the storage array according to the first address, and uses the write circuit to write the data carried in the first instruction into the first bit unit through the first port of the first bit unit.

[0157] 2. The instructions received by the memory only include the second instruction.

[0158] Specifically, when the instruction received by the memory includes only the second instruction, the decoding circuit in the memory determines the second bit unit from the M*N bit units of the storage array array according to the second address, and uses the read circuit to read the data stored in the second bit unit through the second port of the second bit unit.

[0159] 3. The instructions received by the memory include a first instruction and a second instruction.

[0160] It is understandable that when the instructions received by the memory include the first instruction and the second instruction, the memory can simultaneously use the first port and the second port to perform corresponding operations, and the operations between the two ports do not interfere with each other. For example, when the memory receives the first instruction and the second instruction of the first type, it can perform a read operation through the first port and a read operation through the second port; when the memory receives the first instruction and the second instruction of the second type, it can perform a write operation through the first port and a read operation through the second port.

[0161] It can be understood that the memory in the signal processing method of the present application is the memory described in any one of the implementation methods in the above structural embodiments, and the implementation method of each step in the signal processing method of the present application can also refer to the relevant description of the above memory.

[0162] As can be seen from the above, the signal processing method of the present application, based on the 1R1RW memory proposed in the present application, can realize the 1R1RW function.

[0163] Those skilled in the art will appreciate that all or part of the process steps in the above-described method embodiments can be implemented by a computer program instructing the relevant hardware. The program can be stored in a computer-readable storage medium, and when executed, the program can include the process steps in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A memory, characterized in that: include: A latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit, wherein the latch circuit is connected to the decoding circuit, the storage array is connected to the decoding circuit, the read circuit, and the write circuit, and the read circuit includes: a first sense amplifier and a second sense amplifier, wherein the first sense amplifier is SA and the second sense amplifier is ASA, wherein: The storage array includes M rows and N columns of bit cells, each bit cell is used to store 1 bit of data, and the bit cell includes a first port and a second port; The bit cell in the i-th row and j-th column of the storage array includes eight MOS transistors M1-M8, where M1, M3, M5, M6, M7 and M8 are N-MOS transistors, and M2 and M4 are P-MOS transistors. The source of M2 and the source of M4 are connected to a high level, and the source of M1 and the source of M3 are connected to a low level; The source of M6, the gate of M2, the gate of M1, the drain of M4 and the drain of M3 are connected; The source of M5, the gate of M4, the gate of M3, the drain of M2 and the drain of M1 are connected; The gates of M5 and M6 are connected to the jth read / write word line; the drain of M5 is connected to the ith positive bit line, and the drain of M6 is connected to the ith inverted bit line; the gate of M8 is connected to the jth read word line, and the drain of M8 is connected to the ith read bit line; The source of M8 is connected to the drain of M7, and the source of M7 is connected to a low level; Wherein, the first input terminal of the first sense amplifier is connected to the i-th positive bit line, and the second input terminal is connected to the i-th inverted bit line; Wherein, the input end of the second sense amplifier is connected to the i-th read bit line; Wherein, 1≤i≤M, 1≤j≤N, i and j are positive integers; the i-th positive bit line, the i-th inverted bit line and the j-th read / write word line constitute the first port, and the i-th read bit line and the j-th read word line constitute the second port; The latch circuit is used to receive a first address and a second address; The decoding circuit is configured to determine a first bit unit among the M*N bit units according to the first address, and is further configured to determine a second bit unit among the M*N bit units according to the second address; The write circuit is configured to receive data and write the received data into the first bit unit through the first port of the first bit unit; The read circuit is used to amplify the difference between the voltages received at the first input terminal and the second input terminal through the first sensitive amplifier, and output the difference through the output terminal of the first sensitive amplifier. The read circuit is also used to amplify the voltage received at the input terminal of the second sensitive amplifier through the second sensitive amplifier, and output the difference through the output terminal of the second sensitive amplifier.

2. The memory according to claim 1, wherein The latch circuit includes: a first address latch circuit and a second address latch circuit; the first address latch circuit is used to receive the first address, and the second address latch circuit is used to receive the second address; The decoding circuit includes: a first decoding circuit and a second decoding circuit; the first decoding circuit is used to determine the first bit unit in the M*N bit units according to the first address, and the second decoding circuit is used to determine the second bit unit in the M*N bit units according to the second address; Wherein, the first address latch circuit is connected to the first decoding circuit, the second address latch circuit is connected to the second decoding circuit, the first decoding circuit is connected to the storage array through the first port, and the second decoding circuit is connected to the storage array through the second port; The read circuit includes: a first read circuit and a second read circuit; the first read circuit is used to read the data stored in the first bit unit through the first port of the first bit unit, and the second read circuit is used to read the data stored in the second bit unit through the second port of the second bit unit; The first read circuit is connected to the storage array through the first port, and the second read circuit is connected to the storage array through the second port.

3. The memory according to claim 2, wherein: The first decoding circuit includes a first row decoder and a first column decoder, the first row decoder is used to determine the row of the first bit unit in the M*N bit units according to the first address, and the first column decoder is used to determine the column of the first bit unit in the M*N bit units according to the first address; and / or, The second decoding circuit includes a second row decoder and a second column decoder, the second row decoder is used to determine the row of the second bit unit in the M*N bit units according to the second address, and the second column decoder is used to determine the column of the second bit unit in the M*N bit units according to the second address.

4. The memory according to any one of claims 1 to 3, wherein: The memory further includes a control circuit, wherein the control circuit is connected to the latch circuit, the decoding circuit, the write circuit and the read circuit; The control circuit is used to receive a first signal and a second signal, wherein the first signal is used to instruct the memory to perform a read operation or a write operation through the first port, and the second signal is used to instruct the memory to perform a read operation through the second port.

5. The memory according to claim 4, wherein The latch circuit is also used to receive a read / write enable signal. When the read / write enable signal takes a first value, the first signal is specifically used to instruct the memory to perform a write operation through the first port; When the read / write enable signal takes the second value, the first signal is specifically used to instruct the memory to perform a read operation through the first port.

6. The memory according to claim 4, wherein: The first signal includes: a first port enable signal and a first port clock signal; the control circuit is further configured to provide a clock signal to the latch circuit, the decoding circuit, and the write circuit, or provide a clock signal to the latch circuit, the decoding circuit, and the read circuit upon receiving the first signal; The second signal includes: a second port enable signal and a second port clock signal; the control circuit is further configured to provide a clock signal for the latch circuit, the decoding circuit and the read circuit when receiving the second signal.

7. A signal processing method, characterized in that: include: The memory receives an instruction, the memory being the memory according to any one of claims 1 to 6, the instruction comprising at least one of a first instruction or a second instruction; wherein the first instruction carries a first address, or the first instruction carries the first address and data; and the second instruction carries a second address; In a case where the instruction includes the first instruction and the first instruction carries the first address, the memory reads data stored in the first bit unit corresponding to the first address through the first port according to the first instruction; or In a case where the instruction includes the first instruction and the first instruction carries the first address and the data, the memory writes the data to the first bit unit through the first port according to the first instruction; In a case where the instruction includes the second instruction, the memory reads the data stored in the second bit unit corresponding to the second address through the second port according to the second instruction.

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