Vertical storage device

Abstract

A vertical memory device includes: a gate line structure including a cell area in which a vertical channel structure is formed; and a first connection area and a second connection area, which are arranged at a first end and a second end of the cell area in a first direction, respectively. Each of the first connection area and the second connection area includes a first protrusion of a first gate line and a second protrusion of a second gate line, the first protrusion and the second protrusion are parallel to a top surface of a substrate and are arranged as a step in a second direction perpendicular to the first direction. The first protrusion of the second connection area and the first protrusion of the first connection area are arranged diagonally with respect to a center line of the cell area, and the center line is parallel to the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0053203 filed on May 9, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concepts herein relate to a vertical memory device, and more particularly, to a vertical memory device including gate lines stacked in a vertical direction. Background Art

[0004] The demand for large-capacity, highly integrated circuit devices including memory devices continues to increase. Recently, attention has been paid to vertical memory devices, which include memory cells arranged vertically in three dimensions, as a way to provide higher integration. Since vertical memory devices have a structure in which each memory cell is stacked in a vertical direction, a pad structure is generally required to apply an electrical signal to each memory cell stacked in the vertical direction. Summary of the invention

[0005] Embodiments of the inventive concept provide a vertical memory device including gate lines stacked in a vertical direction.

[0006] Embodiments of the present invention provide a vertical memory device, which includes: a gate line structure, which includes a first gate line and a second gate line, which are sequentially stacked on a substrate and extend in a first direction parallel to the top surface of the substrate; and a vertical channel structure, which is configured to penetrate the gate line structure in a direction perpendicular to the top surface of the substrate. The gate line structure includes a cell area in which the vertical channel structure is formed and a first connection area and a second connection area arranged at a first end and a second end of the cell area respectively along the first direction. Each of the first connection area and the second connection area includes a first protrusion of the first gate line and a second protrusion of the second gate line, the first protrusion of the first gate line and the second protrusion of the second gate line are parallel to the top surface of the substrate and are arranged as a step in a second direction perpendicular to the first direction. The first protrusion of the second connection area and the first protrusion of the first connection area are arranged diagonally with respect to the first direction.

[0007] The embodiments of the present invention also provide a vertical memory device, which includes: a gate line structure, which includes a plurality of gate lines, which are sequentially stacked on a substrate and extend parallel to the top surface of the substrate in a first direction; and a vertical channel structure, which is configured to penetrate the gate line structure in a direction perpendicular to the top surface of the substrate. The gate line structure includes: a cell area in which a vertical channel structure is formed, and a first connection area and a second connection area arranged at the first end and the second end of the cell area respectively along the first direction. Each of the first connection area and the second connection area includes a plurality of protrusions of a plurality of gate lines, and the plurality of protrusions are arranged as steps in the first direction and in a second direction perpendicular to the first direction. Each of the plurality of protrusions of the first connection area is arranged along the first direction parallel to the protrusions of the plurality of protrusions of the second connection area located on different layers of the plurality of gate lines.

[0008] The embodiments of the present invention also provide a vertical memory device, which includes: a gate line structure, which includes a plurality of gate lines, which are sequentially stacked on a substrate and extend in a first direction parallel to the top surface of the substrate; a vertical channel structure, which is configured to penetrate the gate line structure in a direction perpendicular to the top surface of the substrate; and a plurality of transfer transistors, which are electrically connected to the plurality of gate lines. The gate line structure includes a cell area in which a vertical channel structure is formed and a first connection area and a second connection area arranged at a first end and a second end of the cell area in the first direction, respectively. Each of the first connection area and the second connection area includes a plurality of protrusions of a plurality of gate lines, and the plurality of protrusions are arranged as steps in the first direction and in a second direction perpendicular to the first direction. The protrusions located on the same layer of the plurality of gate lines among the plurality of protrusions are arranged to be misaligned with each other in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A block diagram illustrating a vertical memory device according to an embodiment of the inventive concept is shown;

[0011] Figure 2 Shows Figure 1 A block diagram of an example implementation of a row decoder in;

[0012] Figure 3 An equivalent circuit diagram of a cell block included in a memory cell region of a vertical memory device according to an embodiment of the inventive concept is shown;

[0013] Figure 4A shows a top view of a vertical memory device according to an embodiment of the inventive concept;

[0014] Figure 4B Shown along Figure 4A A cross-sectional view taken along line AA' in FIG.

[0015] Figure 4C Shows Figure 4A A perspective view of a first grid line structure shown in ;

[0016] Figure 5 A perspective view showing a gate line structure included in a vertical memory device according to an embodiment of the inventive concept;

[0017] Figure 6 A perspective view showing a gate line structure included in a vertical memory device according to another embodiment of the inventive concept;

[0018] Fig. 7A A top view of a vertical memory device according to another embodiment of the inventive concept is shown;

[0019] Figure 7B Shows Fig. 7A A perspective view of a first grid line structure in FIG.

[0020] Figure 8 Shows Fig. 7A An enlarged top view of a portion B of a vertical storage device in FIG.

[0021] Fig. 9 A block diagram illustrating a memory cell array included in a vertical memory device according to an embodiment of the inventive concept; and

[0022] Fig.10 A diagram illustrating a computing system including a vertical memory device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions thereof will be omitted.

[0024] As a convention in the field of the present invention, embodiments can be described and illustrated according to the blocks that perform one or more functions described. These blocks (here may be referred to as units or modules, etc.) are physically implemented by analog circuits and / or digital circuits (e.g., logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.), and may optionally be driven by firmware and / or software. For example, the circuit may be implemented in one or more semiconductor chips, or on substrate supports such as printed circuit boards, etc. The circuits that constitute the blocks may be implemented by dedicated hardware, or by processors (e.g., one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the blocks and processors that perform other functions of the blocks. Without departing from the scope of the present invention, each block of the embodiment may be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of the embodiment may be physically combined into more complex blocks.

[0025] Figure 1 A block diagram of a vertical memory device 100 according to an embodiment of the inventive concept is shown.

[0026] Reference Figure 1 , the vertical memory device 100 includes a memory cell array 110, a row decoder 120, a page buffer 130, an input / output (I / O) buffer 140, a control logic 150, and a voltage generator 160. According to one embodiment, the vertical memory device 100 may be a volatile memory including, for example, a flash memory device, a magnetoresistive random access memory (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), etc. According to one embodiment, the vertical memory device 100 may be implemented with various memory devices including a row decoder driving a row line including a word line.

[0027] The memory cell array 110 is connected to the row decoder 120 via the first word line WL1 to the nth word line WLn. In addition, the memory cell array 110 is connected to the page buffer 130 via the first bit line BL1 to the mth bit line BLm. The page buffer 130 operates as a write driver or a sense amplifier according to the operation mode. For example, in a programming operation, the page buffer 130 may transmit a voltage corresponding to the data to be programmed to the first bit line BL1 to the mth bit line BLm. In addition, in a read operation, the page buffer 130 may sense the data stored in the selected memory cell via the first bit line BL1 to the mth bit line BLm, and may transmit the sensed data to the I / O buffer 140. The I / O buffer 140 may transmit input data to the page buffer 130, or may output data provided from the page buffer 130 to the outside. The input data and output data at the I / O buffer 140 are generally denoted as I / O. Reference will be made later Figure 3 A circuit diagram of a plurality of cell blocks included in the memory cell array 110 is described. Fig. 9 The configuration of a plurality of cell blocks included in the memory cell array 110 is described.

[0028] The control logic 150 may control various components provided in the vertical memory device 100. For example, the control logic 150 may generate an internal control signal according to a command such as a program operation command and a read operation command provided from the outside. For example, the control logic 150 may control the voltage generator 160 to generate voltages of various levels for program operations and read operations, and to generate various other voltages. In addition, the control logic 150 may control the I / O timing of data by controlling the I / O buffer 140. In addition, according to an embodiment of the present invention, the control logic 150 may generate a control signal CTRL_row for controlling the row decoder 120. The row decoder 120 may perform a selection operation on each cell block and the first to nth word lines WL1 to WLn of the memory cell array 110 based on the control signal CTRL_row.

[0029] The voltage generator 160 may generate various types of word line voltages to be supplied to each of the first to nth word lines WL1 to WLn, and a bulk voltage to be supplied to a bulk (e.g., a well region) formed by memory cells based on the control of the control logic 150. For example, during a programming operation, the voltage generator 160 may generate a program voltage supplied to a selected word line and a pass voltage supplied to an unselected word line. In addition, during a read operation, the voltage generator 160 may generate a selected word line voltage and an unselected word line voltage, which have different levels from each other. Moreover, the voltage generator 160 may provide a high erase voltage to a bulk in which the memory cell array 110 selected in an erase operation is formed.

[0030] The memory cell array 110 may include a plurality of cell blocks. Figure 1 , one memory cell array 110 and one row decoder 120 are shown, but this is only for convenience of explanation. In some embodiments of the present inventive concept, one row decoder 120 may be arranged for each cell block of the memory cell array 110. Alternatively, in other embodiments, one row decoder 120 may be shared by at least two cell blocks of the memory cell array 110. In this case, the number of row decoders 120 in the vertical memory device 100 may be less than the number of cell blocks.

[0031] For example, the row decoder 120 may perform an operation related to the selection of the corresponding cell block according to the address ADD received from the host. For example, the row decoder 120 may provide a word line voltage to the first word line WL1 to the nth word line WLn of the selected cell block, and may prevent the word line voltage from being provided to the first word line WL1 to the nth word line WLn of the unselected cell block. Figure 2 The configuration of the row decoder 120 is described.

[0032] The vertical storage device 100 of the embodiment conceived according to the present invention may include a flash memory device, and the memory cell array 110 may include a plurality of NAND cell strings. Each cell string may include a channel in the vertical direction. The vertical storage device 100 may include a gate line structure in which a plurality of gate lines are stacked, and the cell string may be formed to penetrate the gate line structure in the vertical direction. A cell block may be formed in a gate line structure. The memory cell formed in each cell string may be programmed or erased by a high voltage provided from a row decoder 120.

[0033] In addition, in addition to the first to n-th word lines WL1 to WLn, the memory cell array 110 may be connected to the row decoder 120 via other lines. For example, the memory cell array 110 may be connected to the row decoder 120 via one or more string selection lines SSL and ground selection lines GSL. In this case, the string selection lines SSL, the first to n-th word lines WL1 to WLn, and the ground selection lines GSL may be referred to as row lines. In addition, the voltage provided in the row lines may be referred to as a row line voltage.

[0034] Figure 2 Shows Figure 1 0048. A block diagram of an example implementation of a row decoder 120 in FIG. Figure 2 Shows Figure 1 The vertical memory device 100 is an example of a flash memory device and the row decoder 121 drives the flash memory cells. Figure 2 The unit block 111 shown in FIG. 1 may be included in Figure 1The row decoder 121 may correspond to any one of the plurality of cell blocks in the memory cell array 110. Figure 1 In the configuration of the row decoder 120. Figure 2 Two string selection lines SSL and one ground selection line GSL are shown in FIG. 1 , and various numbers of string selection lines SSL and ground selection lines GSL may also be arranged according to other embodiments of the inventive concept.

[0035] Reference Figure 2 The row decoder 121 includes a string selection line (SSL) driver 122, a word line driver 123, a ground selection line (GSL) driver 124, and a block selector 125. The block selector 125 can decode the received address ADD (see Figure 1 ) and selects the cell block 111 from a plurality of corresponding cell blocks. In one embodiment, the block selector 125 may be disposed between the SSL driver 122, the word line driver 123, the GSL driver 124, and the plurality of cell blocks.

[0036] The SSL driver 122 is connected to the string selection line SSL via the block selector 125, and may drive the string selection line SSL via the block selector 125. For example, during an erase operation, the SSL driver 122 may float the string selection line SSL, and during a program operation, the SSL driver 122 may provide a high string selection voltage (e.g., a power supply voltage) via the string selection line SSL.

[0037] The word line driver 123 is connected to the first to n-th word lines WL1 to WLn via the block selector 125, and can drive the first to n-th word lines WL1 to WLn via the block selector 125. For example, during an erase operation, a high erase voltage may be applied to a memory bank in which the cell block 111 is formed, and the word line driver 123 may apply a relatively low-level word line voltage (e.g., a ground voltage) to the first to n-th word lines WL1 to WLn. In addition, during a program operation, the word line driver 123 may provide a high-level program voltage to a selected word line, and provide a pass voltage to an unselected word line.

[0038] The GSL driver 124 may drive the ground selection line GSL via the block selector 125. For example, during an erase operation, the GSL driver 124 may float the ground selection line GSL, and during a program operation, the GSL driver 124 may provide a low level ground selection voltage (eg, ground voltage) to the ground selection line GSL.

[0039] The block selector 125 may include a plurality of transfer transistors TR_P connected between the SSL driver 122, the word line driver 123, the GSL driver 124, and the row lines (string selection line SSL, first word line WL1 to nth word line WLn, and ground selection line GSL). The row line voltage applied to the row line (string selection line SSL, first word line WL1 to nth word line WLn, ground selection line GSL) may be controlled based on the switching operation of the plurality of transfer transistors TR_P. For example, the vertical memory device 100 may include a gate line structure in which a plurality of gate lines are stacked, and each of the plurality of transfer transistors TR_P may switch the row line voltage applied to a plurality of gate lines constituting one cell block.

[0040] In an embodiment of the inventive concept, one transfer transistor TR_P may be electrically connected to one gate line included in one gate line structure corresponding to one cell block. Figure 4A The connection relationship between the gate line and the transfer transistor TR_P is described.

[0041] Alternatively, in some embodiments, the unit block 111 may include a first sub-unit block and a second sub-unit block. One transfer transistor TR_P may be electrically connected to a gate line included in a bus-gate line structure corresponding to one sub-unit block. However, embodiments of the present inventive concept are not limited thereto, and in other embodiments, one transfer transistor TR_P may be electrically connected to a plurality of gate lines included in a sub-gate line structure corresponding to one sub-unit block.

[0042] Figure 3 An equivalent circuit diagram of a cell block 111 included in a memory cell region of a vertical memory device 100 according to an embodiment of the inventive concept is shown. Figure 3 An equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure is shown.

[0043] Reference Figure 3 , a cell block 111 included in the memory cell array 110 includes a plurality of memory cell strings MS. The cell block 111 may include first to m-th bit lines BL1, BL2 to BLm (also collectively referred to as BL), first to n-th word lines WL1, WL2 to WLn-2, ​​WLn-1, and WLn, first to m-th string selection lines SSL1, SSL2 to SSLm (also collectively referred to as SSL), at least one ground selection line GSL, and a common source line CSL. A plurality of memory cell strings MS may be formed between the first to m-th bit lines BL1 to BLm (BL) and the common source line CSL.

[0044] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and first to nth memory cell transistors MC1, MC2 to MCn-2, MCn-1, and MCn. The drain region of the string selection transistor SST may be connected to a corresponding one of the bit lines BL, and the source region of the ground selection transistor GST may be connected to a common source line CSL. The common source line CSL may be a region where the source regions of the plurality of ground selection transistors GST are commonly connected to each other.

[0045] The string selection transistors SST respectively included in the plurality of memory cell strings MS may be connected to string selection lines different from each other so that each of the plurality of memory cell strings MS is independently controlled. For example, the string selection transistor SST may be connected to one string selection line (e.g., one of the first string selection line SSL1, the second string selection line SSL2, and the third string selection line SSL3).

[0046] The ground selection transistor GST may be connected to a ground selection line GSL. In one embodiment, different ground selection transistors GST in a plurality of memory cell strings MS included in the cell block 111 may be connected to the same ground selection line GSL. However, embodiments of the inventive concept are not limited thereto, and different ground selection transistors GST may be connected to different ground selection lines GSL.

[0047] The first to nth memory cell transistors MC1 to MCn may be connected to a plurality of word lines WL, respectively.

[0048] The first to nth memory cell transistors MC1 to MCn constituting the memory cell string MS in the cell block 111 may have a structure connected in series in a vertical direction on a main surface of the substrate. In the cell block 111, at least one string selection line SSL, at least one ground selection line GSL, and a plurality of word lines WL may extend in a horizontal direction parallel to the main surface of the substrate, and may be arranged to overlap each other in a vertical direction perpendicular to the main surface of the substrate.

[0049] Figure 4A A top view of a vertical memory device 100 a according to an embodiment of the inventive concept is shown. Figure 4B Shown along Figure 4A A cross-sectional view taken along line AA'. Figure 4C Shows Figure 4A A perspective view of the first gate line structure GS1 is shown in FIG. Figure 4B FIG. 1 shows a cross section of the first gate line structure GS1, and the description of the first gate line structure GS1 can also be applied to the second gate line structure GS2. Figure 4COnly the first gate line structure GS1 is shown, but the description of the first gate line structure GS1 may also be applied to the second gate line structure GS2.

[0050] Reference Figure 4A and Figure 4B , the vertical memory device 100a can be implemented in a semiconductor chip, and includes a memory cell region CR, and a first connection region PR1 and a second connection region PR2 arranged at both ends (e.g., a first end and a second end) of the memory cell region CR. The memory cell region CR is located at an intermediate position between the first connection region PR1 and the second connection region PR2 along a first direction (X). In addition, the vertical memory device 100a includes a first row decoder region RR1 and a second row decoder region RR2. The first row decoder region RR1 is arranged adjacent to the first connection region PR1 in a direction opposite to the first direction (X), and the second row decoder region RR2 is arranged adjacent to the second connection region PR2 in the first direction (X).

[0051] The vertical memory device 100a includes a first gate line structure GS1 and a second gate line structure GS2. Figure 4A The vertical memory device 100a is shown as including two gate line structures, but this illustration is only for convenience of explanation. In other embodiments, the vertical memory device 100a may include more than three gate line structures, and the inventive concept is not limited to the number of gate line structures.

[0052] The vertical memory device 100a includes a plurality of word line cutting regions. The plurality of word line cutting regions may include a first word line cutting region WLC1 and a second word line cutting region WLC2.

[0053] The first word line cutting area WLC1 extends in a first direction (X) parallel to the top surface of the substrate 101. The first word line cutting area WLC1 can limit the width of the first gate line 116_1 to the sixteenth gate line 116_16 in a second direction (Y), and the second direction (Y) is perpendicular to the first direction (X) and parallel to the top surface of the substrate 101. Therefore, the first gate line 116_1 to the sixteenth gate line 116_16 can be repeatedly spaced apart from each other at regular intervals by a plurality of first word line cutting areas WLC1, and the first gate line structure GS1 and the second gate line structure GS2 can be separated by the first word line cutting area WLC1. The first gate line structure GS1 and the second gate line structure GS2 separated by the first word line cutting area WLC1 can correspond to a unit block respectively. For example, the first gate line structure GS1 can constitute a first unit block, and the second gate line structure GS2 can constitute a second unit block.

[0054] The second word line cutting region WLC2 is formed in one cell block. Therefore, the second word line cutting region WLC2 extends in a first direction (X) parallel to the top surface of the substrate 101, but unlike the first word line cutting region WLC1, the second word line cutting region WLC2 may include some disconnected regions.

[0055] Each of the first gate line structure GS1 and the second gate line structure GS2 includes first to sixteenth gate lines 116_1 to 116_16 that are sequentially stacked from a top surface of the substrate 101 in the third direction (Z).

[0056] The substrate 101 may include a semiconductor material, such as silicon and germanium. In one embodiment, the substrate 101 may include single crystal silicon. The insulating layer 102 may be disposed on the substrate 101 .

[0057] The first gate line 116_1 to the sixteenth gate line 116_16 may include a metal (e.g., tungsten, nickel, cobalt, and tantalum, etc.), a metal silicide (e.g., tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide, etc.), polysilicon doped with impurities, or a combination thereof. Each of the first gate line 116_1 to the sixteenth gate line 116_16 may be referred to as a word line WL, a string selection line SSL, or a ground selection line GSL. For example, the first gate line 116_1 on the bottom layer may be set to a ground selection line GSL, and the sixteenth gate line 116_16 on the top layer may be set to a string selection line SSL. The second gate line 116_2 to the fifteenth gate line 116_15 between the ground selection line GSL and the string selection line SSL may be set to a word line WL.

[0058] The first to sixteenth gate insulating layers 118_1 to 118_16 are respectively arranged under or over the first to sixteenth gate lines 116_1 to 116_16. For example, the first gate insulating layer 118_1 is arranged under the second gate line 116_2 and on (over) the first gate line 116_1. The first to sixteenth gate insulating layers 118_1 to 118_16 may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0059] The first gate line structure GS1 and the second gate line structure GS2 include a memory cell region CR in which a vertical channel structure CH is formed. The vertical channel structure CH is formed by penetrating the first gate line structure GS1 or the second gate line structure GS2 in a third direction (Z) perpendicular to the top surface of the substrate 101. A plurality of memory cells MC are formed in the memory cell region CR and may have a reference Figure 3 The circuit structure described with reference to the first memory cell transistor MC1 to the nth memory cell transistor MCn.

[0060] The vertical channel structure CH includes a gate dielectric layer 112, a channel region 113, a buried insulating layer 114, and a drain region 119. In some embodiments, a barrier metal film may be formed between the gate dielectric layer 112 and the first to sixteenth gate lines 116_1 to 116_16. In one embodiment, the semiconductor pattern 115 is also included between the top surface of the substrate 101 and the vertical channel structure CH. The semiconductor pattern 115 may contact the top surface of the substrate 101. The semiconductor pattern 170 may have a columnar shape, and the vertical channel structure CH may be formed on the top surface of the semiconductor pattern 115.

[0061] The channel region 113 may include doped polysilicon and / or undoped polysilicon. The channel region 113 may have, for example, a cylindrical shape. An inner space of the channel region 113 may be filled with a buried insulating layer 114 .

[0062] The gate dielectric layer 112 may include a tunnel insulating layer, a charge storage layer, and a blocking dielectric layer. The tunnel insulating layer, the charge storage layer, and the blocking dielectric layer may be sequentially stacked on the outer wall of the channel region 113, and may be formed to surround the outer wall of the channel region 113. The tunnel insulating layer may include an oxide such as silicon oxide. The charge storage layer may include, for example, silicon nitride. The blocking dielectric layer may include, for example, silicon oxide or a metal oxide (such as hafnium oxide or aluminum oxide).

[0063] The buried insulating layer 114 may include an insulating material. For example, the buried insulating layer 114 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating layer 114 may be omitted, in which case the channel region 113 may have a pillar structure without an inner space thereof.

[0064] The drain region 119 may include a polysilicon layer doped with impurities.

[0065] Each of the first gate line structure GS1 and the second gate line structure GS2 includes a first connection area PR1 and a second connection area PR2 respectively arranged at both ends of the memory cell area CR. The memory cell area CR is located at an intermediate position between the first connection area PR1 and the second connection area PR2 along the first direction (X). The first protrusions P1 to the sixteenth protrusions P16 of the first gate line structure GS1 and the second gate line structure GS2, which are formed as pad structures or provide pad structures, are arranged in the first connection area PR1 and the second connection area PR2. The protrusion should be understood as an extension (i.e., a protrusion) in the layer (e.g., layers L1 to L16) that exceeds the area of ​​the corresponding layer arranged above the layer. In other words, the protrusion is an area in a layer that does not have another corresponding layer or multiple corresponding layers (e.g., in layers L1 to L16) thereon. Multiple transfer transistors TR_P can be connected to the first gate line 116_1 to the sixteenth gate line 116_16 of each of the first gate line structure GS1 and the second gate line structure GS2 via the pad structures of the first connection area PR1 and the second connection area PR2. Reference will be made later Figure 4C The shapes of the first to sixteenth protrusions P1 to P16 of the first and second connection regions PR1 and PR2 are described.

[0066] In an embodiment of the present inventive concept, each of the first to sixteenth gate lines 116_1 to 116_16 included in the first gate line structure GS1 may be connected to one transmission transistor TR_P, and each of the first to sixteenth gate lines 116_1 to 116_16 included in the second gate line structure GS2 may be connected to one transmission transistor TR_P.

[0067] Reference Figure 3 , Figure 4A and Figure 4B , Figure 3 The value of n in the formula may be 16, and the first word line WL1 to the sixteenth word line WL16 may be connected to Figure 4A , Figure 4B and Figure 4C For example, the first word line WL1 may be connected to the first gate line 116_1, and the second word line WL2 may be connected to the second gate line 116_2. Figure 4A and Figure 4B In the embodiment, the first gate line 116_1 to the sixteenth gate line 116_16 are shown to include a total of 16 layers, but the present inventive concept is not limited thereto. In other words, in other embodiments, Figure 3The value of n in may be less than or greater than 16. The number of the first to sixteenth gate lines 116_1 to 116_16 may vary according to the structure of cell strings included in the memory cell array 110. The vertical memory device 100 according to an embodiment of the inventive concept is not limited to the number of the first to sixteenth gate lines 116_1 to 116_16 (e.g., 16).

[0068] More gate lines may be further formed on or over the first to sixteenth gate lines 116_1 to 116_16 and may be connected to the string selection line SSL. Figure 4A and Figure 4B In the illustrated embodiment, the number of string selection lines SSL connected to a block (e.g., the first gate line structure GS1 or the second gate line structure GS2) is 4, but is not limited thereto, and in other embodiments, the number of string selection lines may be greater than or less than 4 based on the number of second word line cutting regions WLC2.

[0069] Reference FIG. 4A to FIG. 4C The first gate line 116_1 and the first gate insulating layer 118_1 form a first layer L1, and the second gate line 116_2 and the second gate insulating layer 118_2 form a second layer L2. The third gate lines 116_3 to the sixteenth gate lines 116_16 and the third gate insulating layers 118_3 to the sixteenth gate insulating layers 118_16 corresponding thereto respectively form third layers L3 to sixteenth layers L16. The exposed portions of the first layer L1 to the sixteenth layer L16 respectively constitute the first protrusions P1 to the sixteenth protrusions P16.

[0070] Each of the first gate line 116_1 to the sixteenth gate line 116_16 includes a first protrusion P1 to a sixteenth protrusion P16, respectively, for forming or providing a pad structure. Here, each of the first gate line 116_1 to the sixteenth gate line 116_16 may include a protrusion in the first connection region PR1 and a protrusion in the second connection region PR2. For example, the first gate line 116_1 may include a first protrusion P1 arranged in the first connection region PR1 and a first protrusion P1 arranged in the second connection region PR2. The second gate line 116_2 may include a second protrusion P2 arranged in the first connection region PR1 and a second protrusion P2 arranged in the second connection region PR2. The description of the first protrusion P1 of the first gate line 116_1 and the second protrusion P2 of the second gate line 116_2 may be applied identically to the third protrusion P3 to the sixteenth protrusion P16 of the third gate line 116_3 to the sixteenth gate line 116_16.

[0071] The first protrusions P1 to the sixteenth protrusions P16 of the first connection region PR1 have a step shape (i.e., are arranged) in the first direction (X) and the second direction (Y). In other words, the protrusions P1 to P19 are arranged as steps along the first direction (X) and the second direction (Y) perpendicular to the first direction (X). For example, Figure 4C As shown, the protrusions P13, P9, P5, and P1 sequentially arranged along the first direction (X) are arranged in a stepped manner relative to each other, whereby the protrusion P13 is arranged at a layer relatively higher than (i.e., above) the protrusion P9, the protrusion P9 is arranged at a layer relatively higher than the protrusion P5, and the protrusion P5 is arranged at a layer relatively higher than the protrusion P1. Figure 4C As shown, the protrusions P13, P14, P15 and P16 sequentially arranged in the second direction (Y) are arranged in a stepped manner relative to each other, whereby the protrusion P13 is arranged at a layer relatively lower than (i.e., below) the protrusion P14, the protrusion P14 is arranged at a layer relatively lower than the protrusion P15, and the protrusion P15 is arranged at a layer relatively lower than the protrusion P16. In addition, the first protrusion P1 to the sixteenth protrusion P16 of the second connection region PR2 have a stepped shape (i.e., arranged) in the first direction (X) and the second direction (Y). Figure 4A and Figure 4B In each of the first connection region PR1 and the second connection region PR2, four protrusions are arranged along the first direction (X), and four protrusions are arranged along the second direction (Y). However, the vertical memory device 100a according to the inventive concept is not limited to Figure 4A and Figure 4B In the illustrated case, and in other embodiments, the first to sixteenth protrusions P1 to P16 in each of the first and second connection regions PR1 and PR2 may be arranged in various ways.

[0072] The protrusions included in the same layer among the first protrusions P1 to the sixteenth protrusions P16 in each of the first gate line 116_1 to the sixteenth gate line 116_16 are arranged diagonally relative to each other in the first direction (X). In other words, the protrusions arranged on the same layer are not arranged parallel to each other in the first direction (X), or in other words, the protrusions arranged on the same layer are not collinear with each other in the first direction (X) and are not aligned relative to each other in the second direction (Y). For example, Figure 4AAs shown in the top view of , the first protrusion P1 of the first connection area PR1 is located at the leftmost boundary of the first connection area PR1 and serves as the fourth protrusion from the first word line cutting area WLC1 along the second direction (Y). On the other hand, the first protrusion P1 of the second connection area PR2 is located at the rightmost boundary of the second connection area PR2 and serves as the first protrusion from the first word line cutting area WLC1 along the second direction (Y). Therefore, the first connection area PR1 and the first protrusion P1 of the second connection area PR2 within the first gate line structure GS1 are diagonally positioned relative to each other with respect to the center line CL of the memory cell area (i.e., the cell area), and the center line CL is parallel to the center line CL as shown in FIG. Figure 4C In other words, for example, the first protrusion P1 of the first connection region PR1 is formed or arranged to be parallel to the protrusion (or protrusions) in the second connection region PR2 formed in a (different) layer other than the first layer L1 among the layers L1 to L16 in the first connection region PR1 in the first direction (X). The protrusions P2 to P16 in the first connection region PR1 are diagonally positioned relative to the protrusions P2 and P16 in the second connection region PR2, respectively.

[0073] Therefore, each of the first to sixteenth protrusions P1 to P16 of the first connection region PR1 may be arranged side by side with protrusions formed on different layers among the first to sixteenth protrusions P1 to P16 of the second connection region PR2 in the first direction (X). For example, the first protrusion P1, the fifth protrusion P5, the ninth protrusion P9, and the thirteenth protrusion P13 of the first connection region PR1 may be arranged side by side with the sixteenth protrusion P16, the twelfth protrusion P12, the eighth protrusion P8, and the fourth protrusion P4 of the second connection region PR2 in the first direction (X).

[0074] In an embodiment of the present invention, among the first to sixteenth protrusions P1 to P16 included in each of the first to sixteenth gate lines 116_1 to 116_16, the protrusions arranged on the same layer are arranged in directions opposite to each other relative to a center line CL, which is parallel to the first direction (X) and passes through the center of the width of the first gate line structure GS1 in the second direction (Y). In other words, among the protrusions arranged on the same layer, one protrusion may be arranged in the second direction (Y) relative to the center line CL, and another protrusion may be arranged in a direction opposite to the second direction (Y). For example, Figure 4C As shown, the sixteenth protrusion P16 of the first connection region PR1 is located on a first side of the center line CL, and the sixteenth protrusion P16 of the second connection region PR2 is located on a second side of the center line CL opposite to the first side.

[0075] In an embodiment of the present inventive concept, the first protrusions P1 to the sixteenth protrusions P16 of the first connection region PR1 are sequentially arranged at corresponding lower layers along the second direction (Y), and the first protrusions P1 to the sixteenth protrusions P16 of the second connection region PR2 are sequentially arranged at corresponding higher layers along the second direction (Y). For example, one of the protrusions in contact with the first word line cutting region WLC1 among the first protrusions P1 to the sixteenth protrusions P16 included in the first connection region PR1 may be arranged to be higher (e.g., from the substrate 101) than other protrusions sequentially arranged along the second direction (Y). Moreover, one of the protrusions in contact with the first word line cutting region WLC1 among the first protrusions P1 to the sixteenth protrusions P16 included in the second connection region PR2 may be arranged to be lower than other protrusions sequentially arranged in the second direction (Y) (e.g., from the substrate 101).

[0076] In one embodiment, the first to sixteenth protrusions P1 to P16 of the first connection region PR1 and the first to sixteenth protrusions P1 to P16 of the second connection region PR2 are arranged symmetrically with respect to the center line CL (or center point) of the memory cell region CR. Figure 4C In the second connection area PR2, the protrusions P1, P2, P3 and P4 are arranged sequentially from the first word line cutting area WLC1 along the second direction (Y), and in the first connection area PR1, the protrusions P4, P3, P2 and P1 are arranged sequentially from the first word line cutting area WLC1 along the second direction.

[0077] A pad structure for providing electrical connection with the transfer transistor TR_P is formed on the first to sixteenth protrusions P1 to P16 of each of the first to second connection regions PR1 to PR2. The pad structure is formed as a portion of the first to sixteenth gate lines 116_1 to 116_16 exposed to the outside by removing a portion of each of the first to sixteenth gate insulating layers 118_1 to 118_16 from the corresponding first to sixteenth protrusions P1 to P16.

[0078] By forming the first to sixteenth protrusions P1 to P16 that can form a pad structure at both ends of the memory cell region CR, the vertical memory device 100a according to an embodiment of the inventive concept may include: a plurality of transfer transistors TR_P arranged at both sides of the vertical memory device 100a to be adjacent to each of the first connection region PR1 and the second connection region PR2. Therefore, conductive lines for connecting the plurality of transfer transistors TR_P to the first to sixteenth gate lines 116_1 to 116_16 can be easily formed, and the area of ​​the first connection region PR1 and the area of ​​the second connection region PR2 can be reduced.

[0079] Figure 5A perspective view illustrating a gate line structure GS1 a included in a vertical memory device 100 a according to an embodiment of the inventive concept. Figure 6 FIG. 1 is a perspective view showing a gate line structure GS1b included in a vertical memory device 100a according to another embodiment of the inventive concept. Figure 5 and Figure 6 in FIG. 4A to FIG. 4C The same figure numbers are used in the description.

[0080] Reference Figure 5 ,and Figure 4A Compared with the first gate line structure GS1 in the vertical memory device 100a according to the illustrated embodiment, the gate line structure GS1a included in the vertical memory device 100a includes at least one protrusion among the first protrusions P1 to the sixteenth protrusions P16 included in the first connection region PR1 and the second connection region PR2 (for example, at least one of the fourth protrusion P4, the eighth protrusion P8, the twelfth protrusion P12, and the sixteenth protrusion P16 in the first connection region PR1 and the second connection region PR2), and the at least one protrusion is aligned with the first word line cutting region (for example, Figure 4A In other words, the first protrusion P1 to the sixteenth protrusion P16 of the second connection region PR2 are not all stepped relative to each other in the second direction (Y) so that the height of the steps increases sequentially along the second direction (Y). Moreover, the first protrusion P1 to the sixteenth protrusion P16 of the first connection region PR1 are not all stepped relative to each other in the second direction (Y) so that the height of the steps decreases sequentially along the second direction (Y). For example, Figure 4C compared to, Figure 5 The position of the sixteenth protrusion P16 in is interchanged with the position of the fifteenth protrusion P15. Figure 5 In the embodiment, the protrusions P13, P14, P16 and P15 sequentially arranged in the second direction (Y) are arranged in a stepped manner relative to each other, whereby the protrusion P13 is arranged at a layer relatively lower than (i.e., below) the protrusion P14, the protrusion P14 is arranged at a layer relatively lower than (i.e., above) the protrusion P16, and the protrusion P16 is arranged at a layer relatively higher than (i.e., above) the protrusion P15.

[0081] Reference Figure 6 ,and Figure 4A The first gate line structure GS1 and Figure 5Compared with the gate line structure GS1a of the embodiment, the gate line structure GS1b included in the vertical memory device 100a according to the example embodiment includes the first to sixteenth protrusions P1 to P16 of the first connection region PR1, which are asymmetrically arranged with the first to sixteenth protrusions P1 to P16 of the second connection region PR2. Figure 6 In the second connection area PR2, the protrusions P13, P14, P15 and P16 are arranged sequentially from the first word line cutting area WLC1 along the second direction (Y), and in the first connection area PR1, the protrusions P15, P16, P14 and P13 are arranged sequentially from the first word line cutting area WLC1 along the second direction.

[0082] A vertical memory device 100a according to the inventive concept may include Figure 4C The first gate line structure GS1, Figure 5 The gate line structure GS1a and Figure 6 In addition, the gate line structure included in the vertical memory device 100a according to the inventive concept is not limited to Figure 4C The first gate line structure GS1, Figure 5 The gate line structure GS1a and Figure 6 In other embodiments, the plurality of protrusions may have various arrangements.

[0083] The vertical memory device 100a according to an embodiment of the inventive concept may include the first to sixteenth protrusions P1 to P16 at each end of the cell region CR, and a plurality of pass transistors TR_P adjacent to each of the first and second connection regions PR1 and PR2 on both sides of the vertical memory device 100a. Therefore, conductive lines for connecting the plurality of pass transistors TR_P to the first to sixteenth gate lines 116_1 to 116_16 may be easily formed.

[0084] Fig. 7A A top view of a vertical memory device 100 b according to an embodiment of the inventive concept is shown. Figure 7B Shows Fig. 7A The perspective view of the first gate line structure GS1' is shown. Fig. 7A and Figure 7B in FIG. 4A to FIG. 4C The same reference numerals are used in the description.

[0085] Reference Fig. 7A and Figure 7BThe vertical memory device 100b includes a first gate line structure GS1′ and a second gate line structure GS2. Each of the first gate line structure GS1′ and the second gate line structure GS2 includes first to sixteenth gate lines 116_1 to 116_16, which are sequentially stacked from the top surface of the substrate 101 in the third direction (Z).

[0086] The first gate line structure GS1' and the second gate line structure GS2 include a memory cell region CR in which a vertical channel structure CH is formed. The first gate line structure GS1' and the second gate line structure GS2 include a first connection region PR1 and a second connection region PR2 respectively arranged at two ends (e.g., a first end and a second end) of the memory cell region CR. The memory cell region CR is located at a middle position between the first connection region PR1 and the second connection region PR2 along a first direction (X). The first protrusion P1 to the sixteenth protrusion P16 of the first gate line structure GS1' and the second gate line structure GS2 for providing a pad structure are arranged in the first connection region PR1 and the second connection region PR2.

[0087] The vertical memory device 100b includes a first row decoder region RR1 and a second row decoder region RR2. The first row decoder region RR1 is arranged adjacent to the first connection region PR1 in a direction opposite to the first direction (X), and the second row decoder region RR2 is arranged adjacent to the second connection region PR2 in the first direction (X). A plurality of transfer transistors TR_P are formed in the first row decoder region RR1 and the second row decoder region RR2.

[0088] The vertical memory device 100 b includes a plurality of word line cutting regions including a first word line cutting region WLC1 and a second word line cutting region WLC2 . Figure 4A The description of the first word line cutting region WLC1 in Fig. 7A and Figure 7B The first word line cutting area WLC1 in the Figure 4A The description of the second word line cutting region WLC2 in FIG. Fig. 7A and Figure 7B The second word line cutting region WLC2 in the.

[0089] The vertical memory device 100b includes a sub-word line cutting region WLC_S. The sub-word line cutting region WLC_S may be formed within the first gate line structure GS1'. For example, the sub-word line cutting region WLC_S may be formed to pass through the center of the width of the first gate line structure GS1' in the second direction (Y) and extend in a direction parallel to the first direction (X).

[0090] Therefore, the first gate line structure GS1' is divided into a first sub-gate line structure SGS1 and a second sub-gate line structure SGS2 by the sub-word line cutting region WLC_S. The first word line cutting region WLC1 and the sub-word line cutting region WLC_S may limit the width of the first sub-gate line structure SGS1 and the second sub-gate line structure SGS2 in the second direction (Y).

[0091] Each of the first sub-grid structure SGS1 and the second sub-grid structure SGS2 may correspond to a sub-unit block. For example, the first sub-grid structure SGS1 may constitute a first sub-unit block, and the second sub-grid structure SGS2 may constitute a second sub-unit block. The first sub-unit block and the second sub-unit block may operate as different unit blocks, and therefore, the control logic ( Figure 1 150) can control the row decoder ( Figure 1 120) respectively controls the first sub-unit block and the second sub-unit block. Compared with the second unit block formed by the second gate line structure GS2, the first sub-unit block and the second sub-unit block may have a smaller width in the second direction (Y) and include a smaller number of memory cells therein.

[0092] Reference will be made later Figure 8 The connection relationship between the first sub-gate line structure SGS1 , the second sub-gate line structure SGS2 , and the transfer transistor TR_P is described.

[0093] Similar to About FIG. 4A to FIG. 4C The arrangement described above, the first protrusion P1 to the sixteenth protrusion P16 of the first connection region PR1 have a step shape (ie, arrangement) in the first direction (X) and the second direction (Y). FIG. 4A to FIG. 4C In the arrangement described, the first protrusion P1 to the sixteenth protrusion P16 of the second connection area PR2 have a step shape (i.e., arrangement) in the first direction (X) and the second direction (Y). In other words, the protrusions P1 to P16 are arranged as steps along the first direction (X) and the second direction (Y) perpendicular to the first direction (X). The first sub-gate line structure SGS1 includes 8 protrusions of the first protrusion P1 to the sixteenth protrusion P16 arranged in each of the first connection area PR1 and the second connection area PR2 of the first gate line structure GS1', and the second sub-gate line structure SGS2 includes the remaining 8 protrusions of the first protrusion P1 to the sixteenth protrusion P16 arranged in each of the first connection area PR1 and the second connection area PR2 of the first gate line structure GS1'.

[0094] About FIG. 4A to FIG. 4CSimilar to the above, the protrusions arranged on the same layer among the plurality of protrusions P1 to P16 are arranged diagonally relative to each other in the first direction (X). Therefore, the first protrusions P1 of the first connection area PR1 and the second connection area PR2 in the first gate line structure GS1' are placed diagonally relative to the first direction (X) (for example, the center line of the memory cell area (i.e., the cell area) along the sub-word line cutting area WLC_S, the center line of the memory cell area is parallel to the first direction (X)). The protrusions arranged on the same layer are arranged non-parallel to each other in the first direction (X), or in other words, the protrusions arranged on the same layer are not collinear with each other in the first direction (X), and are not aligned with each other in the second direction (Y). In other words, the first protrusion P1 of the first connection area PR1 is, for example, formed or arranged to be parallel to the protrusion (or multiple protrusions) formed on the (different) layer other than the first layer L1 among the layers L1 to L16 in the second connection area PR2 in the first direction (X). For example, the first protrusion P1 of the first sub-gate line structure SGS1 is arranged in the first connection region PR1, and the first protrusion P1 of the second sub-gate line structure SGS2 is arranged in the second connection region PR2.

[0095] In an embodiment of the present invention, among the first to sixteenth protrusions P1 to P16 included in each of the first to sixteenth gate lines 116_1 to 116_16, the protrusions arranged on the same layer may be arranged in opposite directions relative to a center line (e.g., along a center line of a sub-word line cutting region WLC_S) that is parallel to the first direction (X) and passes through the center of the width of the first gate line structure GS1' in the second direction (Y). Therefore, even if the sub-word line cutting region WLC_S is formed at the center of the first gate line structure GS1' and the first and second sub-gate line structures SGS1 and SGS2 are separated from each other, each of the first and second sub-gate line structures SGS1 and SGS2 may include at least one of the first to sixteenth protrusions P1 to P16.

[0096] About FIG. 4A to FIG. 4CSimilar to what has been described, in an embodiment of the present invention, the first protrusions P1 to the sixteenth protrusions P16 of the first connection region PR1 are arranged sequentially below the corresponding layer along the second direction (Y), and the first protrusions P1 to the sixteenth protrusions P16 of the second connection region PR2 are arranged sequentially above the corresponding layer along the second direction (Y). For example, one protrusion among the first protrusions P1 to the sixteenth protrusions P16 included in the first connection region PR1 that contacts the first word line cutting region WLC1 may be arranged higher (e.g., from the substrate 101) than other protrusions sequentially arranged along the second direction (Y). Moreover, one protrusion among the first protrusions P1 to the sixteenth protrusions P16 included in the second connection region PR2 that contacts the first word line cutting region WLC1 may be arranged lower than other protrusions sequentially arranged in the second direction (Y). However, the vertical memory device 100b according to the present invention is not limited thereto, and in the example of Figure 5 and Figure 6 In other embodiments shown, among the first to sixteenth protrusions P1 to P16 included in the first connection region PR1 and the second connection region PR2, at least one protrusion spaced apart from the first word line cutting region WLC1 may be arranged higher from the substrate 101 than other protrusions arranged along the second direction (Y).

[0097] exist Fig. 7A , the vertical memory device 100b is shown to include a first gate line structure GS1' having a first sub-gate line structure SGS1 and a second sub-gate line structure SGS2 and a second gate line structure GS2 that is not divided into sub-gate line structures. However, the inventive concept is not limited thereto, and in other embodiments, the vertical memory device 100b may include at least one gate line structure divided into a plurality of sub-gate line structures.

[0098] The vertical memory device 100b of the embodiment conceived according to the present invention includes a gate line structure divided into a plurality of sub-gate line structures, so that the vertical memory device 100b may include a sub-unit block (e.g., a first sub-unit block and a second sub-unit block corresponding to the first sub-gate line structure SGS1 and the second sub-gate line structure SGS2, respectively) whose capacity is smaller than that of a general unit block (e.g., a second unit block corresponding to the second gate line structure GS2). In these corresponding embodiments, when only some memory cells of a general unit block are sufficient, the vertical memory device 100b can use a sub-unit block instead of a general unit block. Therefore, the waste of using all parts of a general unit block can be reduced. Therefore, the size of the semiconductor chip in which the vertical memory device 100b is implemented can be reduced.

[0099] Figure 8 Shown according to Fig. 7A FIG. 1 is an enlarged top view of a portion B of a vertical memory device 100 b of an embodiment of FIG. Figure 8 1 is a diagram for explaining the connection relationship between the first protrusion P1 to the sixteenth protrusion P16 and the transfer transistor TR_P. Figure 8 in Fig. 7A and Figure 7B The same reference numerals as in the description are used in conjunction with the reference numerals in the accompanying drawings.

[0100] Reference Figure 8 A first transfer transistor TR11 electrically connected to the first sub-gate line structure SGS1 and a second transfer transistor TR12 electrically connected to the second sub-gate line structure SGS2 are formed in the first row decoder region RR1. A first transfer transistor TR21 electrically connected to the second sub-gate line structure SGS2 and a second transfer transistor TR22 electrically connected to the first sub-gate line structure SGS1 are formed in the second row decoder region RR2.

[0101] At least one of the first and second transfer transistors TR11 and TR12 of the first row decoder region RR1 and the first and second transfer transistors TR21 and TR22 of the second row decoder region RR2 may be electrically connected to a plurality of different protrusions.

[0102] For example, the first protrusion P1 and the second protrusion P2 of the first connection region PR1 may be electrically connected to each other, and thus may be electrically connected to the same transfer transistor TR_P. The third protrusion P3 and the fourth protrusion P4 of the second connection region PR2 may be electrically connected to each other, and thus may be electrically connected to the same transfer transistor TR_P. In addition, the ninth protrusion P9, the tenth protrusion P10, the thirteenth protrusion P13, and the fourteenth protrusion P14 of the first connection region PR1 may be electrically connected to each other, and thus may be electrically connected to the same transfer transistor TR_P. The eleventh protrusion P11, the twelfth protrusion P12, the fifteenth protrusion P15, and the sixteenth protrusion P16 of the second connection region PR2 may be electrically connected to each other, and thus may be electrically connected to the same transfer transistor TR_P. Therefore, each of the fifth protrusion P5, the sixth protrusion P6, the seventh protrusion P7, and the eighth protrusion P8 in the first sub-gate line structure SGS1 may be connected to respective different corresponding transfer transistors.

[0103] The description of the first to sixteenth protrusions P1 to P16 of the first sub-gate line structure SGS1 may also be applied to the first to sixteenth protrusions P1 to P16 of the second sub-gate line structure SGS2.

[0104] In the vertical memory device 100b according to the present invention, the first sub-gate line structure SGS1 may correspond to the first sub-unit block, and the second sub-gate line structure SGS2 may correspond to the second sub-unit block. When only some memory cells of the first sub-unit block and the second sub-unit block are used, the gate line and the transfer transistor may be connected to each other in a one-to-one manner so that the gate line (in which only some memory cells used (for example, Figure 4B The row line voltages (e.g., word line voltages) of the gate lines 116_5, 116_6, 116_7, and 116_8) in the memory cells are controlled respectively. On the other hand, the gate lines of the layers on which the unused memory cells are formed may be electrically connected to each other, and one transfer transistor TR_P may switch the row line voltages (e.g., word line voltages, ground selection line voltages, or string selection line voltages) applied to the plurality of gate lines connected to each other.

[0105] The vertical memory device 100b may include a smaller number of pass transistors TR_P than the number corresponding to the number of the plurality of gate lines included in the first sub-gate line structure SGS1 and the number of the plurality of gate lines included in the second sub-gate line structure SGS2. Therefore, the vertical memory device 100b according to the inventive concept may include a reduced number of pass transistors TR_P and may simultaneously control the operations of unused memory cells.

[0106] Fig. 9 A block diagram of a memory cell array 110 included in a vertical memory device 100 b according to an embodiment of the inventive concept is shown.

[0107] Reference Fig. 9 , the memory cell array 110 includes first to n-th cell blocks BLK1 , BLK2 to BLKn. Figure 2 The cell block 111 in the embodiment may be one of the first to nth cell blocks BLK1 to BLKn.

[0108] The first unit block BLK1 to the kth unit block BLKk may include the first data block BLK1 to the (k-1)th data block BLKk-1 for storing data and at least one spare block BLKk. Here, k may be a natural number of 3 or greater. In one embodiment, the spare block BLKk may be a unit block for replacing a bad block when a bad block is generated among the first data block BLK1 to the (k-1)th data block BLKk-1. In one embodiment, the spare block BLKk may be used to store data recovered after an error correction code (ECC) decoding process fails in the first data block BLK1 to the (k-1)th data block BLKk-1.

[0109] Since the purpose of use of the spare block BLKk is different from that of the first to (k-1)th data blocks BLKk-1, it may be important to utilize the unit blocks differently by increasing the number of unit blocks rather than by increasing the storage capacity of the unit blocks. Therefore, the spare block BLKk may be implemented to include a first sub-unit block and a second sub-unit block, such as by utilizing Fig. 7A When the spare block BLKk includes a plurality of sub-cell blocks, the size of the entire semiconductor chip in which the vertical memory device 100b is implemented can be reduced.

[0110] The vertical memory device 100b according to the inventive concept is not limited to the spare block BLKk including a plurality of sub-unit blocks, and in other embodiments, at least one data block among the first to (k-1)th data blocks BLKk-1 may include a plurality of sub-unit blocks.

[0111] Fig.10 A diagram of a computing system device 1000 including a vertical memory device according to an embodiment of the inventive concept is shown.

[0112] Reference Fig.10 , the computing system device 1000 includes a central processing unit (CPU) 1030 electrically connected to a bus 1060 , a user interface 1050 , and a nonvolatile memory device 1010 including a memory controller 1012 and a nonvolatile memory device 1011 .

[0113] The nonvolatile memory device 1011 may include Figure 1 The vertical storage device 100 shown in Figure 4A The vertical memory device 100a or Fig. 7A Therefore, the size of a memory chip in which the nonvolatile memory device 1011 is implemented can be reduced, and a manufacturing process thereof can be facilitated.

[0114] The computing system device 1000 may further include a RAM 1040 and a power supply 1020 .

[0115] When the computing system device 1000 is a mobile device, a battery for supplying its operating voltage and a modem such as a baseband chipset may be additionally provided. In addition, it should be understood by those skilled in the art that the computing system device 1000 may also include, for example, an application chipset, a camera image processor (CIS), a mobile dynamic RAM (DRAM), and various other components, and a detailed description thereof is omitted.

[0116] The memory controller 1012 and the nonvolatile memory device 1011 may constitute, for example, a solid state drive / solid state disk (SSD) that uses a nonvolatile memory to store data.

[0117] Although the inventive concept has been particularly shown and described with reference to example embodiments of the inventive concept, the inventive concept is not limited to the example embodiments, and various changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the inventive concept.

Claims

1. A vertical storage device, comprising: A gate line structure, comprising a first gate line and a second gate line, wherein the first gate line and the second gate line are sequentially stacked on a substrate and extend in a first direction parallel to a top surface of the substrate; as well as a vertical channel structure configured to penetrate the gate line structure in a direction perpendicular to the top surface of the substrate, The gate line structure includes a unit area in which the vertical channel structure is formed, and a first connection area and a second connection area respectively arranged at a first end and a second end of the unit area along the first direction. Each of the first connection region and the second connection region includes a first protrusion of the first gate line and a second protrusion of the second gate line, the first protrusion of the first gate line and the second protrusion of the second gate line are parallel to the top surface of the substrate and are arranged as steps in a second direction perpendicular to the first direction, and The first protrusions of the second connection region and the first protrusions of the first connection region are arranged diagonally with respect to the first direction.

2. The vertical storage device according to claim 1, wherein: The first and second protrusions of the first connection region and the first and second protrusions of the second connection region are arranged symmetrically about a center point of the unit region.

3. The vertical storage device according to claim 1, wherein: The first and second protrusions of the first connection region and the first and second protrusions of the second connection region are asymmetrically arranged.

4. The vertical storage device according to claim 1, wherein: The gate line structure also includes a third gate line, which is stacked on the second gate line and extends in the first direction parallel to the top surface of the substrate, wherein each of the first connection area and the second connection area includes a third protrusion of the third gate line, the third protrusion is arranged as a step with the first protrusion and the second protrusion in the second direction, and the third protrusion of the second connection area is arranged diagonally with the third protrusion of the first connection area with respect to the first direction.

5. The vertical storage device according to claim 4, wherein: In the first connection region, the first protrusion, the second protrusion, and the third protrusion are sequentially arranged in the second direction.

6. The vertical storage device according to claim 4, wherein: In the first connection region, the first protrusion, the third protrusion, and the second protrusion are sequentially arranged in the second direction.

7. The vertical storage device according to claim 1, wherein: The first protrusion of the first connection region and the first protrusion of the second connection region are arranged in opposite regions with respect to a center line of the unit region parallel to the first direction.

8. The vertical memory device according to claim 7, further comprising a word line cutting region extending along the center line, wherein The gate line structure includes a first sub-gate line structure and a second sub-gate line structure separated by the word line cutting region.

9. A vertical storage device, comprising: A gate line structure, comprising a plurality of gate lines, the plurality of gate lines being sequentially stacked on a substrate and extending in a first direction parallel to a top surface of the substrate; as well as a vertical channel structure configured to penetrate the gate line structure in a direction perpendicular to the top surface of the substrate, The gate line structure includes: a unit region in which the vertical channel structure is formed, and a first connection region and a second connection region respectively arranged at a first end and a second end of the unit region along the first direction. Each of the first connection region and the second connection region includes a plurality of protrusions of the plurality of gate lines, the plurality of protrusions being arranged as steps in the first direction and in a second direction perpendicular to the first direction, and Each of the plurality of protrusions of the first connection region is arranged along the first direction parallel to the protrusions of the plurality of protrusions of the second connection region that are located on different layers of the plurality of gate lines, The plurality of protrusions in the first connection area are arranged as steps with decreasing heights along the second direction, and the plurality of protrusions in the second connection area are arranged as steps with increasing heights along the second direction.

10. The vertical storage device according to claim 9, wherein: The plurality of protrusions of the first connection region and the plurality of protrusions of the second connection region are arranged symmetrically with respect to a center point of the unit region.

11. The vertical storage device according to claim 9, wherein: The protrusions among the multiple protrusions located on the same layer of the multiple gate lines include a first protrusion in the first connection area and a second protrusion in the second connection area, wherein the first protrusion and the second protrusion are arranged in opposite directions to each other about a center line, and the center line is parallel to the first direction and passes through the center of the width of the gate line structure in the second direction.

12. The vertical memory device according to claim 11, further comprising a word line cutting region extending along the center line, wherein The gate line structure includes a first sub-gate line structure and a second sub-gate line structure separated by the word line cutting region.

13. A vertical storage device comprising: A gate line structure, comprising a plurality of gate lines, the plurality of gate lines being sequentially stacked on a substrate and extending in a first direction parallel to a top surface of the substrate; a vertical channel structure configured to penetrate the gate line structure in a direction perpendicular to a top surface of the substrate; and a plurality of transfer transistors electrically connected to the plurality of gate lines, The gate line structure includes a unit region in which the vertical channel structure is formed, and a first connection region and a second connection region respectively arranged at a first end and a second end of the unit region in the first direction. Each of the first connection region and the second connection region includes a plurality of protrusions of the plurality of gate lines, the plurality of protrusions being arranged as steps in the first direction and in a second direction perpendicular to the first direction, and Protrusions among the plurality of protrusions located on the same layer of the plurality of gate lines are arranged to be misaligned with each other in the second direction.

14. The vertical storage device according to claim 13, wherein: Each of the plurality of gate lines is connected to one transfer transistor among the plurality of transfer transistors via at least one protrusion among the plurality of protrusions that is located on a same layer as the plurality of gate lines.

15. The vertical storage device according to claim 13, further comprising: A word line cutting region, wherein the word line cutting region is configured to pass through the center of the width of the gate line structure in the second direction and is configured to extend along a center line parallel to the first direction, wherein the gate line structure includes a first sub-gate line structure and a second sub-gate line structure separated by the word line cutting region.

16. The vertical storage device according to claim 15, wherein: Some of the protrusions located on different layers of the plurality of gate lines among the plurality of protrusions in the first sub-gate line structure are electrically connected to each other, and the some of the protrusions are electrically connected to one transfer transistor among the plurality of transfer transistors.

17. The vertical storage device according to claim 15, wherein: The plurality of transfer transistors include: a plurality of first transfer transistors connected to protrusions located in the first sub-gate line structure among the plurality of protrusions; and a plurality of second transfer transistors connected to protrusions located in the second sub-gate line structure among the plurality of protrusions.

18. The vertical storage device according to claim 17, wherein: Some of the plurality of first transfer transistors are arranged in a first row decoder region adjacent to the first connection region, and other of the plurality of first transfer transistors are arranged in a second row decoder region adjacent to the second connection region, and Some of the plurality of second pass transistors are arranged in the first row decoder region, and other second pass transistors of the plurality of second pass transistors are arranged in the second row decoder region.

19. The vertical storage device according to claim 13, wherein: The plurality of protrusions of the first connection region and the plurality of protrusions of the second connection region are arranged symmetrically about a center point of the unit region.

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