Integrated Circuit Devices

Abstract

An integrated circuit device includes: a substrate having a cell array region including a first active region and a peripheral circuit region including a second active region; a direct contact connected to the first active region in the cell array region; a bit line structure connected to the direct contact in the cell array region; and a peripheral circuit gate structure on the second active region in the peripheral circuit region, wherein the peripheral circuit gate structure includes two doped semiconductor layers, each of which is doped with carrier impurities having different doping concentrations from each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0055654 filed on May 15, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept according to exemplary embodiments relates to an integrated circuit device, and

[0004] More particularly, it relates to an integrated circuit device including a conductive contact plug and a conductive line connected to each other. Background Art

[0005] As integrated circuit devices are rapidly reduced in size in recent years, it may be difficult to ensure a sufficient contact area because the gap between conductive lines is narrowed and the area occupied by contact plugs connected to the conductive lines is gradually reduced. Therefore, it is necessary to develop a technology for realizing an integrated circuit device in which a contact plug arranged in a narrow space with a relatively high aspect ratio and a conductive line formed thereon have a stable and reliable structure. Summary of the invention

[0006] The inventive concept according to exemplary embodiments provides an integrated circuit device in which a contact plug and a conductive line have a stable and reliable structure even if an area of ​​a device region is reduced due to size reduction of a semiconductor device.

[0007] According to one aspect of the present invention, an integrated circuit device is provided, which includes: a substrate having a cell array region and a peripheral circuit region, the cell array region including a first active region, and the peripheral circuit region including a second active region; a direct contact connected to the first active region in the cell array region; a bit line structure connected to the direct contact in the cell array region; and a peripheral circuit gate structure located on the second active region in the peripheral circuit region, wherein the peripheral circuit gate structure includes two doped semiconductor layers, each of which is doped with carrier impurities having different doping concentrations from each other.

[0008] According to another aspect of the inventive concept, an integrated circuit device is provided, which includes: a substrate having a cell array region and a peripheral circuit region, the cell array region including a plurality of first active regions spaced apart from each other, and the peripheral circuit region including a second active region; a plurality of direct contacts, each of which is connected to a corresponding one of the plurality of first active regions in the cell array region; a plurality of bit line structures, which extend parallel to each other in a first direction in the cell array region, each of the plurality of bit line structures is connected to a corresponding one of the plurality of direct contacts; and a peripheral circuit gate structure, which is located on the second active region in the peripheral circuit region, wherein the peripheral circuit gate structure includes two doped semiconductor layers, each of which is doped with carrier impurities and has different doping concentrations from each other, and wherein each of the plurality of direct contacts includes a contact semiconductor layer having a doping concentration lower than the doping concentration of at least one of the two doped semiconductor layers.

[0009] According to another aspect of the inventive concept, an integrated circuit device is provided, the integrated circuit device comprising: a substrate having a cell array region and a peripheral circuit region, the cell array region comprising a first active region, and the peripheral circuit region comprising a second active region; a direct contact connected to the first active region in the cell array region and comprising a doped contact semiconductor layer doped with carrier impurities having a first doping concentration; a bit line structure located above the substrate in the cell array region, the bit line structure comprising a bit line semiconductor layer, the bit line semiconductor layer contacting a top surface of the direct contact and having a doping concentration higher than the first doping concentration; A direct contact spacer, which contacts a first side wall portion of a side wall of the direct contact and includes an undoped semiconductor that is not doped with carrier impurities, the first side wall portion being between the substrate and the bit line structure; an insulating spacer, which contacts a second side wall portion of the side wall of the direct contact and covers the side wall of the bit line structure; and a peripheral circuit gate structure, which is located on a second active region in the peripheral circuit region, wherein the peripheral circuit gate structure includes a first gate semiconductor layer and a second gate semiconductor layer, the first gate semiconductor layer having a doping concentration equal to or higher than the first doping concentration, and the second gate semiconductor layer having a doping concentration higher than the first doping concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing an example of a configuration of an integrated circuit device including a DRAM device;

[0012] Figure 2 is a plan view showing a schematic configuration of an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 3 It is shown Figure 2 A schematic planar layout of the major components of the memory cell array region is shown;

[0014] Figures 4 to 7 are cross-sectional views each showing a main part of an integrated circuit device according to an embodiment of the inventive concept;

[0015] FIG. 8A to FIG. 8P are cross-sectional views illustrating sequential processes of a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept;

[0016] 9A to 9E are cross-sectional views showing sequential processes of a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept;

[0017] FIG. 10A to FIG. 10C are cross-sectional views showing sequential processes of a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept;

[0018] FIG. 11A to FIG. 11E are cross-sectional views illustrating sequential processes of a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept; and

[0019] FIG. 12A to FIG. 12F are cross-sectional views illustrating sequential processes of a method of fabricating an integrated circuit device according to other embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to the same components, and repeated descriptions thereof will be omitted.

[0021] Figure 1 is a block diagram showing an example of the configuration of an integrated circuit device 10 including a DRAM device.

[0022] Reference Figure 1 In the integrated circuit device 10, the first region 22 may be a memory cell region of a DRAM device, and the second region 24 may be a peripheral circuit region of the DRAM device. The first region 22 may include a memory cell array 22A. In the memory cell array 22A, a plurality of memory cells for storing data may be arranged in row and column directions.

[0023] The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, a mode register set / extended mode register set (MRS / EMRS) circuit 62, an address buffer 64 and a data input / output circuit 66.

[0024] The sense amplifier 54 may sense and amplify data of the memory cell, and may store the data in the memory cell. The sense amplifier 54 may be implemented as a cross-coupled amplifier connected between a bit line and a complementary bit line included in the memory cell array 22A.

[0025] The data DQ input through the data input / output circuit 66 may be written to the memory cell array 22A based on the address signal ADD, and the data DQ read from the memory cell array 22A based on the address signal ADD may be output to a device (not shown) outside the integrated circuit device 10 through the data input / output circuit 66. In order to specify a memory cell to which data is written or from which data is read, the address signal ADD may be input to the address buffer 64. The address buffer 64 may temporarily store the address signal ADD input from a device (not shown) outside the integrated circuit device 10.

[0026] The row decoder 52 may decode a row address in the address signal ADD output from the address buffer 64 to specify a word line connected to a memory cell to which data is input or from which data is output. For example, in a data write or read mode, the row decoder 52 may decode a row address output from the address buffer 64, thereby enabling a corresponding word line. In addition, in a self-refresh mode, the row decoder 52 may decode a row address generated from an address counter, thereby enabling a corresponding word line.

[0027] The column decoder 56 can decode the column address in the address signal ADD output from the address buffer 64 to specify the bit line connected to the memory cell to which data is input or from which data is output. The memory cell array 22A can output data from the memory cell specified by the row address and the column address, or write data to the memory cell.

[0028] The command decoder 60 may receive command signals CMD applied from a device (not shown) outside the integrated circuit device 10 and may decode these signals to internally generate decoded command signals, such as a self refresh entry command or a self refresh exit command.

[0029] The MRS / EMRS circuit 62 may set an internal mode register in response to the address signal ADD and an MRS / EMRS command for designating an operation mode of the integrated circuit device 10 .

[0030] The integrated circuit device 10 may further include a clock circuit for generating a clock signal, a power supply circuit that receives a power supply voltage applied from a device (not shown) outside the integrated circuit device 10 and generates or distributes an internal voltage, and the like.

[0031] The self-refresh control circuit 58 may control the self-refresh operation of the integrated circuit device 10 in response to a command output from the command decoder 60. The command decoder 60 may include an address counter, a timer, and a core voltage generator. The address counter may generate a row address for specifying a row address as a target of self-refresh in response to a self-refresh entry command output from the command decoder 60, and apply the row address to the row decoder 52. The address counter may stop the counting operation in response to a self-refresh exit command output from the command decoder 60.

[0032] Figure 2 is a plan view illustrating a schematic configuration of an integrated circuit device according to an embodiment of the inventive concept.

[0033] Reference Figure 2 , the integrated circuit device 70 includes a plurality of first regions 22. Each of the plurality of first regions 22 may be surrounded by a second region 24, and an interface region 26 is located therebetween. In the integrated circuit device 70, each of the plurality of first regions 22 may be a memory cell array region MCA of a DRAM device, and the second region 24 may be a peripheral circuit region of the DRAM device. Among the plurality of first regions 22, the memory cell array region MCA may include reference Figure 1 Memory cell array 22A is described.

[0034] The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a connection block CJT. A plurality of bit line sense amplifiers may be arranged in the sense amplifier block S / A. The connection block CJT may be arranged at a cross point between the sub-word line driver block SWD and the sense amplifier block S / A. A power driver and a ground driver for driving the bit line sense amplifier may be alternately arranged in the connection block CJT. Peripheral circuits such as an inverter chain, an input / output circuit, etc. may also be formed in the second region 24.

[0035] Figure 3 It is shown Figure 2 FIG. 4 is a schematic plan layout of main components of the memory cell array area MCA shown.

[0036] Reference Figure 3 The memory cell array area MCA may include a plurality of cell active areas A1. Each of the plurality of cell active areas A1 may be arranged to have a long axis in an inclined direction with respect to an X direction and a Y direction that are perpendicular to each other.

[0037] The plurality of word lines WL may extend parallel to each other in the X direction across the plurality of cell active regions A1. The plurality of bit lines BL may extend parallel to each other in the Y direction on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of cell active regions A1 via direct contacts DC.

[0038] A plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged linearly in the X direction and the Y direction. A plurality of landing pads LP may be formed on the plurality of buried contacts BC, respectively. The plurality of buried contacts BC and the plurality of mounting pads LP may connect the bottom electrode (not shown) of the capacitor formed on the plurality of bit lines BL to the cell active region A1. Each of the plurality of mounting pads LP may partially overlap the buried contact BC.

[0039] Figure 4 is a cross-sectional view illustrating a main portion of an integrated circuit device 100 according to an embodiment of the inventive concept. Figure 4 The cross-sectional structure of the cell array region CELL and the peripheral circuit region CORE / PERI is shown. The cell array region CELL can be referred to as Figure 1 and Figure 2 The peripheral circuit region CORE / PERI may be referred to as Figure 1 and Figure 2 A portion of the second region 24 is described. Figure 4 The cell array region CELL shows the Figure 3 Cross-sectional structures of some areas intercepted by lines AA' and BB'.

[0040] Reference Figure 4 , the integrated circuit device 100 includes a substrate 110 having a cell array region CELL and a peripheral circuit region CORE / PERI. The semiconductor substrate 110 may be formed of a crystalline semiconductor material, and may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a single crystal silicon substrate. For example, the substrate 110 may include a semiconductor element such as Si, Ge, etc., or at least one compound semiconductor selected from SiGe, SiC, GaAs, InAs, and InP. The substrate 110 may include a conductive region, for example, a well doped with impurities (for example, doped with carrier impurities having N-type or P-type impurities).

[0041] In the cell array region CELL and the peripheral circuit region CORE / PERI, a plurality of device isolation trenches 112T are formed in the substrate 110, and a plurality of device isolation films 112 may respectively fill the plurality of device isolation trenches 112T. Through the plurality of device isolation films 112, a plurality of cell active regions A1 may be defined in the cell array region CELL of the substrate 110, and a peripheral circuit active region A2 may be defined in the peripheral circuit region CORE / PERI of the substrate 110.

[0042] The width of the device isolation film 112 arranged in the cell array region CELL in a direction parallel to the top surface of the substrate 110 may be smaller than the width of the device isolation film 112 arranged in the peripheral circuit region CORE / PERI in a direction parallel to the top surface of the substrate 110. The device isolation film 112 may include a silicon oxide film, a silicon nitride film, or a combination thereof. The device isolation film 112 may include a single layer including one insulating film, a double layer including two insulating films, or a multilayer including a combination of at least three insulating films. In the peripheral circuit region CORE / PERI, the device isolation film 112 may include a first insulating pad 112A and a second insulating pad 112B, which are formed on the inner wall of the device isolation trench 112T in the stated order; and the device isolation film 112 may include a filling insulating film 112C, which is located on the second insulating pad 112B and fills the device isolation trench 112T. Therefore, according to this exemplary embodiment, the second insulating pad 112B is formed between the first insulating pad 112A and the filling insulating film 112C. In some embodiments, the first insulating pad 112A may include an oxide film, the second insulating pad 112B may include a nitride film, and the filling insulating film 112C may include an oxide film. The oxide film constituting the first insulating pad 112A may include a medium temperature oxidation (MTO) film, a high density plasma (HDP) oxide film, a thermal oxide film, a tetraethyl orthosilicate (TEOS) film, or an undoped silicate glass (USG) film. The second insulating pad 112B may include a silicon nitride film. The oxide film constituting the filling insulating film 112C may include an HDP oxide film, a USG oxide film, a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), a polysilazane, or a combination thereof.

[0043] In the cell array region CELL, a plurality of word line trenches 120T may be formed in the substrate 110, and the plurality of word line trenches 120T may extend parallel to each other. A gate dielectric film 122, a word line 124, and a buried insulating film 126 may be formed inside each of the plurality of word line trenches 120T. The plurality of word lines 124 may be arranged in a direction ( Figure 3 Extend parallel to each other in the X direction (in the X direction).

[0044] The gate dielectric film 122 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. The high-k dielectric film may have a dielectric constant of about 10 to about 25, and may include, for example, HfO 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 or TiO 2 Terms such as "substantially," "about," or "approximately" may reflect an amount, size, orientation, or arrangement that varies only in a relatively minor manner and / or in a manner that does not appreciably alter the operation, function, or structure of a particular element. For example, a range of "about 0.1 to about 1" may encompass, for example, a range of 0%-5% deviations around 0.1 and a range of 0%-5% deviations around 1, especially if such deviations maintain the same effect as the recited range.

[0045] The word line 124 may include a gate pad 124A, a lower gate line 124B, and an upper gate line 124C. The gate pad 124A may contact the gate dielectric film 122, and the lower gate line 124B may be surrounded by the gate pad 124A and the upper gate line 124C and separated from the gate dielectric film 122. In some embodiments, the gate pad 124A may include TiN, the lower gate line 124B may include W, and the upper gate line 124C may include doped polysilicon. The word line 124 may constitute Figure 3 Multiple word lines WL are shown. It should be understood that when an element is referred to as contacting another element, there are no intervening elements at the point of contact.

[0046] The buried insulating film 126 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0047] A plurality of source / drain regions 116 may be formed in portions of the plurality of unit active regions A1 near a top surface of the substrate 110 .

[0048] In the cell array region CELL, a buffer insulating film 130 may be formed on the substrate 110. The buffer insulating film 130 may include a single insulating film or a plurality of insulating films. In some embodiments, the buffer insulating film 130 may include an oxide film, a nitride film, a metal-containing insulating film, or a combination thereof. In some embodiments, the metal-containing insulating film may constitute the uppermost portion of the buffer insulating film 130. For example, the metal-containing insulating film may include a hafnium oxide film, an aluminum oxide film, or an aluminum nitride film, but is not limited thereto.

[0049] In the cell array region CELL, a plurality of bit line structures BLS may be arranged in a direction intersecting the word line 124 ( Figure 3 The bit line structures BLS extend parallel to each other on the substrate 110 in the Y direction (in the Y direction). Each of the plurality of bit line structures BLS may be connected to a corresponding one of the plurality of cell active regions A1 via a direct contact DC.

[0050] A peripheral circuit transistor PTR may be formed in the peripheral circuit region CORE / PERI. The peripheral circuit transistor PTR may include a peripheral circuit gate structure PGS formed on the peripheral circuit active region A2. The peripheral circuit gate structure PGS may include a dielectric layer 142, a metal-containing work function adjustment layer 144, a first gate semiconductor layer 150P, a second gate semiconductor layer 156P, a first conductive layer 162P, a second conductive layer 164P, and an insulating capping layer 166P, which are stacked on the substrate 110 in the stated order. For example, the top surface of the dielectric layer 142 and the bottom surface of the metal-containing work function adjustment layer 144 are in contact with each other, the top surface of the metal-containing work function adjustment layer 144 and the bottom surface of the first gate semiconductor layer 150P are in contact with each other, the top surface of the first gate semiconductor layer 150P and the bottom surface of the second gate semiconductor layer 156P are in contact with each other, the top surface of the second gate semiconductor layer 156P and the bottom surface of the first conductive layer 162P are in contact with each other, the top surface of the first conductive layer 162P and the bottom surface of the second conductive layer 164P are in contact with each other, and the top surface of the second conductive layer 164P and the bottom surface of the insulating capping layer 166P are in contact with each other. In the peripheral circuit gate structure PGS, the first gate semiconductor layer 150P and the second gate semiconductor layer 156P may have different doping concentrations from each other. The first gate semiconductor layer 150P and the second gate semiconductor layer 156P may be used to control the work function of the peripheral circuit transistor PTR.

[0051] In some embodiments, the peripheral circuit transistor PTR may be formed only in the peripheral circuit region CORE / PERI instead of the cell array region CELL, and the direct contact DC may be formed only in the cell array region CELL instead of the peripheral circuit region CORE / PERI.

[0052] The dielectric layer 142 may include a single dielectric layer or a plurality of dielectric layers. The dielectric layer 142 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, a high-k dielectric film, or a combination thereof. The high-k dielectric film is a film having a dielectric constant higher than that of the silicon oxide film, and may include, for example, HfO 2 、Al 2 O 3 、HfAlO 3 、 2 O 3 or TiO 2 .

[0053] The metal-containing work function adjustment layer 144 may include a metal, a conductive metal nitride, a conductive metal carbide, a conductor including metal atoms, or a combination thereof. The metal-containing work function adjustment layer 144 may have a single-layer structure or a multi-layer structure. The metal-containing work function adjustment layer 144 may include at least one material selected from Ti, Ta, Al, Ni, Co, La, Pd, Nb, Mo, Hf, Ir, Ru, Pt, Yb, Dy, Er, Pd, TiAl, HfSiMo, TiN, WN, TaN, RuN, MoN, TiAlN, TaC, TiC, and TaC. In some embodiments, the metal-containing work function adjustment layer 144 may include at least one material selected from TiN / TaN, Al 2 O 3 At least one stacked structure of TiN / TiN, Al / TiN, TiN / Al / TiN, TiN / TiON, Ta / TiN, TaN / TiN, La / TiN, Mg / TiN, and Sr / TiN. Here, TiN may be replaced by TaN, TaCN, TiCN, CoN, or CoCN, and La may be replaced by LaO or LaON. In some embodiments, the metal-containing work function adjustment layer 144 may be omitted.

[0054] In some embodiments, each of the first gate semiconductor layer 150P and the second gate semiconductor layer 156P may include polysilicon doped with a P-type dopant (e.g., a carrier impurity) or an N-type dopant (e.g., a carrier impurity). The P-type dopant may include B, In, or a combination thereof. The N-type dopant may include P, As, Sb, or a combination thereof. The first gate semiconductor layer 150P and the second gate semiconductor layer 156P may be doped with dopants of the same conductivity type. The doping concentration of the second gate semiconductor layer 156P may be the same as or different from the doping concentration of the first gate semiconductor layer 150P. In some embodiments, the doping concentration of the second gate semiconductor layer 156P may be lower than the doping concentration of the first gate semiconductor layer 150P. In some other embodiments, the doping concentration of the second gate semiconductor layer 156P may be higher than the doping concentration of the first gate semiconductor layer 150P. For example, the first gate semiconductor layer 150P may include a doped polysilicon layer having a doping concentration selected from about 1×10 21 cm -3 About 9×10 21 cm -3 The second gate semiconductor layer 156P may include a doped polysilicon layer, and the doping concentration thereof is selected from about 2×10 20 cm -3 About 9×10 21 cm -3 range.

[0055] In the peripheral circuit gate structure PGS, each of the first conductive layer 162P and the second conductive layer 164P may include TiSiN, TiN, TaN, CoN, a metal, a metal silicide, or a combination thereof. The metal and the metal silicide may include W, Mo, Au, Cu, Al, Ni, or Co. For example, the first conductive layer 162P may include TiSiN, and the second conductive layer 164P may include W. The insulating capping layer 166P may include a silicon nitride film.

[0056] The integrated circuit device 100 may include an insulating spacer 168 covering both sidewalls of the peripheral circuit gate structure PGS, and an interlayer dielectric 169 around the peripheral circuit gate structure PGS and covering the substrate 110. The peripheral circuit gate structure PGS, the insulating spacer 168, and the interlayer dielectric 169 may be covered with an insulating film 190. In some embodiments, the insulating spacer 168 may include an oxide film, a nitride film, or a combination thereof. The insulating spacer 168 may include a single layer or multiple layers. The interlayer dielectric 169 may include an HDP oxide film or a silicon oxide film formed by chemical vapor deposition (CVD) (e.g., flowable CVD (FCVD)). The insulating film 190 may include an oxide film.

[0057] In the cell array region CELL, the direct contact DC may include a contact semiconductor layer having a doping concentration lower than a doping concentration of at least one of the first gate semiconductor layer 150P and the second gate semiconductor layer 156P constituting the peripheral circuit gate structure PGS. In some embodiments, the contact semiconductor layer may include polysilicon doped with a P-type dopant or an N-type dopant. In some embodiments, the direct contact DC may be doped with a dopant having the same conductivity type as the dopant doped in the first gate semiconductor layer 150P and the second gate semiconductor layer 156P. For example, the direct contact DC may include a doped polysilicon layer having a doping concentration selected from about 1×10 20 cm -3 About 9×10 20 cm -3 In some embodiments, each of the direct contact DC, the first gate semiconductor layer 150P, and the second gate semiconductor layer 156P may include doped polysilicon, and the doping concentration of the direct contact DC may be lower than the doping concentration of the first gate semiconductor layer 150P and lower than the doping concentration of the second gate semiconductor layer 156P.

[0058] The integrated circuit device 100 may further include a direct contact spacer 152 covering a sidewall of the direct contact DC in the cell array region CELL. The direct contact spacer 152 may include undoped polysilicon.

[0059] The direct contact spacer 152 may cover only some of the sidewalls of the direct contact DC. Figure 4 As shown in the cross-sectional area taken along line BB' in , the direct contact spacer 152 may cover two side walls of the direct contact DC that are opposite to each other in a direction parallel to the extension direction of the bit line structure BLS, and may not cover two side walls of the direct contact DC that are opposite to each other in a direction orthogonal to the extension direction of the bit line structure BLS.

[0060] In the cell array region CELL, the buffer insulating film 130 may have a hole 130H penetrated by the direct contact DC and the direct contact spacer 152. Each of the direct contact DC and the direct contact spacer 152 may include a portion extending through the buffer insulating film 130 into the substrate 110 and thus buried in the substrate 110. Therefore, not all of the direct contact DC but only a portion of the direct contact DC extending through the buffer insulating film 130 into the substrate 110 is buried in the substrate 110, and not all of the direct contact spacer 152 but a portion of the direct contact spacer 152 extending through the buffer insulating film 130 into the substrate 110 is buried in the substrate 110.

[0061] The plurality of bit line structures BLS may be separated from the substrate 110 using a buffer insulating film 130 between the plurality of bit line structures BLS and the substrate 110. Each of the plurality of bit line structures BLS may include a bit line semiconductor layer 156C, a first conductive layer 162C, a second conductive layer 164C, and an insulating capping layer 166C, which are stacked on the buffer insulating film 130 in the stated order. For example, a top surface of the buffer insulating film 130 and a bottom surface of the bit line semiconductor layer 156C are in contact with each other, a top surface of the bit line semiconductor layer 156C and a bottom surface of the first conductive layer 162C are in contact with each other, a top surface of the first conductive layer 162C and a bottom surface of the second conductive layer 164C are in contact with each other, and a top surface of the second conductive layer 164C and a bottom surface of the insulating capping layer 166C are in contact with each other. The bit line semiconductor layer 156C, the first conductive layer 162C, and the second conductive layer 164C may constitute Figure 3 A plurality of bit line structures BLS may be connected to a direct contact DC.

[0062] The bit line semiconductor layer 156C may contact the top surface of the direct contact DC. The doping concentration of the bit line semiconductor layer 156C may be higher than the doping concentration of the contact semiconductor layer constituting the direct contact DC. In some embodiments, the bit line semiconductor layer 156C may include polysilicon doped with a P-type dopant or an N-type dopant. The bit line semiconductor layer 156C may be doped with a dopant of the same conductivity type as that of the dopant included in the direct contact DC. The bit line semiconductor layer 156C may be doped with a dopant of the same conductivity type as that of the dopant doped in the first gate semiconductor layer 150P and the second gate semiconductor layer 156P formed in the peripheral circuit region CORE / PERI. For example, the bit line semiconductor layer 156C may include a doped polysilicon layer having a doping concentration selected from about 2×10 20 cm -3 About 9×10 21 cm -3 In some embodiments, the bit line semiconductor layer 156C may include the same material as the second gate semiconductor layer 156P constituting the peripheral circuit gate structure PGS. For example, the bit line semiconductor layer 156C and the second gate semiconductor layer 156P may include doped polysilicon layers with the same doping concentration, and the doping concentration is selected from about 2×10 20 cm -3 About 9×10 21 cm -3 range.

[0063] In the bit line structure BLS, each of the first conductive layer 162C and the second conductive layer 164C may include TiSiN, TiN, TaN, CoN, a metal, a metal silicide, or a combination thereof. The metal and the metal silicide may include W, Mo, Au, Cu, Al, Ni, or Co. For example, the first conductive layer 162C may include TiSiN, and the second conductive layer 164C may include W. The insulating capping layer 166C may include a silicon nitride film.

[0064] exist Figure 4 , although each of the plurality of bit line structures BLS is shown as including three conductive layers, namely: a bit line semiconductor layer 156C, a first conductive layer 162C, and a second conductive layer 164C, the inventive concept is not limited thereto. For example, the bit line structure BLS may include a single conductive layer, a double conductive layer, or a stacked structure of four or more conductive layers.

[0065] Each of the plurality of bit line structures BLS may be covered with an insulating pattern 170. The insulating pattern 170 may include a silicon nitride film. Both sidewalls of each of the bit line structures BLS and the insulating pattern 170 may be covered with an insulating spacer 172. The insulating spacer 172 may include an oxide film, a nitride film, an air spacer, or a combination thereof. The air spacer may include air or other gases that may be present during the manufacturing process of the integrated circuit device 100.

[0066] In the cell array region CELL, a plurality of buried contact structures BCS may be arranged between a plurality of bit line structures BLS. Each of the plurality of buried contact structures BCS may include a filling conductive layer 182, a metal silicide film 184, a conductive barrier film 186, and a conductive layer 188, which are stacked in the stated order on the cell active region A1 while filling each of the plurality of recesses RC. For example, a top surface of the filling conductive layer 182 and a bottom surface of the metal silicide film 184 may contact each other, a top surface of the metal silicide film 184 and a bottom surface of the conductive barrier film 186 may contact each other, and a top surface of the conductive barrier film 186 and a bottom surface of the conductive layer 188 may contact each other. The lower portions of the filling conductive layer 182, the metal silicide film 184, the conductive barrier film 186, and the conductive layer 188 may constitute Figure 3 In addition, the upper portion of the conductive layer 188 (eg, the portion of the conductive layer 188 extending above the top surface of the bit line structure BLS) may constitute a reference Figure 3 The conductive layer 182 may include a semiconductor material doped with impurities, a metal, a conductive metal nitride, a metal silicide, or a combination thereof. The metal silicide film 184 may include cobalt silicide, nickel silicide, or manganese silicide. In some embodiments, the metal silicide film 184 may be omitted. The conductive barrier film 186 may include a Ti / TiN stacked structure. The conductive layer 188 may include doped polysilicon, a metal, a metal silicide, a conductive metal nitride, or a combination thereof. For example, the conductive layer 188 may include tungsten (W). A plurality of buried contact structures BCS may be electrically insulated from each other by an insulating film 190.

[0067] In the cell array region CELL, each of the plurality of direct contacts DC may have a sidewall portion covered with the insulating spacer 172. Figure 4 As shown in the cross-sectional area taken along the line AA' in FIG. 1 , the insulating spacer 172 may cover the sidewall portion of the direct contact DC facing the filled conductive layer 182 of the buried contact structure BCS. Each of the plurality of direct contacts DC may include a sidewall portion contacting the direct contact spacer 152, such as along Figure 4 The cross-sectional area taken along the line BB' in FIG. 1 and may include a sidewall portion of the contact insulating spacer 172, such as along Figure 4The cross-sectional area taken along the line AA' is shown.

[0068] In the cell array region CELL, a plurality of capacitor bottom electrodes that may be electrically connected to the plurality of conductive layers 188 may be formed on the insulating film 190 .

[0069] Figure 5 2 is a cross-sectional view showing a main part of an integrated circuit device 200 according to another embodiment of the inventive concept. Figure 5 In, with Figure 4 The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0070] Reference Figure 5 , the integrated circuit device 200 and Figure 4 The integrated circuit device 100 shown has substantially the same configuration. However, the integrated circuit device 200 further includes a semiconductor oxide film 150B between the buffer insulating film 130 and the bit line structure BLS in the cell array region CELL.

[0071] In the cell array region CELL, each of the direct contact DC, the direct contact spacer 152, and the insulating spacer 172 may include a portion extending into the substrate 110 through the semiconductor oxide film 150B and the buffer insulating film 130 and thus buried in the substrate 110. Therefore, not all of each of the direct contact DC, the direct contact spacer 152, and the insulating spacer 172 in the cell array region CELL but only a portion of each of the direct contact DC, the direct contact spacer 152, and the insulating spacer 172 extending into the substrate 110 through the semiconductor oxide film 150B and the buffer insulating film 130 is buried in the substrate 110.

[0072] The semiconductor oxide film 150B may include a doped silicon oxide film. In some embodiments, the semiconductor oxide film 150B may include a silicon oxide film including a dopant corresponding to a P-type dopant (including B, In, or a combination thereof). In some other embodiments, the semiconductor oxide film 150B may include a silicon oxide film including a dopant corresponding to an N-type dopant (including P, As, Sb, or a combination thereof).

[0073] As along Figure 5As shown in the cross-sectional area taken along the line BB' in FIG. 1 , the entrance portion of each of the plurality of direct contact holes DCH may be defined by the buffer insulating film 130 and the semiconductor oxide film 150B, and each of the plurality of direct contact spacers 152 may cover the sidewalls of the buffer insulating film 130 and the semiconductor oxide film 150B. In the cell array region CELL, a plurality of bit line structures BLS may be formed on the semiconductor oxide film 150B. Therefore, a structure in which the semiconductor oxide film 150B is between the buffer insulating film 130 and the plurality of bit line structures BLS may be obtained. The bit line semiconductor layer 156C of each of the plurality of bit line structures BLS may contact the semiconductor oxide film 150B.

[0074] Figure 6 2 is a cross-sectional view showing a main part of an integrated circuit device 300 according to other embodiments of the present inventive concept. Figure 6 In, with Figure 4 The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0075] Reference Figure 6 , the integrated circuit device 300 and Figure 4 The integrated circuit device 100 shown has a substantially identical configuration. However, in the peripheral circuit region CORE / PERI of the integrated circuit device 300, the peripheral circuit gate structure PGS constituting the peripheral circuit transistor PTR may include a dielectric layer 142, a metal-containing work function adjustment layer 144, a first gate semiconductor layer 154P, a second gate semiconductor layer 156P, a first conductive layer 162P, a second conductive layer 164P, and an insulating capping layer 166P, which are stacked on the substrate 110 in the stated order.

[0076] In the peripheral circuit gate structure PGS, the first gate semiconductor layer 154P and the second gate semiconductor layer 156P may be used to control the work function of the peripheral circuit transistor PTR. The doping concentration of the first gate semiconductor layer 154P may be equal to the doping concentration of the contact semiconductor layer constituting the plurality of direct contacts DC in the cell array region CELL. In some embodiments, the plurality of direct contacts DC and the first gate semiconductor layer 154P may each include a doped polysilicon layer, the doping concentration of which is selected from about 1×10 20 cm -3 About 9×10 20 cm -3 range.

[0077] Figure 7 4 is a cross-sectional view showing a main part of an integrated circuit device 400 according to other embodiments of the present inventive concept. Figure 7 In, with Figure 4The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0078] Reference Figure 7 , the integrated circuit device 400 and Figure 4 The integrated circuit device 100 shown has a substantially similar configuration. However, in the integrated circuit device 400, the substrate 110 further includes an interface region INTERFACE between the cell array region CELL and the peripheral circuit region CORE / PERI. The buffer insulating film 130 extends from the cell array region CELL to the interface region INTERFACE on the substrate 110. The end 130T of the buffer insulating film 130 in the interface region INTERFACE may cover the top surface of the device isolation film 112 to define an undercut region UA ​​above the top surface of the device isolation film 112. The undercut region UA ​​may be filled with a filling insulating pattern 132. In the interface region INTERFACE, the end 130T of the buffer insulating film 130 and the filling insulating pattern 132 may be covered by an interlayer dielectric 169.

[0079] According to reference Figures 4 to 7 In the integrated circuit device 100, 200, 300 or 400, when doped polysilicon is deposited to form a direct contact DC in the cell array region CELL, in order to prevent a gap from being formed in the direct contact hole DCH, the aspect ratio of the structure including the direct contact hole DCH exposed during the deposition of polysilicon is reduced compared to a conventional process for forming the direct contact DC, and the doping concentration of the polysilicon is reduced compared to a conventional process to control the step coverage characteristic. Therefore, according to the reference Figures 4 to 7 The integrated circuit device 100, 200, 300 or 400 can provide a direct contact DC having a seamless and stable structure in the cell array region CELL, and can provide a bit line structure BLS that can include a bit line semiconductor layer 156C having a reduced thickness and thus suppressing parasitic capacitance. Figures 4 to 7In the integrated circuit device 100, 200, 300 or 400, in the process of performing the process of forming the peripheral circuit transistor PTR in the peripheral circuit region CORE / PERI and simultaneously performing the process of forming the direct contact DC and the bit line structure BLS in the cell array region CELL, since a seamless process is applied to form the direct contact DC, the peripheral circuit transistor PTR in the peripheral circuit region CORE / PERI may have a stacked structure including two polysilicon layers having different doping concentrations from each other. For example, the peripheral circuit gate structure PGS arranged in the peripheral circuit region CORE / PERI includes two gate semiconductor layers, for example, a first gate semiconductor layer 150P and a second gate semiconductor layer 156P, or a first gate semiconductor layer 154P and a second gate semiconductor layer 156P, which can be controlled to a desired doping concentration, and the doping concentration of each of them can be independently controlled, thereby effectively controlling the work function of the peripheral circuit transistor PTR. Therefore, the reliability of the integrated circuit device 100, 200, 300 or 400 can be improved. The detailed process of forming the seamless direct contact DC will be described below.

[0080] FIG. 8A to FIG. 8P 1 is a cross-sectional view showing sequential processes of a method for manufacturing an integrated circuit device according to an embodiment of the inventive concept. FIG. 8A to FIG. 8P Description Manufacturing Figure 4 An example of a method of an integrated circuit device 100 is shown. FIG. 8A to FIG. 8P In, with Figure 4 The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0081] Reference Fig. 8A , a plurality of device isolation trenches 112T and a plurality of device isolation films 112 respectively filling the plurality of device isolation trenches 112T are formed in the substrate 110, thereby defining a plurality of cell active areas A1 in the cell array region CELL and defining a peripheral circuit active area A2 in the peripheral circuit region CORE / PERI.

[0082] In the cell array region CELL, a plurality of word line trenches 120T extending parallel to each other are formed in the substrate 110 , and then a gate dielectric film 122 , a word line 124 , and a buried insulating film 126 are sequentially formed inside each of the plurality of word line trenches 120T.

[0083] Impurity ions (e.g., carrier impurities) are implanted into portions of the plurality of unit active regions A1 on both sides of the plurality of word lines 124, thereby forming a plurality of source / drain regions 116 in upper portions of the plurality of unit active regions A1. In some embodiments, the plurality of source / drain regions 116 may be formed before forming the plurality of word lines 124.

[0084] Reference Figure 8B , a buffer insulating film 130 is formed on the substrate 110 in the cell array region CELL, and a dielectric layer 142 and a metal-containing work function adjustment layer 144 are formed on the substrate 110 in the peripheral circuit region CORE / PERI in the stated order. In some embodiments, the process of forming the metal-containing work function adjustment layer 144 may be omitted. Each of the buffer insulating film 130, the dielectric layer 142, and the metal-containing work function adjustment layer 144 may be formed by a CVD or atomic layer deposition (ALD) process, and their formation order is not particularly limited.

[0085] Reference Figure 8C , a first doped semiconductor layer 150 and a protective layer PL are formed in the cell array region CELL and the peripheral circuit region CORE / PERI in the stated order over the substrate 110, and then a first mask pattern M11 covering the protective layer PL in the peripheral circuit region CORE / PERI is formed. In the cell array region CELL, the protective layer PL may be exposed.

[0086] The first doped semiconductor layer 150 may include polysilicon doped with a P-type dopant or an N-type dopant. The P-type dopant may include B, In, or a combination thereof. The N-type dopant may include P, As, Sb, or a combination thereof. For example, the first doped semiconductor layer 150 may include about 1×10 21 cm -3 About 9×10 21 cm -3 The first doping concentration is doped with .

[0087] The protection layer PL may protect a portion of the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI. The protection layer PL may include an oxide film, a nitride film, or a combination thereof, and is not limited thereto. The first mask pattern M11 may include a photoresist pattern.

[0088] Reference Fig.8D , the protection layer PL and the first doped semiconductor layer 150 are removed from the cell array region CELL by anisotropic etching using the first mask pattern M11 as an etching mask, thereby exposing the buffer insulating film 130 in the cell array region CELL.

[0089] Next, the first mask pattern M11 remaining on the protection layer PL is removed from the peripheral circuit region CORE / PERI. In order to remove the first mask pattern M11, ashing and stripping processes may be used, but the present disclosure is not limited thereto.

[0090] Reference Fig. 8E, a plurality of direct contact holes DCH are formed to expose the cell active area A1 in the cell array region CELL.

[0091] In some embodiments, in order to form a plurality of direct contact holes DCH, a second mask pattern M12 may be formed over the substrate 110 in the cell array region CELL and the peripheral circuit region CORE / PERI, and then a plurality of holes 130H penetrating the buffer insulating film 130 are formed by partially etching the buffer insulating film 130 in the cell array region CELL using the second mask pattern M12 as an etching mask, and then a portion of the substrate 110 and a portion of the device isolation film 112 may be etched through the plurality of holes 130H. In some embodiments, the second mask pattern M12 may include an amorphous carbon layer (ACL).

[0092] Reference Figure 8F , by Fig. 8E The second mask pattern M12 is removed from the resultant product to expose the buffer insulating film 130 in the cell array region CELL and the top surface of the protection layer PL in the peripheral circuit region CORE / PERI, and then a plurality of direct contact spacers 152 are formed to cover inner sidewalls of a plurality of holes 130H in the cell array region CELL and inner sidewalls of a plurality of direct contact holes DCH, the plurality of holes 130H being formed in the buffer insulating film 130. In order to remove the second mask pattern M12, an ashing and stripping process may be used, but the present disclosure is not limited thereto.

[0093] Each direct contact spacer 152 may include undoped polysilicon. In order to form the direct contact spacer 152, an undoped polysilicon liner may be formed to cover the inner sidewalls of the plurality of holes 130H and the inner sidewalls of the plurality of direct contact holes DCH formed in the buffer insulating film 130, and then the undoped polysilicon liner is etched back to leave only some portions of the undoped polysilicon liner covering the inner sidewalls of the plurality of holes 130H and the inner sidewalls of the plurality of direct contact holes DCH. After forming the plurality of direct contact spacers 152, the cell active area A1 may be exposed through the plurality of direct contact holes DCH in the cell array region CELL. In some embodiments, the direct contact spacers 152 may be omitted. Figure 8F A process for forming direct contact spacers 152 is described.

[0094] During the formation of the plurality of direct contact spacers 152 , the protection layer PL may prevent damage to the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI.

[0095] Reference Figure 8G, while the protection layer PL covers the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI, a second doped semiconductor layer 154 is formed over the substrate 110 in the cell array region CELL and the peripheral circuit region CORE / PERI. The second doped semiconductor layer 154 may have a thickness sufficient to fill the plurality of direct contact holes DCH in the cell array region CELL.

[0096] The second doped semiconductor layer 154 may include polysilicon doped with a P-type dopant or an N-type dopant. In some embodiments, the second doped semiconductor layer 154 may be doped with a dopant of the same conductivity type as the first doped semiconductor layer 150. In some other embodiments, the second doped semiconductor layer 154 may be doped with a dopant of a different conductivity type than the first doped semiconductor layer 150.

[0097] The second doped semiconductor layer 154 may include a semiconductor doped with a doping concentration lower than that of the first doped semiconductor layer 150. For example, the second doped semiconductor layer 154 may be doped with a concentration selected from about 1×10 20 cm -3 About 9×10 20 cm -3 The device is doped with a second doping concentration in a range of .

[0098] As a comparative example, when the doping concentration of the second doped semiconductor layer 154 is equal to or higher than the doping concentration of the first doped semiconductor layer 150 formed in the peripheral circuit region CORE / PERI, although a plurality of direct contacts DC (see Figure 8H ) may be reduced due to the relatively high doping concentration of the second doped semiconductor layer 154, but in the deposition process for forming the second doped semiconductor layer 154, the tendency of the second doped semiconductor layer 154 to be conformally deposited on the substrate 110 may increase due to the relatively high doping concentration of the second doped semiconductor layer 154. As a result, in the deposition product obtained after forming the second doped semiconductor layer 154 to fill the narrow space such as the plurality of direct contact holes DCH, gaps may remain in the plurality of direct contact holes DCH. When the gaps remain in the plurality of direct contact holes DCH, the plurality of direct contacts DC are formed (see Figure 8H ), the electrical characteristics of multiple direct contacts DC may deteriorate.

[0099] However, according to the present invention, a second doped semiconductor layer 154 having a relatively low doping concentration is formed in a plurality of direct contact holes DCH, so that the second doped semiconductor layer 154 can fill the direct contact holes DCH without gaps of the second doped semiconductor layer 154 remaining in the direct contact holes DCH which are relatively narrow spaces.

[0100] Reference Figure 8H In the cell array region CELL and the peripheral circuit region CORE / PERI, the second doped semiconductor layer 154 is etched back (see Figure 8G ), so that the top surface of the buffer insulating film 130 is exposed, thereby forming a plurality of direct contacts DC.

[0101] The protection layer PL may prevent the first doped semiconductor layer 150 from being damaged during etching back the second doped semiconductor layer 154 .

[0102] Reference Fig.8I ,from Figure 8H The resulting product removes the protective layer PL, thereby exposing the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI. To remove the protective layer PL, a wet etching process may be used.

[0103] Reference Figure 8J , a third doped semiconductor layer 156 is formed over the substrate 110 in the cell array region CELL and the peripheral circuit region CORE / PERI.

[0104] The third doped semiconductor layer 156 may include polysilicon doped with a P-type dopant or an N-type dopant. The P-type dopant may include B, In, or a combination thereof. The N-type dopant may include P, As, Sb, or a combination thereof. In some embodiments, the third doped semiconductor layer 156 may include a semiconductor doped with a doping concentration higher than the doping concentration of the second doped semiconductor layer 154 constituting the plurality of direct contacts DC. In some embodiments, the third doped semiconductor layer 156 may include a doping concentration selected from, for example, about 2×10 20 cm -3 About 9×10 21 cm -3 The third doping concentration may be the same as or different from the first doping concentration of the first doped semiconductor layer 150. In some embodiments, the third doping concentration may be lower than the first doping concentration. In some other embodiments, the third doping concentration may be higher than the first doping concentration.

[0105] In the peripheral circuit region CORE / PERI, the thickness D12 of the third doped semiconductor layer 156 in the direction perpendicular to the top surface of the substrate 110 may be less than the thickness D11 of the first doped semiconductor layer 150 in the direction perpendicular to the top surface of the substrate 110, but is not limited thereto. Among the first doped semiconductor layer 150 and the third doped semiconductor layer 156, the thickness D12 of the third doped semiconductor layer 156 remaining in the peripheral circuit region CORE / PERI and the cell array region CELL is less than the thickness D11 of the first doped semiconductor layer 150 remaining only in the peripheral circuit region CORE / PERI, so that when a plurality of bit line structures BLS (see FIG. 1 ) each including the third doped semiconductor layer 156 are formed in the cell array region CELL in a subsequent process, Figure 4 ), the thickness of the conductive layer of the plurality of bit line structures BLS can be reduced. As a result, it is possible to suppress undesirable parasitic capacitance that may be generated between the plurality of bit line structures BLS.

[0106] In the cell array region CELL, the third doped semiconductor layer 156 may contact the buffer insulating film 130 and the plurality of direct contacts DC. In the peripheral circuit region CORE / PERI, the third doped semiconductor layer 156 may contact the first doped semiconductor layer 150 .

[0107] Reference Figure 8K , in the cell array region CELL and the peripheral circuit region CORE / PERI, a first conductive layer 162 , a second conductive layer 164 , and an insulating capping layer 166 are formed on the third doped semiconductor layer 156 in the stated order.

[0108] In some embodiments, each of the first conductive layer 162 and the second conductive layer 164 may include TiSiN, TiN, TaN, CoN, a metal, a metal silicide, or a combination thereof. Each of the metal and the metal silicide may include W, Mo, Au, Cu, Al, Ni, or Co. For example, the first conductive layer 162 may include TiSiN, and the second conductive layer 164 may include W. The insulating capping layer 166 may include a silicon nitride film.

[0109] Reference Figure 8L, while the cell array region CELL is protected by a mask pattern (not shown), a peripheral circuit gate structure PGS is formed in the peripheral circuit region CORE / PERI by etching a peripheral circuit stack structure in the peripheral circuit region CORE / PERI, the peripheral circuit stack structure including a dielectric layer 142, a metal-containing work function adjustment layer 144, a first doped semiconductor layer 150, a third doped semiconductor layer 156, a first conductive layer 162, a second conductive layer 164, and an insulating capping layer 166. The portion of the first doped semiconductor layer 150 remaining in the peripheral circuit gate structure PGS may be referred to as a first gate semiconductor layer 150P, and the portion of the third doped semiconductor layer 156 remaining in the peripheral circuit gate structure PGS may be referred to as a second gate semiconductor layer 156P. The portions of the first conductive layer 162, the second conductive layer 164, and the insulating capping layer 166 remaining in the peripheral circuit gate structure PGS may be referred to as a first conductive layer 162P, a second conductive layer 164P, and an insulating capping layer 166P, respectively.

[0110] An insulating spacer 168 may be formed to cover both sidewalls of the peripheral circuit gate structure PGS, and then an interlayer dielectric 169 may be formed.

[0111] Reference Figure 8M , an insulating pattern 170 is formed over the substrate 110. In the peripheral circuit region CORE / PERI, the peripheral circuit gate structure PGS may be protected by the insulating pattern 170. In the cell array region CELL, a top surface of the insulating capping layer 166 may be partially exposed by the insulating pattern 170. The insulating pattern 170 may include a silicon nitride film.

[0112] Reference Figure 8N , a cell stack structure including a direct contact spacer 152, a direct contact DC, a third doped semiconductor layer 156, a first conductive layer 162, a second conductive layer 164, and an insulating capping layer 166 in a cell array region CELL is etched using an insulating pattern 170 as an etching mask, thereby forming a plurality of bit line structures BLS extending parallel to each other in the cell array region CELL. The portion of the third doped semiconductor layer 156 remaining in each of the plurality of bit line structures BLS may be referred to as a bit line semiconductor layer 156C. The portions of the first conductive layer 162, the second conductive layer 164, and the insulating capping layer 166 remaining in each of the plurality of bit line structures BLS may be referred to as a first conductive layer 162C, a second conductive layer 164C, and an insulating capping layer 166C, respectively.

[0113] While the cell stack structure is being etched in order to form the plurality of bit line structures BLS, the insulating pattern 170 may be partially removed, and thus the height of the insulating pattern 170 is reduced.

[0114] Reference Fig.8O In the cell array region CELL, a plurality of insulating spacers 172 are formed to cover both sidewalls of each of the plurality of bit line structures BLS, and a portion of the substrate 110 and a portion of the device isolation film 112 exposed by the plurality of insulating spacers 172 are etched, thereby forming a plurality of grooves RC exposing the plurality of cell active regions A1. Each of the plurality of grooves RC is connected to a buried contact hole BCH between two adjacent bit line structures BLS, and the width of the buried contact hole BCH is defined by a pair of insulating spacers 172.

[0115] In some embodiments, a spacer insulating film may be formed to cover a plurality of bit line structures BLS, a plurality of insulating spacers 172 may be formed by performing etching back on the spacer insulating film, and a plurality of recesses RC may be formed by etching a portion of the substrate 110 and a portion of the device isolation film 112 using the insulating pattern 170 and the plurality of insulating spacers 172 as etching masks.

[0116] Reference Figure 8P , forming a filling conductive layer 182 to fill the plurality of grooves RC between the plurality of bit line structures BLS and partially filling the plurality of buried contact holes BCH between the plurality of bit line structures BLS, and forming a buried contact structure BCS, the buried contact structure BCS including a metal silicide film 184, a conductive barrier film 186 and a conductive layer 188, which are stacked on the buried contact structure BCS in the stated order. The plurality of buried contact structures BCS may be electrically insulated from each other by forming an insulating film 190 around the conductive barrier film 186 and the conductive layer 188.

[0117] During the formation of the plurality of conductive barrier films 186 and the plurality of conductive layers 188 in the cell array region CELL, a contact plug (not shown) electrically connectable to the peripheral circuit active area A2 may be formed in the peripheral circuit region CORE / PERI.

[0118] In the cell array region CELL, a plurality of capacitor bottom electrodes electrically connected to the plurality of conductive layers 188 may be formed on the insulating film 190. As used herein, unless otherwise specified, items described as "electrically connected" are configured such that an electrical signal can be transferred from one item to another. 9A to 9E 1 is a cross-sectional view showing sequential processes of a method of manufacturing an integrated circuit device according to other embodiments of the inventive concept. 9A to 9E Description of manufacturing Figure 4 Another example of a method of an integrated circuit device 100 is shown. 9A to 9E In, with FIG. 8A to FIG. 8P The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0119] Reference Fig.9A , according to the reference FIG. 8A to FIG. 8C In the same manner as described above, in the cell array region CELL and the peripheral circuit region CORE / PERI, a first doped semiconductor layer 150 and a protective layer PL are formed over the substrate 110, and a first mask pattern M11 is formed to cover the protective layer PL in the peripheral circuit region CORE / PERI. Fig.8D In a manner similar to that described above, the protection layer PL is removed from the cell array region CELL by using the first mask pattern M11 as an etching mask, thereby exposing the first doped semiconductor layer 150. During the removal of the protection layer PL, the first doped semiconductor layer 150 in the cell array region CELL may be partially etched due to over-etching. As a result, the thickness D22 of the first doped semiconductor layer 150 in the cell array region CELL may be less than the thickness D21 of the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI.

[0120] Reference Fig. 9B , the first mask pattern M11 remaining on the protective layer PL is removed from the peripheral circuit region CORE / PERI (see Fig.9A ), then follow the reference Fig. 8E A plurality of direct contact holes DCH are formed in the cell array region CELL in a manner similar to the described manner, and the plurality of direct contact holes DCH expose the cell active region A1.

[0121] In order to form a plurality of direct contact holes DCH, a second mask pattern M12 may be formed to cover the first doped semiconductor layer 150 in the cell array region CELL and the protective layer PL in the peripheral circuit region CORE / PERI, and each of the first doped semiconductor layer 150, the buffer insulating film 130, the substrate 110, and the device isolation film 112 in the cell array region CELL may be partially etched by using the second mask pattern M12 as an etching mask.

[0122] Reference Fig. 9C , according to the reference Figure 8F The second mask pattern M12 is removed in a manner similar to the description, and then a plurality of direct contact spacers 152 are formed in the cell array region CELL. The plurality of direct contact spacers 152 may cover inner sidewalls of the plurality of direct contact holes DCH, inner sidewalls of the plurality of holes 130H formed in the buffer insulating film 130, and sidewalls of the first doped semiconductor layer 150 remaining in the cell array region CELL.

[0123] Reference Fig.9D , according to the reference Figure 8GIn a similar manner to that described, while the protection layer PL covers the first doped semiconductor layer 150 in the peripheral circuit region CORE / PERI, the second doped semiconductor layer 154 is formed in the cell array region CELL and the peripheral circuit region CORE / PERI.

[0124] Reference Fig.9E , according to the reference Figure 8H In a similar manner as described above, the second doped semiconductor layer 154 in the cell array region CELL and the peripheral circuit region CORE / PERI is etched back to form a plurality of direct contacts DC. Then, the first doped semiconductor layer 150 remaining in the cell array region CELL is also removed to expose the top surface of the buffer insulating film 130.

[0125] Next, you can execute the reference FIG. 8I to FIG. 8P The integrated circuit device 100 is thereby manufactured by the process described.

[0126] Although the reference FIG. 8A to FIG. 8P and 9A to 9E Describes the manufacturing Figure 4 The method of the integrated circuit device 100 is shown as an example, but may be used in conjunction with reference to FIG. 8A to FIG. 8P Description methods and references 9A to 9E Various changes may be made in the described methods without departing from the spirit and scope of the present inventive concept.

[0127] In some embodiments, in reference to Figure 8C In the process described above, the process of forming the protective layer PL may be omitted. In this exemplary embodiment, in the peripheral circuit region CORE / PERI, a first doped semiconductor layer 150 may be formed. Figure 8C and Fig.9A , so that a bottom surface of the first mask pattern M11 contacts a top surface of the first doped semiconductor layer 150, and Fig. 8E and Fig. 9B The second mask pattern M12 shown in FIG. 1 may be formed directly on the first doped semiconductor layer 150 so that the bottom surface of the second mask pattern M12 contacts the top surface of the first doped semiconductor layer 150. In addition, the reference pattern M12 may be performed without the protective layer PL. FIG. 8F to FIG. 8H Processing and reference of description FIG. 9C to FIG. 9E Description of the process.

[0128] FIG. 10A to FIG. 10C are cross-sectional views showing sequential processes of a method for manufacturing an integrated circuit device according to other embodiments of the inventive concept. FIG. 10A to FIG. 10C Description Manufacturing Figure 5 An example of a method of an integrated circuit device 200 is shown. FIG. 10A to FIG. 10C In, with FIG. 8A to FIG. 8P The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0129] Reference Fig. 10A , according to the reference FIG. 8A to FIG. 8C In the same manner as described above, a first doped semiconductor layer 150 and a protective layer PL extending over the substrate 110 in the cell array region CELL and the peripheral circuit region CORE / PERI and a first mask pattern M11 covering the protective layer PL in the peripheral circuit region CORE / PERI are formed, and then the first doped semiconductor layer 150 and the protective layer PL are formed in the cell array region CELL and the peripheral circuit region CORE / PERI. Fig.8D The protective layer PL and the first doped semiconductor layer 150 in the cell array region CELL are anisotropically etched by using the first mask pattern M11 as an etching mask in a similar manner as described above. However, in this example, only a certain thickness of the first doped semiconductor layer 150 is removed instead of being completely removed from the cell array region CELL, thereby leaving a first doped semiconductor residual film 150A on the buffer insulating film 130, which is a remaining portion of the first doped semiconductor layer 150. Although

[0130] Fig. 10A An example is shown in which the first doped semiconductor residual film 150A completely covers the top surface of the buffer insulating film 130, but the present inventive concept is not limited to Fig. 10A For example, the first doped semiconductor residual film 150A may expose a portion of the top surface of the buffer insulating film 130 instead of completely covering the top surface of the buffer insulating film 130. The first doped semiconductor residual film 150A may include doped polysilicon.

[0131] Reference Fig. 10B In the peripheral circuit region CORE / PERI, while the protection layer PL is covered with the first mask pattern M11, the first doped semiconductor residual film 150A in the cell array region CELL is oxidized (see Fig. 10A ), thereby forming a semiconductor oxide film 150B.

[0132] In some embodiments, to form the semiconductor oxide film 150B, a plasma oxidation process or a thermal oxidation process may be used.

[0133] Reference Fig. 10C ,from Fig. 10B The first mask pattern M11 remaining on the protective layer PL is removed from the resulting product, and then reference is performed Figures 8E to 8P The integrated circuit device 200 is thereby manufactured by the process described.

[0134] FIG. 11A to FIG. 11Eare cross-sectional views showing sequential processes of a method for manufacturing an integrated circuit device according to other embodiments of the inventive concept. FIG. 11A to FIG. 11E Description Manufacturing Figure 6 An example of a method of an integrated circuit device 300 is shown. FIG. 11A to FIG. 11E In, with FIG. 8A to FIG. 8P The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0135] Reference Fig.11A , according to the reference Fig. 8A and Figure 8B In the same manner as described above, a buffer insulating film 130 is formed on the substrate 110 in the cell array region CELL, and a dielectric layer 142 and a metal-containing work function adjustment layer 144 are formed on the substrate 110 in the peripheral circuit region CORE / PERI in the stated order, and then the second mask pattern M12 is used in the same manner as described above. Fig. 8E A plurality of direct contact holes DCH are formed in a manner similar to the described manner, and the plurality of direct contact holes DCH expose the cell active area A1.

[0136] In the peripheral circuit region CORE / PERI, the second mask pattern M12 may be formed directly on the metal-containing work function adjustment layer 144 so that the bottom surface of the second mask pattern M12 contacts the top surface of the metal-containing work function adjustment layer 144. In some embodiments, the metal-containing work function adjustment layer 144 may be omitted. In this case, in the peripheral circuit region CORE / PERI, the second mask pattern M12 may be formed directly on the dielectric layer 142 so that the bottom surface of the second mask pattern M12 contacts the top surface of the dielectric layer 142.

[0137] Reference Fig. 11B , by Fig.11A The second mask pattern M12 is removed from the obtained product to expose the buffer insulating film 130 in the cell array region CELL and the metal-containing work function adjustment layer 144 in the peripheral circuit region CORE / PERI, and then Figure 8F A plurality of direct contact spacers 152 are formed in the cell array region CELL in a manner similar to that described above. In some embodiments, the reference numerals 154 may be omitted. Fig. 11B The process of forming the direct contact spacers 152 has been described.

[0138] Reference Fig. 11C , according to the reference Figure 8G In a similar manner to that described in Fig. 11B A second doped semiconductor layer 154 is formed on the resulting product.

[0139] In the peripheral circuit region CORE / PERI, the second doped semiconductor layer 154 may be directly formed on the metal-containing work function adjustment layer 144 so that the bottom surface of the second doped semiconductor layer 154 contacts the top surface of the metal-containing work function adjustment layer 144. In the case where the metal-containing work function adjustment layer 144 is omitted, the second doped semiconductor layer 154 may be directly formed on the dielectric layer 142 in the peripheral circuit region CORE / PERI so that the bottom surface of the second doped semiconductor layer 154 contacts the top surface of the dielectric layer 142.

[0140] Reference Fig.11D , according to the reference Figure 8H In a manner similar to that described above, the second doped semiconductor layer 154 in the cell array region CELL and the peripheral circuit region CORE / PERI is etched back. However, in this example, a direct contact DC is formed from the second doped semiconductor layer 154 in the cell array region CELL, and a residual portion of the second doped semiconductor layer 154 remains on the metal-containing work function adjustment layer 144 in the peripheral circuit region CORE / PERI. In the case where the metal-containing work function adjustment layer 144 is omitted, the residual portion of the second doped semiconductor layer 154 may remain directly on the dielectric layer 142 in the peripheral circuit region CORE / PERI, so that the residual portion of the second doped semiconductor layer 154 contacts the top surface of the dielectric layer 142. In some embodiments, the residual portion of the second doped semiconductor layer 154 may have a thickness of about 100 Å. to about The thickness is not limited thereto.

[0141] Reference Fig.11E , can be Fig.11D The obtained product is executed with reference to Figure 8J to Figure 8P The integrated circuit device 300 is manufactured by the process described above. Fig.11D In the resulting product, the first gate semiconductor layer 154P of the peripheral gate structure PGS may be obtained from the remaining portion of the second doped semiconductor layer 154 remaining on the metal-containing work function adjusting layer 144 .

[0142] FIG. 12A to FIG. 12F are cross-sectional views showing sequential processes of a method for manufacturing an integrated circuit device according to other embodiments of the inventive concept. FIG. 12A to FIG. 12F Description Manufacturing Figure 7 An example of a method of an integrated circuit device 400 is shown. FIG. 12A to FIG. 12F , a cell array region CELL, a peripheral circuit region CORE / PERI, and a region adjacent to the cell array region CELL are shown. Figure 3The interface area INTERFACE of the cross-sectional area taken by the line BB'. The interface area INTERFACE can be referenced Figure 2 A portion of the interface region 26 is depicted. FIG. 12A to FIG. 12F In, with FIG. 8A to FIG. 8P The same reference numerals in the drawings respectively refer to the same components, and repeated descriptions thereof will be omitted.

[0143] Reference Fig. 12A , according to the reference Fig. 8A and Figure 8B In a similar manner as described above, a buffer insulating film 130 is formed on the substrate 110. However, in this example, the buffer insulating film 130 may extend from the cell array region CELL to the interface region INTERFACE. The buffer insulating film 130 may cover only a portion of the top surface of the device isolation film 112 in the interface region INTERFACE.

[0144] In this example, the buffer insulating film 130 may include a silicon oxide film.

[0145] Reference Fig. 12B , in the peripheral circuit region CORE / PERI, the exposed surface of the peripheral circuit active area A2 is cleaned, thereby removing an undesirable natural oxide film on the peripheral circuit active area A2.

[0146] In some embodiments, in order to clean the exposed surface of the peripheral circuit active area A2, a plasma dry cleaning process or a wet cleaning process may be used. In the plasma dry cleaning process, hydrogen may be used as a cleaning gas. The wet cleaning process may be performed by using an HF solution. During the cleaning of the exposed surface of the peripheral circuit active area A2, a portion of the peripheral circuit region CORE / PERI and the interface region INTERFACE may be exposed to the cleaning atmosphere, and as a result, a portion of the device isolation film 112 in the interface region INTERFACE may be removed due to the cleaning atmosphere. Specifically, in the interface region INTERFACE, since the cleaning etchant may penetrate into the interface between the buffer insulating film 130 and the filling insulating film 112C, wherein the filling insulating film 112C is below the end 130T of the buffer insulating film 130 and constitutes the device isolation film 112, a portion of the filling insulating film 112C below the end 130T of the buffer insulating film 130 may be removed, and as a result, an undercut region UA ​​may be formed below the end 130T of the buffer insulating film 130.

[0147] Reference Fig. 12C , forming a filling insulating pattern 132 to fill Fig. 12B The resulting product has an undercut area UA.

[0148] In some embodiments, in order to form the filling insulating pattern 132, Fig. 12B An insulating film having a thickness sufficient to fill the undercut area UA is formed on the entire surface of the resultant product, and then the insulating film is etched back so that only a portion of the insulating film filling the undercut area UA remains. The insulating film may include a silicon oxide film.

[0149] Reference Fig.12D , according to the reference Figure 8B In a similar manner as described above, a dielectric layer 142 and a metal-containing work function adjustment layer 144 are formed on the substrate 110 in the peripheral circuit region CORE / PERI. However, in this example, the dielectric layer 142 and the metal-containing work function adjustment layer 144 may be formed to extend from the peripheral circuit region CORE / PERI to a portion of the interface region INTERFACE.

[0150] Reference Fig.12E ,right Fig.12D The obtained product is executed with reference to FIG. 8C to FIG. 8N The described process thereby forms a peripheral circuit gate structure PGS in the peripheral circuit region CORE / PERI, and forms a plurality of bit line structures BLS in the cell array region CELL.

[0151] In the patterning process for forming the peripheral circuit gate structure PGS in the peripheral circuit region CORE / PERI, the dielectric layer 142 and the metal-containing work function adjustment layer 144 in the interface region INTERFACE may be removed. The end portion 130T of the buffer insulating film 130 and the filling insulating pattern 132 in the interface region INTERFACE may be covered with an interlayer dielectric 169.

[0152] Reference Fig.12F , can be Fig.12E The obtained product is executed with reference to Fig.8O and Figure 8P The described process is followed to manufacture the integrated circuit device 400 .

[0153] According to reference Figures 4 to 7 The integrated circuit device 100, 200, 300 or 400, when depositing doped polysilicon to utilize the above reference 8A to 12F In the process described above, when forming the direct contact DC in the cell array region CELL, in order to prevent the formation of a gap in the direct contact hole DCH, the aspect ratio of the structure including the direct contact hole DCH exposed during the deposition of polysilicon is reduced compared to the conventional process of forming the direct contact DC, and the doping concentration of the polysilicon is reduced compared to the conventional process to control the step coverage characteristic. 8A to 12FThe process described above can provide a direct contact DC having a seamless and stable structure in the cell array region CELL, and can provide a bit line structure BLS that can include a bit line semiconductor layer 156C having a reduced thickness and thus suppressing parasitic capacitance. 8A to 12F In the process described above, in the process of performing the process of forming the direct contact DC and the bit line structure BLS in the cell array region CELL while performing the process of forming the peripheral circuit transistor PTR in the peripheral circuit region CORE / PERI, since a seamless process is applied to form the direct contact DC, the peripheral circuit transistor PTR in the peripheral circuit region CORE / PERI may have a stacked structure including two polysilicon layers having different doping concentrations from each other. Therefore, the reliability of the integrated circuit device 100, 200, 300, or 400 may be improved.

[0154] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. An integrated circuit device comprising: a substrate having a cell array region and a peripheral circuit region, the cell array region including a first active region, and the peripheral circuit region including a second active region; a direct contact connected to the first active region in the cell array region; a bit line structure connected to the direct contact in the cell array region; as well as a peripheral circuit gate structure located on the second active region in the peripheral circuit region, The peripheral circuit gate structure includes two doped semiconductor layers, each of which is doped with carrier impurities having different doping concentrations. The two doped semiconductor layers included in the peripheral circuit gate structure include a first gate semiconductor layer having a first doping concentration, The direct contact includes a contact semiconductor layer having a second doping concentration lower than the first doping concentration.

2. The integrated circuit device according to claim 1, in, The bit line structure includes a bit line semiconductor layer having a third doping concentration higher than the second doping concentration.

3. The integrated circuit device according to claim 2, wherein: The two doped semiconductor layers included in the peripheral circuit gate structure further include a second gate semiconductor layer having a doping concentration equal to the third doping concentration.

4. The integrated circuit device according to claim 1, wherein: The direct contact includes a contact semiconductor layer having a doping concentration lower than a doping concentration of each of the two doped semiconductor layers included in the peripheral circuit gate structure.

5. The integrated circuit device according to claim 1, in, The direct contact comprises a contact semiconductor layer, the contact semiconductor layer comprises a doped semiconductor layer doped with carrier impurities, and Wherein, the contact semiconductor layer has a doping concentration equal to a doping concentration of one of the two doped semiconductor layers included in the peripheral circuit gate structure.

6. The integrated circuit device according to claim 1, further comprising: a direct contact spacer covering a side wall of the direct contact, Wherein, each of the direct contact and the direct contact spacer comprises a semiconductor layer.

7. The integrated circuit device according to claim 6, in, The direct contact spacer includes undoped polysilicon that is not doped with carrier impurities, and The direct contact comprises doped polysilicon doped with carrier impurities, and the doped polysilicon has a doping concentration lower than a doping concentration of each of the two doped semiconductor layers included in the peripheral circuit gate structure.

8. The integrated circuit device according to claim 6, in, The bit line structure extends along the substrate in a first direction, and The direct contact spacer covers two side walls of the direct contact located at opposite sides in the first direction, and does not cover two side walls of the direct contact located at opposite sides in a second direction orthogonal to the first direction.

9. The integrated circuit device according to claim 6, wherein: Each of the direct contact and the direct-contact spacer includes a portion buried in the substrate.

10. The integrated circuit device according to claim 1, further comprising: a buffer insulating film located between the substrate and the bit line structure in the cell array region, the buffer insulating film having a hole penetrated by the direct contact; as well as a direct contact spacer in the hole, the direct contact spacer being located between the direct contact and the buffer insulating film, Wherein, the direct contact spacer comprises undoped polysilicon which is not doped with carrier impurities, and The direct contact includes doped polysilicon doped with carrier impurities.

11. The integrated circuit device according to claim 10, further comprising: a semiconductor oxide film located between the buffer insulating film and the bit line structure in the cell array region, The semiconductor oxide film includes a dopant comprising B, In, P, As, Sb, or a combination thereof.

12. An integrated circuit device comprising: a substrate having a cell array region and a peripheral circuit region, the cell array region including a plurality of first active regions spaced apart from each other, and the peripheral circuit region including a second active region; a plurality of direct contacts each connected to a corresponding one of the plurality of first active regions in the cell array region; a plurality of bit line structures extending parallel to each other in a first direction in the cell array region, each of the plurality of bit line structures being connected to a corresponding one of the plurality of direct contacts; as well as a peripheral circuit gate structure located on the second active region in the peripheral circuit region, The peripheral circuit gate structure includes two doped semiconductor layers each doped with carrier impurities and having different doping concentrations, and Wherein, each of the plurality of direct contacts comprises a contact semiconductor layer having a doping concentration lower than a doping concentration of at least one of the two doped semiconductor layers.

13. The integrated circuit device according to claim 12, in, The peripheral circuit gate structure includes a first gate semiconductor layer having a first doping concentration and a second gate semiconductor layer having a second doping concentration, wherein the first gate semiconductor layer is located between the substrate and the second gate semiconductor layer and separates the substrate from the second gate semiconductor layer, and The contact semiconductor layer has a doping concentration lower than the first doping concentration and lower than the second doping concentration.

14. The integrated circuit device according to claim 12, in, The peripheral circuit gate structure includes a first gate semiconductor layer having a first doping concentration and a second gate semiconductor layer having a second doping concentration, wherein the first gate semiconductor layer is located between the substrate and the second gate semiconductor layer and separates the substrate from the second gate semiconductor layer, and The contact semiconductor layer has a doping concentration equal to the first doping concentration.

15. The integrated circuit device according to claim 12, further comprising: a plurality of buried contacts located between the plurality of bit line structures; a plurality of direct contact spacers each contacting a corresponding first sidewall portion of a sidewall of each of the plurality of direct contacts, each of the first sidewall portions being located in a region between a corresponding one of the plurality of bit line structures and the substrate; as well as A plurality of insulating spacers are each arranged between a corresponding one of the plurality of buried contacts and a corresponding one of the plurality of direct contacts, and each contacts a corresponding second side wall portion of a side wall of each of the plurality of direct contacts, each of the second side wall portions facing the plurality of buried contacts.

16. The integrated circuit device according to claim 12, further comprising: a buffer insulating film and a semiconductor oxide film, the buffer insulating film and the semiconductor oxide film being located between the substrate and the plurality of bit line structures in the cell array region and being stacked on the substrate in the listed order; a plurality of direct contact spacers penetrating the buffer insulating film and the semiconductor oxide film and contacting first sidewall portions of the plurality of direct contacts in the substrate; as well as A plurality of insulating spacers penetrate the buffer insulating film and the semiconductor oxide film and contact second side wall portions of the plurality of direct contacts in the substrate.

17. The integrated circuit device according to claim 12, further comprising: a device isolation film located in an interface region between the cell array region and the peripheral circuit region in the substrate; a buffer insulating film extending from the cell array region to the interface region on the substrate, the buffer insulating film covering a top surface of the device isolation film to define an undercut region above the top surface of the device isolation film in the interface region; as well as filling an insulating pattern which fills the undercut region, Wherein, each of the buffer insulating film and the filling insulating pattern includes an oxide film.

18. An integrated circuit device comprising: a substrate having a cell array region and a peripheral circuit region, the cell array region including a first active region, and the peripheral circuit region including a second active region; a direct contact connected to the first active region in the cell array region and comprising a doped contact semiconductor layer doped with carrier impurities having a first doping concentration; a bit line structure located above the substrate in the cell array region, the bit line structure comprising a bit line semiconductor layer contacting a top surface of the direct contact and having a doping concentration higher than the first doping concentration; a direct contact spacer contacting a first sidewall portion of a sidewall of the direct contact and comprising an undoped semiconductor not doped with carrier impurities, the first sidewall portion being between the substrate and the bit line structure; an insulating spacer contacting a second sidewall portion of the sidewall of the direct contact and covering a sidewall of the bit line structure; as well as A peripheral circuit gate structure is located on the second active area in the peripheral circuit area, wherein the peripheral circuit gate structure includes a first gate semiconductor layer and a second gate semiconductor layer, the first gate semiconductor layer has a doping concentration equal to or higher than the first doping concentration, and the second gate semiconductor layer has a doping concentration higher than the first doping concentration.

19. The integrated circuit device according to claim 18, in, The doping concentration of the first gate semiconductor layer is higher than the first doping concentration, and The bit line semiconductor layer and the second gate semiconductor layer have the same doping concentration.

20. The integrated circuit device according to claim 18, in, The doping concentration of the first gate semiconductor layer is equal to the first doping concentration, and The bit line semiconductor layer and the second gate semiconductor layer have the same doping concentration.

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