Transcendental function evaluation

Abstract

The present application discloses transcendental function evaluation. In the described example, an apparatus 500 is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function in response to the least significant bit of an input operand 510 and in response to first, second, and third table 520 values, respectively, using first circuit 530, second circuit 550, and third circuit 580, respectively. The first, second, and third table 520 values are retrieved in response to first, second, and third indices, respectively, which are generated in response to the most significant bit of the input operand. The third circuit 580 is further arranged to generate a mantissa of an output operand in response to the sum of the linear term, the quadratic term, and the constant term.

Description

Technical Field Background Art

[0001] A process for performing nonlinear control at a high performance level can evaluate a transcendental function to generate a corrected error signal in a feedback control loop. The corrected error signal is generated in response to a control loop error. The function |x| α is a transcendental function that typically uses a substantial amount of digital computation for its calculation / evaluation. In digital systems, such transcendental functions can be evaluated by determining a Taylor series expansion that consumes a high level of computing power and a large number of clock cycles for its execution. Hardware implementations for evaluating transcendental functions have been proposed, such as by using a CORDIC (Coordinate Rotation Digital Computer), which is an iterative process that converges to accuracy during successive steps. Accordingly, in a control loop, a function such as |x| α The evaluation of a transcendental function may consume a relatively large amount of power and time. Summary of the Invention

[0002] In the described example, an apparatus is arranged to generate, using first, second, and third circuits, a linear term, a quadratic term, and a constant term of a transcendental function in response to a least significant bit of an input operand and in response to first, second, and third table values retrieved in response to first, second, and third indices, respectively, the first, second, and third indices being generated in response to a most significant bit of the input operand. The third circuit is further arranged to generate an output operand in response to a sum of the linear term, the quadratic term, and the constant term. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an example system including an example execution unit for determining a transcendental function.

[0004] Figure 2 is a block diagram of an example CPU including an example execution unit for determining a transcendental function.

[0005] Figure 3 is a block diagram of an example FPU including an example execution unit for determining a transcendental function.

[0006] Figure 4 is a block diagram of registers of an example execution unit for determining a transcendental function.

[0007] Figure 5 is a high-level block diagram of an example execution unit for determining a transcendental function.

[0008] Figure 6 is a block diagram of an example data path of an example logarithmic execution unit for determining a log transcendental function.

[0009] Figure 7 is a block diagram of an example data path of an example exponentiation execution unit for determining an exponential transcendental function. DETAILED DESCRIPTION

[0010] This paper describes a method for performing a computation such as |x| α A system for evaluating transcendental functions. A transcendental function can be evaluated in response to curve fitting the transcendental function over a series of equally or unequally spaced segments, where the segments used for such curve fitting are determined relative to the mantissa of an input operand, and the curve fitting generates an approximation of the value of the transcendental function. Examples of digital circuits (such as execution units and / or hardware accelerators) for evaluating transcendental functions (such as logarithmic or exponential functions) in response to linear or quadratic curve fitting are described herein.

[0011] An example execution unit can be arranged to evaluate transcendental functions by rapidly evaluating functions that would otherwise be executed by a general-purpose processor executing software (or otherwise executing over a longer period of time). The execution unit can operate in conjunction with a processing unit such as a floating point unit (FPU) to provide improved speed, accuracy, and applicability for real-time control applications. The example execution units described herein can be emulated, for example, with programmable logic circuits and provide speed, accuracy, and applicability for real-time control applications.

[0012] To evaluate the logarithmic function of the input value, the input floating-point number is separated into its constituent mantissa and exponent parts. The linear and quadratic terms of the transcendental function can be evaluated in response to a curve fit on the mantissa. The linear and quadratic terms of the curve fit can be shifted and combined with the exponent value determined in response to the input exponent. In the case where the exponent is zero and the mantissa has leading zeros, the mantissa can be left-shifted. The final result can be left-shifted to generate a floating-point number of appropriate form containing an adjusted exponent.

[0013] To evaluate an inverse exponential function (which is an exponential function) of an input value, the input floating-point number is segmented in response to the slope of the function determined by the input mantissa and exponent. The linear and quadratic terms of the transcendental function can be evaluated in response to curve fitting the mantissa on non-equally spaced segments. The linear and quadratic terms are combined to form a final result. In response to the higher resolution x-value component in the curve fit due to floating-point representation (e.g., compared to the resolution of very large input values), the final result for the input value having points near zero is determined. The segments are separated (and the number of segments is selected) in response to the slope of the function determined by the input exponent to maintain the cardinality of the samples within the input value range to a selected precision when evaluating the exponential function.

[0014] Accordingly, an example execution unit for evaluating a transcendental function may be included in a digital implementation of a system, such as a real-time feedback system, that substantially reduces the delay in the time period for calculating the result of the transcendental function.

[0015] In the example system described below, when referencing a table of 128 segments, the function log2|x| can be evaluated to approximately 2 in six computer cycles. -23 The example FPU executing the software can evaluate the function in as few as 35 computer cycles. When referencing a table of 249 segments, the example system can evaluate function 2 in seven computer cycles. -|x| Evaluate with a precision of approximately 2 -20 , and the example FPU executing the software can evaluate the function in just 69 computer cycles. The example system can evaluate the function log in eight computer cycles. e |x|=log2|x|*(1 / (log2(e))), and the example FPU executing the software can evaluate this function in as few as 31 computer cycles. The example system can evaluate the function e in nine computer cycles. x =2 x*log2(e) The example FPU executing the software can evaluate the function in as few as 43 computer cycles. This level of precision and reduced latency provides sufficiently accurate and timely numerical results for real-time nonlinear control applications. In other systems designed according to the techniques of this disclosure, various combinations of a greater, lesser, or the same number of cycles can be used to evaluate one or more of the above functions.

[0016] In the example described below, an FPU is coupled to an example execution unit and is arranged to provide the execution unit with an indication of the floating point number and the instruction type. The FPU is arranged to wait six computer cycles for the result of a logarithm function and seven computer cycles for the result of an inverse exponentiation function. However, the FPU is pipelined so that the FPU does not need to remain idle while waiting for the result. Accordingly, for example, the latency of the FPU is reduced, allowing the FPU to adjust a nonlinear feedback loop more quickly.

[0017] In some examples, the execution units are arranged into at least two pipeline stages, wherein the second stage determines a second portion of the computation / evaluation of the first input operand, while the first stage determines a first half of the computation of the second input operand. Accordingly, the throughput of the example pipelined hardware acceleration system can be doubled compared to an otherwise similar example non-pipelined hardware acceleration system.

[0018] Figure 11 is a block diagram of an example system 100 including an example hardware accelerator for determining a transcendental function. For example, system 100 includes a control system to be controlled (also referred to as a "controlled system") 130. System 100 includes a feedback path 160 for operating in response to an output state signal 150 generated by controlled system 130. Output state signal 150 is coupled to an inverting input of adder 110 via feedback path 160. A non-inverting input of adder 110 receives a target output state signal 140 representing a target output state of controlled system 130. In response to output state signal 150 and the target output state signal, adder 110 generates a state error signal 170 for processing by a central processing unit (CPU) 120.

[0019] The CPU 120 includes a processor 122, a memory 124, an FPU 126, and an execution unit 128 that generates a nonlinear state error signal 170 that is presented as a control input to the controlled system 130. The execution unit 128 is arranged to digitally compute the (e.g., nonlinearized) state error signal 170. The state error signal 170 may be represented by a transcendental function |x| α , where x represents the state error signal 170 and α is a constant in a range (e.g., extending from 0.2 to 2.0). In this manner, the nonlinear response of the controlled system 130 can be accurately generated by the execution unit 128. The processor 122 is configured to generate input operands for hardware-accelerated calculation of the transcendental function, while the memory 124 is configured to receive and store the input operands. The execution unit 128 is arranged to generate an approximation of the transcendental function in response to the input operands stored and retrieved from the memory 124.

[0020] Figure 2 is a block diagram of an example CPU 200 including an example execution unit for determining a transcendental function. CPU 200 may be a processor, such as CPU 120. CPU 200 includes an operand bus 220 coupled to receive data from a data read bus 210. CPU 200 also includes a result bus 270 coupled to write data to a data write bus 280. Computation results generated by CPU 200 are asserted on result bus 270.

[0021] The CPU 200 also includes an FPU 250 coupled (e.g., tightly coupled) to an execution unit 260. The execution unit 260 (which may include hardware accelerators and / or digital logic circuits as described further below) is arranged to generate approximate (e.g., approximately estimated) results of transcendental functions in response to input operands stored and retrieved from register memory accessible to the FPU 250.

[0022] In an example multiplication operation that does not involve an execution unit, the CPU instruction controller 240 indicates a "multiplication" instruction to the FPU 250. In response to the "multiplication" instruction indication (and other control signals from the CPU instruction controller 240), the FPU 250 reads two floating-point numbers as input operands. The input operands may be stored in the CPU registers 230 (and received by the FPU 250 via the data read bus 210) or received by the FPU 250 from an external memory (via the data read bus 210 and the operand bus 220). In response to the received operation code (e.g., instruction), the CPU instruction controller 240 coordinates the scheduling and execution of FPU-related instructions and operands between, for example, the external memory, the CPU registers 230, and the FPU 250.

[0023] Figure 3 is a block diagram of an example FPU 300 including an example execution unit for determining a transcendental function. FPU 300 may be a processor, such as FPU 250. FPU 300 includes execution unit 370 arranged as a coprocessor (e.g., relative to a processor such as CPU 200). Register file 310 (such as R1, R2, ..., R7) is configured as scratch pad memory. FPU 300 includes multiplier hardware 320 and adder hardware 330, which are arranged to perform floating-point arithmetic operations.

[0024] The FPU 300 includes an execution unit 370. The execution unit 370 is arranged to evaluate at least exponential and logarithmic transcendental functions. The execution unit 370 includes exponential hardware (EXP hardware) 340, which is arranged to evaluate exponential functions (including inverse exponential functions), and also includes logarithmic hardware (LOG hardware) 350, which is arranged to evaluate logarithmic functions.

[0025] The top-level controller 360 of the FPU 300 executes instructions in response to clocked operations of a state machine configured to execute opcodes. For example, the top-level controller 360 generates and outputs bus control signals during a clock cycle for communicating information in response to an opcode received during a previous clock cycle. The top-level controller 360 may also operate in response to its own previous outputs. The FPU 300 is coupled to the execution units 370 such that the FPU 300 and the execution units 370 are arranged to execute instructions (e.g., transcendental functions) faster (e.g., more) than the FPU 300 could execute the same instructions alone (e.g., using a firmware-coded algorithm to sequence operations of adders and multipliers).

[0026] Figure 44 is a block diagram of registers and example registers of an execution unit for determining a transcendental function. Programming model 400 may include registers 420 of an FPU (which may be a processor such as FPU 300) and registers 430 of an execution unit 440 (which may be an accelerator such as execution unit 370). In the architecture described herein, the FPU is tightly coupled to the execution unit 440, which facilitates the passing of operands to and from the execution unit 440.

[0027] Registers 420 (e.g., registers forming part of an FPU) may include latches and / or flip-flops for accessibly storing digital information. Registers 420 include registers R0, R1, ..., R7 (represented as 421, 422, 423, and 424, respectively), a coefficient table 425, and flags 426 such as the LVF (overflow flag) and the LUF (underflow flag). Flags 426 may indicate an underflow or overflow condition encountered as a result of a calculation performed by the FPU in response to a received operand. Registers 420 are used to store information that is relatively quickly accessed internally (compared to external memory) by the FPU.

[0028] Data bus 460 is a data read bus (from the perspective of execution unit 440) through which information (such as operands) stored in FPU registers (such as register 420) can be read and stored in a selected register of execution unit 440 (e.g., at least one register 431, 432, 433, 434, 435, or 436). Data bus 450 is a data write bus (from the perspective of execution unit 440) through which a selected register of execution unit registers 430 can be accessed and stored in at least one selected register of FPU registers 420. For example, execution unit 440 includes circuitry (e.g., dedicated hardware) for evaluating a selected mathematical function, which can be executed in hardware more quickly than a general-purpose processor executing instructions for evaluating the corresponding mathematical function.

[0029] Execution unit 440 includes registers 430, which are arranged to store input and / or output operands for the underlying execution unit. Registers 430 are arranged to read and write (e.g., mathematical function input and / or output) operands such as ADDF32 operand (32-bit floating-point addition operand) 431, MPYF32 operand (32-bit floating-point multiplication operand) 432, CMPF32 opcode (32-bit floating-point comparator operand) 435, and ABSF32 operand (32-bit floating-point absolute value operand) 436.

[0030] Additionally, execution unit 440 includes registers for accessible storage of operations used to accelerate the evaluation of transcendental operations. For example, a 32-bit operand for floating-point exponentiation (IEXP2F32) can be read from and / or written to IEXP2F32 register 433, and a 32-bit operand for floating-point base-2 logarithm (LOG2F32) can be read from and / or written to LOG2F32 register 434. Registers 433 and 444 are tightly coupled to specialized circuitry within execution unit 440 (such as a high-speed floating-point integer exponentiation engine and a floating-point logarithm engine, respectively).

[0031] In an example IEXP2F32 operation, execution unit 440 may read the input operands from register 420 via data bus 460, causing the input operands to be stored in register 433. For example, when not pipelined, the FPU may execute a no-op opcode to account for the execution unit 440 time used by execution unit 440 to evaluate the exponential function. After execution unit 440 has evaluated the exponentiation of the input operands and has stored the output operand (e.g., the result) in register 433, execution unit 440 writes the contents of register 433 to the FPU (via data write bus 450), causing the FPU to obtain the exponentiation result generated by execution unit 440.

[0032] In an example LOG2F32 operation, execution unit 440 may read input operands from register 420 via data bus 460, causing the input operands to be stored in register 434. For example, when not pipelined, the FPU may execute a no-op opcode to account for execution unit 440 time used by execution unit 440 to evaluate the logarithm function. After execution unit 440 has evaluated the logarithm of the input operands and has stored the output operand (e.g., the result) in register 434, execution unit 440 writes the contents of register 434 to the FPU (via data write bus 450), causing the FPU to obtain the logarithm result generated by execution unit 440.

[0033] In an example, registers 432 and 433 can each store (e.g., simultaneously) both input and output operands. Additionally, registers 432 and 433 can each be arranged (e.g., replicated) to store one or both of the input / output operands for overlapping, pipelined execution of two transcendental functions of the same type (e.g., two exponentiations or two logarithms) or different types (e.g., one exponentiation and one logarithm).

[0034] Figure 55 is a high-level block diagram of an example execution unit for determining a transcendental function. Circuit 500 is an accelerator, such as execution unit 440 described above. Circuit 500 is arranged to determine the value (e.g., an estimate) of a transcendental function, such as a logarithmic function or an exponential function. The type of transcendental function to be performed can be determined in response to a register storing an input operand. The transcendental calculation is approximated by a quadratic curve fitting operation, wherein a curve of the form a*x is fitted over a range of values in response to the input operand x. 2 Evaluate the quadratic equation +b*x+c.

[0035] The circuit 500 is operable as an execution unit configured to receive data from and write data to registers of the FPU. The circuit 500 and the FPU may be arranged to generate a nonlinear state error signal for controlling the system in response to (e.g., determining a difference between) the output state of the system and the target output state.

[0036] For example, circuit 500 receives an input operand 510. Input operand 510 can be a floating point number, such that input operand 510 includes a mantissa 511, an exponent 514, and a sign bit. Mantissa 511 includes (e.g., a set of) mantissa most significant bits (MSBs) 512 and (e.g., a set of) mantissa least significant bits (LSBs) 513. (The MSBs and LSBs are not necessarily the highest-order or lowest-order bits available, respectively: accordingly, the term "most significant bit" can mean "more significant bit," and the term "least significant bit" can mean "less significant bit.") Circuit 500 is configured to receive input operand 510, which can be read from a register of an FPU. Circuit 500 is configured to generate a result in response to input operand 510 and write output operand 590 to a register of the FPU. The result is generated by evaluating (e.g., estimating) a quadratic equation in response to the input operand. In various examples, different numbers of bits of input operands (and formats of real numbers) may be used depending on computation speed, circuit complexity, precision of output values, and combinations thereof.

[0037] The first circuit 530 is arranged to generate a linear term (e.g., "b*x") of a transcendental function for curve fitting. The linear term is generated in response to a selected LSB 513 of a mantissa 511 of an input operand 510 and in response to a first table value retrieved from the table(s) 520 in response to a first index generated in response to a selected MSB 512 of the mantissa 511. When the transcendental function being evaluated is an exponential function, the first index is also determined in response to the exponent 514.

[0038] The second circuit 550 is arranged to generate a quadratic term of a transcendental function for curve fitting (eg, "a*x 2A quadratic term is generated in response to a selected LSB 513 of the mantissa 511 of the input operand 510 and in response to a second table value retrieved from the table(s) 520 in response to a second index, the second index being generated in response to the MSB 512 of the mantissa 511 of the input operand 510. When the transcendental function being evaluated is an exponential function, the second index is also determined in response to the exponent 514.

[0039] The third circuit 580 is arranged to generate (e.g., output) a constant term (e.g., "c") and combine the linear term and the quadratic term generated by the first circuit 530 and the second circuit 550. The constant term of the transcendental function used for the curve fit is generated in response to the linear term and the quadratic term and in response to a third table value retrieved from the table(s) 520 in response to a third index, which is generated in response to the MSB 512 of the mantissa 511. When the transcendental function being evaluated is an exponential function, the third index is also determined in response to the exponent 514. Additionally, the third circuit 580 is arranged to generate the mantissa of the output operand 590 in response to the sum of the linear term, the quadratic term, and the constant term. The table(s) 520 may be a unified table or may be divided into a first table, a second table, and a third table.

[0040] In an example, the first and second circuits 530 and 550 are arranged for parallel execution (e.g., where the linear term and the quadratic term are each determined during respective time periods that overlap in time). The first and second circuits 530 and 550 can be arranged as a first stage 501 in a pipeline, and the third circuit 580 can be arranged as a second stage 502 in the pipeline, such that the second stage 502 can add the quadratic term, the linear term, and the constant term of a first operand (e.g., evaluated by a first transcendental function) during a first time interval that overlaps in time with a second time interval in which the first stage 501 is determining the linear and quadratic terms in response to a second operand (e.g., evaluated by a second transcendental function). Arranging the first and second stages 501 and 502 in a pipeline configuration facilitates repeated execution of consecutive operations, such that throughput can be doubled (e.g., after the pipeline is filled).

[0041] Circuit 500 is programmable to selectively generate output operand 590 as a logarithmic result or an exponentiation result in response to a command generated by an external processor such as an FPU. For example, the third circuit can select one of a logarithmic and an exponential function in response to a decoded instruction. The logarithmic function can be evaluated in response to a curve fit of a table value indexed in response to the mantissa, while the exponentiation function can be evaluated in response to a piecewise curve fitting method, in which the domain of the table value is divided into segments (e.g., non-equally spaced segments) and the table is indexed in response to a curve fit of each indexed segment.

[0042] For an exponentiation function, a table (such as Table 2 described below) includes a sequence of non-equally spaced segments of values for approximating a result of the function in response to an index derived in response to a mantissa 511 and an exponent 514 of an input operand 510. A first table value retrieved from a first table in response to a first index, a second table value retrieved from a second table in response to a second index, and a third table value retrieved from a third table in response to a third index are values associated with endpoints of each of the non-equally spaced segments of the table of values. As an example, a transcendental function (|x|) for different values of x and α can be generated by determining intermediate values Z1 and Z2. α ), the final result Z3=(|x| α ):

[0043]

[0044]

[0045] Accordingly, we can express it as a transcendental function (|x| α ) to evaluate the logarithmic and exponential functions using the intermediate values Z1, Z2, and Z3 determined by .

[0046] For transcendental functions (such as exponential function 2 x ) can produce different precisions for a given computational quantity. For example, the exponential function 2 x The slope of the exponential function increases exponentially in response to a given increase in the x value. When x approaches zero, the density of floating-point numbers is the highest, and when x deviates from zero, the density decreases on either side of the number line. These two nonlinear effects cause the exponential function output to have a maximum density near zero (e.g., a smaller range of y values for a given range of x values), and a lower density (e.g., a larger range of y values for a given range of x values) away from zero. For example, the curve fitting technique described herein for evaluating the exponentiation function maintains accuracy on the value domain in response to the curve fitting values from non-equally spaced table segments. The (e.g., ordinate) spacing between the values in the table value domain for curve fitting is determined based on the index (e.g., the slope of its function) at the point (e.g., for a given exponent value). The optimal (e.g., for the target application) spacing of each interval can be determined in response to the least mean square analysis of the regression of the interval spacing and table length to determine the result of sufficient accuracy (e.g., cardinality) and table length (e.g., the number of index entries). Table 1 includes the number of entries in the table for each exponent in the range of -18 to 5.

[0047] Table 1

[0048] index entry -18 1 -17 1 -16 1 -15 1 -14 1 -13 1 -12 1 -11 1 -10 1 -9 1 -8 1 -7 2 -6 4 -5 8 -4 8 -3 16 -2 32 -1 32 0 32 1 32 2 32 3 32 4 8 5 0

[0049] An example table for evaluating the IEXP2F32 and LOG2F32 functions is listed below in Table 2. The coefficients of the curve fitting method may be determined based on a least mean squares method.

[0050] The symbols "IEXP2F32" and "LOG2F32" in the following example table represent macro names for extended instructions (opcodes) for computing 32-bit floating-point exponential or logarithmic results with a base of 2. Table entries are represented as hexadecimal numbers. "SL" is the slice / index number used to access the table entry; Y0i is the constant value for the quadratic fit of the transcendental function; and the terms "S1i" and "S2i" are the linear and quadratic coefficients, respectively. In this example, Table 2 includes 249 slices, each of which can be accessed using an index varying from 1 to 249. For the logarithmic table, the spacing of the slices (e.g., along the x-axis of the function of Table 2) is constant, and for the exponential table, the spacing of the slices (e.g., along the x-axis of the function of Table 2) is variable.

[0051] Table 2

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

[0059]

[0060]

[0061] Different tables may be used for different example transcendental functions. One set of tables for a particular transcendental function may have a fixed distance between input entry points, while another set of tables for another transcendental function may have a variable distance between input entry points.

[0062] Figure 6 6 is a block diagram of an example data path of an example logarithmic execution unit for determining a logarithmic transcendental function. For example, the logarithmic accelerator 600 is arranged to calculate the result of a logarithmic function (e.g., log2(x)) in response to an input operand. The input operand is a floating point number in the form of "1.M" (where "M" is the mantissa) and has a value between 1 and 2.

[0063] The logarithm accelerator 600 described herein is arranged to calculate floating-point logarithms in response to a curve fit including quadratic interpolation to generate a logarithmic result. The mantissa (e.g., for addressing a segment in the range [1.0, 2.0]) is represented by a number of equally spaced linear approximation segments. The coefficients of the curve fit can be derived using the least mean square method.

[0064] In operation, the logarithm accelerator 600 reads an input operand 610, wherein the input operand 610 includes a sign bit 611, an exponent bit 612, and a mantissa 613. The mantissa 613 is segmented into a most significant bit (MSB) 614 and a least significant bit (LSB) 615. In this example, the input operand 610 includes 32 bits (e.g., as in the range [31:0]). The input operand 610 is parsed to detect any formatting errors by the exception detection logic 616, and the detected errors are reported as indicated by the error_result module 617.

[0065] The module 651 is arranged to generate a 15-bit number in response to the LSBs (e.g., 16 bits) 615 of the mantissa 613 of the input operand 610. For example, the module 651 is arranged to determine the absolute value of the result of subtracting the hexadecimal number 0x8000 from the LSBs 615. The output of the module 651 is used, for example, to interpolate values determined from the first table 634 and the second table 655, as described below.

[0066] The first circuit 630 is arranged to generate a linear term of the logarithmic function in response to the LSB 615 of the mantissa 613 of the input operand 610 and in response to a first table value S1 retrieved from a first table 634 in response to a first index Index1, which is generated in response to the MSB 614 of the mantissa 613 of the input operand 610. As indicated by module 632, the 15-bit output of module 651 is left-shifted 10 times to produce a 25-bit number dx. For example, the least significant seven bits of bits [30:16] of the input operand can be selected to address the 128 entries of the LOG2F32 table of Table 2. (In various examples, the exponent is used only to generate the index, although otherwise additional circuitry would be required to accommodate nonlinearities in the logarithmic transfer function.) The notation dx<<10 indicates a 10-bit shift operation. As indicated by module 633, the number dx is multiplied by the first table value S1, resulting in a 49-bit number S1*dx. As indicated by block 635 , the 49-bit number is truncated / truncated to a 26-bit number with the least significant 22 bits discarded. The 26-bit number or term S1*dx is provided to a combiner 660 .

[0067] The second circuit 650 is arranged to generate a quadratic term of the logarithmic function in response to the LSB 615 of the mantissa 613 of the input operand 610 and in response to a second table value S2 retrieved from the second table 655 in response to a second index Index2, which is generated in response to the MSB 614 of the mantissa 613 of the input operand 610. For example, the least significant seven bits of bits [30:16] of the input operand can be selected to address the 128 entries of the LOG2F32 table of Table 2. As described above, the module 651 is arranged to generate a 15-bit number dx in response to the absolute value of the hexadecimal number 0x8000 subtracted from the 16-bit LSB number 615. As indicated by the module 652, the number dx is squared to produce the 29-bit number dx*dx.

[0068] The 29-bit number is truncated to an 18-bit number as indicated by module 653, wherein the least significant 11 bits are discarded (e.g., by truncation). The truncated 18-bit number dx*dx is multiplied by the second table value S2 as indicated by module 654, resulting in a 38-bit number S2*dx*dx. The 38-bit number is truncated to a 20-bit number as indicated by module 656, wherein the least significant 18 bits are discarded. The 20-bit term S2*dx*dx is provided to combiner 660.

[0069] The third circuit 680 is arranged to generate (e.g., output) a constant term of the logarithmic function in response to the LSB 615 of the mantissa 613 of the input operand 610 and in response to retrieving a third table value Y0 from a third table 684 in response to a third index Index3, which is generated in response to the MSB 614 of the mantissa 613 of the input operand 610. For example, the least significant 7 bits of bits [30:16] of the input operand can be selected to address the 128 entries of the LOG2F32 table of Table 2. As indicated by block 681, the terms S1*dx, S2*dx*dx obtained from the combiner 660 and the round-up constant 1 are added to produce a first result R1. As indicated by blocks 670, 682, the 26-bit result R1 is truncated to a 25-bit result R1, wherein the least significant bit is discarded. As indicated by module 683, the third table value Y0 is added to the 25-bit result R1 to produce a second result R2. As indicated by module 685, the exponent bits 612 of the input operand 610 minus the number 127 are added to the result R2. The result R2 is the value of the logarithmic function of the input operand 610. Accordingly, the third circuit 680 is arranged to generate the mantissa of the output operand (result R2) in response to the sum of the linear term, the quadratic term, and the constant term (in the possible results, any of the linear term, the quadratic term, and the constant term may have a value of zero). Additionally, as indicated by module 686, anomaly detection logic and output exponent and mantissa adjustments are performed on the result R2 to identify data failures.

[0070] Figure 7 is a block diagram of an example data path of an example exponentiation execution unit for determining an exponentiation transcendental function. For example, the exponentiation accelerator 700 is arranged to calculate an exponential function (e.g., 2 -|x| ) result. The exponentiation accelerator 700 described herein is arranged to calculate floating-point exponents in response to a curve fit including quadratic interpolation to generate an exponential result. A floating-point number is represented by a number of non-equally spaced linear approximation segments. The non-equally spaced segments (e.g., slices) are addressed by the mantissa and exponent of the input operands and are used to approximate the value of a transcendental function. The table used to evaluate the exponential function is different from the table used to evaluate the logarithmic function.

[0071] In operation, the exponentiation accelerator 700 reads an input operand 710 into the logarithm accelerator 700, where the input operand 710 includes a sign bit 711, an exponent bit 712, and a mantissa 713. The mantissa 713 is segmented into a most significant bit (MSB) 714 and a least significant bit (LSB) 715 (e.g., where X can be any value from 22 to 1). In this example, the input operand 710 includes 32 bits (e.g., such as a range of [31:0]). The input operand 710 is evaluated to detect any exceptional conditions (e.g., infinity, NaN (not a number), and denormality) through the exception detection logic 716, and detected errors are reported as indicated by the error_result module 717.

[0072] The module 751 is arranged to generate a 15-bit number in response to the LSBs (e.g., 16 bits) 715 of the mantissa 713 of the input operand 710. For example, the module 751 is arranged to determine the absolute value of the result of subtracting the hexadecimal number 0x8000 from the LSBs 715. The output of the module 751 is used, for example, to interpolate values determined from the first table 734 and the second table 755, as described below.

[0073] The first circuit 730 is arranged to generate a linear term of an exponential function in response to the LSB 715 of the mantissa 713 of the input operand 710 and in response to a first table value S1 retrieved from a first table 734 in response to a first index Index1, which is generated in response to the MSB 714 of the mantissa 713 and the exponent (bits 30:23 of the exponent) 712. For example, the least significant eight bits of bits [30:16] of the input operand may be selected for addressing the 249 entries of the IEXP2F32 table of Table 2. As indicated by module 732, the LSB 715 of the mantissa 713 is shifted left by 10 bits to produce a 25-bit number dx (the notation dx<<10 indicates a 10-bit shift operation). As indicated by module 733, the number dx is multiplied by the first table value S1, and the result is a 49-bit number S1*dx. As indicated by module 735 , the 49-bit number is truncated to a 26-bit number, with the least significant 22 bits discarded. The 26-bit term S1*dx is provided to combiner 760 .

[0074] The second circuit 750 is arranged to generate a quadratic term of the exponential function in response to the LSB 715 of the mantissa 713 of the input operand 710 and in response to a second table value S2 retrieved from the second table 755 in response to a second index Index2, which is generated in response to the MSB 714 of the mantissa 713 and the exponent 712. For example, the least significant eight bits of bits [30:16] of the input operand can be selected to address the 249 entries of the IEXP2F32 table of Table 2. As described above, the module 751 is arranged to generate a 15-bit number dx in response to the absolute value of the hexadecimal number 0x8000 subtracted from the 16-bit LSB number. The number dx is squared to produce a 29-bit number dx*dx, as indicated by the module 752.

[0075] As indicated by module 753, the 29-bit number is truncated to an 18-bit number, with the least significant 11 bits discarded. As indicated by module 754, the truncated 18-bit number dx*dx is multiplied by the second table value S2, resulting in a 38-bit number S2*dx*dx. The 38-bit number is truncated to a 20-bit number, as indicated by module 756, with the least significant 18 bits discarded. The 20-bit term S2*dx*dx is provided to combiner 760.

[0076] The third circuit 780 is arranged to generate a constant term for the exponential function in response to the LSB 715 of the mantissa 713 of the input operand 710 and in response to a third table value Y0 retrieved from a third table 784 in response to a third index Index3, which is generated in response to the MSB 714 of the mantissa 713 and the exponent 712. For example, the least significant eight bits of bits [30:16] of the input operand can be selected to address the 249 entries of the IEXP2F32 table of Table 2. As indicated by module 781, the terms S1*dx, S2*dx*dx obtained from the combiner 760 and the round-up constant 1 are added to produce a first result R1. As indicated by modules 770 and 782, the 26-bit result R1 is truncated to a 25-bit result R1, wherein the least significant bit is discarded. As indicated by module 783, the third table value Y0 is added to the 25-bit result R1 to produce a result R2. The result R2 is the value of the exponential function of the input operand 710. Accordingly, the third circuit 780 is arranged to generate the mantissa of the output operand (result R2) in response to the sum of the linear term, the quadratic term, and the constant term. Additionally, as indicated by module 786, anomaly detection logic and output exponent and mantissa adjustments are performed on the result R2 to identify data failures.

[0077] Continuing with reference to the previous figures, a process and related method for operating a device to calculate the value of a transcendental function have been described herein. In one embodiment, the method includes generating a linear term of the transcendental function in response to the least significant bit of the mantissa of an input operand and in response to a first table value retrieved from a first table in response to a first index, the first index being generated in response to the most significant bit of the mantissa of the input operand. The method also includes generating a quadratic term of the transcendental function in response to the least significant bit of the mantissa of the input operand and in response to a second table value retrieved from a second table in response to a second index, the second index being generated in response to the most significant bit of the mantissa of the input operand. The method also includes generating a constant term of the transcendental function in response to the least significant bit of the mantissa of the input operand and in response to a third table value retrieved from a third table in response to a third index, the third index being generated in response to the most significant bit of the mantissa of the input operand. The method also includes generating an output operand in response to the sum of the linear term, the quadratic term, and the constant term, and / or approximations thereof.

[0078] In one embodiment, the transcendental function is an exponential function, wherein a first index is further generated in response to the MSB of the exponent and mantissa of the input operand, wherein a second index is further generated in response to the MSB of the exponent and mantissa of the input operand, and wherein a third index is further generated in response to the MSB of the exponent and mantissa of the input operand.

[0079] In one embodiment, the output operand of the transcendental function is generated in response to a quadratic approximation of a linear term, a quadratic term, and a constant term, and wherein the quadratic approximation of the linear term, the quadratic term, and the constant term are generated in response to first, second, and third circuits, respectively, that are arranged to truncate and discard low-order bits to produce the linear term, the quadratic term, and the constant term, respectively.

[0080] Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. An apparatus for determining a transcendental function, comprising: a first circuit arranged to generate a linear term of the transcendental function in response to a least significant bit of an input operand and in response to a first table value retrieved from a first table in response to a first index, the first index being generated in response to a most significant bit of the input operand; a second circuit arranged to generate a quadratic term of the transcendental function in response to a least significant bit of the input operand and in response to a second table value retrieved from a second table in response to a second index, the second index being generated in response to a most significant bit of the input operand; as well as a third circuit arranged to generate a constant term of the transcendental function in response to a least significant bit of the input operand and in response to a third table value retrieved from a third table in response to a third index, the third index being generated in response to a most significant bit of the input operand, and wherein the third circuit is arranged to generate an output operand in response to a sum of the linear term, the quadratic term and the constant term.

2. The device according to claim 1, wherein The first circuit and the second circuit are arranged as parallel branches of a hardware pipeline to generate the linear term and the quadratic term, respectively, in parallel.

3. The device according to claim 1, wherein The third circuit is programmable to generate the output operand as a logarithm result or an exponentiation result in response to a command generated by an external processor.

4. The device according to claim 1, wherein The first table, the second table, and the third table are different tables.

5. The device according to claim 1, wherein The output operand of the transcendental function is generated in response to a quadratic approximation formed using the linear term, the quadratic term, and the constant term.

6. The device according to claim 1, wherein The third circuit is arranged to selectively generate the output operand as a result of one of an exponential function and a logarithmic function.

7. The device according to claim 1, wherein The transcendental function is an exponential function, wherein the first index is further generated in response to the exponentiation of the input operand, wherein the second index is further generated in response to the exponentiation of the input operand, and wherein the third index is further generated in response to the exponentiation of the input operand.

8. The device according to claim 1, wherein The output operand of the transcendental function is generated in response to quadratic approximations of the linear term, the quadratic term, and the constant term, and wherein the quadratic approximations of the linear term, the quadratic term, and the constant term are generated in response to the first circuit, the second circuit, and the third circuit, respectively, which are arranged to truncate and discard low-order bits to produce the linear term, the quadratic term, and the constant term, respectively.

9. The device according to claim 1, wherein The apparatus comprises an execution unit configured to receive the input operand from a register of a floating point unit (FPU).

10. The device according to claim 9, wherein The execution unit is configured to write the output operand to the register of the FPU.

11. The device according to claim 1, wherein The output operand is arranged to provide an input signal to the system to be controlled, and the input operand is responsive to a difference between an output state of the system to be controlled and a target state of the system to be controlled.

12. The device according to claim 1, wherein The first table value retrieved from the first table in response to the first index, the second table value retrieved from the second table in response to the second index, and the third table value retrieved from the third table in response to the third index are generated from one of a series of non-equally spaced segments addressed by the mantissa and exponent of the input operand for approximating a value of the transcendental function.

13. A system for determining a transcendental function, comprising: a processor arranged to generate input operands for hardware accelerated computation of said transcendental function; a memory configured to receive and store the input operand; as well as an execution unit arranged to generate an approximation of a transcendental function in response to said input operands stored and retrieved from said memory, comprising: a first circuit arranged to generate a linear term of the transcendental function in response to a least significant bit of a mantissa of the input operand and in response to a first table value retrieved from a first table in response to a first index, the first index being generated in response to a most significant bit of the mantissa of the input operand; a second circuit arranged to generate a quadratic term of the transcendental function in response to a least significant bit of the mantissa of the input operand and in response to a second table value retrieved from a second table in response to a second index, the second index being generated in response to a most significant bit of the mantissa of the input operand; and a third circuit arranged to generate a constant term of the transcendental function in response to a third table value retrieved from a third table in response to a third index generated in response to a most significant bit of the mantissa of the input operand, and wherein the third circuit is arranged to generate an output operand in response to a sum of the linear term, the quadratic term and the constant term.

14. The system according to claim 13, wherein: The output operand of the transcendental function is generated in response to a quadratic approximation formed by the linear term, the quadratic term, and the constant term.

15. The system according to claim 13, wherein: The transcendental function is an exponential function, wherein the first index is further generated in response to a least significant bit of an exponent of the input operand, wherein the second index is further generated in response to a least significant bit of the exponent of the input operand, and wherein the third index is further generated in response to a least significant bit of the exponent of the input operand.

16. The system of claim 13, wherein: The output operand of the transcendental function is generated in response to quadratic approximations of the linear term, the quadratic term, and the constant term, and wherein the quadratic approximations of the linear term, the quadratic term, and the constant term are generated in response to the first circuit, the second circuit, and the third circuit, respectively, which are arranged to truncate and discard low-order bits to produce the linear term, the quadratic term, and the constant term, respectively.

17. A method for determining a transcendental function by using a hardware accelerator, comprising: generating a linear term of the transcendental function in response to a least significant bit of an input operand and in response to a first table value retrieved from a first table in response to a first index generated in response to a most significant bit of the input operand; generating a quadratic term of the transcendental function in response to a least significant bit of the input operand and in response to a second table value retrieved from a second table in response to a second index generated in response to a most significant bit of the input operand; generating a constant term of the transcendental function in response to a least significant bit of the input operand and in response to a third table value retrieved from a third table in response to a third index, the third index being generated in response to a most significant bit of the input operand; as well as An output operand is generated in response to a sum of the linear term, the quadratic term, and the constant term.

18. The method according to claim 17, wherein The output operand of the transcendental function is generated in response to a quadratic approximation formed using the linear term, the quadratic term, and the constant term.

19. The method according to claim 17, wherein The transcendental function is an exponential function, wherein the first index is further generated in response to an exponent of the input operand, wherein the second index is further generated in response to the exponent of the input operand, and wherein the third index is further generated in response to the exponent of the input operand.

20. The method according to claim 17, wherein The output operand of the transcendental function is generated in response to quadratic approximations of the linear term, the quadratic term, and the constant term, and wherein the quadratic approximations of the linear term, the quadratic term, and the constant term are generated in response to first, second, and third circuits, respectively, the first, second, and third circuits being arranged to truncate and discard low-order bits to produce the linear term, the quadratic term, and the constant term, respectively.

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