Traveling wave carry adder

Abstract

The application provides a kind of travelling wave carry adder, comprising a plurality of input terminals for providing operation data and carry input;A plurality of output terminals for outputting operation results and providing carry output;At least one set of cascaded full adder connected between the input terminals and the output terminals for operating the operation data and the carry input of the input terminals;Wherein, the cascaded full adder is complementary structure.The travelling wave carry adder of the application can effectively reduce the calculation delay of the adder chain.

Description

Technical Field

[0001] This invention relates to a ripple carry adder, and more particularly to a multi-bit ripple carry adder for use in computing devices. Background Technology

[0002] In computer systems, addition is the core of all arithmetic operations. Therefore, improving the speed of addition is a common goal pursued by professionals in the field.

[0003] Early computers all used ripple-carry adders. For this type of adder, the sum Si of the i-th bit is...

[0004]

[0005] Where Ai and Bi are the i-th bits of the two operands, and Ci is the carry-in to the i-th bit. The carry-in to the next level (i+1) bits is...

[0006] C i+1 =A i ·B i +C i ·(A i +B i )

[0007] Therefore, adding two n-bit operands requires a maximum of n-1 carry delays and a summation delay. This is clearly insufficient to meet the high-speed requirements of modern computers.

[0008] After years of continuous improvement, adders are now mainly divided into two categories: asynchronous adders and synchronous adders. The vast majority of adders in today's computer systems use the latter. Although there are many types of synchronous adders, each with its own design philosophy and resulting circuit structure, they all share the common characteristic of overcoming the serial carry of ripple carry adders by increasing the parallelism between summation and carry calculation to minimize the delay of waiting for carry during summation, thereby improving the execution speed of the adder. However, their common drawback is that they still cannot meet the ever-increasing demands for processing speed.

[0009] CN104020980 discloses a full adder. For example... Figure 1As shown, full adder 400 receives one bit of input A and B at input 401 and adds these inputs, taking into account the value of the carry-in signal Cin at input 402. The carry-in signal Cin corresponds to the carry-out output generated by the adjacent adder, corresponding to the position of the lower bit. The final sum of the inputs at inputs 401 and 402 is provided at output 403 as a SUM and carry-out signal Cout. When adders 400 are chained, the carry-out signal Cout can be routed to the Cin input line of the next adder. A full adder like full adder 400 can be constructed using two half adders and an OR gate. The first half adder receives A and B. The second half adder receives the sum output from the first half adder and receives Cin. The second half adder generates the SUM signal for the full adder. The second half adder can also generate a carry-out signal. The carry output signal from the second half-adder and the carry output signal from the first half-adder can be combined using an OR gate, and the final output of the OR gate can be used as the Cout signal of the full adder.

[0010] A ripple carry adder can be formed from a chain of full adders, such as... Figure 2 As shown, the ripple carry adder 500 is formed by multiple full adder chains (FA0, FA1, FA2, etc.), with the carry input Cin of each full adder connected to the carry output Cout of the preceding full adder. For example, full adder FA1 receives the carry output signal C1 of the preceding full adder FA0 in the chain and provides its carry output signal C2 to the next full adder FA2.

[0011] These adders are called ripple carry adders because the correct value of the carry bit is propagated "ripple-wise" from one bit to the next. Ripple carry adders can be implemented efficiently but have limited performance. A valid output signal is not produced until the carry output of the last bit has been calculated. Because the carry signal travels ripple-wise through all stages of the adder, there is a computation delay proportional to the length of the adder chain. Summary of the Invention

[0012] To address the aforementioned problems, this invention provides a ripple carry adder that can effectively reduce the computational delay of the adder chain.

[0013] To achieve the above objectives, the present invention provides a ripple carry adder, comprising:

[0014] Multiple input terminals are used to provide calculation data and carry input;

[0015] Multiple output terminals are used to output the calculation results and provide carry output;

[0016] At least one cascaded full adder is connected between the input terminal and the output terminal for performing operations on the operation data at the input terminal and the carry input;

[0017] The cascaded full adders are complementary in structure.

[0018] In the aforementioned ripple carry adder, the complementary structure is such that the carry input and carry output of the cascaded full adder are out of phase.

[0019] In the aforementioned traveling-wave carry adder, the cascaded full adder includes a first full adder and a second full adder. The first full adder provides an inverted carry signal to the second full adder, and the second full adder receives the inverted carry signal and provides an in-phase carry signal.

[0020] The aforementioned ripple carry adder, wherein the cascaded full adder consists of multiple cascaded units.

[0021] The aforementioned ripple carry adder includes, as follows: the input terminals include a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and a fifth input terminal; the output terminals include a first output terminal, a second output terminal, and a third output terminal; the first, second, third, and fourth input terminals provide the computational data, and the fifth input terminal provides the carry input; the first output terminal outputs the computational result of the first full adder, the second output terminal outputs the computational result of the second full adder, and the third output terminal provides the carry output.

[0022] The aforementioned ripple carry adder, wherein the first full adder includes:

[0023] The first XOR gate has its inputs connected to the first input terminal and the second input terminal;

[0024] The second XOR gate has one input connected to the fifth input terminal and the other input connected to the output of the first XOR gate.

[0025] The output of the second XOR gate is connected to the first output terminal;

[0026] The AND, OR, and NOT gate has its first group of two inputs connected to the first input terminal and the second input terminal, its second group of two inputs connected to the output of the first XOR gate and the fifth input terminal, and its output connected to the third output terminal.

[0027] The aforementioned ripple carry adder, wherein the second full adder includes:

[0028] An XOR gate, whose input is connected to the first input terminal and the second input terminal;

[0029] An XOR gate, with one input connected to the fifth input terminal and the other input connected to the output of the XOR gate;

[0030] The output of the XOR gate is connected to the second output terminal;

[0031] A NAND gate, whose input is connected to the first input terminal and the second input terminal;

[0032] An AND gate, the input of which is connected to the output of the XOR gate and the fifth input terminal;

[0033] The NOR gate has its inputs connected to the NAND gate and the output of the AND gate, respectively, and its output is connected to the third output.

[0034] To achieve the above objectives, the present invention also provides a data processing unit, including interconnected control circuit, processing circuit, storage circuit, and one or more ripple carry adders, wherein the ripple carry adder is any of the ripple carry adders described above.

[0035] To achieve the above objectives, the present invention also provides a chip, wherein the chip includes any of the data processing units described above.

[0036] To achieve the above objectives, the present invention also provides a computing board for use in a computing device, wherein the computing board includes any of the chips described above, and the chips are mounted on the computing board.

[0037] To better achieve the above objectives, the present invention also provides a computing device, including a power board, a control board, a connection board, a heat sink, and a plurality of computing boards. The control board is connected to the computing boards through the connection board. The heat sink is disposed around the computing boards. The power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards. The computing boards are any of the aforementioned computing boards.

[0038] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of an existing full adder;

[0040] Figure 2 This is a schematic diagram of an existing traveling wave carry adder;

[0041] Figure 3 This is a schematic diagram of the structure of the ripple carry adder according to an embodiment of the present invention;

[0042] Figure 4This is a schematic diagram of the structure of a full adder according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the structure of a full adder according to another embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the data processing unit structure of the present invention;

[0045] Figure 7 This is a schematic diagram of the chip structure of the present invention;

[0046] Figure 8 This is a schematic diagram of the computing board structure of the present invention;

[0047] Figure 9 This is a schematic diagram of the computing device structure of the present invention.

[0048] In the attached figures, the following labels are used:

[0049] 100, 500: Traveling ripple carry adder

[0050] 200, 300, 400: Full adder; 201, 202, 203: Input terminals

[0051] 204, 205: Output terminals; 206, 207: XOR gates

[0052] 208: AND, OR, NOT gates

[0053] 301, 302, 303: Input terminals; 304, 305: Output terminals

[0054] 306: XOR gate; 307: XOR gate

[0055] 308, 310: NAND gate; 309: OR gate

[0056] A1, B1, A2, B2, CI: Input

[0057] S1, S2, CO: Output

[0058] 401, 402: Inputs; 403: Outputs

[0059] 700: Data processing unit; 701: Control circuit

[0060] 702: Operational circuit; 703: Storage circuit

[0061] 800: Chip; 801: Control Unit

[0062] 900: Computing board; 1000: Computing equipment

[0063] 1001: Connecting plate; 1002: Control plate

[0064] 1003: Radiator Detailed Implementation

[0065] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0066] Certain terms are used in the specification and subsequent claims to refer to specific components. It will be understood by those skilled in the art that manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but rather by differences in function. Throughout the specification, the same reference numerals denote the same elements.

[0067] Throughout this specification and in the following claims, the terms "comprising" and "including" are open-ended and should therefore be interpreted as "comprising but not limited to". Furthermore, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0068] For semiconductor devices in integrated circuits, the parasitic capacitance and load capacitance in metal-oxide-semiconductor (MOS) transistors cause the output voltage of the semiconductor device to lag behind changes in the input voltage. The time that the output voltage lags behind the change in the input voltage is called the "propagation delay time".

[0069] Typically, the average propagation delay time of a CMOS NOT gate is calculated as follows:

[0070] T pd =(T PHL +T PLH ) / 2, T PHL =T PLH .

[0071] in:

[0072] T pd Indicates the average transmission delay time.

[0073] T PHL This indicates the propagation delay time when the output transitions from a high level to a low level;

[0074] T PLH This indicates the transmission delay time when the output transitions from low to high.

[0075] If we define the average propagation delay time of a CMOS NOT gate as "T", then the propagation delay times of some common gate circuits can be found in Table 1:

[0076] Table 1

[0077]

[0078] Figure 1 This is a circuit diagram of an existing full adder. (Example:) Figure 1 As shown, the signal C input at input terminal 402 IN As the carry input of the full adder, it passes through an AND gate and an OR gate, and is output to the output terminal 403 as the carry output C. OUT As shown in Table 1, the carry input "C" of each full adder... IN "A transmission delay of 4T is required to obtain the carry output "C" OUT Table 2 is the truth table of the existing full adder 400.

[0079] Table 2

[0080]

[0081] Figure 2 This is a schematic diagram of an existing ripple carry adder. (Example:) Figure 2 As shown, the ripple carry adder 500 is formed by multiple full adder chains (FA0, FA1, FA2, etc.), and the carry input C of each full adder... IN The carry output C connected to the preceding full adder OUT part. Figure 2 The diagram only shows a ripple carry adder with a 3-stage full adder chain, where the carry output C of full adder FA2 is shown. OUT With the carry input C of the full adder IN There is a propagation delay of 3*4T between them. If the ripple carry adder 500 has an n-stage full adder chain, then the carry output C of the last full adder... OUT With the carry input C of the first-stage full adder IN There is a transmission delay of n*4T between them.

[0082] Figure 3 This is a schematic diagram of the traveling wave carry adder of the present invention. Figure 3 As shown, the ripple carry adder 100 includes two full adders 200 and 300; wherein the carry signal between the two full adders 200 and 300 is a complementary carry signal. The ripple carry adder of the present invention may also include more full adders, and their connection method can be the same as that of the two full adders. Here, a two-stage connection is used as an example for specific explanation.

[0083] The full adder 200 receives the first input A1, the second input B1, and the carry input CI at its input terminals. The carry input CI is connected to... Figure 1 Carry input C of the full adder 400 INThe signals are in phase. The full adder 200 outputs a summation signal S1 and a carry output CON. The carry output CON is in phase with... Figure 1 Carry-out C of a 400 full adder OUT The signals are out of phase.

[0084] The full adder 300 receives the third input A2, the fourth input B2, and the carry input CIN at its input terminals, respectively. The carry input CIN and... Figure 1 Carry input C of the full adder 400 IN The signals are out of phase. The full adder 300 outputs a summation signal S2 and a carry output CO. The carry output CO is... Figure 1 Carry-out C of a 400 full adder OUT The signals are in phase.

[0085] Figure 4 This is a circuit diagram of a full adder according to the present invention. Figure 4 As shown, the full adder 200 includes input terminals 201, 202, and 203, and output terminals 204 and 205. Input terminals 201 and 202 are used to receive the first input A1 and the second input B1, and input terminal 203 is used to receive the carry input CI; output terminal 204 is used to output the sum S1, and output terminal 205 is used to output the carry output CON.

[0086] XOR gate 206 has two input terminals, which are connected to the input terminals 201 and 202 of full adder 200 respectively; XOR gate 207 has two input terminals, one of which is connected to the input terminal 203 of full adder 200, and the other input terminal is connected to the output terminal of XOR gate 206. The output terminal of XOR gate 207 is connected to the output terminal 204 of full adder 200.

[0087] The AND-OR-NOT gate 208 has four inputs. Two inputs from one group are connected to inputs 201 and 202 of the full adder 200, respectively. One input from the other group is connected to the carry input CI, and the other is connected to the output of the XOR gate 206. The output of the AND-OR-NOT gate 208 is connected to output 205 of the full adder 200, outputting the carry output signal CON. The truth table of the full adder 200 is shown in Table 3.

[0088] Table 3

[0089]

[0090] As can be seen from Tables 2 and 3, when inputting A... i B i C i Under completely identical conditions, the summation signal S output by the full adder 200 i With Figure 1The summation signal of the full adder 400 is the same; the carry output signal C of the full adder 200 is the same. i+1 With Figure 1 The carry output signal of the full adder 400 is inverted.

[0091] Figure 5 This is a circuit diagram of another full adder of the present invention. Figure 5 As shown, the full adder 300 includes input terminals 301, 302, and 303, and output terminals 304 and 305. Input terminals 301 and 302 are used to receive the third input A2 and the fourth input B2, and input terminal 303 is used to receive the carry input CIN after being inverted by the full adder 200. Output terminal 304 is used to output the sum S2, and output terminal 305 is used to output the carry output CO.

[0092] The XOR gate 306 has two inputs, connected to inputs 301 and 302 of the full adder 300 respectively; the XOR gate 307 has two inputs, one connected to input 303 of the full adder 300, and the other connected to the output of the XOR gate 306, while the output of the XOR gate 307 is connected to the output 304 of the full adder 300; the NAND gate 308 has two inputs, connected to inputs 301 and 302 of the full adder 300 respectively; the OR gate 309 has two inputs, one connected to the carry input CIN, and the other connected to the output of the XOR gate 306; the NAND gate 310 has two inputs, connected to the outputs of both the NAND gate 308 and the OR gate 309, while the output of the NAND gate 310 is connected to the output 305 of the full adder 300, outputting the carry output signal CO. The truth table of the full adder 300 is shown in Table 4.

[0093] Table 4

[0094]

[0095] As can be seen from Tables 2 and 4, when inputting A... i B i Same, C i In the inverted state, the summation signal S output by the full adder 300 i Carry output signal C i+1 With Figure 1 The summation signal and carry output signal of the full adder 400 are exactly the same.

[0096] In summary, it can be seen that the ripple carry adder 100, composed of a two-stage adder chain of full adders 200 and 300, can produce the same result as... Figure 1 The two-stage adder chain of full adders 400 yields the same operational result. The propagation delay of the two-stage adder chain consisting of full adders 400 is 2 * 4T = 8T.

[0097] The carry input CI of the full adder 200 is passed through AND, OR, and NOT gates 208 to obtain the carry output CON. According to Table 1, the carry input CI of the full adder 200 only needs a propagation delay of "3T" to obtain the carry output CON.

[0098] The carry input CIN of the full adder 300 is also passed through OR gate 309 and NAND gate 310 to obtain the carry output CO. According to Table 1, the carry input CIN of the full adder 300 only needs a propagation delay time of "3T" to obtain the carry output CO.

[0099] Therefore, the carry input CI of the ripple carry adder 100, after passing through two full adders 200 and 300, results in a carry output CO with a propagation delay of only 3T + 3T = 6T. This saves the waiting time of the ripple carry adder chain for the carry signal.

[0100] The present invention also provides a data processing unit. Figure 6 This is a schematic diagram of the data processing unit of the present invention. Figure 6 As shown, the data processing unit 700 includes a control circuit 701, an arithmetic circuit 702, a storage circuit 703, and multiple ripple carry adders 100. The control circuit 701 performs addition operations on the data read from the storage circuit 703 using the ripple carry adders 100, the arithmetic circuit 702 performs other operations on the read data, and then the control circuit 701 outputs the operation results.

[0101] The present invention also provides a chip, Figure 7 This is a schematic diagram of the chip used in this invention. Figure 7 As shown, chip 800 includes a control unit 801 and one or more data processing units 700. The control unit 801 inputs data to the data processing units 700 and processes the data output by the data processing units 700.

[0102] The present invention also provides a computing board, Figure 8 This is a schematic diagram of the computing board of the present invention. Figure 8 As shown, each computing board 900 includes one or more chips 800, which perform hash calculations on the working data issued by the mining pool.

[0103] The present invention also provides a computing device, which is preferably used for mining virtual digital currencies, but of course, the computing device can also be used for any other massive computation. Figure 9 This is a schematic diagram of the computing device of the present invention. Figure 9As shown, each computing device 1000 includes a connection board 1001, a control board 1002, a heat sink 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the computing board 900 via the connection board 1001, and the heat sink 1003 is disposed around the computing board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the heat sink 1003, and the computing board 900.

[0104] It should be noted that in the description of this invention, the terms "lateral", "longitudinal", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0105] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

[0106] In other words, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A ripple carry adder, characterized in that, include: Multiple input terminals are provided for providing computational data and carry input, including: a third input terminal, a fourth input terminal, and a fifth input terminal; the third input terminal and the fourth input terminal provide the computational data, and the fifth input terminal provides the carry input; Multiple output terminals are used to output the calculation results and provide carry output, including: a first output terminal, a second output terminal, and a third output terminal; At least one cascaded full adder is connected between the input terminal and the output terminal for performing operations on the operation data at the input terminal and the carry input; The cascaded full adders are complementary in structure and include at least a first full adder and a second full adder. The inputs of both the first and second full adders receive the operational data and the carry input. The first full adder provides an inverted carry signal to the second full adder, and the second full adder receives the inverted carry signal and provides a non-inverted carry signal. The first output terminal outputs the operational result of the first full adder, the second output terminal outputs the operational result of the second full adder, and the third output terminal provides a carry output. The second full adder includes: The XOR gate has its inputs connected to the third input terminal and the fourth input terminal; An XOR gate, with one input connected to the fifth input terminal and the other input connected to the output of the XOR gate; The output of the XOR gate is connected to the second output terminal; A NAND gate, the input of which is connected to the third input terminal and the fourth input terminal; An OR gate, the input of which is connected to the output of the XOR gate and the fifth input terminal; The inputs of the NAND gate are connected to the outputs of the NAND gate and the OR gate, respectively, and the outputs are connected to the third output.

2. The ripple carry adder as described in claim 1, characterized in that, The complementary structure is such that the carry input and carry output of the cascaded full adder are out of phase.

3. The ripple carry adder as described in claim 2, characterized in that, The cascaded full adders consist of multiple cascaded units.

4. The ripple carry adder as described in claim 3, characterized in that, The input terminal also includes a first input terminal and a second input terminal, which provide the computational data.

5. The ripple carry adder as described in claim 4, characterized in that, The first full adder includes: The first XOR gate has its inputs connected to the first input terminal and the second input terminal; The second XOR gate has one input connected to the fifth input terminal and the other input connected to the output of the first XOR gate. The output of the second XOR gate is connected to the first output terminal; The AND, OR, and NOT gate has its first group of two inputs connected to the first input terminal and the second input terminal, its second group of two inputs connected to the output of the first XOR gate and the fifth input terminal, and its output connected to the third output terminal.

6. A data processing unit, comprising interconnected control circuitry, processing circuitry, storage circuitry, and one or more ripple carry adders, characterized in that: The ripple carry adder is any one of the ripple carry adders described in claims 1-5.

7. A chip, characterized in that, Includes any of the data processing units described in claim 6.

8. A computing board for use in a computing device, characterized in that, Includes any one of the chips described in claim 7, wherein the chip is mounted on the computing board.

9. A computing device, comprising a power board, a control board, a connection board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards via the connection board, the heat sink is disposed around the computing boards, and the power board is used to provide power to the connection board, the control board, the heat sink, and the computing boards, characterized in that: The computing board is any one of the computing boards described in claim 8.

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