Display module, display device, and method of manufacturing display module

Abstract

The present application relates to a method for manufacturing a display module, a display module, and a display device including at least one display module. The method for manufacturing a display module includes: providing a carrier substrate; providing a base layer on the carrier substrate, the base layer defining a display area and a pad area; providing a circuit layer on the display area of ​​the base layer and the pad area of ​​the base layer; forming a through hole in the circuit layer on the pad area and in the base layer; forming a conductive portion by providing a conductive material from an upper surface of the circuit layer to the through hole formed in the pad area; and providing a circuit member electrically connected to the circuit layer under the base layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2018-0073864, filed on Jun. 27, 2018, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The disclosure herein relates to a display module having a reduced width of a non-display area, a display device including the display module, and a method of manufacturing the display module. Background Art

[0004] In a module assembly device as a post-processing device for a display panel, a process of electrically connecting a display panel and a driving chip may be performed. This connection process may be classified into a process of a chip on glass ("COG") mounting method and a process of a tape automated bonding ("TAB") mounting method according to a driving chip mounting method.

[0005] The COG mounting method is a method by which a driving chip is directly mounted on a gate region and a data region of a display panel to transmit electrical signals to the display panel. For example, the COG mounting method may bond the driving chip to the display panel using an anisotropic conductive film ("ACF").

[0006] The TAB mounting method is a method of bonding a tape carrier package or a flexible film on which a driver chip is mounted to a display panel. This method also uses an ACF to bond the display panel to one end of the tape carrier package or the flexible film and to bond a printed circuit board to the other end of the tape carrier package or the flexible film. Summary of the invention

[0007] The present disclosure relates to a display module having a reduced width of a non-display area, and to a display module manufacturing method for manufacturing the display module and a display device having the display module.

[0008] An embodiment of the present invention provides a method for manufacturing a display module, the method comprising: providing a carrier substrate; providing a base layer on the carrier substrate, wherein the base layer defines a display area and a pad area; providing a circuit layer on the display area of ​​the base layer and the pad area of ​​the base layer; forming through holes in the circuit layer and the base layer located on the pad area; providing a conductive material from the upper surface of the circuit layer to the through hole formed in the pad area to form a conductive portion; and providing a circuit component electrically connected to the circuit layer under the base layer.

[0009] In an embodiment, the pad area of ​​the base layer may define a first pad area, a bending area, and a second pad area, wherein forming a through hole may include: forming a first contact hole in a circuit layer located on the first pad area and in the first pad area of ​​the base layer, and forming a second contact hole in a circuit layer located on the second pad area and in the second pad area of ​​the base layer.

[0010] In an embodiment, the method may further include: removing a portion of the bent area; and bending the bent area so that the first contact hole and the second contact hole overlap with each other when viewed from a plan view in a thickness direction of the display module, wherein forming the conductive portion may include providing a conductive material to the first contact hole and the second contact hole.

[0011] In an embodiment, the method may further include: setting a first mask layer on the upper surface of the circuit layer; forming a first mask pattern by patterning the first mask layer; forming a first contact hole and a second contact hole using the first mask pattern; removing a portion of the bent area using the first mask pattern; setting a second mask layer on the upper surface of the circuit layer; forming a second mask pattern by patterning the second mask layer; and patterning the circuit layer using the second mask pattern.

[0012] In an embodiment, the method may further include: disposing a mask layer on the upper surface of the circuit layer; forming a first mask pattern by patterning the mask layer; forming a first contact hole and a second contact hole using the first mask pattern; forming a second mask pattern by ashing a portion of the first mask pattern; and patterning the circuit layer using the second mask pattern.

[0013] In an embodiment, the method may further include grinding a portion of the bending region after the bending of the bending region.

[0014] In an implementation, removing the portion of the bending area may include removing the portion of the bending area so that a first thickness of at least a portion of the base layer in the bending area is less than a second thickness of the base layer in the first pad area.

[0015] In an embodiment, removing the portion of the bent region may include removing the portion of the bent region such that the first pad region and the second pad region are connected to each other through a remaining portion of the bent region.

[0016] In an embodiment, the method may further include: half-cutting an upper surface of the curved area of ​​the substrate layer or a lower surface of the curved area of ​​the substrate layer; and bending the curved area so that the first contact hole and the second contact hole may overlap with each other when viewed from a plan view in a thickness direction of the display module, wherein forming the conductive portion may include providing a conductive material to the first contact hole and the second contact hole.

[0017] In an implementation, the base layer may include a first alignment pattern disposed in the first pad region and a second alignment pattern disposed in the second pad region, and the method may further include bending the bending region so that the second alignment pattern is aligned with the first alignment pattern.

[0018] In an embodiment, the base layer may include a first alignment pattern, and the circuit member includes a second alignment pattern, and the method may further include disposing the circuit member on a back surface of the base layer such that the second alignment pattern is aligned with the first alignment pattern.

[0019] In an embodiment, the base layer may be set to multiple, and forming the base layer may include: setting a preliminary base layer on a carrier substrate, wherein portions of the preliminary base layer respectively define the base layers; and forming a connecting portion connecting the base layers to each other by removing a portion of the preliminary base layer, wherein forming the connecting portion and forming the through hole may be performed simultaneously.

[0020] In an embodiment, the method may further include separating the substrate layers from each other by cutting the connection portion.

[0021] In an embodiment of the present invention, a display module includes: a base layer, the base layer defining a first hole; a wiring layer, arranged on the base layer, wherein, when observed from a plan view in the thickness direction of the display module, a second hole is defined on an area of ​​the wiring layer corresponding to the first hole; an image display element layer, electrically connected to the wiring layer; a circuit component, arranged below the base layer; and a conductive portion, arranged from an upper portion of the wiring layer to the first hole and the second hole, and electrically connecting the wiring layer and the circuit component.

[0022] In an embodiment, the display module may further include: a sub-base layer disposed below the base layer, wherein a third hole is defined in an area corresponding to the second hole in the sub-base layer when viewed from a plan view in the thickness direction of the display module; and a sub-wiring layer disposed below the sub-base layer, wherein a fourth hole is defined in an area corresponding to the third hole in the sub-wiring layer when viewed from a plan view in the thickness direction of the display module. In such an embodiment, the sub-wiring layer may be electrically connected to the circuit member, and the conductive portion may be disposed in the first hole, the second hole, the third hole, and the fourth hole to electrically connect the wiring layer to the circuit member.

[0023] In an embodiment, the sub substrate layer and the circuit member may be disposed on a rear surface of the substrate layer, and the display module may further include a connection conductive portion connecting the sub substrate layer and the circuit member.

[0024] In an embodiment, the base layer may include a first alignment pattern, and the sub-base layer may include a second alignment pattern, wherein the first alignment pattern may be aligned with the second alignment pattern when viewed from a plan view in a thickness direction of the display module.

[0025] In an embodiment, the base layer may include a first alignment pattern and the circuit member may include a second alignment pattern, wherein the first alignment pattern may be aligned with the second alignment pattern when viewed from a plan view in a thickness direction of the display module.

[0026] In an embodiment, when viewed from a plan view in a thickness direction of the display module, the base layer may include: a first side extending in a first direction and spaced apart from each other; a second side extending in a second direction intersecting the first direction and spaced apart from each other; and a connecting side connecting one of the first sides to one of the second sides.

[0027] In an embodiment of the present invention, a display device includes: at least one display module, wherein the display module includes: a base layer, the base layer defining a first hole; a wiring layer, arranged on the base layer, wherein, when viewed from a plan view in the thickness direction of the display module, a second hole is defined in an area of ​​the wiring layer corresponding to the first hole; a sub-base layer, arranged below the base layer, wherein, when viewed from a plan view in the thickness direction of the display module, a third hole is defined in an area of ​​the sub-base layer corresponding to the second hole; a sub-wiring layer, arranged below the sub-base layer, wherein, when viewed from a plan view in the thickness direction of the display module, a fourth hole is defined in an area of ​​the sub-wiring layer corresponding to the third hole; a circuit component, arranged below the base layer; and a conductive portion, arranged in the first hole and the second hole to electrically connect the wiring layer and the circuit component. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the embodiments of the present disclosure will become more apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a perspective view of a display device according to an embodiment of the present invention;

[0030] Figure 2A is a plan view showing a display module constituting a display device according to an embodiment of the present invention;

[0031] Figure 2B is a plan view showing a display module constituting a display device according to an embodiment of the present invention;

[0032] Figure 3 is a diagram showing an embodiment of a display module, along Figure 2B A cross-sectional view taken along line II' shown in FIG.

[0033] Figure 4 is an alternative embodiment of the display module, along the Figure 2B A cross-sectional view taken along line II' shown in FIG.

[0034] Figure 5A It is shown Figure 3 and Figure 4 A plan view of a first alignment pattern shown in ;

[0035] Figure 5B It is shown Figure 3 and Figure 4 A plan view of a second alignment pattern shown in ;

[0036] Figure 6 is a circuit diagram showing a pixel according to an embodiment of the present invention;

[0037] Fig. 7A is a cross-sectional view of a pixel according to an embodiment of the present invention;

[0038] Figure 7B is a cross-sectional view of a pixel according to an alternative embodiment of the present invention;

[0039] FIG. 8A to FIG. 8K is a cross-sectional view showing a part of a manufacturing process of a display module according to an embodiment of the present invention;

[0040] 9A to 9C is a cross-sectional view showing a portion of a manufacturing process of a display module according to an alternative embodiment of the present invention;

[0041] FIG. 10A to FIG. 10C is a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention;

[0042] FIG. 11A to FIG. 11C is a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention;

[0043] Fig.12 is a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention;

[0044] FIG. 13A to FIG. 13D is a cross-sectional view showing a part of a manufacturing process of a display module according to an embodiment of the present invention;

[0045] Fig.13E is a plan view of a substrate layer according to an embodiment of the present invention; and

[0046] Fig.13F It is along Fig.13E A cross-sectional view taken along line II-II' shown in FIG. DETAILED DESCRIPTION

[0047] The present invention will now be described more fully below with reference to the accompanying drawings showing various embodiments. However, the present invention can be implemented in a variety of different forms and should not be construed as being limited to the embodiments set forth herein. More specifically, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the text, the same reference numerals indicate the same elements.

[0048] It will be understood that when a component (or region, layer, portion, etc.) is referred to as being "on," "connected to," or "combined to" another component, the component may be directly on, directly connected to, or directly combined to the other component, or a third component may be present in between.

[0049] In addition, in the drawings, the thickness, proportion and size of components are exaggerated for effective description. "Or" means "and / or". "At least one of A and B" means "A and / or B". "And / or" includes all of one or more combinations defined by the relevant components.

[0050] It will be understood that although the terms "first", "second", "third" etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part. As used herein, the singular forms "one", "one" and "the" are intended to include plural forms, including "at least one", unless the context clearly indicates otherwise.

[0051] In addition, terms such as "lower", "lower side", "upper", and "upper side" are used to describe the relationship of the configurations shown in the drawings. The terms are described as relative concepts based on the directions shown in the drawings.

[0052] In various embodiments of the present invention, the terms “include,” “comprise,” “including,” or “comprising” specify properties, regions, fixed numbers, steps, processes, elements, and / or components, but do not exclude other properties, regions, fixed numbers, steps, processes, elements, and / or components.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be understood to have the same meaning as their meaning in the context of the relevant technical field, and unless explicitly defined as such in this article, should not be interpreted in an idealized or overly formal meaning.

[0054] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Likewise, variations in the shapes shown in the illustrations, such as due to manufacturing techniques and / or tolerances, should be expected. Therefore, the exemplary embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but should include deviations in shapes, such as those caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0055] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0057] Reference Figure 1 , the display device DD can display an image through the display area DA. Figure 1 , an embodiment in which the display area DA has a surface defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1 is shown, but embodiments of the present invention are not limited thereto. In an alternative embodiment of the present invention, the display area DA of the display device DD may have a curved shape.

[0058] The thickness direction of the display device DD is indicated by the third direction DR3. As a relative concept, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be converted into other directions. In this specification, the term "on a plane" refers to the situation when observed from a plan view in the third direction DR3.

[0059] In an embodiment, if Figure 1As shown in , the display device DD may be a television. Alternatively, in addition to large-sized electronic devices such as monitors or external billboards, the display device DD may be used for medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation units, game consoles, smart phones, tablet computers, and cameras, for example, but is not limited thereto. The display device DD may be used in other electronic devices without departing from the scope of the present invention.

[0060] Figure 2A is a plan view showing a display module constituting a display device according to an embodiment of the present invention.

[0061] Reference Figure 1 and Figure 2A In order to expand the size of the display device DD, the display device DD may include a plurality of display modules DM. The display modules DM may be arranged along a first direction DR1 and a second direction DR2, respectively. Figure 2A As shown in FIG. 1 , three display modules DM are arranged in the first direction DR1, and three display modules DM are arranged in the second direction DR2. In this embodiment, a total of nine display modules DM are arranged, but not limited thereto. In this embodiment, the number of display modules DM included in the display device DD may be modified differently according to the size of the display device DD or the size of the display modules DM. In an embodiment, as shown in FIG. Figure 2A As shown in , each of the display modules DM may have a rectangular shape on a plane, but is not limited thereto. Alternatively, the shape of each of the display modules DM may be variously modified.

[0062] Each of the display modules DM may include a display area DA0 and a non-display area NDA0. In one embodiment, for example, the display area DA0 may be an area where the pixel light emitting area PXA is defined and displays an image, and the non-display area NDA0 may surround the display area DA0 and may not display an image.

[0063] In this embodiment where the display device DD comprises a display module DM, the display device DD ( Figure 1 The display area DA of the display module DM shown in FIG. 1 may overlap both the display area DA0 and the non-display area NDA0 of the display module DM. Therefore, if the width of the non-display area NDA0 is greater than a predetermined width, the non-display area NDA0 may be observed or recognized by a viewer. When the width of the non-display area NDA0 is reduced, the possibility that the boundary between the display modules DM is visible may be reduced. Therefore, in such an embodiment, as the width of the non-display area NDA0 is reduced, the display quality of the display device DD may be improved.

[0064] Figure 2Bis a plan view showing a display module constituting a display device according to an embodiment of the present invention.

[0065] Reference Figure 1 and Figure 2B , an embodiment of the display device DD may include a display module DM1.

[0066] The display module DM1 may include a display area DA1 and a non-display area NDA1. The display area DA1 of the display module DM1 may correspond to the display area DA of the display device DD. However, this is merely exemplary, and the display area DA1 may have a larger area than the display area DA. As the width of the non-display area NDA1 in the substrate of the display module DM1 decreases, the area ratio of the display area DA1 of the display module DM1 relative to the total area of ​​the display module DM1 may increase. Therefore, without increasing the size of the substrate, the size of the display screen may be increased by increasing the area ratio of the display area DA1.

[0067] Figure 3 is a diagram showing an embodiment of a display module, along Figure 2B A cross-sectional view taken along line II' shown in FIG.

[0068] Figure 3 The display module DMa is Figure 2B Display module DM1 or Figure 2A Implementation method of the display module DM. Figure 2A Each of the display modules DM in the Figure 2B The display module DM1 has different sizes, but can have the same Figure 2B The display module DM1 has basically the same structure.

[0069] The display module DMa includes a base layer BL, a sub base layer SBL, a wiring layer LL, a sub wiring layer SLL, an image display element layer IDL, a circuit member CM, a cover layer CL, and a conductive portion CP.

[0070] Each of the base layer BL and the sub-base layer SBL may include a flexible material, and may be, for example, a plastic substrate. The plastic substrate may include at least one selected from acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane-based resin, polyimide-based resin, polyamide-based resin, and perylene resin. In one embodiment, for example, the base layer BL and the sub-base layer SBL may include a single layer of polyimide-based resin. However, the present invention is not limited thereto, and alternatively, the base layer BL may have a multilayer structure (e.g., a stacked structure) including a plurality of insulating layers.

[0071] The first hole HL1 may be defined in the base layer BL. The first hole HL1 may be a hole extending from an upper surface of the base layer BL toward a lower surface of the base layer BL.

[0072] The wiring layer LL may be disposed on the upper surface of the base layer BL. The wiring layer LL may define a conductive layer constituting a circuit layer. The second hole HL2 may be defined in a region of the wiring layer LL. In one embodiment, for example, a region may be a region overlapping the first hole HL1 on a plane or when viewed from the thickness direction of the display panel DMa or the base layer BL (i.e., the third direction DR3). The second hole HL2 may be a hole extending from the upper surface of the wiring layer LL toward the lower surface of the wiring layer LL.

[0073] The sub-base layer SBL may be disposed under the base layer BL. The sub-base layer SBL may have the same layer structure as the base layer BL and include the same material as the base layer BL. The sub-base layer SBL may be a layer cut from the base layer BL. Figure 3 , for ease of explanation, the base layer BL and the sub-base layer SBL are shaded in the same manner.

[0074] The third hole HL3 may be defined in the sub base layer SBL. On a plane, the third hole HL3 may be defined in a region overlapping the first hole HL1 and the second hole HL2. The third hole HL3 may be a hole extending from an upper surface of the sub base layer SBL toward a lower surface of the sub base layer SBL.

[0075] The sub wiring layer SLL may be disposed under the sub base layer SBL. The sub wiring layer SLL may have the same layer structure as the wiring layer LL. The sub wiring layer SLL may be a layer formed by the same process as the wiring layer LL.

[0076] The fourth hole HL4 may be defined in the sub wiring layer SLL. On a plane, the fourth hole HL4 may be defined in a region overlapping the first hole HL1, the second hole HL2, and the third hole HL3. The fourth hole HL4 may be a hole extending from the upper surface of the sub wiring layer SLL toward the lower surface of the sub wiring layer SLL.

[0077] According to an embodiment of the present invention, the first hole HL1, the second hole HL2, the third hole HL3 and the fourth hole HL4 may overlap each other on a plane. Therefore, the upper surface of the uppermost wiring layer LL to the lower surface of the lowermost sub-wiring layer SLL may be penetrated by the first hole HL1, the second hole HL2, the third hole HL3 and the fourth hole HL4. The through hole is defined by the first hole HL1, the second hole HL2, the third hole HL3 and the fourth hole HL4.

[0078] The conductive portion CP may be disposed in the first hole HL1, the second hole HL2, the third hole HL3, and the fourth hole HL4. The conductive portion CP may be disposed in the first hole HL1, the second hole HL2, the third hole HL3, and the fourth hole HL4 from the upper portion of the wiring layer LL. A portion CPP of the conductive portion CP may be disposed on the upper surface of the wiring layer LL. Therefore, at least a portion of the upper surface of the wiring layer LL may be covered by the portion CPP of the conductive portion CP. In such an embodiment, the contact between the wiring layer LL and the conductive portion CP may be more stable, and the contact resistance between the wiring layer LL and the conductive portion CP may be reduced due to the increase in the contact area between the two.

[0079] According to an embodiment of the present invention, the conductive portion CP extends through the first hole HL1, the second hole HL2, the third hole HL3, and the fourth hole HL4 to electrically connect the first structure disposed on the upper surface of the base layer BL and the second structure disposed on the lower surface of the base layer BL. Therefore, in this embodiment, a connection member for connecting the first structure and the second structure may be omitted, and an area for a connection member to be disposed in the base layer BL may be omitted. Therefore, in this embodiment, the non-display area NDA1 (see Figure 2B ) can be reduced in width.

[0080] The image display element layer IDL may be disposed above the wiring layer LL. The image display element layer IDL may be a layer that operates to display an image. In an embodiment of the present invention, the image display element layer IDL may include a light emitting diode ("LED") element, such as a small LED element. In an alternative embodiment of the present invention, the image display element layer IDL may include an organic LED, an inorganic LED, or an organic-inorganic hybrid LED. In another alternative embodiment of the present invention, the image display element layer IDL may include liquid crystal molecules that control light transmission.

[0081] The cover layer CL may be disposed on the image display element layer IDL. The cover layer CL may be used to seal the image display element layer IDL. In one embodiment, for example, the cover layer CL may protect the image display element layer IDL from foreign substances such as moisture / oxygen or dust particles. The cover layer CL may have a stacked structure or may be a substrate. In one embodiment, for example, the stacked structure may include at least one organic sealing layer and at least one inorganic sealing layer alternately stacked with each other. The substrate may be a glass substrate or a plastic substrate.

[0082] The circuit member CM may be disposed below the base layer BL. The circuit member CM may provide a signal for controlling the image display element layer IDL. In one embodiment, for example, the circuit member CM may be a printed circuit board ("PCB"), a flexible printed circuit board ("FPCB"), a flexible film on which a driver chip is mounted, or a tape carrier package on which a driver chip is mounted.

[0083] The sub-base layer SBL and the circuit member CM may be disposed on the lower surface or the back surface BCS of the base layer BL. In an embodiment, an adhesive member (not shown) may be disposed between the back surface BCS of the base layer BL and the sub-base layer SBL and between the back surface BCS of the base layer BL and the circuit member CM. In one embodiment, for example, the adhesive member may be a double-sided tape.

[0084] In an embodiment, a connection conductive portion CCP connecting the sub-wiring layer SLL and the circuit member CM may be disposed below the sub-wiring layer SLL and the circuit member CM. The connection conductive portion CCP may include a conductive material. In an embodiment, for example, a conductive material may be printed on each of the sub-wiring layer SLL and the circuit member CM to form a connection conductive portion CCP. Therefore, the wiring layer LL may be electrically connected to the circuit member CM through the conductive portion CP, the sub-wiring layer SLL, and the connection conductive portion CCP.

[0085] The conductive material may be, for example, conductive ink or conductive glue. Conductive ink may be a material in which conductive particles are mixed with ink, and conductive glue may be a material in which conductive particles are dispersed in a liquid resin solution. Conductive particles may be, for example, an organic metal complex, a metal powder, or an inorganic compound, and may include, for example, copper, carbon, graphene, gold, silicon, platinum, or quantum dots. However, the materials of the conductive particles described above are merely exemplary, and the conductive particles are not limited to the above examples.

[0086] The base layer BL may include a first alignment pattern AP1, and the sub-base layer SBL may include a second alignment pattern AP2. The first alignment pattern AP1 may be aligned with the second alignment pattern AP2 on a plane. The first alignment pattern AP1 may be printed on the base layer BL, and the second alignment pattern AP2 may be printed on the sub-base layer SBL. Alignment between the base layer BL and the sub-base layer SBL may be performed with improved accuracy by the first alignment pattern AP1 and the second alignment pattern AP2.

[0087] Figure 4 is an alternative embodiment of the display module, along the Figure 2B A cross-sectional view taken along line II' shown in FIG. Figure 4 In the description of Figure 3Components that are identical to those described in , and any repeated detailed description thereof will be omitted or simplified.

[0088] Figure 4 The display module DMb shows Figure 2B Display module DM1 or Figure 2A An alternative implementation of the display module DM. Figure 2A Each of the display modules DM in the Figure 2B The display module DM1 has different sizes, but can have the same Figure 2B The display module DM1 has basically the same structure.

[0089] The display module DMb may include a base layer BL, a wiring layer LL, an image display element layer IDL, a circuit member CM, a cover layer CL, and a conductive portion CPa.

[0090] In this embodiment, if Figure 4 As shown in FIG, the subbase layer SBL (see Figure 3 ) and sub-wiring layer SLL (see Figure 3 ) can be found in Figure 4 is omitted.

[0091] The conductive portion CPa may be disposed from the upper portion of the wiring layer LL into the first hole HL1 and the second hole HL2. The through hole is defined by the first hole HL1 and the second hole HL2. A portion CPPa of the conductive portion CPa may be disposed on the upper surface of the wiring layer LL. Therefore, at least a portion of the upper surface of the wiring layer LL may be covered by a portion CPPa of the conductive portion CPa.

[0092] The circuit member CM is disposed under the base layer BL and may be disposed in a region overlapping the conductive portion CPa on a plane or when viewed from a plan view in the thickness direction of the display module DMb. Therefore, the circuit member CM may be electrically connected to the wiring layer LL through the conductive portion CPa.

[0093] The base layer BL may include a first alignment pattern AP1, and the circuit member CM may include a second alignment pattern AP2a. The second alignment pattern AP2a may be aligned to correspond to the first alignment pattern AP1. The first alignment pattern AP1 may be printed on the base layer BL, and the second alignment pattern AP2a may be printed on the circuit member CM. Alignment between the base layer BL and the circuit member CM may be performed with improved accuracy by the first alignment pattern AP1 and the second alignment pattern AP2a.

[0094] Figure 5A It is shown Figure 3 and Figure 4 A plan view of a first alignment pattern shown in Figure 5B It is shown Figure 3 and Figure 4 A plan view of the second alignment pattern shown in FIG.

[0095] In an embodiment, if Figure 5A As shown in , the first alignment pattern AP1 may have a cross shape. The second alignment pattern AP2 may have a shape corresponding to the shape of the first alignment pattern AP1, so that the first alignment pattern AP1 can be aligned with the second alignment pattern AP2. In one embodiment, for example, Figure 5B As shown in FIG. 1 , the second alignment pattern AP2 may include four rectangular shapes arranged to be disposed around the first alignment pattern AP1 .

[0096] Reference Figure 5A and Figure 5B The shapes of the first alignment pattern AP1 and the second alignment pattern AP2 described are merely exemplary, and the shapes of the first alignment pattern AP1 and the second alignment pattern AP2 may be changed differently. In one embodiment, for example, the shapes of the first alignment pattern AP1 and the second alignment pattern AP2 may be opposite, that is, the first alignment pattern AP1 and the second alignment pattern AP2 may have Figure 5B and Figure 5A In an alternative embodiment, the first alignment pattern AP1 may have a circular shape or a polygonal shape, and as long as the second alignment pattern AP2 has a shape that can be aligned with the circular first alignment pattern AP1 or the polygonal first alignment pattern AP1, the second alignment pattern AP2 has a shape corresponding to the shape of the first alignment pattern AP1. In one embodiment, for example, on a plane (or when viewed from a plan view in the thickness direction of the display module), the second alignment pattern AP2 may have a shape that does not overlap with the first alignment pattern AP1.

[0097] Figure 6 is a circuit diagram showing a pixel according to an embodiment of the present invention.

[0098] Reference Figure 6 In an embodiment, the pixel PX may be connected to a plurality of signal lines. In such an embodiment, among the signal lines, Figure 6 The scan line SL, the data line DL, the first power line PL1 and the second power line PL2 are shown. However, this is merely exemplary, and the pixel PX may be additionally connected to various signal lines and is not limited to a specific configuration.

[0099] The pixel PX may include an image display element ED and a pixel circuit PXC. The pixel circuit PXC may include a first thin film transistor TR1, a capacitor CAP, and a second thin film transistor TR2.

[0100] The first thin film transistor TR1 may be a switching transistor for controlling turning on and off of the pixel PX. The first thin film transistor TR1 may transmit or block a data signal transmitted through the data line DL in response to a gate signal transmitted through the scan line SL.

[0101] The capacitor CAP is connected to the first thin film transistor TR1 and the first power line PL1. The capacitor CAP is charged with an amount of charge corresponding to a difference between a data signal transferred from the first thin film transistor TR1 and a first power source voltage ELVDD applied to the first power line PL1.

[0102] The second thin film transistor TR2 is connected to the first thin film transistor TR1, the capacitor CAP and the image display element ED. The second thin film transistor TR2 controls the driving current flowing in the image display element ED corresponding to the amount of charge stored in the capacitor CAP. The on time of the second thin film transistor TR2 can be determined by the amount of charge charged in the capacitor CAP. During the on time, the second thin film transistor TR2 provides the first power supply voltage ELVDD transmitted through the first power line PL1 to the image display element ED.

[0103] The image display element ED is connected to the second thin film transistor TR2 and the second power line PL2. The image display element ED emits light at a voltage corresponding to a difference between a signal transmitted through the second thin film transistor TR2 and a second power source voltage ELVSS received through the second power line PL2.

[0104] The image display element ED includes a light emitting material. The image display element ED may generate light corresponding to the color of the light emitting material. The color of the light generated in the image display element ED may be any one of red, green, blue, and white.

[0105] In an embodiment, each of the first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type thin film transistor or a P-type thin film transistor. In an alternative embodiment, for example, one of the first thin film transistor TR1 and the second thin film transistor TR2 may be an N-type thin film transistor, and the other of the first thin film transistor TR1 and the second thin film transistor TR2 may be a P-type thin film transistor.

[0106] Fig. 7A is a cross-sectional view of a pixel according to an embodiment of the present invention.

[0107] Reference Figure 6 and Fig. 7A, the image display element ED is a micro-sized LED element ED1. In one embodiment, the micro-sized LED element ED1 may be an LED element having a size ranging from a few nanometers to hundreds of micrometers. However, the size of the micro-sized LED element ED1 described above is merely exemplary, and the size of the micro-sized LED element ED1 is not limited to the above-mentioned numerical range.

[0108] Fig. 7A : is a cross-sectional view showing the first thin film transistor TR1 , the second thin film transistor TR2 , and the micro-sized LED element ED1 .

[0109] The first thin film transistor TR1 may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, and a first semiconductor pattern SP1. The second thin film transistor TR2 may include a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, and a second semiconductor pattern SP2.

[0110] The first and second control electrodes CE1 and CE2 may be disposed on the base layer BL. The first and second control electrodes CE1 and CE2 may include metal.

[0111] The first insulating layer L1 may be disposed on the base layer BL and may cover the first and second control electrodes CE1 and CE2. In an embodiment, the first and second control electrodes CE1 and CE2 may be disposed between the first insulating layer L1 and the base layer BL.

[0112] The first and second semiconductor patterns SP1 and SP2 may be disposed on the first insulating layer L1. The first and second semiconductor patterns SP1 and SP2 may be spaced apart from the first and second control electrodes CE1 and CE2 in a cross-section or in a thickness direction of the base layer BL.

[0113] Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include a semiconductor material. In one embodiment, for example, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include the same semiconductor material as each other. Alternatively, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include semiconductor materials different from each other. The semiconductor material may include at least one selected from amorphous silicon, polycrystalline silicon, single crystal silicon, an oxide semiconductor, and a compound semiconductor.

[0114] The first input electrode IE1 and the first output electrode OE1 are disposed on the first semiconductor pattern SP1, and the second input electrode IE2 and the second output electrode OE2 may be disposed on the second semiconductor pattern SP2.

[0115] The second insulating layer L2 may be disposed on the first insulating layer L1, and may cover the first and second semiconductor patterns SP1 and SP2, the first and second input electrodes IE1 and IE2, and the first and second output electrodes OE1 and OE2. In an embodiment, the first and second semiconductor patterns SP1 and SP2, the first and second input electrodes IE1 and IE2, and the first and second output electrodes OE1 and OE2 may be disposed between the first insulating layer L1 and the second insulating layer L2.

[0116] The third insulating layer L3 may be disposed on the second insulating layer L2. In one embodiment, for example, the first insulating layer L1 and the second insulating layer L2 may include an inorganic material, and the third insulating layer L3 may include an organic material. The third insulating layer L3 may have a flat upper surface to provide a flat surface on a layer therebelow.

[0117] A connection electrode CCE connecting the first output electrode OE1 and the second control electrode CE2 may be disposed on the third insulating layer L3. In an embodiment, a through hole may be defined in the second insulating layer L2 and the third insulating layer L3, and a portion of the first output electrode OE1 may be exposed through the through hole. The connection electrode CCE may be electrically connected to the exposed portion of the first output electrode OE1. The through hole is defined to penetrate the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3, and a portion of the second control electrode CE2 may be exposed through the through hole. The connection electrode CCE may be electrically connected to the exposed portion of the second control electrode CE2.

[0118] The first electrode E1 may be disposed on the third insulating layer L3. A through hole is defined in the second insulating layer L2 and the third insulating layer L3, and a portion of the second output electrode OE2 may be exposed through the through hole. The first electrode E1 may be electrically connected to the exposed portion of the second output electrode OE2.

[0119] The second electrode E2 may be disposed on the third insulating layer L3. The second electrode E2 may be electrically connected to the second power line PL2 (see FIG. Figure 6 ) to receive the second power voltage ELVSS.

[0120] In an embodiment, the first electrode E1 and the second electrode E2 may include the same material as each other, such as a conductive material. In one embodiment, for example, the conductive material may include at least one selected from indium zinc oxide ("IZO"), indium tin oxide ("ITO"), indium gallium oxide ("IGO"), indium zinc gallium oxide ("IGZO"), and combinations thereof (e.g., mixtures and / or compounds). However, the present invention is not limited thereto. In an alternative embodiment, for example, the conductive material may be a metal material. The metal material may include, for example, molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0121] The micro-sized LED element ED1 may be disposed on the first electrode E1 and the second electrode E2. The micro-sized LED element ED1 may be electrically connected to the first electrode E1 and the second electrode E2. The pixel light emitting area PXA may be defined as an area corresponding to an area where the micro-sized LED element ED1 is disposed.

[0122] Figure 7B is a cross-sectional view of a pixel according to an alternative embodiment of the present invention. Figure 7B In the description of Fig. 7A The same components as those described are given the same reference numerals, and any repeated detailed description thereof will be omitted or simplified.

[0123] Reference Figure 6 and Figure 7B , the image display element ED is a light emitting element ED2. The light emitting element ED2 may be, for example, an organic light emitting element.

[0124] The light emitting element ED2 may include a first electrode E1a, a light emitting layer EM, and a second electrode E2a.

[0125] The first electrode E1a may be disposed on the third insulating layer L3. A through hole is defined in the second insulating layer L2 and the third insulating layer L3, and a portion of the second output electrode OE2 may be exposed through the through hole. The first electrode E1a may be electrically connected to the exposed portion of the second output electrode OE2.

[0126] In this embodiment, if Figure 7B As shown in , the fourth insulating layer L4 may be disposed on the third insulating layer L3. The fourth insulating layer L4 may cover a portion of the first electrode E1a and may expose another portion of the first electrode E1a. The fourth insulating layer L4 may be a pixel defining layer. The pixel light emitting area PXA may be defined to correspond to the first electrode E1a exposed by the fourth insulating layer L4.

[0127] The light emitting layer EM is disposed on the first electrode E1a. The light emitting layer EM may include a light emitting material. In one embodiment, for example, the light emitting layer EM may include at least one of a material for emitting red light, green light, or blue light, and may include a fluorescent material or a phosphorescent material. The light emitting layer EM may emit light in response to a potential difference between the first electrode E1a and the second electrode E2a.

[0128] The second electrode E2a is disposed on the light emitting layer EM. The second electrode E2a may be opposite to the first electrode E1a, for example, facing the first electrode E1a. The second electrode E2a may be electrically connected to Figure 6 The light emitting element ED2 may receive the second power voltage ELVSS through the second electrode E2a.

[0129] The second electrode E2a may include a transmissive conductive material or a semi-transmissive and semi-reflective conductive material, so that light generated in the light emitting layer EM may be effectively emitted through the second electrode E2a.

[0130] In an embodiment, although not shown in the drawings, the light emitting element ED2 may further include at least one organic layer or at least one inorganic layer disposed at at least one position between the light emitting layer EM and the first electrode E1a and between the light emitting layer EM and the second electrode E2a. The organic layer or the inorganic layer controls the movement of charges or electrons flowing from the first electrode E1a and the second electrode E2a into the light emitting layer EM to improve the light efficiency and life of the light emitting element ED2.

[0131] FIG. 8A to FIG. 8K is a cross-sectional view showing a part of a manufacturing process of a display module according to an embodiment of the present invention. FIG. 8A to FIG. 8K Schematic diagram of the manufacturing process with Fig. 7A The process of the pixel display module is shown in FIG.

[0132] Reference Fig. 8A , a base layer BL is provided (eg, formed) on a carrier substrate STG1. The carrier substrate STG1 may be, for example, a glass substrate.

[0133] A display area DAB and a pad area PDA may be defined in the base layer BL. A circuit layer CCL is disposed or formed on the display area DAB and the pad area PDA of the base layer BL. The circuit layer CCL may include a plurality of conductive layers, a plurality of insulating layers, and a semiconductor layer. In one embodiment, for example, the plurality of conductive layers may include a first control electrode CE1, a first input electrode IE1, a first output electrode OE1, a second control electrode CE2, a second input electrode IE2, a second output electrode OE2, a wiring layer LL, and a conductive layer CDL. The plurality of insulating layers may include a first insulating layer L1, a second insulating layer L2, and a third insulating layer L3. The semiconductor layer may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2.

[0134] The wiring layer LL may be a layer provided or formed by the same process as the conductive layer CDL and including the same material as the conductive layer CDL. However, the present invention is not limited thereto. In an alternative embodiment, for example, the wiring layer LL may be provided or formed by the same process as the first control electrode CE1 and may be a layer including the same material as the first control electrode CE1. In another alternative embodiment of the present invention, the wiring layer LL may be provided or formed by the same process as the first input electrode IE1 and may be a layer including the same material as the first input electrode IE1.

[0135] The first mask layer MPL is disposed or formed on the upper surface of the circuit layer CCL. The first mask layer MPL may be a polymer layer. In one embodiment, for example, the first mask layer MPL may be a photoresist layer that changes resistance when exposed to light or heat.

[0136] Reference Figure 8B , by the first mask layer MPL (see Fig. 8A ) is patterned to arrange or form the first mask pattern MP1. In one embodiment, for example, at least a portion of the first mask layer MPL arranged in the pad area PDA may be removed to form the first mask pattern MP1. The first mask pattern MP1 may be a photoresist pattern.

[0137] Reference Figure 8C , a hole may be formed in the wiring layer LL and the base layer BL using the first mask pattern MP1. A wet etching process or a dry etching process may be used to form the hole in the wiring layer LL and the base layer BL.

[0138] A first pad area PD1, a bending area BA, and a second pad area PD2 may be defined in the pad area PDA. The bending area BA may be defined between the first pad area PD1 and the second pad area PD2.

[0139] By using the first mask pattern MP1, a first contact hole CTH1 may be formed in the first pad region PD1, a second contact hole CTH2 may be formed in the second pad region PD2, and at least a portion of the bending area BA may be removed.

[0140] In this embodiment, the first contact hole CTH1 is defined by the first hole HL1 and the second hole HL2, and the second contact hole CTH2 is defined by the third hole HL3 and the fourth hole HL4. When viewed from a plan view in the thickness direction of the display module, the first hole HL1 and the second hole HL2 may overlap each other, and the third hole HL3 and the fourth hole HL4 may overlap each other. The bending hole BH may be defined in the bending area BA.

[0141] Reference Fig.8D , a plan view of a first mask pattern MP1 disposed in the pad area PDA is shown. For better understanding, a first contact hole CTH1, a second contact hole CTH2, and a bending hole BH formed by the first mask pattern MP1 are also shown.

[0142] In this embodiment, if Fig.8DAs shown in , the bending hole BH may be an area corresponding to a portion removed from the bending area BA. In the peripheral portion of the bending hole BH of the bending area BA, there may be an unremoved portion. The unremoved portion around the bending hole BH is referred to as a remaining portion RP. The first pad area PD1 and the second pad area PD2 may be connected to each other through the remaining portion RP.

[0143] Refer again Figure 8C After forming the first contact hole CTH1, the second contact hole CTH2, and the bending hole BH, the first mask pattern MP1 is removed. After removing the first mask pattern MP1, a second mask layer (not shown) is formed on the circuit layer CCL. The second mask layer may be Fig. 8A The first mask layer MPL shown in FIG. 2 is substantially the same form. The second mask layer may be a polymer layer. In one embodiment, for example, the second mask layer may be a photoresist layer that changes resistance when exposed to light or heat.

[0144] Reference Fig. 8E , the second mask layer is patterned to form a second mask pattern MP2. In one embodiment, for example, at least a portion of the second mask layer disposed in the display area DAB and the pad area PDA may be removed to form the second mask pattern MP2. The second mask pattern MP2 may be a photoresist pattern.

[0145] The wiring layer LL and the conductive layer CDL are patterned using the second mask pattern MP2. The connection electrode CCE, the first electrode E1, and the second electrode E2 may be patterned by patterning the conductive layer CDL (see FIG. Figure 8C ) is patterned to form. A wet etching process may be used to form the connection electrode CCE, the first electrode E1, and the second electrode E2. However, this is merely exemplary, and alternatively, a dry etching process may be used to form the connection electrode CCE, the first electrode E1, and the second electrode E2.

[0146] In this embodiment, the wiring LNS and the pad PDS can be connected by connecting the wiring layer LL (see Figure 8C ) is patterned to form. The patterned wiring layer LL may include wiring LNS and pads PDS. Figure 8F , a plan view of a second mask pattern MP2 disposed in the pad area PDA is shown.

[0147] The second mask pattern MP2 may have a thickness similar to that of the wiring layer LL (see FIG. Figure 8C ) corresponds to the shapes of the wiring LNS and the pad PDS formed by the second mask pattern MP2. For better understanding, reference numerals of the wiring LNS and the pad PDS formed by the second mask pattern MP2 are also shown.

[0148] In the following, Figure 8G , Figure 8H , Figure 8I and Figure 8J In FIG. 1 , portions that are not arranged on the same cross-sectional plane are shown by dotted lines. For example, the dotted lines shown in the curved area BA may be the same as those in the reference numerals above. Fig.8D The remainder of the description is RP.

[0149] Reference Figure 8G , after removing the second mask pattern MP2 (see Figure 8F ) After that, the micro-sized LED element ED1 is transferred to the first electrode E1 and the second electrode E2. In one embodiment, for example, a plurality of micro-sized LED elements ED1 may be transferred at the same time, or a single micro-sized LED element ED1 may be transferred.

[0150] The method of transferring the micro-sized LED element ED1 to the first electrode E1 and the second electrode E2 may include a direct transfer method or a printing transfer method. The direct transfer method may be a method of directly transferring the micro-sized LED element ED1 to the first electrode E1 and the second electrode E2. The printing transfer method may be a method of transferring the micro-sized LED element ED1 to the first electrode E1 and the second electrode E2 using an electrostatic head, a flat printing, or a roller printing.

[0151] Reference Figure 8H , the base layer BL is moved to the bending jig STG2. Although not shown in the drawings, a protective film (not shown) for protecting the circuit layer CCL may be further provided on the circuit layer CCL.

[0152] The bending area BA of the base layer BL may be bent such that the first contact hole CTH1 and the second contact hole CTH2 overlap.

[0153] After bending, the second pad region PD2 disposed under the first pad region PD1 may define a sub-base layer SBL (see Figure 3 ), and the wiring layer LL disposed on the base layer BL of the second pad region PD2 may define a sub-wiring layer SLL (see Figure 3 ).

[0154] Reference Figure 8I and Figure 8J , a conductive material CI is provided into the first contact hole CTH1 and the second contact hole CTH2 overlapping each other on a plane. A through hole is defined by the first contact hole CTH1 and the second contact hole CTH2. The conductive material CI may be, for example, a conductive ink or a conductive glue. Each of the conductive ink and the conductive glue may include conductive particles. In one embodiment, for example, the conductive particles may be an organic metal complex, a metal powder, or an inorganic compound and may include, for example, copper, carbon, graphene, gold, silicon, platinum, or quantum dots, but is not limited thereto.

[0155] Conductive material CI is provided (eg, injected) into the first and second contact holes CTH1 and CTH2 and then cured to form conductive portion CP. Curing may be thermal curing, dry curing, or ultraviolet ("UV") curing, but is not limited thereto.

[0156] The conductive portion CP may electrically connect the wiring LNS and the pad PDS corresponding one-to-one to the wiring LNS. Disposed in the first contact hole CTH1 may mean filling an empty space defined by the first contact hole CTH1.

[0157] According to an embodiment of the present invention, an object to be connected (e.g., wiring LNS and pad PDS) is formed, and then a conductive portion CP is formed. Therefore, at least a portion of the upper surface of the wiring LNS may be covered by a portion CPP of the conductive portion CP. In such an embodiment, the contact area may be more stable due to the increase in the contact area between the wiring LNS and the conductive portion CP. In such an embodiment, the contact resistance between the wiring LNS and the conductive portion CP may be reduced. In an alternative embodiment of the present invention, a portion of the pad PDS may have a shape covered by a portion of the conductive portion CP.

[0158] like Figure 8J As shown in , the curved area BA may be ground by a grinder GRD. However, this is merely exemplary, and alternatively, the curved area BA may be removed by a laser or the curved area BA may be removed by a knife.

[0159] Reference Figure 8K , a circuit member CM is disposed on the back surface of the base layer BL. In an embodiment, a conductive material may be printed on each of the circuit member CM and the pad PDS to electrically connect the circuit member CM and the pad PDS. Thus, a connection conductive portion CCP connecting the circuit member CM and the pad PDS may be formed.

[0160] In the embodiment of the present invention, as described above, the bent area BA is removed before the circuit member CM is provided (see Figure 8J ), the present invention is not limited thereto. In an alternative embodiment, for example, Figure 8K The process shown removes the bending area BA after the circuit member CM is provided.

[0161] 9A to 9C is a cross-sectional view showing a portion of a manufacturing process of a display module according to an alternative embodiment of the present invention.

[0162] Reference Fig. 8A and Fig. 9AIn an embodiment, the first mask pattern MP1a is formed by patterning the first mask layer MPL. In such an embodiment, at least a portion of the first mask layer MPL disposed in the pad area PDA and at least a portion of the first mask layer MPL disposed in the display area DAB are removed to form the first mask pattern MP1a.

[0163] The first mask pattern MP1a may be formed by, for example, using a half-tone mask. Therefore, a portion of the thickness direction of the first mask layer MPL may be removed in the display area DAB and the pad area PDA. Therefore, the conductive layer CDL of the display area DAB may not be exposed. Fig. 9A 2 shows the remaining portions MP1a-h and MP1a-ha after removing the above-mentioned portion in the thickness direction from the first mask layer MPL. In this embodiment, the portion of the first mask layer MPL completely removed in the thickness direction may correspond to Fig.8D The portion shown in FIG. 1 where the first mask pattern MP1 is not provided, and the remaining portion MP1a-ha after removing a portion of the first mask layer MPL from the pad area PDA may correspond to Figure 8F The portion shown in FIG. 1 is not provided with the second mask pattern MP2.

[0164] By using the first mask pattern MP1a, a first contact hole CTH1 may be formed in the first pad region PD1, a second contact hole CTH2 may be formed in the second pad region PD2, and a bending hole BH may be formed in the bending area BA.

[0165] Reference Fig. 9B , for the first mask pattern MP1a (see Fig. 9A ) is ashed to form a second mask pattern MP2a. The second mask pattern MP2a in the pad area PDA may correspond to Figure 8F The second mask pattern MP2 shown in FIG.

[0166] Reference Fig. 9C , using the second mask pattern MP2a to the wiring layer LL (see Fig. 9B ) and the conductive layer CDL (see Fig. 9B ) is patterned. The connection electrode CCE, the first electrode E1 and the second electrode E2 may be formed by patterning the conductive layer CDL, and the wiring layer LL may be patterned to form the wiring LNS and the pad PDS. The wiring layer LL may include the wiring LNS and the pad PDS.

[0167] Since the subsequent process is similar to the above reference Figure 8G to Figure 8K The described processes are basically the same, so any repeated detailed description thereof will be omitted.

[0168] FIG. 10A to FIG. 10Cis a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention.

[0169] Reference Fig. 8A and Fig. 10A In an embodiment, the first mask pattern MP1b is formed by patterning the first mask layer MPL. In such an embodiment, at least a portion of the first mask layer MPL disposed in the pad area PDA and at least a portion of the first mask layer MPL disposed in the display area DAB are removed to form the first mask pattern MP1b.

[0170] The first mask pattern MP1b may be formed by, for example, using a half-tone mask. A portion of the first mask layer MPL in the thickness direction may be removed in the display area DAB and the pad area PDA. Therefore, the conductive layer CDL of the display area DAB and the wiring layer LL of the bending area BA may not be exposed. Fig. 10A 2 shows remaining portions MP1 b - h and MP1 b - ha after a portion in the thickness direction is removed from the first mask layer MPL.

[0171] Reference Fig. 10A and Fig. 10B , a first contact hole CTH1 is formed in the first pad area PD1 by using a first mask pattern MP1b, and a second contact hole CTH2 is formed in the second pad area PD2. Thereafter, the first mask pattern MP1b is ashed, and the wiring layer LL and the conductive layer CDL are patterned using the ashed mask pattern. The connecting electrode CCE, the first electrode E1, and the second electrode E2 may be formed by patterning the conductive layer CDL. In such an embodiment, a portion of the wiring layer LL of the bending area BA and a portion of the base layer BLa of the bending area BA may also be removed. The first thickness TN1 of at least a portion of the base layer BLa located in the bending area BA may be less than the second thickness TN2 of the base layer BLa of each of the first pad area PD1 and the second pad area PD2.

[0172] Reference Fig. 10C , the base layer BLa is moved to the bending jig STG2. The bending area BA may be bent in such a manner that the first contact hole CTH1 and the second contact hole CTH2 overlap.

[0173] According to the embodiment of the present invention, due to the first thickness TN1 (see Fig. 10B ) is smaller than the second thickness TN2 of the base layer BLa in each of the first pad region PD1 and the second pad region PD2 (see Fig. 10B ), therefore, the bending of the bending area BA can become easier.

[0174] FIG. 11A to FIG. 11C is a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention.

[0175] Reference Fig. 8A and Fig.11A In an embodiment, the first mask pattern MP1c is formed by patterning the first mask layer MPL. In such an embodiment, at least a portion of the first mask layer MPL disposed in the pad area PDA may be removed to form the first mask pattern MP1c, and at least a portion of the first mask layer MPL disposed in the first pad area PD1 and the second pad area PD2 may be removed.

[0176] By using the first mask pattern MP1c, a first contact hole CTH1 is formed in the first pad region PD1 and a second contact hole CTH2 is formed in the second pad region PD2. After forming the first contact hole CTH1 and the second contact hole CTH2, the first mask pattern MP1c is removed.

[0177] Then, a second mask layer (not shown) is disposed or formed on the circuit layer CCL. The second mask layer may be disposed to be Fig. 8A The first mask layer MPL shown is of substantially the same form.

[0178] Reference Fig. 11B , the second mask layer is patterned to form a second mask pattern MP2c. In one embodiment, for example, at least a portion of the second mask layer disposed in the display area DAB and the pad area PDA may be removed to form the second mask pattern MP2c. The second mask pattern MP2c may be a photoresist pattern.

[0179] The wiring layer LL and the conductive layer CDL are patterned using the second mask pattern MP2c. The connection electrode CCE, the first electrode E1, and the second electrode E2 may be formed by patterning the conductive layer CDL. In such an embodiment, the wiring layer LL may be patterned by the second mask pattern MP2c.

[0180] Reference Fig. 11C , after removing the second mask pattern MP2c (see Fig. 11B ), the curved area BA of the base layer BL is half-cut. In one embodiment, for example, the base layer BL may be half-cut by a laser LS or may be half-cut by a cutter. Half-cutting means cutting a portion of the thickness of the base layer BL instead of cutting the entire thickness of the base layer BL.

[0181] In such an embodiment, since the base layer BL of the bending area BA is half-cut, the bending of the base layer BL may become easier.

[0182] Fig.12 is a cross-sectional view showing a portion of a manufacturing process of a display module according to another alternative embodiment of the present invention.

[0183] In an embodiment, if Fig. 11C As shown in FIG. , the upper surface of the base layer BL may be half-cut, but in an alternative embodiment, as shown in FIG. Fig.12 As shown in FIG. 8 , the lower surface of the base layer BL may be half-cut.

[0184] FIG. 13A to FIG. 13D is a cross-sectional view showing a part of a manufacturing process of a display module according to an embodiment of the present invention. Fig.13E is a plan view of a base layer according to an embodiment of the present invention. Fig.13F It is along Fig.13E A cross-sectional view taken along line II-II' shown in FIG.

[0185] Reference Fig.13A , a preliminary base layer BBL is disposed or formed on the carrier substrate STG. The preliminary base layer BBL may include a material for ensuring flexibility. In one embodiment, for example, the preliminary base layer BBL may include the same Figure 3 The described basal layer BL (see Figure 3 )same materials.

[0186] Reference Fig. 13B A circuit layer CCL is disposed or formed on the preliminary base layer BBL. The circuit layer CCL may include a plurality of conductive layers, a plurality of insulating layers, and a semiconductor layer.

[0187] Reference Fig. 13C , a through hole CTH and a boundary hole BCTH are formed in the preliminary base layer BBL and the circuit layer CCL using a photoresist pattern (PR). The through hole CTH and the boundary hole BCTH may be formed at the same time (eg, simultaneously during the same process).

[0188] Via CTH may include reference Figure 4 At least a portion of the preliminary base layer BBL may be removed to form a boundary hole BCTH, and the base layers BLS1, BLS2, and BLS3 may be separated by the boundary hole BCTH. In addition, as the boundary hole BCTH is formed, a connection portion CBL may be formed (see Fig.13D ).

[0189] Reference Fig.13D , the two base layers BLS1 and BLS2 may be spaced apart from each other with the boundary hole BCTH located therebetween. Each of the base layers BLS1, BLS2, and BLS3 may constitute a display module.

[0190] The boundary hole BCTH may be defined between the two base layers BLS1 and BLS2 and between the two connection parts CBL on a plane. Fig. 13C , an embodiment having a structure in which a boundary hole BCTH is formed between two base layers BLS1 and BLS2 and between two connection parts CBL is shown, but the present invention is not limited thereto. In an alternative embodiment of the present invention, for example, a plurality of boundary holes BCTH may be provided, and a connection part CBL may be additionally provided between the plurality of boundary holes BCTH.

[0191] According to an embodiment of the present invention, as the width of the non-display area is reduced, an area for processing during a display module manufacturing process may also be reduced. The connection portion CBL may be provided to ensure an area for processing.

[0192] Reference Fig.13E , the connecting part CBL can be removed in the subsequent process (see Fig.13D In one embodiment, for example, the connection portion CBL may be removed by a chamfering process. The connection portion CBL may be removed by a laser or may be removed by a cutter.

[0193] Therefore, in such an embodiment, the base layer BLS1 may include a first side SD1 extending in the first direction DR1 and a second side SD2 extending in the second direction DR2, and a connection side CD for connecting one of the first side SD1 and one of the second side SD2. In an embodiment, in the case where the connection portion CBL is disposed in a portion adjacent to four vertices, the number of the connection sides CD may be four. In an alternative embodiment of the present invention, in the case where the connection portion CBL is disposed in a portion adjacent to two vertices, there may be two connection sides CD.

[0194] Fig.13E An embodiment in which the connection side CD has a straight line shape is shown, but the present invention is not limited thereto. In an alternative embodiment, for example, the connection side CD may have a curved shape on a plane.

[0195] Fig.13F It is along Fig.13E The circuit member CM may be disposed directly under the base layer BL, and the circuit member CM may be electrically connected to the circuit layer CCL through the conductive portion CP disposed in the through hole CTH. Therefore, the width of the non-display area may be reduced.

[0196] According to an embodiment of the present invention, a hole is defined in a base layer of a display panel, and a wiring layer disposed on one side of the base layer and a circuit member disposed on the other side of the base layer can be electrically connected through a conductive portion disposed in the hole. Therefore, the width of a non-display area of ​​the display panel can be reduced.

[0197] In this embodiment, a portion of the conductive portion may cover a portion of the wiring layer. As the contact area between the conductive portion and the wiring layer increases, the contact resistance may decrease, and in addition, as the contact area increases, the contact between the wiring layer and the conductive portion may be more stable.

[0198] Although some exemplary embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these exemplary embodiments, but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the invention as claimed hereto.

Claims

1. A method for manufacturing a display module, the method comprising: providing a carrier substrate; A base layer is provided on the carrier substrate, wherein the base layer defines a display area and a pad area, wherein the pad area of ​​the base layer defines a first pad area, a bending area, and a second pad area, and the bending area is arranged between the first pad area and the second pad area; Disposing a circuit layer on the display area of ​​the base layer and the pad area of ​​the base layer; forming a first contact hole in the circuit layer on the first pad region and in the first pad region of the base layer; forming a second contact hole in the circuit layer on the second pad region and in the second pad region of the base layer; bending the bending region so that the first contact hole and the second contact hole overlap each other when viewed from a plan view in a thickness direction of the display module; forming a conductive portion by supplying a conductive material from an upper surface of the circuit layer to the first contact hole and the second contact hole formed in the pad region; and A circuit member electrically connected to the circuit layer is disposed under the base layer.

2. The method of claim 1, further comprising: Portions of the curved region are removed.

3. The method of claim 2, further comprising: Disposing a first mask layer on the upper surface of the circuit layer; forming a first mask pattern by patterning the first mask layer; forming the first contact hole and the second contact hole using the first mask pattern; removing the portion of the curved region using the first mask pattern; Disposing a second mask layer on the upper surface of the circuit layer; forming a second mask pattern by patterning the second mask layer; as well as The circuit layer is patterned using the second mask pattern.

4. The method of claim 2, further comprising: Disposing a mask layer on the upper surface of the circuit layer; forming a first mask pattern by patterning the mask layer; forming the first contact hole and the second contact hole using the first mask pattern; forming a second mask pattern by ashing a portion of the first mask pattern; as well as The circuit layer is patterned using the second mask pattern.

5. The method of claim 2, further comprising: After the bending region is bent, a portion of the bending region is ground.

6. The method of claim 2, wherein: Removing the portion of the bending area includes removing the portion of the bending area so that a first thickness of at least a portion of the base layer in the bending area is smaller than a second thickness of the base layer in the first pad area.

7. The method of claim 2, wherein: Removing the portion of the bending region includes removing the portion of the bending region such that the first pad region and the second pad region are connected to each other through a remaining portion of the bending region.

8. The method of claim 1, further comprising: The upper surface of the curved region of the base layer or the lower surface of the curved region of the base layer is cut in half, Wherein, forming the conductive portion includes: providing the conductive material to the first contact hole and the second contact hole.

9. The method of claim 1, wherein: The base layer includes a first alignment pattern disposed in the first pad region and a second alignment pattern disposed in the second pad region, and The method further includes bending the bending region so that the second alignment pattern is aligned with the first alignment pattern.

10. The method of claim 1, wherein: The base layer includes a first alignment pattern, and the circuit member comprises a second alignment pattern, The method further includes disposing the circuit member on a back surface of the base layer such that the second alignment pattern is aligned with the first alignment pattern.

11. Display module, including: a base layer defining a first aperture; a wiring layer disposed on the base layer, wherein a second hole is defined on a region of the wiring layer corresponding to the first hole when viewed from a plan view in a thickness direction of the display module; an image display element layer electrically connected to the wiring layer; a sub-base layer disposed below the base layer, wherein, when viewed from the plan view in the thickness direction of the display module, a third hole is defined on a region of the sub-base layer corresponding to the second hole; a sub-wiring layer disposed below the sub-base layer, wherein, when viewed from the plan view in the thickness direction of the display module, a fourth hole is defined on a region of the sub-wiring layer corresponding to the third hole; A circuit component is disposed below the base layer; a conductive portion provided from an upper portion of the wiring layer into the first hole, the second hole, the third hole, and the fourth hole and electrically connecting the wiring layer and the circuit member; and a connecting conductive portion disposed below the sub-wiring layer and the circuit member, wherein the sub-base layer and the circuit member are arranged on the back surface of the base layer, and The sub-base layer, the sub-wiring layer and the circuit member are arranged between the connecting conductive portion and the rear surface of the base layer.

12. The display module according to claim 11, wherein: The base layer includes a first alignment pattern, and The sub-base layer comprises a second alignment pattern, Wherein, when viewed from the plan view in the thickness direction of the display module, the first alignment pattern is aligned with the second alignment pattern.

13. The display module according to claim 11, wherein: The base layer includes a first alignment pattern, and the circuit member comprises a second alignment pattern, Wherein, when viewed from the plan view in the thickness direction of the display module, the first alignment pattern is aligned with the second alignment pattern.

14. The display module according to claim 11, wherein: When viewed from the plan view in the thickness direction of the display module, the base layer includes: first sides extending in a first direction and spaced apart from each other; second sides extending in a second direction intersecting the first direction and spaced apart from each other; and Connecting the sides, connecting one of the first sides to one of the second sides.

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