Display module and control method thereof, display driving circuit, and electronic device

Abstract

The embodiments of the present application provide a display module and a control method thereof, a display driving circuit, and an electronic device, which relate to the field of display technology and are used to reduce screen flicker when a display screen displays images at a low refresh rate. The display module includes a display screen, a display driver, and at least one driving group. The display screen includes M rows of sub-pixels arranged in a matrix form. Each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light-emitting device. Each driving group includes M gating circuits. The Nth gating circuit is coupled to the second pole of the first reset transistor in the Nth row of sub-pixels. The gating circuit is used to output a second initial voltage Vint2 to the second pole of the first reset transistor when the pixel circuit is in the reset stage and the data voltage writing stage, and to output a first initial voltage Vint1 to the second pole of the first reset transistor when the pixel circuit is in the light-emitting stage, |Vint2|>|Vint1|.

Description

[0001] This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office on July 31, 2019, with application number 201910704186.1 and application name “A display screen, electronic device and control method thereof”, the entire contents of which are incorporated by reference in this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display module and a control method thereof, a display driving circuit, and an electronic device. Background Art

[0003] With the continuous development of display technology, electronic devices, such as mobile phones, can display not only dynamic images but also static images. When displaying some dynamic images, in order to reduce the dynamic blur phenomenon, it is necessary to increase the refresh rate of the image (i.e., the number of times the image is refreshed per second). However, when displaying static images, such as standby images, a higher refresh rate will cause the power consumption of the electronic device to increase. In order to reduce power consumption, a lower refresh rate can be used when the electronic device displays static images. However, at this time, the electronic device will experience screen flicker, which reduces the display effect. Summary of the invention

[0004] The embodiments of the present application provide a display module and a control method thereof, a circuit system, and an electronic device, which are used to reduce the probability of screen flicker when the display screen displays images at a low refresh rate.

[0005] To achieve the above objectives, the present application embodiment adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a display module is provided. The display module includes a display screen, a display driving circuit and at least one driving group. The display screen includes sub-pixels arranged in a matrix of M rows. The pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device. Wherein, M≥2, and M is a positive integer. In addition, the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor. The second end of the first capacitor is coupled to the first power supply voltage input terminal. The first electrode of the driving transistor is coupled to the first power supply voltage input terminal during the light-emitting stage. The second electrode of the driving transistor is coupled to the light-emitting device. The data voltage output port is used to output the data voltage. The first electrode of the first reset transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the first reset transistor is the drain electrode and the second electrode is the source electrode. The first electrode of the driving transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the driving transistor is the drain electrode and the second electrode is the source electrode. The first power supply voltage input terminal is used to input the first power supply voltage, and is coupled to the data voltage output port of the display driving circuit during the data voltage writing stage. In addition, each driving group includes M gating circuits. Each gating circuit is coupled to the display driving circuit and is used to receive the first initial voltage Vint1 and the second initial voltage Vint2 output by the display driving circuit. Wherein, |Vint2|>|Vint1|. The Nth gating circuit is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. The gating circuit is also used to output the second initial voltage Vint2 to the second electrode of the first reset transistor when the pixel circuit is in the reset stage and the data voltage writing stage, and to output the first initial voltage Vint1 to the second electrode of the first reset transistor when the pixel circuit is in the light-emitting stage. Wherein, 1≤N≤M, N is a positive integer. The above reset stage is the stage in which the first reset transistor is turned on. The data voltage writing stage is the stage in which the data voltage is applied to the first electrode of the driving transistor. The light-emitting stage is the stage in which the light-emitting device is driven to emit light. Based on this, when the light-emitting device emits light, the source-drain voltage of the first reset transistor can be reduced to reduce the leakage current of the first reset transistor. In this way, when switching from a high refresh rate to a low refresh rate, the gate voltage of the driving transistor can be reduced due to leakage current, which causes a large voltage drop in the light-emitting stage, so that the sub-pixel light-emitting brightness is equivalent when the low refresh rate is used and when the high refresh rate is used. Therefore, when the refresh rate is switched, the probability of a sudden increase in the display brightness can be reduced, so that the human eye cannot keenly capture the change in brightness, and the probability of screen flickering is reduced.

[0007] Optionally, the display screen further includes M first initial voltage lines. Among them, the Nth first initial voltage line is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. Each gating circuit includes a first gating transistor and a second gating transistor. The first electrode of the first gating transistor in the Nth gating circuit is coupled to the display driving circuit, the second electrode of the first gating transistor is coupled to the Nth first initial voltage line, and the gate of the first gating transistor is used to receive the first gating signal. When the first gating signal is a valid signal, the first gating transistor is turned on, so that the initial voltage output by the display driving circuit is transmitted to the first initial voltage line. In addition, the first electrode of the second gating transistor in the Nth gating circuit is coupled to the display driving circuit, the second electrode of the second gating transistor is coupled to the Nth first initial voltage line, and the gate of the second gating transistor is used to receive the second gating signal, and the second gating signal is an inverted signal of the first gating signal. When the second gating signal is a valid signal, the second gating transistor is turned on, so that the initial voltage output by the display driving circuit is transmitted to the first initial voltage line. The first electrode of the first selection transistor is the source and the second electrode is the drain, or the first electrode of the first selection transistor is the drain and the second electrode is the source; the first electrode of the second selection transistor is the source and the second electrode is the drain, or the first electrode of the second selection transistor is the drain and the second electrode is the source.

[0008] Optionally, the display driving circuit has at least one first signal terminal and at least one second signal terminal. The first signal terminal outputs a first initial voltage Vint1. The second signal terminal outputs a second initial voltage Vint2. The first electrode of the first selection transistor is coupled to the first signal terminal. The first electrode of the second selection transistor is coupled to the second signal terminal. In this way, when the first selection transistor is turned on, the first initial voltage Vint1 can be transmitted to the first initial voltage line. When the second selection transistor is turned on, the second initial voltage Vint2 can be transmitted to the first initial voltage line. The display driving circuit can output the first initial voltage Vint1 and the second initial voltage Vint2 through two different signal terminals, thereby reducing the probability of signal crosstalk.

[0009] Optionally, the pixel circuit further includes a second reset transistor. The gate of the second reset transistor is coupled to the gate of the first reset transistor. The first electrode of the second reset transistor is coupled to the light emitting device. The second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth first initial voltage line. When the second reset transistor is turned on, the voltage on the first initial voltage line can be transmitted to the anode of the light emitting device to reset the anode of the light emitting device. The first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source.

[0010] Optionally, the display screen further includes M second initial voltage lines. The pixel circuit further includes a second reset transistor. The gate of the second reset transistor is coupled to the gate of the first reset transistor. The first electrode of the second reset transistor is coupled to the light emitting device. The second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line. The second initial voltage line is also coupled to the second signal terminal of the display driving circuit. The first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source. Since the second electrode of the second reset transistor is coupled to the second initial voltage line, the voltage of the drain of the second reset transistor can be the second initial voltage Vint2 in the first stage, the second stage and the third stage. In this way, the probability of the leakage current of the second reset transistor flowing to the light emitting device due to the increase of the drain of the second reset transistor in the third stage, thereby causing the light emitting device to emit light when the sub-pixel displays a black screen, and causing light leakage, can be reduced.

[0011] Optionally, the driving group also includes M inverters and M cascaded shift registers. The output end of the Nth shift register is coupled to the input end of the Nth inverter and the gate of the first gating transistor in the Nth gating circuit. The output end of the shift register is used to output a first gating signal. The output end of the Nth inverter is coupled to the gate of the second gating transistor in the Nth gating circuit. The output end of the inverter is used to output a second gating signal. In this way, the above-mentioned shift register can provide the first gating signal to the gate of the first gating transistor, and can also provide the gating signal to the gate of the second gating transistor through the inverter, thereby eliminating the need to separately set up a circuit for providing the first gating signal.

[0012] Optionally, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is coupled to the first power supply voltage input terminal. The second electrode of the first light-emitting control transistor is coupled to the first electrode of the driving transistor. The first electrode of the second light-emitting control transistor is coupled to the second electrode of the driving transistor. The second electrode of the second light-emitting transistor is coupled to the light-emitting device. The light-emitting device is also coupled to the second power supply voltage input terminal, and the second power supply voltage input terminal is used to input the second power supply voltage. The output terminal of the shift register is also coupled to the gates of the first light-emitting control transistor and the second light-emitting control transistor. When the signal output by the shift register controls the first light-emitting control transistor and the second light-emitting control transistor to turn on, the driving current generated by the driving transistor can flow through the light-emitting device to drive the light-emitting device to emit light. The first electrode of the first light-emitting control transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the first light-emitting control transistor is the drain electrode and the second electrode is the source electrode; the first electrode of the second light-emitting control transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the second light-emitting control transistor is the drain electrode and the second electrode is the source electrode.

[0013] Optionally, the display module includes a first driving group and a second driving group; the first driving group and the second driving group are respectively located on both sides of the display area of ​​the display screen. The Nth gating circuit in the first driving group and the Nth gating circuit in the second driving group are coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. In this case, when the resolution of the display screen is high, the number of sub-pixels in a row is large. By arranging the first driving group and the second driving group on the left and right sides of the display area, respectively, a gating circuit in the first driving group and a gating circuit in the second driving group provide the above-mentioned first initial voltage Vint1 and the second initial voltage Vint2 to the second electrodes of each first reset transistor in the same row of sub-pixels from the left and right sides, respectively, thereby effectively reducing the problem of signal attenuation.

[0014] Optionally, the display module includes a substrate. The pixel circuit, the display driving circuit and the driving group are arranged on the substrate. The material constituting the substrate includes a flexible material or a stretchable material. In this case, the display screen can be a flexible display screen that can be stretched and bent. The electronic device with the flexible display screen can be a foldable mobile phone or a foldable tablet.

[0015] According to a second aspect of the embodiment of the present application, an electronic device is provided, comprising the display module as described above. The electronic device has the same technical effect as the display module provided in the above embodiment, which will not be described in detail here.

[0016] In a third aspect of an embodiment of the present application, a control method for a display module is provided, wherein the display module includes a display screen, a display driving circuit, and at least one driving group. The display screen includes sub-pixels arranged in a matrix form of M rows. The pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light-emitting device. Wherein, M≥2, and M is a positive integer. In addition, the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor. The second end of the first capacitor is coupled to the first power supply voltage input terminal. The first electrode of the driving transistor is coupled to the first power supply voltage input terminal in the light-emitting stage and to the data voltage output port of the display driving circuit in the data voltage writing stage. The second electrode of the driving transistor is coupled to the light-emitting device. The first electrode of the first reset transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the first reset transistor is the drain electrode and the second electrode is the source electrode; the first electrode of the driving transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the driving transistor is the drain electrode and the second electrode is the source electrode; the first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage. In addition, each driving group includes M gating circuits. Each gating circuit is coupled to the display driving circuit and is used to receive the first initial voltage Vint1 and the second initial voltage Vint2 output by the display driving circuit. Wherein, |Vint2|>|Vint1|. The Nth gating circuit is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. The gating circuit is also used to output the second initial voltage Vint2 to the second electrode of the first reset transistor when the pixel circuit is in the reset stage and the data voltage writing stage, and to output the first initial voltage Vint1 to the second electrode of the first reset transistor when the pixel circuit is in the light-emitting stage. Wherein, 1≤N≤M, N is a positive integer. The control method of the display module includes: first, controlling M rows of sub-pixels to display row by row. When the Nth row of sub-pixels in the M rows of sub-pixels is controlled to display, the Nth gating circuit receives the first initial voltage Vint1 and the second initial voltage Vint2 output by the display driving circuit. The Nth gating circuit outputs the second initial voltage Vint2 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. The first reset transistor is turned on, and the second initial voltage Vint2 is transmitted to the gate of the driving transistor. The pixel circuit of the Nth row of sub-pixels is in the reset stage. The reset stage is the stage in which the first reset transistor is turned on. Next, the data voltage is written to the first electrode of the driving transistor, and the first reset transistor is controlled to be cut off, and the pixel circuit of the Nth row of sub-pixels is in the data voltage writing stage. The Nth gating circuit outputs the second initial voltage Vint2 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. The data voltage writing stage is the stage in which the data voltage is applied to the first electrode of the driving transistor.Next, the light-emitting device in the pixel circuit of the Nth row of sub-pixels is controlled to emit light, and the pixel circuit of the Nth row of sub-pixels is in the light-emitting stage, and the Nth selection circuit outputs the first initial voltage Vint1 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. The light-emitting stage is the stage of driving the light-emitting device to emit light. The control method of the above display module has the same technical effect as the display module provided in the above embodiment. It will not be repeated here.

[0017] Optionally, the value range of the first initial voltage Vint1 is 0 to 2V. When the first initial voltage Vint1 is less than 0V, the difference between the source-drain voltage of the first reset transistor in the light-emitting stage and the source-drain voltage of the first reset transistor in the other two stages (reset stage, data voltage writing stage) is small, so that the leakage current of the first reset transistor cannot be effectively reduced in the light-emitting stage, reducing the effect of eliminating the screen flicker phenomenon. In addition, when the first initial voltage Vint1 is greater than 2V, the leakage current of the second reset transistor will flow to the light-emitting device, thereby causing the light-emitting device to emit light when the sub-pixel displays a black screen, resulting in light leakage.

[0018] In a fourth aspect of an embodiment of the present application, a control method for a display module is provided. The display module includes a display screen and a display driving circuit. The display screen includes sub-pixels arranged in a matrix form of M rows. The pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light-emitting device. Wherein, M≥2, and M is a positive integer. In addition, the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor. The second end of the first capacitor is coupled to the first power supply voltage input terminal. The first electrode of the driving transistor is coupled to the first power supply voltage input terminal in the light-emitting stage, and to the data voltage output port of the display driving circuit in the data voltage writing stage. The second electrode of the driving transistor is coupled to the light-emitting device. The data voltage output port is used to output the data voltage; wherein the first pole of the first reset transistor is the source and the second pole is the drain, or the first pole of the first reset transistor is the drain and the second pole is the source; the first pole of the driving transistor is the source and the second pole is the drain, or the first pole of the driving transistor is the drain and the second pole is the source; the first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage. Based on this, the control method of the above-mentioned display module includes: first, controlling the M rows of sub-pixels to display row by row at a first refresh rate. When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset stage, the data voltage writing stage and the light-emitting stage, the display driving circuit outputs the second initial voltage Vint2 to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. Next, the M rows of sub-pixels are controlled to display row by row at a second refresh rate. Wherein, the second refresh rate is less than the first refresh rate. When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset stage, the data voltage writing stage and the light-emitting stage, the display driving circuit outputs the first initial voltage Vint1 to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. Among them, |Vint2|>|Vint1|. In addition, the reset stage is a stage for turning on the first reset transistor. The data voltage writing stage is a stage for writing the data voltage to the first electrode of the driving transistor. The light-emitting stage is a stage for driving the light-emitting device to emit light. The control method of the above display module has the same technical effect as the display module provided in the above embodiment. It will not be repeated here.

[0019] In a fifth aspect of an embodiment of the present application, a display driving circuit is provided. The display screen includes sub-pixels arranged in a matrix of M rows. The pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor, and a light-emitting device. Wherein, M≥2, and M is a positive integer. The first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor. The second end of the first capacitor is coupled to the first power supply voltage input terminal; the first electrode of the driving transistor is coupled to the first power supply voltage input terminal in the light-emitting stage, and is coupled to the data voltage output port of the display driving circuit in the data voltage writing stage. The second electrode of the driving transistor is coupled to the light-emitting device. Wherein, the first electrode of the first reset transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the first reset transistor is the drain electrode and the second electrode is the source electrode; the first electrode of the driving transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the driving transistor is the drain electrode and the second electrode is the source electrode. The first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage. Based on this, the display driving circuit is used to: control M rows of sub-pixels to display row by row at a first refresh rate; when controlling the Nth row of sub-pixels in the M rows of sub-pixels to display, in the reset stage, the data voltage writing stage and the light-emitting stage, output the second initial voltage Vint2 to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; control the M rows of sub-pixels to display row by row at a second refresh rate; wherein the second refresh rate is less than the first refresh rate; when controlling the Nth row of sub-pixels in the M rows of sub-pixels to display, in the reset stage, the data voltage writing stage and the light-emitting stage, output the first initial voltage Vint1 to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; wherein |Vint2|>|Vint1|. In addition, the reset stage is the stage in which the first reset transistor is turned on. The data voltage writing stage is the stage in which the data voltage is applied to the first pole of the driving transistor. The light-emitting stage is the stage in which the light-emitting device emits light. The control method of the above circuit system has the same technical effect as the control method of the display module provided in the above embodiment. It will not be repeated here.

[0020] In a sixth aspect of an embodiment of the present application, an electronic device is provided. The electronic device includes a display screen and a display driving circuit. The display screen includes sub-pixels arranged in a matrix form of M rows; the pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device. Wherein, M≥2, and M is a positive integer. The first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input terminal; the first electrode of the driving transistor is coupled to the first power supply voltage input terminal in the light-emitting stage, and to the data voltage output port of the display driving circuit in the data voltage writing stage. The second electrode of the driving transistor is coupled to the light-emitting device. Wherein, the first electrode of the first reset transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the first reset transistor is the drain electrode and the second electrode is the source electrode; the first electrode of the driving transistor is the source electrode and the second electrode is the drain electrode, or the first electrode of the driving transistor is the drain electrode and the second electrode is the source electrode. The first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage. Based on this, the display driving circuit is used to: control the M rows of sub-pixels to display row by row at a first refresh rate. When the Nth row of sub-pixels in the M rows of sub-pixels is controlled to display, in the reset stage, the data voltage writing stage and the light-emitting stage, the second initial voltage Vint2 is output to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels. In addition, the display driving circuit is also used to control the M rows of sub-pixels to display row by row at a second refresh rate. Wherein, the second refresh rate is less than the first refresh rate. When the Nth row of sub-pixels in the M rows of sub-pixels is controlled to display, in the reset stage, the data voltage writing stage and the light-emitting stage, the first initial voltage Vint1 is output to the second pole of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; wherein, |Vint2|>|Vint1|. In addition, the reset stage is the stage in which the first reset transistor is turned on; the data voltage writing stage is the stage in which the data voltage is applied to the first pole of the driving transistor; the light-emitting stage is the stage in which the light-emitting device emits light. The control method of the above-mentioned electronic device has the same technical effect as the control method of the display module provided in the aforementioned embodiment. It will not be repeated here.

[0021] In a seventh aspect of the embodiments of the present application, a computer readable medium is provided, which stores a computer program. When the computer program is executed by a processor, any one of the methods described above is implemented. The computer readable medium has the same technical effect as the control method of the display module provided in the above embodiment, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1a A schematic diagram of the structure of an electronic device provided for some embodiments of the present application;

[0023] Figure 1b for Figure 1aThe structural diagram of the display screen;

[0024] Figure 2a A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0025] Figure 2b , Figure 2c , Figure 2d They are the equivalent circuit diagrams of the pixel circuit in the first stage ①, the second stage ② and the third stage ③ respectively;

[0026] Figure 3 for Figure 2a The timing control diagram of the pixel circuit shown;

[0027] Figure 4 A time comparison diagram of a 60 Hz and 30 Hz image frame provided for some embodiments of the present application;

[0028] Figure 5 A comparison diagram of gate voltage and gate-source voltage of a 60 Hz and 30 Hz driving transistor provided in some embodiments of the present application;

[0029] Figure 6 A schematic diagram of an IV curve of a transistor provided for some embodiments of the present application;

[0030] Figure 7a A schematic diagram of the structure of a display module provided in an embodiment of the present application;

[0031] Figure 7b The embodiment of the present application provides Figure 2a A structural schematic diagram of a display screen of a pixel circuit shown;

[0032] Figure 7c A coupling method between a data line and a display driving circuit provided in an embodiment of the present application;

[0033] Figure 7d Another coupling method between the data line and the display driving circuit provided in the embodiment of the present application;

[0034] Figure 8a A schematic diagram of the structure of another display module provided in an embodiment of the present application;

[0035] Figure 8b The embodiment of the present application provides Figure 2a Another structural schematic diagram of a display screen of a pixel circuit shown;

[0036] Figure 9a A schematic diagram of the structure of another display module provided in an embodiment of the present application;

[0037] Figure 9bThe embodiment of the present application provides Figure 2a Another structural schematic diagram of a display screen of a pixel circuit shown;

[0038] Fig.9c A schematic diagram of a partial structure of another pixel circuit provided in an embodiment of the present application;

[0039] Fig.10 A signal timing diagram provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of the structure of another display module provided in an embodiment of the present application;

[0041] Fig.12a A schematic diagram of the structure of another display module provided in an embodiment of the present application;

[0042] Figure 12b The embodiment of the present application provides Figure 2a Another structural schematic diagram of a display module of a pixel circuit shown;

[0043] Fig.12c A schematic diagram of a partial structure of another pixel circuit provided in an embodiment of the present application;

[0044] Fig.13 A signal timing diagram provided in an embodiment of the present application;

[0045] Fig.14 A schematic diagram of the structure of another display module provided in an embodiment of the present application;

[0046] Fig.15 A flow chart of a control method for a display module provided in an embodiment of the present application.

[0047] Reference numerals:

[0048] 01-electronic device; 10-display screen; 11-middle frame; 12-housing; 20-sub-pixel; 201-pixel circuit; 100-AA area; 101-non-display area; 30-driving group; 301-selection circuit; 302-inverter; 40-display driving circuit. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0050] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0051] In addition, in the present application, directional terms such as "up", "down", "left" and "right" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to the changes in the orientation of the components in the drawings.

[0052] The embodiment of the present application provides an electronic device. The electronic device includes, for example, a television, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device. For the convenience of description, the following description is made by taking the electronic device as an example of a mobile phone.

[0053] In this case, the electronic device mainly includes a display module. The display module may include Figure 1a The display screen 10, the middle frame 11 and the housing 12 are shown. The display screen 10 is mounted on the middle frame 11, and the middle frame 11 is connected to the housing 12. The display screen 10 has a display surface and a back surface away from the display surface.

[0054] When the display screen 10 is mounted on the middle frame 11 and connected to the housing 12 through the middle frame 11, the housing 12 is disposed on the back of the display screen 10. The electronic device 01 further includes a printed circuit board (PCB) provided with an application processor (AP).

[0055] It should be noted that the above is an example of the display module structure. In other embodiments of the present application, the display module may also have two display screens 10, and the two display screens 10 may be respectively arranged on both sides of the middle frame 11. Thus, both the front and back sides of the electronic device can be displayed.

[0056] In addition, if Figure 1b As shown, the display screen 10 includes an active area (AA) 100 and a non-display area 101 located around the AA area 100 .

[0057] The AA area 100 is used to display the picture. Figure 1bAs shown, the AA region 100 includes a plurality of sub-pixels 20. Sub-pixels may also be referred to as sub-pixels or sub-pixels. For the convenience of description, the plurality of sub-pixels 20 are described in this application by taking a matrix arrangement as an example.

[0058] It should be noted that, in the embodiment of the present application, sub-pixels 20 arranged in a row along the horizontal direction X are referred to as sub-pixels in the same row, and sub-pixels 20 arranged in a row along the vertical direction Y are referred to as sub-pixels in the same column. For the convenience of explanation, the following is an example of M rows of sub-pixels 20 arranged in the AA area 100, where M ≥ 2, and M is a positive integer.

[0059] In the sub-pixel 20 in the AA region 100, a pixel circuit for controlling the sub-pixel 20 to display is disposed. Figure 2a As shown, the pixel circuit 201 at least includes a driving transistor M4, a first reset transistor M1, a first capacitor Cst and a light emitting device L. The first electrode of the first reset transistor M1, such as the source (source, s) and the gate (gate, g) of the driving transistor M4, the first end (such as the first end) of the first capacitor Cst Figure 2a The second end of the first capacitor Cst (such as Figure 2a The lower plate of Cst is coupled to the first power voltage input terminal (for outputting the first power voltage ELVDD).

[0060] It should be noted that the first electrode of the first reset transistor M1 may be a source s, and the second electrode may be a drain d. Alternatively, the first electrode of the first reset transistor M1 may be a drain d, and the second electrode may be a source s. For the convenience of description, the embodiments of the present application are all described by taking the first electrode of the first reset transistor M1 as a source s, and the second electrode as a drain d as an example.

[0061] In addition, the first electrode, for example, the source electrode s, of the driving transistor M4 is in the light emitting stage (eg Figure 3 In the third stage ③ shown in FIG. 1 , the first electrode of the driving transistor M4, for example, the source electrode s, is coupled to the first power supply voltage input terminal, so that the first power supply voltage ELVDD provided by the first power supply voltage input terminal can be received during the light emitting stage. Figure 3 The second stage ②) shown is coupled to the data voltage input terminal, so that the data voltage Vdata provided by the data voltage input terminal can be received in the data voltage writing stage. The second electrode of the driving transistor M4, such as the drain (d for short), is coupled to the light emitting device L.

[0062] It should be noted that the first electrode of the driving transistor M4 may be a source electrode s, and the second electrode may be a drain electrode d. Alternatively, the first electrode of the driving transistor M4 may be a drain electrode d, and the second electrode may be a source electrode s. For the convenience of description, the embodiments of the present application are all described by taking the first electrode of the driving transistor M4 as a source electrode s, and the second electrode as a drain electrode d as an example.

[0063] In addition, the light emitting device L may be an organic light emitting diode (OLED). In this case, the display screen 10 is an OLED display screen. Alternatively, the light emitting device L may be a micro light emitting diode (mirco light emitting diode, mirco LED). In this case, the display screen 10 is a mirco LED display screen. The display screen 10 can realize self-luminescence. For the convenience of description, the following examples are all taken as examples in which the light emitting device L is an OLED.

[0064] In this case, the second electrode, for example, the drain electrode d, of the driving transistor M4 may be coupled to the anode (anode, a) of the light emitting device L. The cathode (cathode, c) of the light emitting device L is coupled to the second power voltage input terminal (for outputting the second power voltage ELVSS).

[0065] In addition, the pixel circuit 201 is as follows Figure 2a Taking the structure of 7T1C shown as an example, the pixel circuit 201 may further include a first capacitor Cst and a plurality of transistors (M2, M3, M5, M6, M7). For the convenience of explanation, the transistor M7 is called a second reset transistor, the transistor M6 is called a first light emission control transistor, and the transistor M5 is called a second light emission control transistor.

[0066] The first electrode, for example, source s, of the first light-emitting control transistor M6 is coupled to the first power supply voltage input terminal to receive the first power supply voltage ELVDD provided by the first power supply voltage input terminal. The second electrode, for example, drain d, of the first light-emitting control transistor M6 is coupled to the first electrode, for example, source s, of the driving transistor M4. The first electrode, for example, source s, of the second light-emitting control transistor M5 is coupled to the second electrode, for example, drain d, of the driving transistor M4. The second electrode, for example, drain d, of the second light-emitting transistor M5 is coupled to the anode of the light-emitting device L, for example, an OLED.

[0067] It should be noted that the first electrode of the first light-emitting control transistor M6 may be a source electrode s, and the second electrode may be a drain electrode d. Alternatively, the first electrode of the first light-emitting control transistor M6 may be a drain electrode d, and the second electrode may be a source electrode s. For the convenience of explanation, the embodiments of the present application are all illustrated by taking the first electrode of the first light-emitting control transistor M6 as a source electrode s, and the second electrode as a drain electrode d as an example. Similarly, the first electrode of the second light-emitting control transistor M5 may be a source electrode s, and the second electrode may be a drain electrode d. Alternatively, the first electrode of the second light-emitting control transistor M5 may be a drain electrode d, and the second electrode may be a source electrode s. For the convenience of explanation, the embodiments of the present application are all illustrated by taking the first electrode of the second light-emitting control transistor M5 as a source electrode s, and the second electrode as a drain electrode d as an example. Similarly, the first electrode of the second reset transistor M7 may be a source electrode s, and the second electrode may be a drain electrode d. Alternatively, the first electrode of the second reset transistor M7 may be a drain electrode d, and the second electrode may be a source electrode s. For the convenience of explanation, the embodiments of the present application are all illustrated by taking the first electrode of the second reset transistor M7 as a source electrode s, and the second electrode as a drain electrode d as an example.

[0068] In addition, the display screen 10 also includes a substrate for carrying the above-mentioned pixel circuit 201. In some embodiments of the present application, the substrate can be made of a flexible material. The flexible material can be flexible glass, or polyimide (PI). Alternatively, in other embodiments of the present application, the substrate material can be a stretchable material. The deformation of the stretchable material can be greater than or equal to 5%. For example, the stretchable material can be polydimethylsiloxane (PDMS). In this case, the display screen 10 can be a flexible display screen that can be stretched and bent. The electronic device 01 with the flexible display screen can be a folding mobile phone or a folding tablet.

[0069] Alternatively, the substrate may also be made of a relatively hard material, such as hard glass, sapphire, etc. In this case, the display screen 10 is a hard display screen.

[0070] based on Figure 2a The structure of the pixel circuit 201 shown in FIG. 201 and the working process of the pixel circuit 201 include: Figure 3 There are three stages shown, the first stage ①, the second stage ② and the third stage ③. Figure 2b , Figure 2c as well as Figure 2d For the convenience of explanation, the transistors that are cut off are distinguished by adding an "×" mark.

[0071] In the first stage ①, under the control of the selection signal N-1, such as Figure 2bAs shown, the first reset transistor M1 and the second reset transistor M7 are turned on. The initial voltage Vint is transmitted to the gate of the driving transistor M4 through the first reset transistor M1, thereby resetting the gate of the driving transistor M4. In addition, the initial voltage Vint is transmitted to the anode a of the OLED through the second reset transistor M7, resetting the anode a of the OLED. At this time, the voltage Va of the anode a of the OLED and the voltage Vg4 of the gate g of the driving transistor M4 are Vint.

[0072] In this way, in the first stage ①, the voltage of the gate g of the driving transistor M4 and the anode a of the OLED can be reset to the initial voltage Vint, thereby preventing the voltage remaining on the gate g of the driving transistor M4 and the anode a of the OLED in the previous image frame from affecting the next image frame. Therefore, the first stage ① can be called a reset stage. As can be seen from the above, the reset stage is the stage in which the first reset transistor M1 is turned on.

[0073] In the second stage ②, under the control of the selection signal N, Figure 2c As shown, transistor M2 and transistor M3 are turned on. When transistor M3 is turned on, the gate g of the driving transistor M4 is coupled to the drain d, and the driving transistor M4 is in a diode-on state. At this time, the data voltage Vdata is written to the source s of the driving transistor M4 through the turned-on transistor M2. Therefore, the second stage ② above can be called the data voltage Vdata writing stage of the pixel circuit. As can be seen from the above, the data voltage writing stage is the stage in which the data voltage Vdata is applied to the first electrode of the driving transistor M4, such as the source s.

[0074] At this time, the source voltage Vs4 of the driving transistor M4 is Vdata. According to the conduction characteristics of the transistor, the drain voltage Vd4 of the driving transistor M4 is Vdata-|Vth_M4|. Since the transistor M3 is turned on, the gate voltage Vg4 of the driving transistor M4 is the same as the drain voltage Vd4.

[0075] Therefore, the gate voltage Vg4 of the driving transistor M4 is Vdata-|Vth_M4|. In this way, the gate voltage Vg4 of the driving transistor M4 is related to the threshold voltage Vth_M4 of the driving transistor M4, thereby achieving compensation for the threshold voltage Vth_M4.

[0076] In the third stage ③, under the control of the light emitting control signal EM, the second light emitting control transistor M5 and the first light emitting control transistor M6 are turned on, and the current path between the first power supply voltage ELVDD and the second power supply voltage ELVSS is turned on. The driving current I generated by the driving transistor M4 is transmitted to the OLED through the above current path to drive the OLED to emit light. As can be seen from the above, the light emitting stage is the stage of driving the light emitting device L to emit light.

[0077] The source-gate voltage of the driving transistor M4 is Vsg4=Vs4-Vg4=ELVDD-(Vdata-|Vth_M4|). In addition, the current driving the OLED to emit light satisfies the following formula:

[0078] Isd=1 / 2×μ×Cgi×W / L×(Vsg4-|Vth_M4|) 2 (1)

[0079] According to the current formula of OLED, the driving current flowing through OLED is Isd = 1 / 2 × μ × Cgi × W / L × (ELVDD-Vdata+|Vth_M4|-|Vth_M4|) 2 =1 / 2×μ×Cgi×W / L×(ELVDD-Vdata) 2 .

[0080] Wherein, μ is the carrier mobility of the driving transistor M4; Cgi is the capacitance between the gate g and the channel of the driving transistor M4; W / L is the width-to-length ratio of the driving transistor M4, and Vth_M4 is the threshold voltage of the driving transistor M4.

[0081] Since the current Isd is independent of the threshold voltage Vth_M4 of the driving transistor M4, the difference in the threshold voltage of the driving transistors of each sub-pixel can be solved, resulting in uneven brightness. Therefore, after the threshold voltage compensation in the second stage ②, the effect of achieving uniform brightness of the display screen 10 can be reflected in the third stage ③. Since the OLED emits light in the third stage ③, the third stage ③ can be called the light-emitting stage.

[0082] Based on the structure of the above-mentioned pixel circuit, the sub-pixels 20 in the display screen 10 are scanned and emitted light row by row. Therefore, when displaying a frame of image, after the first row of sub-pixels 20 emit light, it is necessary to maintain the emitting state until the last row of sub-pixels 20 emit light in order to display a frame of image.

[0083] In this case, when the display screen 10 is used to display dynamic images, a refresh rate of 60 Hz may be used. Figure 4As shown, the time T2 of an image frame is 1 / 60s. In order to reduce the power consumption of the electronic device 01, when the display screen 10 of the electronic device 01 is used to display a static image, such as a standby image, a refresh rate less than 60Hz, such as 30Hz, can be used. Figure 4 As shown, the time T1 of one image frame is 1 / 30 s, wherein T1>T2.

[0084] In this way, when the display screen 10 adopts a lower refresh rate, the time of an image frame increases. Therefore, for the same row of sub-pixels 20, when the refresh rate is 30 Hz, the time △t1 for the sub-pixels 20 in the row to keep emitting light is, that is, Figure 3 The duration of the third stage ③ is about 1 / 30s. When the refresh rate is 60Hz, the duration △t2 of the sub-pixels 20 in this row remaining lit is about 1 / 60s. △t1 is greater than △t2.

[0085] Based on this, when a sub-pixel 20 emits light, the amount Q of the first capacitor Cst in the pixel circuit 201 of the sub-pixel 20 satisfies the following formula:

[0086] Q=C×△V=I off_M1 ×△t (2)

[0087] Wherein, in formula (2), C is the capacitance value of the first capacitor Cst; I off_M1 is the leakage current of the first reset transistor M1 in the third stage ③, ie, the above-mentioned light-emitting stage; △V is the voltage drop of the gate voltage Vg4 of the driving transistor M4 in the third stage ③; △t is the duration for which the sub-pixel keeps emitting light.

[0088] As can be seen from the above, Δt1 is greater than Δt2, so the capacitance C of the first capacitor Cst and the leakage current I of the first reset transistor M1 are off_M1 Under certain conditions, it can be seen from the above formula (2) that when the display screen 10 displays at 30 Hz, the voltage drop △V1 of the gate voltage Vg4 of the driving transistor M4 is greater than the voltage drop △V2 of the gate voltage Vg4 of the driving transistor M4 when the display screen 10 displays at 60 Hz.

[0089] Based on this, Figure 5 As shown, the gate-source voltage Vsg4 of the driving transistor M4 is Vs4-Vg4. Figure 2a It can be seen that Vs = ELVDD. Therefore, when Vs4 remains unchanged, since ΔV1>ΔV2, when the display screen 10 is displayed at 30 Hz, the gate-source voltage Vsg4 of the driving transistor M4 is _ 1, greater than the gate-source voltage Vsg4 of the driving transistor M4 when the display screen 10 is displayed at 60Hz _2, namely Vsg4 _ 1>Vsg4 _ 2.

[0090] In this case, it can be seen from formula (1) that the current Isd driving the OLED to emit light is proportional to the square of the gate-source voltage Vsg4 of the driving transistor M4. _ 1>Vsg4 _ 2, so when the display screen 10 uses 30Hz for display, the current Isd1 that drives the OLED to emit light is greater than the current Isd2 that drives the OLED to emit light when the display screen 10 uses 60Hz for display, that is, Isd1>Isd2. In this way, when the display screen 10 switches from a higher refresh rate of 60Hz to a lower refresh rate of 30Hz for display, the current flowing through the OLED in the sub-pixel 20 will increase. At this time, when the refresh frequency alternates, the brightness of the OLED will suddenly change, and the human eye will keenly capture the sudden change in brightness, resulting in the phenomenon of screen flicker.

[0091] Based on the reasons why the display screen 10 appears flickering, the embodiment of the present application provides a method for reducing the probability of the screen flickering phenomenon. It can be seen from formula (2) that when the display screen 10 displays at a low refresh rate of 30Hz, the time △t for the sub-pixel 20 to remain luminous increases. In this case, in order to keep the value on the left side of formula (2) unchanged, the leakage current I of the first reset transistor M1 can be reduced. off_M1 .

[0092] In this way, when the display screen 10 displays at a low refresh rate of 30 Hz, the voltage drop △V1 of the gate voltage Vg4 of the driving transistor M4 in the third stage ③ can be approximately equal to the voltage drop △V2 of the gate voltage Vg4 of the driving transistor M4 when the display screen 10 displays at 60 Hz.

[0093] Based on this, Figure 5 It can be seen that when the values ​​of △V1 and △V2 are approximately equal, when the display screen 10 is displayed at 30 Hz, the gate-source voltage Vsg4 of the driving transistor M4 is _ 1, when the display screen 10 is displayed at 60Hz, the gate-source voltage Vsg4 of the driving transistor M4 _ 2 are approximately equal.

[0094] Furthermore, from formula (1), it can be obtained that when the display screen 10 is displayed at 30 Hz, the current Isd1 driving the OLED to emit light is approximately equal to the current Isd2 driving the OLED to emit light when the display screen 10 is displayed at 60 Hz. Therefore, when the display screen 10 is switched from a higher refresh rate of 60 Hz to a lower refresh rate of 30 Hz, the current flowing through the OLED in the sub-pixel 20 remains substantially unchanged, thereby effectively reducing the probability of screen flicker.

[0095] In summary, in order to effectively solve the above screen flicker problem, it is necessary to reduce the leakage current I of the first reset transistor M1 in the pixel circuit 201. off_M1 Based on this, Figure 6 It can be seen from the IV curves of the transistors in the figure that the source-drain voltage Vsd of the transistors at each curve is equal. For example, the source-drain voltage Vsd1 of the transistor corresponding to curve ① and the source-drain voltage Vsd2 of the transistor corresponding to curve ②.

[0096] Curve ① is above curve ②, so Vsd1>Vsd2. In this case, the drain current I of the transistor corresponding to curve ① is off_1 , which is greater than the leakage current I corresponding to curve ② off_2 Therefore, in order to achieve the desired effect during the light-emitting phase, Figure 3 In the third stage ③, the leakage current I of the first reset transistor M1 is reduced off_M1 , the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced in the third stage ③.

[0097] It should be noted that if Figure 2a As shown, the transistors connected to the driving transistor M4 include the first reset transistor M1 and the transistor M3. Therefore, the leakage current of the first reset transistor M1 and the leakage current of the transistor M3 will cause the gate voltage Vg4 of the driving transistor M4 to generate a voltage drop △V during the time when the sub-pixel 20 keeps emitting light. However, since the voltages of the drain d and the gate g of the driving transistor M4 can be made the same when the transistor M3 is turned on in the second stage ②, in the third stage ③, when the transistor M3 is turned off, the source-drain voltage Vsd3 of the transistor M3 is small, so the leakage current generated is also small, and the influence on the gate voltage Vg4 of the driving transistor M4 is small.

[0098] However, it can be seen from the working process of the pixel circuit 201 that in the third stage ③, the source-drain voltage Vsd1 of the first reset transistor M1 is Vdata-|Vth_M4|-Vint. For example, the above Vint can be -4V. Therefore, the source-drain voltage Vsd1 of the first reset transistor M1 is relatively large, so the leakage current generated is also relatively large, which has a greater impact on the gate voltage Vg4 of the driving transistor M4. Therefore, the following embodiments are to reduce the source-drain voltage Vsd1 of the first reset transistor M1 to achieve the purpose of reducing the probability of screen flicker. Below, the structure of the display screen 10 that can reduce the source-drain voltage Vsd1 of the first reset transistor M1 is described.

[0099] It should be noted that the above embodiment is based on the pixel circuit 201. Figure 2a Taking the 7T1C structure as an example, the purpose of reducing screen flicker by reducing the source-drain voltage Vsd1 of the first reset transistor M1 is described. The present application does not limit the structure of the pixel circuit 201, as long as the pixel circuit 201 has the driving transistor M4 and the first reset transistor M1.

[0100] The display module provided in the embodiment of the present application also includes a non-display area 101, such as Figure 7a At least one driving group 30 and a display driving circuit 40 are shown. In some embodiments of the present application, the display driving circuit 40 may be a display driver integrated circuit (DDIC). The DDIC has a data voltage output terminal VO for outputting a data voltage Vdata. In this case, during the data voltage writing phase (e.g. Figure 3 In the second stage ②), the data voltage input terminal coupled to the first electrode, such as the source electrode s, of the driving transistor M4 is the data voltage output port VO of the DDIC.

[0101] DDIC passed Figure 1a The flexible printed circuit (FPC) shown is coupled to the AP, so that the DDIC can receive the display data output by the AP. The data voltage output port VO of the DDIC is coupled to the data line (DL) in the display area 100. Figure 2a The first electrode of the middle transistor M2 is coupled to each other, so that the data line Vdata output by DDIC can be transmitted to the pixel circuit 201 of each sub-pixel 20 through the above DL.

[0102] It should be noted that, in the embodiments of the present application, Figure 7cAs shown, one end of each data line DL is connected to the transistor M2 (eg, Figure 2a The other end of each data line DL can be connected to the data voltage output terminal VO (as shown in FIG. 1 ) of the DDIC (i.e., the display driving circuit 40) through a data selector (multiplexer, MUX) circuit. Figure 7a The MUX can select only part of the data lines DL to receive the data voltages Vdata output by the data voltage output terminals VO of the DDIC in a time period as required.

[0103] In some embodiments of the present application, when the size of the display screen 10 is large and the number of a row (horizontal direction X) is large, the number of data lines DL set in the display screen 10 will also increase. In this case, the electronic device 01 may include multiple MUXs and multiple DDICs. Figure 7d As shown, part of the data lines DL in the display screen 10 are coupled to a data voltage output terminal VO of a DDIC through a MUX. In addition, the driving group 30 includes M gating circuits 301. Each gating circuit 301 is coupled to the display driving circuit 40. The gating circuit 301 is used to receive the first initial voltage Vint1 and the second initial voltage Vint2 output by the display driving circuit 40. Wherein, |Vint2|>|Vint1|.

[0104] In some embodiments of the present application, Figure 7b The display driving circuit 40 has the first signal terminal O1 and the second signal terminal O2, wherein the first signal terminal O1 can output the first initial voltage terminal Vint1, and the second signal terminal O2 is used to output the second initial voltage Vint2.

[0105] In addition, if Figure 7b As shown, the Nth (for example, N=1) strobe circuit 301 is coupled to the second electrode, for example, the drain electrode d, of the first reset transistor M1 in the pixel circuit 201 of the Nth (for example, N=1) row of sub-pixels 20. The strobe circuit 301 is also used for resetting the pixel circuit 201 when the pixel circuit 201 is in the reset phase ( Figure 3 The first stage ①) and the data voltage writing stage ( Figure 3 In the second stage ②), the second initial voltage Vint2 is output to the second electrode, for example, the drain electrode d, of the first reset transistor M1.

[0106] Thus, during the reset phase ( Figure 3 In the first stage ①), when the first reset transistor M1 is turned on, the second initial voltage Vint2 can be transmitted to the gate of the driving transistor M4, thereby resetting the gate of the driving transistor M4.

[0107] Furthermore, in the case where the pixel circuit 201 includes the second reset transistor M7 and the OLED, when the second reset transistor M7 is turned on, the second initial voltage Vint2 may also be transmitted to the anode of the OLED, thereby resetting the anode of the OLED.

[0108] In addition, during the data voltage writing phase ( Figure 3 In the second stage ②), since the transistor M3 is turned on, the gate g voltage Vg4 of the driving transistor M4 and the source s voltage Vs1 of the first reset transistor M1 are Vdata-|Vth_M4|.

[0109] At this time, the source-drain voltage Vsd1_A of the first reset transistor M1 = Vdata-|Vth_M4|-Vint2. In some embodiments of the present application, Vint2 = -4 V. The source-drain voltage Vsd1_A of the first reset transistor M1 = Vdata-|Vth_M4|-(-4) = Vdata-|Vth_M4|+4.

[0110] In addition, the gating circuit 301 is also used to Figure 3 In the third stage ③), the first initial voltage Vint1 is output to the second electrode, for example, the drain electrode d, of the first reset transistor M1. Wherein, 1≤N≤M, and N is a positive integer.

[0111] In this way, during the light-emitting phase ( Figure 3 In the third stage ③), since the gating circuit 301 outputs the first initial voltage Vint1 to the second electrode, for example, the drain electrode d, of the first reset transistor M1, in this light-emitting stage, the source-drain voltage Vsd1_B of the first reset transistor M1 is Vdata-|Vth_M4|-Vint1. Since |Vint2|>|Vint1|, Vsd1_B<Vsd1_A.

[0112] In this case, the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced in the light-emitting stage, thereby reducing the leakage current I of the first reset transistor M1 in the light-emitting stage. off When a low refresh rate display is adopted, the probability of screen flickering caused by a large voltage drop of the gate voltage Vg4 of the driving transistor M4 during the light-emitting phase due to leakage current can be reduced.

[0113] In some embodiments of the present application, the value range of the first initial voltage Vint1 can be 0 to 2 V. When the first initial voltage Vint1 is less than 0 V, the difference between Vsd1_B and Vsd1_A is small during the light-emitting stage, so that the leakage current I of the first reset transistor M1 cannot be effectively reduced during the light-emitting stage. offIn addition, when the first initial voltage Vint1 is greater than 2V, the leakage current of the second reset transistor M7 flows to the OLED, thereby causing the OLED to emit light when the sub-pixel displays a black screen, resulting in light leakage.

[0114] Based on this, in some embodiments of the present application, the first initial voltage Vint1 may be 0V, 1V, or 2V.

[0115] On this basis, the above display module includes: Figure 8a The first driving group 30A and the second driving group 30B are shown. The first driving group 30A and the second driving group 30B are respectively on the left and right sides of the display area 100 of the display screen.

[0116] Based on this, Figure 8b As shown, the Nth (e.g., N=1) gating circuit 301 in the first driving group 30A and the Nth (e.g., N=1) gating circuit 301 in the second driving group 30B are both coupled to the second electrode, e.g., the drain d, of the first reset transistor M1 in the pixel circuit 201 of the Nth (e.g., N=1) row of sub-pixels 20.

[0117] In this case, when the resolution of the display screen 10 is high, the number of sub-pixels 20 in a row is large. If the above-mentioned driving group 30 is only set on the left side or the right side of a row of sub-pixels 20, then the signal received at the end of the row of sub-pixels 20 that is farther from the output end of the selection circuit 30 in the driving group 30 will be attenuated, thereby reducing the accuracy of the signal.

[0118] Therefore, by respectively arranging the first driving group 30A and the second driving group 30B on the left and right sides of the display area 100, a gating circuit 301 in the first driving group 30A and a gating circuit 301 in the second driving group 30B respectively provide the first initial voltage Vint1 and the second initial voltage Vint2 to the second electrode, for example, the drain d, of each first reset transistor M1 in the same row of sub-pixels 20 from the left and right sides, thereby effectively reducing the problem of signal attenuation.

[0119] In the following, the structure of the gating circuit 301 in the driving group 30 and the display screen 10 having the gating circuit 301 are described by way of different examples.

[0120] Example 1

[0121] In this example, Figure 9a As shown, the display screen 10 further includes M first initial voltage lines S1. Each gating circuit 301 includes a first gating transistor Ms1 and a second gating transistor Ms2. Figure 9bAs shown, the Nth (eg, N=1) first initial voltage line S1 is coupled to the second electrode, eg, drain d, of the first reset transistor M1 in the pixel circuit 201 of the Nth (eg, N=1) row of sub-pixels 20 .

[0122] It should be noted that the first electrode of the first selection transistor Ms1 can be a source s, and the second electrode can be a drain d. Alternatively, the first electrode of the first selection transistor Ms1 can be a drain d, and the second electrode can be a source s. For the convenience of explanation, the embodiments of the present application are all illustrated by taking the first electrode of the first selection transistor Ms1 as the source s, and the second electrode as the drain d as an example. Similarly, the first electrode of the second selection transistor Ms2 can be a source s, and the second electrode can be a drain d. Alternatively, the first electrode of the second selection transistor Ms2 can be a drain d, and the second electrode can be a source s. For the convenience of explanation, the embodiments of the present application are all illustrated by taking the first electrode of the second selection transistor Ms2 as the source s, and the second electrode as the drain d as an example.

[0123] In addition, the first electrode, for example, the source electrode s, of the first selection transistor Ms1 in the Nth (for example, N=1) selection circuit 301 is coupled to the display driving circuit 40. The display driving circuit 40 may have a first signal terminal O1 and a second signal terminal O2. The first electrode, for example, the source electrode s, of the first selection transistor Ms1 is coupled to the first signal terminal O1 of the display driving circuit 40 to receive the first initial voltage Vint1 outputted by the first signal terminal O1 of the display driving circuit 40.

[0124] The second electrode, for example, the drain electrode d, of the first selection transistor Ms1 is coupled to the Nth (for example, N=1) first initial voltage line S1. The gate electrode g of the first selection transistor Ms1 is used to receive the first selection signal E.

[0125] The first electrode, for example, source s, of the second selection transistor Ms2 in the Nth (for example, N=1) selection circuit 301 is coupled to the display driving circuit 40. The display driving circuit 40 may have a first signal terminal O1 and a second signal terminal O2. The first electrode, for example, source s, of the second selection transistor Ms2 is coupled to the second signal terminal O2 of the display driving circuit 40 to receive the second initial voltage Vint2 output by the second signal terminal O2 of the display driving circuit 40.

[0126] The second electrode, for example, drain electrode d, of the second selection transistor Ms2 is coupled to the Nth (for example, N=1) first initial voltage line S1. The gate electrode g of the first selection transistor Ms1 is used for the second selection signal XE. The second selection signal XE is the inverted signal of the first selection signal E.

[0127] In this case, combined Figure 3 , Fig.10The timing diagram shown in the figure is used to obtain Figure 2a ,as well as Figure 9b In the pixel circuit shown, the drain voltage Vd1 and the source-drain voltage Vsd1 of the first reset transistor M1 at various stages and the drain voltage Vd7 of the second reset transistor M7 at various stages are shown in FIG1 .

[0128] Table 1

[0129]

[0130] It can be seen from Table 1 that in the first stage ①, i.e., the reset stage, the first reset transistor M1 is turned on, and the voltage Vd1 of the drain of the first reset transistor M1 is equal to Vint=Vint2=-4V. At this time, under the influence of the resistance of the first reset transistor M1 itself, the voltage Vs1 of the source s of the first reset transistor M1 is less than -4V, for example, it can be -3.9V. At this time, the source-drain voltage Vsd1 of the first reset transistor M1 is equal to Vs1-Vd1=-3.9-(-4)=0.1V.

[0131] In addition, if Figure 9b As shown, the pixel circuit 201 further includes a second reset transistor M7. The gate g of the second reset transistor M7 is coupled to the gate of the first reset transistor M1, and both are used to receive the selection signal N-1. Figure 3 In the first stage ① shown in the figure, when the selection signal N-1 inputs a valid signal, the first reset transistor M1 and the second reset transistor M7 can both be turned on.

[0132] On this basis, the first electrode, for example, the source electrode s, of the second reset transistor M7 is coupled to the anode electrode a of the OLED. Furthermore, the second electrode, for example, the drain electrode d, of the second reset transistor M7 in the pixel circuit 201 of the Nth (for example, N=1)th row of sub-pixels 20 is coupled to the Nth (for example, N=1)th first initial voltage line S1.

[0133] In this way, in the above-mentioned first stage ①, the first reset transistor M1 and the second reset transistor M7 are turned on, and the first initial voltage line S1 transmits the second initial voltage Vint2 with a larger value to the gate g of the driving transistor M4 through the first reset transistor M1, and transmits the second initial voltage Vint2 to the anode a of the OLED through the second reset transistor M7. Thus, the gate g of the driving transistor M4 and the anode a of the OLED can be reset respectively through the first reset transistor M1 and the second reset transistor M7.

[0134] In the second stage ②, i.e., the data voltage writing stage, the first reset transistor M1 is turned off, and the voltage Vd1 of the drain of the first reset transistor M1 is Vint=Vint2=-4 V. At this time, it can be seen from the above that the transistor M3 in the pixel circuit 201 is turned on, so the source-drain voltage Vsd1 of the first reset transistor M1 is Vdata-|Vth_M4|-(-4).

[0135] In addition, in the third stage, i.e., the light emitting stage, the first reset transistor M1 is turned off. Figure 2a The scheme shown uses Figure 9b In the scheme shown, since the drain voltage Vd1 of the first reset transistor M1 and the drain voltage Vd7 of the second reset transistor M7 are: Vd1=Vd7=Vint1=1V, the source-drain voltage Vsd1 of the first reset transistor M1 is Vdata-|Vth_M4|-1<Vdata-|Vth_M4|-(-4).

[0136] Based on this, when the OLED emits light, the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced to reduce the leakage current I off _M1. In this way, when switching from a high refresh rate, such as 60Hz, to a low refresh rate, such as 30Hz, the gate voltage Vg4 of the driving transistor M4 can be reduced due to leakage current, which causes a large voltage drop in the light-emitting stage, so that the light-emitting brightness of the sub-pixel 20 is equivalent when the display is displayed at 30Hz and when the display is displayed at 60Hz. Therefore, when the refresh rate is alternating, the probability of a sudden increase in the display brightness can be reduced, so that the human eye cannot keenly capture the change in brightness, and the probability of screen flickering is reduced.

[0137] It should be noted that the above description is based on the example of Vint1 = 1V. As can be seen from the above, Vint1 can be selected within the range of 0V to 2V.

[0138] In addition, the above description is based on the example that the first reset transistor M1, the second reset transistor M7 and the driving transistor M4 are P-type metal oxide semiconductor field effect transistors (positive channel metal oxide semiconductor, PMOS) in the pixel circuit 201 of the sub-pixel 20. In this case, the first electrode of the transistor is the source s, and the second electrode is the drain d. And when the gate g of the transistor receives a low level, the transistor is in the on state. When the gate g of the transistor receives a high level, the transistor is in the off state.

[0139] In other embodiments of the present application, Fig.9cAs shown, in the pixel circuit 201, the first reset transistor M1, the second reset transistor M7 and the driving transistor M4 can be N-type metal oxide semiconductor field effect transistors (negative channel metal oxide semiconductor, NMOS). In this case, the first electrode of the above transistor is the drain d, the second electrode is the source s, and when the gate g of the above transistor receives a high level, the transistor is in a conducting state. When the gate g of the above transistor receives a low level, the transistor is in a cut-off state.

[0140] In this example, when the first reset transistor M1 and the second reset transistor M7 are N-type transistors, the above-mentioned first initial voltage Vint1 and the second initial voltage Vint2 can be set in the same way. For example, the source voltage Vs1 of the first reset transistor M1 and the source voltage Vs7 of the second reset transistor M7 can be Vint2=-4V in the first stage ① and the second stage ②. The source voltage Vs1 of the first reset transistor M1 and the source voltage Vs7 of the second reset transistor M7 can be Vint1=1V in the third stage ③.

[0141] In this example, for the convenience of description, the following description is made by taking the first reset transistor M1 , the second reset transistor M7 , and the driving transistor M4 as P-type.

[0142] In some embodiments of the present application, in order to output the first initial voltage Vint1 and the second initial voltage Vint2 to the drain electrode d of the first reset transistor M1 in the sub-pixel 20 row by row, the driving group 30 further includes: Fig.11 The illustrated embodiment includes M inverters 302 and M cascaded shift registers (SR).

[0143] The output terminal Op of the Nth (for example, N=1) SR is coupled to the input terminal of the Nth (for example, N=1) inverter 302 and the gate g of the first gating transistor Ms1 in the Nth (for example, N=1) gating circuit 301. The output terminal Op of the SR is used to output the first gating signal E.

[0144] The output terminal of the Nth inverter 302 is coupled to the gate g of the second selection transistor Ms2 in the Nth selection circuit 301. The output terminal of the inverter 302 is used to output the second selection signal XE.

[0145] In this case, when multiple SRs are cascaded in sequence, for example, Fig.11As shown, the signal output terminal (Output, referred to as Op) of the first-stage shift register, i.e., SR1, is coupled to the signal input terminal (Input, referred to as Ip) of the second-stage shift register, i.e., SR2. SR2 is adjacent to SR1. The signal output terminal Op of SR2 is coupled to the signal input terminal Ip of the third-stage shift register, i.e., SR3. SR3 is adjacent to SR2. In addition, the cascade method of the remaining SRs is the same as described above.

[0146] The signal input terminal Ip of SR1 is used to receive a start vertical frame signal (STV). In some embodiments of the present application, when STV is at a high level (High voltage), the start signal STV is a valid signal, and the SR1 starts to work. When STV is at a low level (low voltage), the start signal STV is an ineffective signal, and SR1 does not work.

[0147] Based on this, when the pixel circuit 201 is in the above-mentioned first stage ① and second stage ②, SR1 outputs an invalid signal, such as a high level. At this time, the first selection transistor Ms1 is turned off. In addition, after the above-mentioned high level is inverted by the inverter 302, the gate of the second selection transistor Ms2 in the first selection circuit 301 receives the effective second selection signal XE. The second selection transistor Ms2 is turned on.

[0148] The second initial voltage Vint2 outputted by the second signal terminal O2 of the display driving circuit 40 is transmitted to the drain d of the first reset transistor M1 of each sub-pixel 20 of the first row through the second selection transistor Ms2. Thus, as shown in Table 1, the source-drain voltage Vsd1 of the first reset transistor M1 can be 0.1V in the first stage ① and Vsd1=Vdata-|Vth_M4|-(-4) in the second stage ②.

[0149] When the pixel circuit 201 is in the third stage ③, SR1 outputs a valid signal, such as a low level. At this time, the first selection transistor Ms1 in the first selection circuit 301 is turned on. After the signal output by SR1 is inverted by the inverter 302, the second selection transistor Ms2 is turned off.

[0150] The first initial voltage Vint1 outputted by the first output terminal O1 of the display driving circuit 40 is transmitted to the drain d of the first reset transistor M1 of each sub-pixel in the first row through the first selection transistor Ms1. As shown in Table 1, the source-drain voltage Vsd1 of the first reset transistor M1 can be Vsd1=Vdata-|Vth_M4|-1 in the third stage ③.

[0151] In addition, when SR1 outputs a valid signal, the valid signal can also be transmitted to the signal input terminal Ip of SR2 cascaded with SR1. Therefore, by setting the circuit structure in SR2, after the first row of sub-pixels emit light, SR2 controls the second selection transistor Ms2 and the first selection transistor Ms1 in the second selection circuit 301 to turn on, so that the second row of sub-pixels 201 emit light. In this way, through the above-mentioned multiple cascaded SRs, multiple rows of sub-pixels 20 arranged in sequence can be scanned row by row, so that the sub-pixels 20 emit light row by row.

[0152] It should be noted that Fig.11 In the figure, only a plurality of inverters 302 and a plurality of cascaded SRs are schematically shown on the left side of the display area 100. As can be seen from the above, when the above-mentioned gating circuit 301 is also provided on the right side of the display area 100, in order to control the conduction and cutoff of the first gating transistor Ms1 and the second gating transistor Ms2 in the gating circuit 301, a plurality of inverters 302 and a plurality of cascaded SRs may also be provided on the right side of the display area 100, and the arrangement method is the same as described above, which will not be repeated here.

[0153] As can be seen from the above, the pixel circuit 201 includes the following Fig.11 In the case of the first light emitting control transistor M6 and the second light emitting control transistor M5 shown, the gate g of the first light emitting control transistor M6 and the second light emitting control transistor M5 are both used to receive the light emitting control signal EM, so that in the third stage ③, the first light emitting control transistor M6 and the second light emitting control transistor M5 can be turned on to make the current path between the first power supply voltage ELVDD and the second power supply voltage ELVSS conductive, so that the driving current provided by the driving transistor M4 can flow through the OLED to drive the OLED to emit light.

[0154] As can be seen from the above, the first selection transistor Ms1 in the selection circuit 301 also needs to be turned on in the third stage ③. Therefore, in order to simplify the structure of the driving circuit located in the non-display area 101, as shown in FIG. Fig.11 As shown, the output terminal Op of the SR is also coupled to the gates g of the first light emitting control transistor M6 and the second light emitting control transistor M5.

[0155] In this way, when the pixel circuit 201 is in the third stage ③, the output terminal Op of SR can not only provide the light-emitting control signal EM to the gates g of the first light-emitting control transistor M6 and the second light-emitting control transistor M5 to make the OLED emit light, but also provide the first selection signal E to the gate g of the first selection transistor Ms1 in the selection circuit 301, so that the first initial voltage Vint1 output by the first signal terminal O1 of the display driving circuit 40 is transmitted to the drain d of the first reset transistor M1 of each sub-pixel in the first row through the first selection transistor Ms1.

[0156] Example 2

[0157] In this example, Fig.12a As shown, the display screen 10 includes M first initial voltage lines S1 and M second initial voltage lines S2. The gating circuit 301 includes a first gating transistor Ms1 and a second gating transistor Ms2.

[0158] Among them, the connection method of the first selection transistor Ms1, the second selection transistor Ms2, and the first initial voltage line S1, and the coupling method of the first reset transistor M1 and the first initial voltage line S1 in the pixel circuit of each row of sub-pixels 20 are the same as those in Example 1 and are not repeated here.

[0159] It should be noted that, in order to provide the first selection signal E to the gate g of the first selection transistor Ms1 in the selection circuit 301, and to provide the second selection signal XE to the gate g of the second selection transistor Ms2, as in Example 1, M inverters 302 and M cascaded SRs may be provided in the non-display area. The connection method of the SR and the inverter 302 is the same as described above and will not be repeated here.

[0160] In addition, if Figure 12b As shown, the pixel circuit 201 further includes a second reset transistor M7. As in Example 1, the gate g of the second reset transistor M7 is coupled to the gate g of the first reset transistor M1. The first electrode of the second reset transistor M7, for example, the source s, is coupled to the anode a of the OLED.

[0161] The difference from Example 1 is that the second electrode of the second reset transistor M7 in the pixel circuit 201 of the Nth (eg N=1) row of sub-pixels 20 is coupled to the Nth (eg N=1) second initial voltage line S2 .

[0162] When the display driving circuit 40 has the first signal terminal O1 and the second signal terminal O2 , the second initial voltage line S2 is coupled to the second signal terminal O2 for receiving the second initial voltage Vint2 outputted by the second signal terminal O2 .

[0163] In this case, combined Figure 3 , Fig.13 The timing diagram shown in the figure is used to obtain Figure 2a ,as well as Figure 12b In the pixel circuit shown, the drain voltage Vd1 and the source-drain voltage Vsd1 of the first reset transistor M1 at various stages, and the drain voltage Vd7 of the second reset transistor M7 at various stages are shown in Table 2 .

[0164] Table 2

[0165]

[0166] As can be seen from Table 2, in the first stage ①, i.e., the reset stage, it can be seen from the above that the first-stage SR can control the first selection transistor Ms1 in a selection circuit 201 to be turned off and the second selection transistor Ms2 to be turned on, so that the second initial voltage Vint2 provided by the second signal terminal O2 of the display driving circuit 40 is transmitted to the second electrode, for example, the drain d, of the first reset transistor M1 through the first initial voltage line S1. The voltage at the drain of the first reset transistor M1 is Vd1=Vint=Vint2=-4V.

[0167] The first reset transistor M1 is turned on. Under the influence of its own resistance, the voltage Vs1 at the source s of the first reset transistor M1 is less than -4V, for example, -3.9V. At this time, the source-drain voltage Vsd1 of the first reset transistor M1 is Vs1-Vd1=-3.9-(-4)=0.1V.

[0168] In addition, the second initial voltage line S2 transmits the second initial voltage Vint2 provided by the second signal terminal O2 of the display driving circuit 40 to the second electrode, for example, the drain d, of the second reset transistor M7. The voltage Vd7 of the drain of the second reset transistor M7 is Vint=Vint2=-4V.

[0169] In the second stage ②, i.e., the data voltage writing stage, the first reset transistor M1 is turned off, and the voltage Vd1 of the drain of the first reset transistor M1 is Vint=Vint2=-4 V. At this time, it can be seen from the above that the transistor M3 in the pixel circuit 201 is turned on, so the source-drain voltage Vsd1 of the first reset transistor M1 is Vdata-|Vth_M4|-(-4).

[0170] In addition, the second reset transistor M7 is also in the cut-off state at this stage, so the voltage Vd7 of the drain of the second reset transistor M7 = Vint = Vint2 = -4V.

[0171] In the third stage, i.e., the light emitting stage, the first reset transistor M1 is turned off. Figure 2a The scheme shown uses Figure 12bIn the scheme shown, since the drain voltage Vd1 of the first reset transistor M1 is Vd1=Vint1=1V, the source-drain voltage Vsd1 of the first reset transistor M1 is Vdata-|Vth_M4|-1<Vdata-|Vth_M4|-(-4). Therefore, when the OLED emits light, the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced to reduce the leakage current I of the first reset transistor M1. off _M1.

[0172] In this way, when a low refresh rate, such as 30Hz display, is used, the probability of screen flickering caused by a large voltage drop in the gate voltage Vg4 of the driving transistor M4 during the light-emitting stage due to leakage current can be reduced, so that the light-emitting brightness of the sub-pixel 20 when using 30Hz display is equivalent to that when using 60Hz display.

[0173] In addition, since the second electrode, for example, drain d, of the second reset transistor M7 is coupled to the second initial voltage line S2, the voltage Vd7 of the drain of the second reset transistor M7 = Vint = Vint2 = -4 V. In this case, relative to Example 1, in this example, in the third stage ③, the voltage Vd7 of the drain d of the second reset transistor M7 = -4 V, which is less than 1 V in Example 1.

[0174] In this way, the probability of light leakage due to the drain d of the second reset transistor M7 rising in the third stage ③ causing the leakage current of the second reset transistor M7 to flow to the OLED, thereby causing the OLED to emit light when the sub-pixel displays a black screen, can be reduced.

[0175] It should be noted that, in this example, the above description is made by taking the pixel circuit 201 of the sub-pixel 20 as an example in which the first reset transistor M1 , the second reset transistor M7 and the driving transistor M4 are P-type transistors.

[0176] In other embodiments of the present application, Fig.12c As shown, in the pixel circuit 201, the first reset transistor M1, the second reset transistor M7 and the driving transistor M4 are N-type transistors. In this case, when the first reset transistor M1 and the second reset transistor M7 are N-type transistors, the above-mentioned first initial voltage Vint1 and the second initial voltage Vint2 can be set in the same way. For example, the source voltage Vs1 of the first reset transistor M1 can be Vint2=-4V in the first stage ① and the second stage ②, and the source voltage Vs1 of the first reset transistor M1 can be Vint1=1V in the third stage ③. The source voltage Vs7 of the second reset transistor M7 is Vint2=-4V in the first stage ①, the second stage ② and the third stage ③.

[0177] Some embodiments of the present application also provide a method for controlling a display module. The display module includes a display screen 10 and a display module 11. Fig.14 The display driving circuit 40 is shown. The display screen 10 includes M rows of sub-pixels 20 arranged in a matrix form. Wherein, M≥2, M is a positive integer.

[0178] The pixel circuit 201 of each sub-pixel 20 includes a driving transistor M4, a first reset transistor M1, a first capacitor Cst, and a light emitting device L. The first electrode, for example, the source (source, s) of the first reset transistor M1 is coupled to the gate (gate, g) of the driving transistor M4 and the first end of the first capacitor Cst. The second end of the first capacitor Cst is coupled to the first power supply voltage input end (for outputting the first power supply voltage ELVDD).

[0179] As can be seen from the above, the first electrode of the driving transistor M4, such as the source electrode s, is coupled to the first power supply voltage input terminal in the above-mentioned light-emitting stage, so as to receive the first power supply voltage ELVDD output by the first power supply voltage input terminal. The first electrode of the driving transistor M4, such as the source electrode s, is coupled to the data voltage output port VO of the DDIC in the data voltage writing stage, and is used to receive the data voltage Vdata output by the data voltage output port VO. The second electrode of the above-mentioned driving transistor M4, such as the drain electrode (d for short), is coupled to the light-emitting device L.

[0180] Based on this, the control method of the above display module is as follows Fig.15 The shown one includes S101 and S102.

[0181] S101, control M rows of sub-pixels 20 to display row by row at a first refresh rate, such as 60 Hz. When the Nth row of sub-pixels 20 in the M rows of sub-pixels 20 is controlled to display, in the reset phase ( Figure 3 The first stage ①), data voltage writing stage ( Figure 3 The second stage ②) and the light-emitting stage ( Figure 3 The third stage ③) in Fig.14 The first signal terminal O1 shown outputs the second initial voltage Vint2 to the second electrode, for example, the drain electrode d, of the first reset transistor M1 in the pixel circuit 201 of the Nth row of sub-pixels 20. For example, the second initial voltage Vint2 may be -4V.

[0182] S102, control M rows of sub-pixels 20 to display row by row at a second refresh rate, for example, 30 Hz. The second refresh rate is lower than the first refresh rate. When the Nth row of sub-pixels 20 in the M rows of sub-pixels 20 is controlled to display, in the reset phase ( Figure 3 The first stage ①), data voltage writing stage ( Figure 3The second stage ②) and the light-emitting stage ( Figure 3 The third stage ③) in Fig.14 The first signal terminal O1 shown outputs the first initial voltage Vint1 to the second electrode, for example, the drain electrode d, of the first reset transistor M2 in the pixel circuit 20 of the Nth row of sub-pixels 20. Wherein, |Vint2|>|Vint1|.

[0183] For example, in order to enable the first initial voltage Vint1 to effectively reset the gate g of the driving transistor M4 in the reset phase to clear the residual voltage of the previous image frame, the first initial voltage Vint1 can be selected to be a negative voltage, such as -3V or -2V.

[0184] Based on this, when a high refresh rate, such as 60 Hz, is converted to a low refresh rate, such as 30 Hz, a first initial voltage Vint1 having an absolute value greater than the second initial voltage Vint2 is provided to the second electrode of the first reset transistor M2, so that the source-drain voltage Vsd1 of the first reset transistor M1 can be reduced to reduce the leakage current I of the first reset transistor M1. off _M1. In this way, the large voltage drop of the gate voltage Vg4 of the driving transistor M4 caused by the leakage current in the light-emitting stage can be reduced, so that the light-emitting brightness of the sub-pixel 20 when the display is 30Hz is equivalent to that when the display is 60Hz. Therefore, when the refresh rate is alternating, the probability of a sudden increase in the display brightness is reduced, so that the human eye cannot keenly capture the change in brightness, and the probability of screen flicker is reduced.

[0185] In this case, in order to implement the above S101 and S102, some embodiments of the present application provide a display driving circuit. The display driving circuit is coupled to the display screen 10 and can be used to perform the above S101 and S102. The above display driving circuit has the same technical effect as the control method of the display module provided in the above embodiment, and will not be repeated here.

[0186] Alternatively, in some other embodiments of the present application, the electronic device may include a display screen 10 and a display driving circuit 40 coupled to the display screen 10 .

[0187] The display driving circuit 40 is used to execute the step of controlling M rows of sub-pixels 20 to display row by row at a first refresh rate, such as 60 Hz, in S101 .

[0188] The display driving circuit 40 is used to execute S101 when controlling the Nth row of sub-pixels 20 in the M rows of sub-pixels 20 to display. Figure 3 The first stage ①), data voltage writing stage ( Figure 3 The second stage ②) and the light-emitting stage ( Figure 3The third stage ③) in Fig.14 The first signal terminal O1 shown outputs the second initial voltage Vint2 to the second electrode, for example, the drain electrode d, of the first reset transistor M1 in the pixel circuit 201 of the Nth row of sub-pixels 20. For example, the second initial voltage Vint2 may be -4V.

[0189] In addition, the display driving circuit 40 is further configured to execute the step of controlling M rows of sub-pixels 20 to display row by row at a second refresh rate, such as 30 Hz, in S102 .

[0190] The display driving circuit 40 is also used to execute S102 when controlling the Nth row of sub-pixels 20 in the M rows of sub-pixels 20 to display. Figure 3 The first stage ①), data voltage writing stage ( Figure 3 The second stage ②) and the light-emitting stage ( Figure 3 The third stage ③) in Fig.14 The first signal terminal O1 shown in the figure outputs the first initial voltage Vint1 to the second electrode, for example, the drain electrode d, of the first reset transistor M2 in the pixel circuit 20 of the Nth row of sub-pixels 20. The above electronic device has the same technical effect as the control method of the display module provided in the above embodiment, which will not be repeated here.

[0191] In addition, an embodiment of the present application provides a computer-readable medium storing a computer program. When the computer program is executed by a processor, the method described above is implemented.

[0192] The computer readable medium may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a communication bus. The memory may also be integrated with the processor.

[0193] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer execution instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.

[0194] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display module, characterized in that: It includes a display screen, a display driving circuit and at least one driving group; The display screen includes sub-pixels arranged in a matrix form in M ​​rows; the pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device; wherein M≥2, and M is a positive integer; The first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input terminal; the first electrode of the driving transistor is coupled to the first power supply voltage input terminal and the data voltage output port of the display driving circuit, and the second electrode of the driving transistor is coupled to the light-emitting device; wherein the first electrode of the first reset transistor is the source and the second electrode is the drain, or the first electrode of the first reset transistor is the drain and the second electrode is the source; the first electrode of the driving transistor is the source and the second electrode is the drain, or the first electrode of the driving transistor is the drain and the second electrode is the source; the first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage; Each of the driving groups includes M gating circuits; each of the gating circuits is coupled to the display driving circuit and is used to receive a first initial voltage Vint1 and a second initial voltage Vint2 output by the display driving circuit; wherein |Vint2|>|Vint1|; The Nth gating circuit is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; the gating circuit is further used to output the second initial voltage Vint2 to the second electrode of the first reset transistor when the pixel circuit is in the reset stage and the data voltage writing stage, and is used to output the first initial voltage Vint1 to the second electrode of the first reset transistor when the pixel circuit is in the light emitting stage; wherein 1≤N≤M, and N is a positive integer; The reset phase is a phase in which the first reset transistor is turned on; the data voltage writing phase is a phase in which the data voltage is applied to the first electrode of the driving transistor; the light emitting phase is a phase in which the light emitting device emits light; The display driving circuit has at least one second signal terminal; the second signal terminal outputs the second initial voltage Vint2; the display screen also includes M second initial voltage lines; The pixel circuit also includes a second reset transistor; the gate of the second reset transistor is coupled to the gate of the first reset transistor; the first electrode of the second reset transistor is coupled to the light-emitting device; the second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line; the second initial voltage line is also coupled to the second signal end of the display driving circuit; the first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source.

2. The display module according to claim 1, characterized in that: The display screen further includes M first initial voltage lines; wherein the Nth first initial voltage line is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; Each of the gating circuits includes a first gating transistor and a second gating transistor; A first electrode of the first gating transistor in the Nth gating circuit is coupled to the display driving circuit, a second electrode of the first gating transistor is coupled to the Nth first initial voltage line, and a gate of the first gating transistor is used to receive a first gating signal; A first electrode of the second selection transistor in the Nth selection circuit is coupled to the display driving circuit, a second electrode of the second selection transistor is coupled to the Nth first initial voltage line, and a gate of the second selection transistor is used to receive a second selection signal, which is an inverted signal of the first selection signal; The first electrode of the first selection transistor is the source and the second electrode is the drain, or the first electrode of the first selection transistor is the drain and the second electrode is the source; the first electrode of the second selection transistor is the source and the second electrode is the drain, or the first electrode of the second selection transistor is the drain and the second electrode is the source.

3. The display module according to claim 2, characterized in that: The display driving circuit has at least one first signal terminal; the first signal terminal outputs the first initial voltage Vint1; the first electrode of the first gating transistor is coupled to the first signal terminal; the first electrode of the second gating transistor is coupled to the second signal terminal; The display screen includes an effective display area and a non-display area located around the effective display area, and the effective display area includes a plurality of sub-pixels.

4. The display module according to claim 2, characterized in that: The driving group further includes M inverters and M cascaded shift registers; The output end of the Nth shift register is coupled to the input end of the Nth inverter and the gate of the first gating transistor in the Nth gating circuit; the output end of the shift register is used to output the first gating signal; The output end of the Nth inverter is coupled to the gate of the second gating transistor in the Nth gating circuit; the output end of the inverter is used to output the second gating signal.

5. The display module according to claim 4, characterized in that: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor; The first electrode of the first light emitting control transistor is coupled to the first power supply voltage input terminal; the second electrode of the first light emitting control transistor is coupled to the first electrode of the driving transistor; The first electrode of the second light emitting control transistor is coupled to the second electrode of the driving transistor; The second electrode of the second light emitting control transistor is coupled to the light emitting device; The light emitting device is also coupled to a second power supply voltage input terminal, and the second power supply voltage input terminal is used to input a second power supply voltage; The output end of the shift register is also coupled to the gates of the first light emission control transistor and the second light emission control transistor; The first electrode of the first light emission control transistor is a source electrode and the second electrode is a drain electrode, or the first electrode of the first light emission control transistor is a drain electrode and the second electrode is a source electrode; The first electrode of the second light emission control transistor is a source and the second electrode is a drain, or the first electrode of the second light emission control transistor is a drain and the second electrode is a source.

6. The display module according to claim 1, characterized in that: The display module includes a first driving group and a second driving group; the first driving group and the second driving group are respectively located on both sides of the display area of ​​the display screen; The Nth gating circuit in the first driving group and the Nth gating circuit in the second driving group are both coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels.

7. The display module according to claim 1, characterized in that: The display module includes a base substrate; the pixel circuit, the display driving circuit and the driving group are arranged on the base substrate; the material constituting the base substrate includes a flexible material or a stretchable material.

8. An electronic device, characterized in that: Comprising a display module as described in any one of claims 1-7.

9. A method for controlling a display module, characterized in that: The display module includes a display screen, a display driving circuit and at least one driving group; the display screen includes sub-pixels arranged in a matrix of M rows; the pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device; wherein M≥2, and M is a positive integer; the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input terminal; the first electrode of the driving transistor is coupled to the first power supply voltage input terminal and the data voltage output port of the display driving circuit; the second electrode of the driving transistor is coupled to the light-emitting device; wherein the first electrode of the first reset transistor is a source electrode and the second electrode is a drain electrode, or the first electrode of the first reset transistor is a drain electrode and the second electrode is a source electrode; the first electrode of the driving transistor is a source electrode and the second electrode is a drain electrode, or the first electrode of the driving transistor is a drain electrode and the second electrode is a source electrode; the first power supply voltage input terminal is used to input a first power supply voltage, and the data voltage output port is used to output a data voltage; each of the driving groups includes M gating circuits; each of the gating circuits is coupled to the display driving circuit to receive a first initial voltage Vint1 and a second initial voltage Vin output by the display driving circuit t2; wherein, |Vint2|>|Vint1|; the Nth gating circuit is coupled to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; the gating circuit is also used to output the second initial voltage Vint2 to the second electrode of the first reset transistor when the pixel circuit is in the reset stage and the data voltage writing stage, and is used to output the first initial voltage Vint1 to the second electrode of the first reset transistor when the pixel circuit is in the light-emitting stage; wherein 1≤N≤M, N is a positive integer; the display driving circuit has at least one second signal terminal; the second signal terminal outputs the second initial voltage Vint2; the display screen further includes M second initial voltage lines; the pixel circuit further includes a second reset transistor; the gate of the second reset transistor is coupled to the gate of the first reset transistor; the first electrode of the second reset transistor is coupled to the light-emitting device; the second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line; the second initial voltage line is also coupled to the second signal end of the display driving circuit; the first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source; The control method of the display module includes: Control M rows of sub-pixels to display row by row; When the Nth row of sub-pixels among the M rows of sub-pixels are controlled to display, the Nth gating circuit receives the first initial voltage Vint1 and the second initial voltage Vint2 output by the display driving circuit; The Nth gating circuit outputs the second initial voltage Vint2 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; the first reset transistor is turned on, and the second initial voltage Vint2 is transmitted to the gate of the driving transistor; the pixel circuit of the Nth row of sub-pixels is in a reset stage; the reset stage is a stage in which the first reset transistor is turned on; The data voltage is written to the first electrode of the driving transistor, and the first reset transistor is controlled to be turned off, and the pixel circuit of the Nth row of sub-pixels is in the data voltage writing stage; the Nth gating circuit outputs the second initial voltage Vint2 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; the data voltage writing stage is the stage in which the data voltage is applied to the first electrode of the driving transistor; The light-emitting device in the pixel circuit of the Nth row of sub-pixels is controlled to emit light, the pixel circuit of the Nth row of sub-pixels is in the light-emitting stage, and the Nth selection circuit outputs the first initial voltage Vint1 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; the light-emitting stage is the stage in which the light-emitting device emits light.

10. The control method of the display module according to claim 9, characterized in that: The value range of the first initial voltage Vint1 is 0-2V.

11. A method for controlling a display module, characterized in that: The display module includes a display screen and a display driving circuit; the display screen includes sub-pixels arranged in a matrix of M rows; the pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device; wherein M≥2, and M is a positive integer; the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input terminal; the first electrode of the driving transistor is coupled to the first power supply voltage input terminal and the data voltage output port of the display driving circuit; the second electrode of the driving transistor is coupled to the light-emitting device; wherein the first electrode of the first reset transistor is the source and the second electrode is the drain, or the first electrode of the first reset transistor is the drain and the second electrode is the source; the first electrode of the driving transistor is the source and the second electrode is the drain, or the first electrode of the driving transistor is the drain and the second electrode is the source The first pole is the drain and the second pole is the source; the first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage; the display driving circuit has at least one second signal terminal; the second signal terminal outputs a second initial voltage Vint2; the display screen also includes M second initial voltage lines; the pixel circuit also includes a second reset transistor; the gate of the second reset transistor is coupled to the gate of the first reset transistor; the first pole of the second reset transistor is coupled to the light-emitting device; the second pole of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line; the second initial voltage line is also coupled to the second signal terminal of the display driving circuit; the first pole of the second reset transistor is the source and the second pole is the drain, or the first pole of the second reset transistor is the drain and the second pole is the source; The method comprises: Controlling the M rows of sub-pixels to display row by row at a first refresh rate; When controlling the Nth row of sub-pixels in the M rows of sub-pixels to display, in the reset phase, the data voltage writing phase and the light emitting phase, outputting the second initial voltage Vint2 to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; Controlling the M rows of sub-pixels to display row by row at a second refresh rate, wherein the second refresh rate is less than the first refresh rate; When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset phase, the data voltage writing phase and the light emitting phase, the first initial voltage Vint1 is output to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; wherein |Vint2|>|Vint1|; The reset phase is a phase in which the first reset transistor is turned on; the data voltage writing phase is a phase in which the data voltage is applied to the first electrode of the driving transistor; and the light emitting phase is a phase in which the light emitting device emits light.

12. A display driving circuit, characterized in that: The display screen includes sub-pixels arranged in a matrix form of M rows; the pixel circuit of each sub-pixel includes a driving transistor, a first reset transistor, a first capacitor and a light-emitting device; wherein M≥2, and M is a positive integer; the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input end; the first electrode of the driving transistor is coupled to the first power supply voltage input end in the light-emitting stage, and is coupled to the data voltage output port of the display driving circuit in the data voltage writing stage; the second electrode of the driving transistor is coupled to the light-emitting device; wherein the first electrode of the first reset transistor is a source electrode and the second electrode is a drain electrode, or the first electrode of the first reset transistor is a drain electrode and the second electrode is a source electrode; the first electrode of the driving transistor is a source electrode and the second electrode is a drain electrode, or the first electrode of the driving transistor is a drain electrode. The first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage; the display driving circuit has at least one second signal terminal; the second signal terminal outputs a second initial voltage Vint2; the display screen also includes M second initial voltage lines; the pixel circuit also includes a second reset transistor; the gate of the second reset transistor is coupled to the gate of the first reset transistor; the first electrode of the second reset transistor is coupled to the light-emitting device; the second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line; the second initial voltage line is also coupled to the second signal terminal of the display driving circuit; the first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source; The display driving circuit is used for: Controlling the M rows of sub-pixels to display row by row at a first refresh rate; When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset phase, the data voltage writing phase and the light emitting phase, a second initial voltage Vint2 is output to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; Controlling the M rows of sub-pixels to display row by row at a second refresh rate; wherein the second refresh rate is less than the first refresh rate; When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset phase, the data voltage writing phase and the light emitting phase, the first initial voltage Vint1 is output to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; wherein |Vint2|>|Vint1|; The reset phase is a phase in which the first reset transistor is turned on; the data voltage writing phase is a phase in which the data voltage is applied to the first electrode of the driving transistor; and the light emitting phase is a phase in which the light emitting device emits light.

13. An electronic device, characterized in that: The invention comprises a display screen and a display driving circuit; the display screen comprises sub-pixels arranged in a matrix of M rows; the pixel circuit of each sub-pixel comprises a driving transistor, a first reset transistor, a first capacitor and a light-emitting device; wherein M≥2, and M is a positive integer; the first electrode of the first reset transistor is coupled to the gate of the driving transistor and the first end of the first capacitor; the second end of the first capacitor is coupled to the first power supply voltage input end; the first electrode of the driving transistor is coupled to the first power supply voltage input end in the light-emitting stage, and is coupled to the data voltage output port of the display driving circuit in the data voltage writing stage; the second electrode of the driving transistor is coupled to the light-emitting device; wherein the first electrode of the first reset transistor is the source and the second electrode is the drain, or the first electrode of the first reset transistor is the drain and the second electrode is the source; the first electrode of the driving transistor is the source and the second electrode is the drain, or the driving transistor The first electrode of the body tube is the drain and the second electrode is the source; the first power supply voltage input terminal is used to input the first power supply voltage, and the data voltage output port is used to output the data voltage; the display driving circuit has at least one second signal terminal; the second signal terminal outputs the second initial voltage Vint2; the display screen also includes M second initial voltage lines; the pixel circuit also includes a second reset transistor; the gate of the second reset transistor is coupled to the gate of the first reset transistor; the first electrode of the second reset transistor is coupled to the light-emitting device; the second electrode of the second reset transistor in the pixel circuit of the Nth row of sub-pixels is coupled to the Nth second initial voltage line; the second initial voltage line is also coupled to the second signal terminal of the display driving circuit; the first electrode of the second reset transistor is the source and the second electrode is the drain, or the first electrode of the second reset transistor is the drain and the second electrode is the source; The display driving circuit is used for: Controlling the M rows of sub-pixels to display row by row at a first refresh rate; When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset phase, the data voltage writing phase and the light emitting phase, a second initial voltage Vint2 is output to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; Controlling the M rows of sub-pixels to display row by row at a second refresh rate; wherein the second refresh rate is less than the first refresh rate; When the Nth row of sub-pixels in the M rows of sub-pixels are controlled to display, in the reset phase, the data voltage writing phase and the light emitting phase, the first initial voltage Vint1 is output to the second electrode of the first reset transistor in the pixel circuit of the Nth row of sub-pixels; wherein |Vint2|>|Vint1|; The reset phase is a phase in which the first reset transistor is turned on; the data voltage writing phase is a phase in which the data voltage is applied to the first electrode of the driving transistor; and the light emitting phase is a phase in which the light emitting device emits light.

14. A computer readable medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to claim 11 is implemented.

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