Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device, wherein the display substrate comprises: a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer which are sequentially arranged on the substrate and insulated from each other; the semiconductor layer comprises: an active layer of multiple transistors, the first metal layer comprises: a gate line, a light-emitting control line, a reset signal line, a first electrode of a storage capacitor, and gate electrodes of multiple transistors, the second metal layer comprises: an initial signal line and a second electrode of the storage capacitor; the third metal layer comprises: source-drain electrodes of multiple transistors, the fourth metal layer comprises: a data line and a power line, and the fifth metal layer comprises: an anode of a light-emitting device. The present application can reduce the volume occupied by the data lines connected to the sub-pixels by arranging the data lines and the power lines in different layers from the source-drain electrodes of the multiple transistors, thereby improving the resolution of the high-frequency driven OLED display substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Device (OLED) display substrate is a display substrate different from the traditional Liquid Crystal Display (LCD). It has the advantages of active light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-thinness and low cost. Therefore, it has become one of the important development discoveries of the new generation of display devices and has received more and more attention.

[0003] In order to achieve high-frequency driving of OLED display substrates, a dual-data-line OLED display substrate is proposed in the related art, that is, the same column of pixels is connected to two data lines. However, although the OLED display substrates in the related art can achieve high-frequency driving, the resolution is generally low and cannot meet the market demand for high-resolution display devices. Summary of the invention

[0004] The present application provides a display substrate and a manufacturing method thereof, and a display device, which can improve the resolution of an OLED display substrate.

[0005] In a first aspect, the present application provides a display substrate, wherein a gate line, a data line, a power line, a reset signal line, a light-emitting control line, an initial signal line, and a plurality of sub-pixels are provided in the display substrate, wherein each sub-pixel comprises: a light-emitting device and a driving circuit for driving the light-emitting device to emit light, wherein the driving circuit comprises: a plurality of transistors and a storage capacitor; the display substrate comprises: a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, which are sequentially provided on the substrate and insulated from each other;

[0006] The semiconductor layer includes: an active layer of multiple transistors, the first metal layer includes: a gate line, a light emitting control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of multiple transistors, the second metal layer includes: an initial signal line and a second electrode of the storage capacitor; the third metal layer includes: source and drain electrodes of multiple transistors, the fourth metal layer includes: a data line and a power line, and the fifth metal layer includes: an anode of a light emitting device;

[0007] The i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all the sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, and N is the total number of columns of sub-pixels.

[0008] Optionally, the pixel structures of adjacent sub-pixels located in the same row are mirror-symmetric to each other about the center lines of two sub-data lines located between the adjacent sub-pixels, the pixel structure of the sub-pixel located in the i-th row and j-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j+1-th column, and the pixel structure of the sub-pixel located in the i-th row and j+1-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j-th column.

[0009] Optionally, adjacent sub-pixels in the same column are connected to different sub-data lines;

[0010] The i-th column of sub-pixels is also connected to the i-th column of power lines, and the i-th column of power lines is located between the first sub-data line and the second sub-data line in the i-th column of data lines;

[0011] Two adjacent columns of power lines are mirror-symmetrical about a center line between the two adjacent columns of power lines.

[0012] Optionally, there is an overlapping area between the orthographic projection of the i-th column of sub-pixels on the substrate and the orthographic projection of the i-th column of power lines on the substrate, and the i-th column of power lines includes: a plurality of interconnected sub-power lines, and the plurality of sub-power lines correspond one-to-one to all sub-pixels in the i-th column of sub-pixels.

[0013] Optionally, each sub-power line includes: a first power supply unit, a second power supply unit and a third power supply unit;

[0014] The second power supply unit is used to connect the first power supply unit and the third power supply unit, the first power supply unit and the third power supply unit are arranged in parallel with the data line, and the angle between the second power supply unit and the first power supply unit is greater than 90 degrees and less than 180 degrees;

[0015] The third power supply part has a width smaller than that of the first power supply part.

[0016] Optionally, the first power supply unit in the sub-power line corresponding to the sub-pixel is connected to the third power supply unit in the sub-power line corresponding to the sub-pixel in the previous row in the same column, and the third power supply unit in the sub-power line corresponding to the sub-pixel is connected to the first power supply unit in the sub-power line corresponding to the sub-pixel in the next row in the same column.

[0017] Optionally, each sub-pixel is divided into: a first area, a second area and a third area;

[0018] The storage capacitor is located in the second area, the first area and the third area are respectively located on both sides of the second area, the initial signal line, gate line, and reset signal line connected to the sub-pixel are located in the first area, and the light emitting control line connected to the sub-pixel is located in the third area.

[0019] Optionally, the display substrate further comprises: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer;

[0020] The first insulating layer is arranged between the semiconductor layer and the first metal layer, the second insulating layer is arranged between the first metal layer and the second metal layer, the third insulating layer is arranged between the second metal layer and the third metal layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer.

[0021] Optionally, for each sub-pixel, the plurality of transistors include: a first transistor to a seventh transistor, and a first electrode of the fifth transistor is respectively connected to a power line and a second electrode of a storage capacitor.

[0022] Optionally, the fourth insulating layer is provided with a first via hole exposing a portion of the first electrode of the fifth transistor, and the third insulating layer is provided with a second via hole exposing a portion of the second electrode of the storage capacitor;

[0023] The power line connected to the sub-pixel is connected to the first electrode of the fifth transistor through the first via hole; the first electrode of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole.

[0024] Optionally, for each sub-pixel, the number of the first via hole is one, and the number of the second via hole is at least one;

[0025] When there are multiple second via holes, the multiple second via holes are arranged along the extending direction of the data line;

[0026] The orthographic projection of the power line connected to the sub-pixel on the substrate covers the orthographic projection of the first via hole on the substrate, and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.

[0027] Optionally, the second electrodes of the storage capacitors in adjacent sub-pixels in the same row are in direct contact.

[0028] Optionally, every four consecutive sub-pixels constitute a pixel;

[0029] In the j-th pixel, four consecutive sub-pixels along the gate line are the i-th sub-pixel, the i+1-th sub-pixel, the i+2-th sub-pixel and the i+3-th sub-pixel;

[0030] The second electrode of the storage capacitor of the i-th sub-pixel in each pixel of one of the two adjacent rows of pixels is in direct contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is spaced from the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+3-th sub-pixel;

[0031] The second electrode of the storage capacitor of the i-th sub-pixel in each pixel of the other row of two adjacent rows of pixels is spaced apart from the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is spaced apart from the second electrode of the storage capacitor of the i+3-th sub-pixel;

[0032] Here, i can take the value of 4j-3 in sequence, and j is a positive integer.

[0033] Optionally, for each sub-pixel, an orthographic projection of the first electrode of the fifth transistor on the substrate and an orthographic projection of a data line connected to the sub-pixel on the substrate have an overlapping area.

[0034] Optionally, for the j-th pixel, when the second electrode of the storage capacitor of the i-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, the first electrode of the fifth transistor in the i+1-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+2-th sub-pixel;

[0035] In which, the second electrode of the storage capacitor in the i-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor in the i+3-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i+1-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+2-th sub-pixel.

[0036] Optionally, for the j-th pixel, when the second electrode of the storage capacitor of the i+1-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+2-th sub-pixel, the first electrode of the fifth transistor in the i-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+1-th sub-pixel, and the first electrode of the fifth transistor in the i+2-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+3-th sub-pixel;

[0037] Among them, the second electrode of the storage capacitor of the i-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor of the i+1-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+1-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor of the i+3-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i+2-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+3-th sub-pixel.

[0038] Optionally, the display substrate further comprises: a fifth insulating layer and a planar layer disposed between the fourth metal layer and the fifth metal layer, and an organic material layer and a cathode of the light-emitting device disposed on a side of the fifth metal layer away from the substrate;

[0039] The fifth insulating layer is arranged on a side of the planar layer close to the substrate; and the cathode is arranged on a side of the organic material layer away from the substrate.

[0040] In a second aspect, the present application provides a display device, comprising the display substrate as described above.

[0041] In a third aspect, the present application provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, and the method comprises:

[0042] providing a substrate;

[0043] A mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer are sequentially formed on the substrate; wherein the semiconductor layer includes: an active layer of multiple transistors, the first metal layer includes: a gate line, a light emitting control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of multiple transistors, the second metal layer includes: an initial signal line and a second electrode of a storage capacitor; the third metal layer includes: source and drain electrodes of multiple transistors, the fourth metal layer includes: a data line and a power line, and the fifth metal layer includes: an anode of a light emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, and N is the total number of columns of sub-pixels.

[0044] Optionally, the sequentially forming a mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer on the substrate comprises:

[0045] forming a semiconductor layer and a first insulating layer in sequence on the substrate;

[0046] sequentially forming a first metal layer and a second insulating layer on the first insulating layer;

[0047] forming a second metal layer and a third insulating layer in sequence on the second insulating layer;

[0048] sequentially forming a third metal layer and a fourth insulating layer on the third insulating layer;

[0049] sequentially forming a fourth metal layer, a fifth insulating layer and a planarization layer on the fourth insulating layer;

[0050] A fifth metal layer, an organic light emitting layer of the light emitting device and a cathode of the light emitting device are sequentially formed on the planar layer.

[0051] The present application provides a display substrate and a manufacturing method thereof, and a display device, wherein the display substrate is provided with a gate line, a data line, a power line, a reset signal line, a light-emitting control line, an initial signal line, and a plurality of sub-pixels, each of which includes: a light-emitting device and a driving circuit for driving the light-emitting device to emit light, the driving circuit includes: a plurality of transistors and a storage capacitor; the display substrate includes: a substrate, and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer sequentially arranged on the substrate and insulated from each other; the semiconductor layer includes: an active layer of a plurality of transistors, the first metal layer includes: a gate line, a light-emitting control line, a reset signal line , the first electrode of the storage capacitor and the gate electrodes of multiple transistors, the second metal layer includes: the initial signal line and the second electrode of the storage capacitor; the third metal layer includes: the source and drain electrodes of multiple transistors, the fourth metal layer includes: the data line and the power line, and the fifth metal layer includes: the anode of the light-emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: the first sub-data line and the second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, N is the total number of columns of sub-pixels. The present application can reduce the volume occupied by the data lines connected to the sub-pixels by arranging the data lines and the power lines in different layers from the source and drain electrodes of multiple transistors, thereby improving the resolution of the high-frequency driven OLED display substrate.

[0052] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0054] Figure 1 A schematic diagram of the structure of a display substrate provided in an embodiment of the present application;

[0055] Figure 2 A side view of a sub-pixel in a display substrate provided in an embodiment of the present application;

[0056] Figure 3 A top view of a sub-pixel in a display substrate provided in an embodiment of the present application;

[0057] Figure 4A An equivalent circuit diagram of a driving circuit provided in an embodiment of the present application;

[0058] Figure 4B A working timing diagram of the driving circuit provided in the embodiment of the present application;

[0059] Figure 5 A top view of a plurality of sub-pixels in a display substrate provided in an embodiment of the present application;

[0060] Fig. 6A is a top view of a sub-pixel corresponding to implementation mode 1;

[0061] Figure 6B is another top view of a sub-pixel corresponding to the first embodiment;

[0062] Fig. 7A is a top view of the second metal layer corresponding to the first embodiment;

[0063] Figure 7B is a top view of the third metal layer corresponding to the first embodiment;

[0064] Fig. 8A is a top view of a sub-pixel corresponding to the second implementation mode;

[0065] Figure 8B is another top view of a sub-pixel corresponding to the second embodiment;

[0066] Fig.9A is a top view of the second metal layer corresponding to the second embodiment;

[0067] Fig. 9B is a top view of the third metal layer corresponding to the second embodiment;

[0068] Fig.10 Another top view of a plurality of sub-pixels in a display substrate provided in an embodiment of the present application;

[0069] Fig.11 A flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0070] Fig.12 A first manufacturing schematic diagram of a display substrate provided in an embodiment of the present application;

[0071] Fig.13 A second manufacturing schematic diagram of a display substrate provided in an embodiment of the present application;

[0072] Fig.14A A third manufacturing schematic diagram of a display substrate provided in an embodiment of the present application;

[0073] Fig. 14B Another third manufacturing schematic diagram of the display substrate provided in the embodiment of the present application;

[0074] Fig.15A A fourth manufacturing schematic diagram of a display substrate provided in an embodiment of the present application;

[0075] Fig. 15B Another fourth manufacturing schematic diagram of the display substrate provided in the embodiment of the present application;

[0076] Fig.16A A fifth manufacturing schematic diagram of a display substrate provided in an embodiment of the present application;

[0077] Fig. 16B Another fifth manufacturing schematic diagram of the display substrate provided in the embodiment of the present application. DETAILED DESCRIPTION

[0078] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0079] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0080] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0081] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0082] Some embodiments of the present application provide a display substrate. Figure 1 A schematic diagram of the structure of a display substrate provided in an embodiment of the present application, Figure 2 A side view of a sub-pixel in a display substrate provided in an embodiment of the present application, Figure 3 A top view of a sub-pixel in a display substrate provided in an embodiment of the present application, such as Figures 1 to 3As shown, the display substrate provided in the embodiment of the present application is provided with a gate line G, a data line D, a power line VDD, a reset signal line Reset, a light-emitting control line EM, an initial signal line Vinit and a plurality of sub-pixels P, each sub-pixel includes: a light-emitting device and a driving circuit for driving the light-emitting device to emit light, the driving circuit includes: a plurality of transistors and a storage capacitor, the display substrate includes: a substrate 10 and a semiconductor layer 20, a first metal layer 30, a second metal layer 40, a third metal layer 50, a fourth metal layer 60 and a fifth metal layer 70 which are arranged on the substrate 10 and insulated from each other.

[0083] In this embodiment, the semiconductor layer 20 includes: an active layer of multiple transistors, the first metal layer 30 includes: a gate line G, a light-emitting control line EM, a reset signal line Reset, a first electrode C1 of a storage capacitor and gate electrodes of multiple transistors, the second metal layer 40 includes: an initial signal line Vinit and a second electrode C2 of the storage capacitor; the third metal layer 50 includes: source and drain electrodes of multiple transistors, the fourth metal layer 60 includes: a data line D and a power line VDD, and the fifth metal layer 70 includes: an anode of the light-emitting device.

[0084] Specifically, Figure 1 As shown, the display substrate in this embodiment is provided with M rows and N columns of sub-pixels, N columns of data lines D1~DN, N columns of power lines VDD1~VDDN, M rows of gate lines G1~GM, M-1 rows of light-emitting control lines EM1~EMM-1, a reset signal line Reset and an initial signal line Vinit, and the display substrate also includes: a data driver for providing data signals to the data lines, a scan driver for providing scan signals to the gate lines, a light-emitting driver for providing light-emitting control signals to the light-emitting control lines, and a timing controller for providing drive signals to the data driver, the scan driver and the light-emitting driver.

[0085] Alternatively, if Figure 1 As shown, the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: a first sub-data line DO and a second sub-data line DE; the first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line.

[0086] Wherein, 1≤i≤N, and N is the total number of columns of sub-pixels.

[0087] Specifically, all the data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, that is, when the first sub-data line DOi of the data line in the i-th column is located on the side of the sub-pixel in the i-th column close to the sub-pixel in the i+1-th column, the first sub-data line DOi+1 of the data line in the i+1-th column is located on the side of the sub-pixel in the i+1-th column close to the sub-pixel in the i-th column, and when the second sub-data line DEi of the data line in the i-th column is located on the side of the sub-pixel in the i-th column close to the sub-pixel in the i+1-th column, the second sub-data line DEi+1 of the data line in the i+1-th column is located on the side of the sub-pixel in the i+1-th column close to the sub-pixel in the i-th column.

[0088] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be but is not limited to one or more of glass and metal foil; the flexible substrate may be but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0089] Optionally, the semiconductor layer 20 may be made of polysilicon or metal oxide, which is not limited in the embodiment of the present application.

[0090] Optionally, the first metal layer may be made of metal materials such as silver, aluminum or copper, and this embodiment of the present application does not impose any limitation on this.

[0091] Optionally, the second metal layer may be made of metal materials such as silver, aluminum or copper, which is not limited in the embodiment of the present application.

[0092] Optionally, the third metal layer may be made of metal materials such as silver, aluminum or copper, which is not limited in the present embodiment of the application.

[0093] Optionally, the fourth metal layer may be made of metal materials such as silver, aluminum or copper, which is not limited in any way in the embodiment of the present application.

[0094] Optionally, the fifth metal layer may be made of metal materials such as silver, aluminum or copper, and this embodiment of the present application does not impose any limitation on this.

[0095] Figure 4A is an equivalent circuit diagram of a driving circuit provided in an embodiment of the present application, Figure 4B The working timing diagram of the driving circuit provided in the embodiment of the present application is as follows: Figure 4A and Figure 4B As shown, Figure 4AThe driving circuit included in the i-th column of sub-pixels and the i+1-th column of sub-pixels is used as an example for explanation. The driving circuit provided in the embodiment of the present application is a 7T1C structure, and the driving circuit includes: a first transistor T1 to a seventh transistor T7 and a storage capacitor C, wherein the storage capacitor C includes a first electrode C1 and a second electrode C2.

[0096] Specifically, the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, the second electrode of the first transistor T1 is connected to the first electrode C1 of the storage capacitor C, the gate electrode of the second transistor T2 is connected to the gate line G, the first electrode of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C, the second electrode of the second transistor T2 is connected to the second electrode of the sixth transistor T6, the gate electrode of the third transistor T3 is connected to the first electrode C1 of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, the second electrode of the third transistor T3 is connected to the second electrode of the sixth transistor T6, and the gate electrode of the fourth transistor T4 is connected to the gate line G. A first electrode of the fourth transistor T4 is connected to the data line D, a gate electrode of the fifth transistor T5 is connected to the light emitting control line EM, a first electrode of the fifth transistor T5 is connected to the power line VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, a gate electrode of the sixth transistor T6 is connected to the light emitting control line EM, a second electrode of the sixth transistor T6 is connected to the anode of the light emitting device, a gate electrode of the seventh transistor T7 is connected to the reset signal line Reset, a first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, a second electrode of the seventh transistor T7 is connected to the anode of the light emitting device, a second electrode C2 of the storage capacitor is connected to the power line VDD, and a cathode of the light emitting device OLED is connected to the low-level power supply terminal VSS.

[0097] Among them, the third transistor T3 is a driving transistor, and the other transistors except the third transistor T3 are switching transistors. The first transistor T1 to the seventh transistor T7 provided in this embodiment can all be P-type transistors or N-type transistors, and the embodiment of the present application does not impose any limitation on this.

[0098] Specifically, taking the first transistor T1 to the seventh transistor T7 as P-type transistors as an example, the working process of the driving circuit provided in the embodiment of the present application includes:

[0099] In the first stage S1, the reset stage, the reset signal line Reset provides an effective level, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal line Vinit provides an initial signal to initialize the signal of the second electrode of the sixth transistor T6 and the signal of the first electrode C1.

[0100] In the second stage S2, the writing stage, the gate line G provides a valid level, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal provided by the data line D is written to the first electrode of the third transistor T3, and the potential of the gate electrode of the second transistor T2 and the signal of the second electrode are made the same, so that the third transistor T3 is turned on.

[0101] In the third stage S3, the light emitting stage, the light emitting control line EM provides an effective level, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power line VDD provides a driving current to the light emitting device OLED to drive the light emitting device to emit light.

[0102] Alternatively, if Figure 4A As shown, the light emitting device in the embodiment of the present application may be an OLED.

[0103] The display substrate provided by the embodiment of the present application is provided with a gate line, a data line, a power line, a reset signal line, a light-emitting control line, an initial signal line and a plurality of sub-pixels, each of which includes: a light-emitting device and a driving circuit for driving the light-emitting device to emit light, the driving circuit includes: a plurality of transistors and a storage capacitor; the display substrate includes: a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer which are sequentially arranged on the substrate and insulated from each other; the semiconductor layer includes: an active layer of a plurality of transistors, the first metal layer includes: a gate line, a light-emitting control line, a reset signal line, a first electrode of a storage capacitor The first metal layer includes: the first signal line and the second electrode of the storage capacitor; the third metal layer includes: the source and drain electrodes of the multiple transistors; the fourth metal layer includes: the data line and the power line; the fifth metal layer includes: the anode of the light-emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: the first sub-data line and the second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, and N is the total number of columns of sub-pixels. The present application is provided with five metal layers. By arranging the data lines and the power lines in different layers from the source and drain electrodes of the multiple transistors, the volume occupied by the sub-pixels and the data lines connected to the sub-pixels can be reduced, thereby improving the resolution of the high-frequency driven OLED display substrate.

[0104] Alternatively, if Figure 3 As shown, each sub-pixel in the display substrate provided in the embodiment of the present application is divided into: a first region R1, a second region R2 and a third region R3.

[0105] Specifically, the storage capacitor is located in the second region R2, the first region R2 and the third region R3 are respectively located on both sides of the second region and are arranged along the extension direction of the data line, the initial signal line Vinit, the gate line G and the reset signal line Reset connected to the sub-pixel are located in the first region R1, and the light-emitting control line EM connected to the sub-pixel is located in the third region R3.

[0106] Specifically, adjacent sub-pixels located in the same column are connected to different sub-data lines, that is, if the sub-pixel in the i-th row and j-th column is connected to the first sub-data line DOj in the data line of the j-th column, then the sub-pixel in the i+1-th row and j-th column is connected to the second sub-data line DEj in the data line of the j-th column; if the sub-pixel in the i-th row and j-th column is connected to the second sub-data line DEj in the data line of the j-th column, then the sub-pixel in the i+1-th row and j-th column is connected to the first sub-data line DOj in the data line of the j-th column.

[0107] Alternatively, if Figure 1 and Figure 3 It can be seen that the i-th column of sub-pixels is also connected to the i-th column of power lines, 1≤i≤N.

[0108] The i-th column power line VDDi is located between the first sub-data line DOi and the second sub-data line DEi in the i-th column data lines.

[0109] Figure 5 A top view of a plurality of sub-pixels in a display substrate provided in an embodiment of the present application, such as Figure 5 As shown, the pixel structures of adjacent sub-pixels located in the same row are mirror-symmetric with respect to the center line CL of the two sub-data lines located between the adjacent sub-pixels, the pixel structure of the sub-pixel located in the i-th row and j-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j+1-th column, and the pixel structure of the sub-pixel located in the i-th row and j+1-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j-th column.

[0110] like Figure 5 As shown, two adjacent columns of power lines are mirror-symmetrical about a center line between the two adjacent columns of power lines.

[0111] Specifically, the center line CL of the two sub-data lines between the sub-pixel in the i-th row and j-th column and the sub-pixel in the i-th row and j+1-th column is the same center line as the center line between the power line in the j-th column and the power line in the j+1-th column.

[0112] Alternatively, if Figure 5 As shown, the power line in the i-th column includes: a plurality of interconnected sub-power lines, namely S1 to SN, and the plurality of sub-power lines correspond one-to-one to all sub-pixels in each column of sub-pixels. It should be noted that Figure 5 The description is given by taking the first two rows and four columns of eight sub-pixels as an example.

[0113] Specifically, in this embodiment, the shape of the sub-power line corresponding to the sub-pixel in the i-th row and j-th column after flipping along the center line of the first sub-data line and the second sub-data line located in the j-th column data line is the same as the shape of the sub-power line corresponding to the sub-pixel in the i+1-th row and j-th column.

[0114] Specifically, Figure 5 As shown, each sub-power line includes: a first power supply unit SS1, a second power supply unit SS2 and a third power supply unit SS3, the second power supply unit SS2 is used to connect the first power supply unit SS1 and the third power supply unit SS3, the first power supply unit SS1 and the third power supply unit SS3 are arranged parallel to the data line, and the angle between the second power supply unit SS2 and the first power supply unit SS1 is greater than 90 degrees and less than 180 degrees.

[0115] The first power supply unit SS1 , the second power supply unit SS2 and the third power supply unit SS3 are integrally formed.

[0116] like Figure 5 As shown, the width of the third power supply part SS3 is smaller than that of the first power supply part SS1. On the one hand, it is for the layout of the pixel structure. On the other hand, since the third power supply part SS3 is close to the power line, the smaller width of the third power supply part SS3 can reduce parasitic capacitance.

[0117] Specifically, the first power supply unit SS1 in the sub-power line corresponding to the sub-pixel in the i-th row and j-th column is connected to the third power supply unit SS3 in the sub-power line corresponding to the sub-pixel in the i-1-th row and j-th column, and the third power supply unit SS3 in the sub-power line corresponding to the sub-pixel in the i-th row and j-th column is connected to the first power supply unit SS1 in the sub-power line corresponding to the sub-pixel in the i+1-th row and j-th column, and the interconnected power supply units are arranged along the extension direction of the data line.

[0118] like Figure 5 As shown, the power line in the embodiment of the present application is in the shape of a broken line.

[0119] In this embodiment, combined with Figure 5 The working process of each sub-pixel includes: in the reset stage, the reset signal line Reset located in the first metal layer and the initial signal line Vinit located in the second metal layer provide signals to initialize the driving circuit; in the writing stage, the gate line G located in the first metal layer and the data line D located in the fourth metal layer provide signals to write the data signal provided by the data line D into the driving circuit; in the light-emitting stage, the light-emitting control line EM located in the first metal layer provides a signal, and the power line VDD provides a power signal, so that the driving circuit provides a driving current to the light-emitting device OLED to drive the light-emitting device to emit light.

[0120] Pixels in the same row are displayed simultaneously, and pixels in adjacent rows are displayed sequentially.

[0121] Alternatively, if Figure 2 As shown, the display substrate provided in the present application further includes: a first insulating layer 11 , a second insulating layer 12 , a third insulating layer 13 and a fourth insulating layer 14 .

[0122] Specifically, the first insulating layer 11 is disposed between the semiconductor layer 20 and the first metal layer 30 , the second insulating layer 12 is disposed between the first metal layer 30 and the second metal layer 40 , the third insulating layer 13 is disposed between the second metal layer 40 and the third metal layer 50 , and the fourth insulating layer 14 is disposed between the third metal layer 50 and the fourth metal layer 60 .

[0123] Optionally, the first insulating layer 11 , the second insulating layer 12 , the third insulating layer 13 and the fourth insulating layer 14 may be made of silicon oxide, silicon nitride or a composite of silicon oxide and silicon nitride, which is not limited in any way in the embodiments of the present application.

[0124] In this embodiment, Figure 4A As shown, for each sub-pixel, the plurality of transistors include: a first transistor to a seventh transistor, and a first electrode of the fifth transistor is respectively connected to the power line VDD and the second electrode C2 of the storage capacitor.

[0125] In the embodiment of the present application, for each sub-pixel, the power line in each sub-pixel is connected to the second electrode of the storage capacitor through the first electrode of the fifth transistor.

[0126] Specifically, the second electrodes of the storage capacitors of adjacent sub-pixels located in the second metal layer are also reused as power signal lines to ensure that the power lines of adjacent sub-pixels provide the same power signals, thereby avoiding poor display of the display substrate and ensuring the display effect of the display substrate.

[0127] In this embodiment, every four consecutive sub-pixels constitute a pixel. In the jth pixel, the four consecutive sub-pixels are arranged along the gate line in the direction of the i-th sub-pixel, the i+1-th sub-pixel, the i+2-th sub-pixel and the i+3-th sub-pixel, where i can take the value of 4j-3 in sequence, and j is a positive integer.

[0128] Specifically, there are multiple implementations for connecting the second electrodes of the storage capacitors of the plurality of sub-pixels. As one implementation, Fig. 6A is a top view of a sub-pixel corresponding to the first embodiment, Figure 6B is another top view of a sub-pixel corresponding to the first embodiment, wherein Fig. 6A As shown, the fourth insulating layer is provided with a first via hole V1 exposing a portion of the first electrode 51 of the fifth transistor, and the power line is connected to the first electrode 51 of the fifth transistor through the first via hole V1; Figure 6BAs shown, the third insulating layer is provided with a second via hole V2 exposing a portion of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole V2. It should be noted that, Figure 3 and Figure 5 The description is made by taking the first implementation mode as an example.

[0129] The orthographic projection of the power line connected to the sub-pixel on the substrate covers the orthographic projection of the first via hole V1 on the substrate 10 , and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.

[0130] Optionally, the number of the first via hole V1 is one.

[0131] Optionally, the number of the second via holes V2 is at least one. Since the width of the first electrode of the fifth transistor is narrow, when the number of the second via holes V2 is multiple, the multiple second via holes are arranged along the extension direction of the data line, wherein the multiple second via holes are arranged along the extension direction of the data line. Multiple via holes can be arranged. The more the number of via holes, the better the conductivity of the components connected through the via holes. Fig. 6A is a first via V1, Figure 6B The description is made by taking two second via holes V2 as an example, and the embodiment of the present application does not impose any limitation on this.

[0132] Specifically, Fig. 6A As shown, the fourth insulating layer also includes a via hole exposing the first electrode of the fourth transistor T4, and the data line is connected to the first electrode of the fourth transistor T4 through the via hole. The fourth insulating layer also includes exposing the second electrode of the sixth transistor T6, and the anode of the light-emitting device is connected to the second electrode of the sixth transistor T6 through the via hole.

[0133] Specifically, Figure 6B As shown, the first insulating layer, the second insulating layer and the third insulating layer further include via holes exposing a portion of the active layer, so that the source and drain electrodes of the transistor are connected to the active layer through the via holes.

[0134] Specifically, the first electrode of the fifth transistor is also connected to the active layer through via holes on the first insulating layer, the second insulating layer and the third insulating layer.

[0135] In this embodiment, each pixel includes: four sub-pixels, specifically, Fig. 7A is a top view of the second metal layer corresponding to the first embodiment, Figure 7B FIG. 1 is a top view of the third metal layer corresponding to the first embodiment, in order to more clearly illustrate the structure of the display substrate. Fig. 7A and Figure 7B The description is made by taking two pixels arranged along the column direction as an example.

[0136] like Fig. 7A As shown, the second electrodes of the storage capacitors in adjacent sub-pixels in the same row are in direct contact, such as Figure 7B As shown, the first electrodes 51 of the fifth transistors of adjacent sub-pixels in the same row are arranged alternately.

[0137] In the first embodiment, the second electrodes of the storage capacitors of the plurality of sub-pixels arranged on the second metal layer are in contact with each other, so that the power lines of adjacent sub-pixels provide the same power signal, thereby avoiding poor display of the display substrate and ensuring the display effect of the display substrate.

[0138] As another embodiment, Fig. 8A is a top view of a sub-pixel corresponding to the second embodiment, Figure 8B is another top view of a plurality of sub-pixels corresponding to the second embodiment, wherein Fig. 8A As shown, the fourth insulating layer is provided with a first via hole V1 exposing a portion of the first electrode 51 of the fifth transistor, and the power line is connected to the first electrode 51 of the fifth transistor through the first via hole V1; Figure 8B As shown, the third insulating layer is provided with a second via hole V2 exposing a portion of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole V2.

[0139] like Fig. 8A and Figure 8B As shown, the area occupied by the second electrode of the storage capacitor of each sub-pixel provided in the first embodiment is different and the shape of the first electrode 51 of the fifth transistor is also different.

[0140] Specifically, Fig. 8A As shown, the fourth insulating layer also includes a via hole exposing the first electrode of the fourth transistor T4, and the data line is connected to the first electrode of the fourth transistor T4 through the via hole. The fourth insulating layer also includes exposing the second electrode of the sixth transistor T6, and the anode of the light-emitting device is connected to the second electrode of the sixth transistor T6 through the via hole.

[0141] Specifically, Figure 3 and 8B As shown, the first insulating layer, the second insulating layer and the third insulating layer further include: vias exposing a portion of the active layer, so that the source and drain electrodes of the transistor are connected to the active layer through the vias. Specifically, the first electrode of the fifth transistor is also connected to the active layer through the vias on the first insulating layer, the second insulating layer and the third insulating layer.

[0142] The orthographic projection of the power line connected to the sub-pixel on the substrate covers the orthographic projection of the first via hole V1 on the substrate 10 , and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.

[0143] Optionally, the number of the first via hole V1 is one.

[0144] Optionally, the number of the second via hole V2 is at least one. Since the width of the first electrode of the fifth transistor is relatively narrow, a plurality of second via holes are arranged along the extending direction of the data line to ensure the number of via holes. The more the number of via holes, the better the conductivity of the components connected through the via holes. Fig. 8A is a first via V1, Figure 8B The description is made by taking two second via holes V2 as an example, and the embodiment of the present application does not impose any limitation on this.

[0145] Specifically, Fig.9A is a top view of the second metal layer corresponding to the second embodiment, Fig. 9B is a top view of the third metal layer corresponding to the second embodiment, Fig.10 Another top view of a plurality of sub-pixels in a display substrate provided in an embodiment of the present application is provided to more clearly illustrate the structure of the display substrate. Fig.9A and Fig. 9B The following is an example of two pixels arranged in the column direction. Fig.10 Including other film layers except the anode of the light-emitting device, Fig.10 The multiple sub-pixels included in are sub-pixels corresponding to the second implementation mode.

[0146] like Fig.9A and Fig. 9B As shown, the second electrode of the storage capacitor of the i-th sub-pixel in each pixel of one of the two adjacent rows of pixels is directly in contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel and the second electrode of the storage capacitor of the i+2-th sub-pixel are spaced apart, and the second electrode of the storage capacitor of the i+2-th sub-pixel is directly in contact with the second electrode of the storage capacitor of the i+3-th sub-pixel; the second electrode of the storage capacitor of the i-th sub-pixel in each pixel of the other of the two adjacent rows of pixels is spaced apart from the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is directly in contact with the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is spaced apart from the second electrode of the storage capacitor of the i+3-th sub-pixel.

[0147] It should be noted that Fig.9A The description is made by taking the example that the second electrode of the storage capacitor of the i-th sub-pixel in the first row of pixels is in direct contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel in the second row of pixels is in direct contact with the second electrode of the storage capacitor of the i+3-th sub-pixel.

[0148] Alternatively, if Fig.10As shown, for each sub-pixel, there is an overlapping area between the orthographic projection of the first electrode of the fifth transistor on the substrate and the orthographic projection of the data line connected to the sub-pixel on the substrate.

[0149] In this embodiment, combined with Fig.9A , Fig. 9B and Fig.10 For the j-th pixel, when the second electrode C2 of the storage capacitor of the i-th sub-pixel is in direct contact with the second electrode C2 of the storage capacitor of the i+1-th sub-pixel, the first electrode 51 of the fifth transistor in the i+1-th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the i+2-th sub-pixel; wherein the second electrode C2 of the storage capacitor in the i-th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor in the i+3-th sub-pixel located in the second metal layer through the first electrode 51 of the fifth transistor in the i+1-th sub-pixel located in the third metal layer and the first electrode 51 of the fifth transistor in the i+2-th sub-pixel.

[0150] In the present embodiment, for the jth pixel, under the condition that the second electrode C2 of the storage capacitor of the i+1th sub-pixel is in direct contact with the second electrode C2 of the storage capacitor of the i+2th sub-pixel, the first electrode 51 of the fifth transistor in the i+1th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the i+1th sub-pixel, and the first electrode 51 of the fifth transistor in the i+2th sub-pixel is in direct contact with the first electrode 51 of the fifth transistor in the i+3th sub-pixel; wherein, the second electrode C2 of the storage capacitor of the i-th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+1th sub-pixel located in the second metal layer through the first electrode 51 of the fifth transistor in the i+1th sub-pixel located in the third metal layer and the first electrode 51 of the fifth transistor in the i+1th sub-pixel, and the second electrode C2 of the storage capacitor of the i+2th sub-pixel located in the second metal layer is connected to the second electrode C2 of the storage capacitor of the i+3th sub-pixel located in the second metal layer through the first electrode 51 of the fifth transistor in the i+2th sub-pixel located in the third metal layer and the first electrode 51 of the fifth transistor in the i+3th sub-pixel.

[0151] In the second implementation mode, the embodiment of the present application realizes the function of the power connection line by completing the lateral cross-connection through the second metal layer and the third metal layer, so that the power signal provided to each sub-pixel is the same, thereby ensuring the display effect of the display substrate.

[0152] It should be noted that, since the resistivity of the third metal layer is smaller than that of the second metal layer, the display substrate provided in the second embodiment can further reduce dynamic crosstalk compared with the display substrate provided in the first embodiment.

[0153] Alternatively, if Figure 2As shown, the display substrate provided in the embodiment of the present application also includes: a fifth insulating layer 15 and a planar layer 16 arranged between the fourth metal layer 60 and the fifth metal layer 70, and an organic material layer and a cathode (not shown in the figure) of the light-emitting device arranged on the side of the fifth metal layer 70 away from the substrate 10.

[0154] Specifically, the fifth insulating layer 15 is disposed on a side of the planar layer 16 close to the substrate 10 ; and the cathode is disposed on a side of the organic material layer away from the substrate 10 .

[0155] like Figure 3 As shown, the third metal layer provided in the embodiment of the present application further includes: a connecting electrode 61, wherein the connecting electrode is respectively connected to the fifth metal layer and the second electrode of the sixth transistor.

[0156] Among them, the fifth insulating layer and the planar layer are provided with vias exposing the connecting electrode, the fifth metal layer is connected to the connecting electrode through the vias exposing the connecting electrode, the fourth insulating layer is provided with vias exposing the second pole of the sixth transistor, and the connecting electrode is connected to the second pole of the sixth transistor through the vias exposing the second pole of the sixth transistor.

[0157] Based on the same inventive concept, the embodiment of the present application further provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided in the above embodiment. Fig.11 A flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application, such as Fig.11 As shown, the method for manufacturing a display substrate provided in an embodiment of the present application specifically includes the following steps:

[0158] Step S1, providing a substrate.

[0159] Step S2: sequentially forming a mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer on the substrate.

[0160] Specifically, the semiconductor layer includes: an active layer of multiple transistors, the first metal layer includes: a gate line, a light-emitting control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of multiple transistors, the second metal layer includes: an initial signal line and a second electrode of the storage capacitor; the third metal layer includes: source and drain electrodes of multiple transistors, the fourth metal layer includes: a data line and a power line, and the fifth metal layer includes: an anode of a light-emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line.

[0161] Wherein, 1≤i≤N, and N is the total number of columns of sub-pixels.

[0162] Among them, the manufacturing method of the display substrate provided in the embodiment of the present application is used to manufacture the display substrate provided in the above embodiment, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0163] Optionally, step 200 includes: forming a semiconductor layer and a first insulating layer in sequence on a substrate; forming a first metal layer and a second insulating layer in sequence on the first insulating layer; forming a second metal layer and a third insulating layer in sequence on the second insulating layer; forming a third metal layer and a fourth insulating layer in sequence on the third insulating layer; forming a fourth metal layer, a fifth insulating layer and a flat layer in sequence on the fourth insulating layer; and forming a fifth metal layer, an organic light-emitting layer of a light-emitting device and a cathode of the light-emitting device in sequence on the flat layer.

[0164] Fig.12 This is a first manufacturing schematic diagram of a display substrate provided in an embodiment of the present application. Fig.13 This is a second schematic diagram of manufacturing a display substrate provided in an embodiment of the present application. Fig.14A A third manufacturing schematic diagram of a display substrate provided in an embodiment of the present application, Fig. 14B Another third manufacturing schematic diagram of the display substrate provided in the embodiment of the present application, Fig.15A A fourth manufacturing schematic diagram of a display substrate provided in an embodiment of the present application, Fig. 15B This is another fourth manufacturing schematic diagram of the display substrate provided in the embodiment of the present application. Fig.16A A fifth manufacturing schematic diagram of a display substrate provided in an embodiment of the present application, Fig. 16B Another fifth manufacturing schematic diagram of the display substrate provided in the embodiment of the present application, combined with Figure 12 to Figure 1 6. The following further describes the method for manufacturing the display substrate provided in the embodiment of the present application. The specific description is as follows:

[0165] Optionally, the patterning process includes: photoresist coating, exposure, development, etching, photoresist stripping and other processes.

[0166] Step 100: provide a substrate 10, deposit a semiconductor film on the substrate 10, and process the semiconductor film using a patterning process to form a semiconductor layer 20, such as Fig.12 shown.

[0167] The schematic diagram for manufacturing the active layer in the first embodiment is the same as the schematic diagram for manufacturing the active layer in the second embodiment.

[0168] Step 200: depositing an insulating film on the semiconductor layer 20, processing the insulating film by a patterning process to form a first insulating layer, depositing a metal film on the first insulating layer, processing the metal film by a patterning process to form a first metal layer 30, as shown in FIG. Fig.13 shown.

[0169] The first metal layer 30 includes: a gate line G, a reset signal line Reset, a light emitting control line EM and a first electrode C1 of a storage capacitor.

[0170] The schematic diagram for manufacturing the first metal layer in the first embodiment is the same as the schematic diagram for manufacturing the first metal layer in the second embodiment.

[0171] Step 300, depositing an insulating film on the first metal layer 30, processing the insulating film by a composition process to form a second insulating layer, depositing a metal film on the second insulating layer, processing the metal film by a composition process to form a second metal layer of an initial signal line Vinit and a second electrode C2 of a storage capacitor, forming a deposited insulating film on the second metal layer, processing the insulating film by a composition process to form a third insulating layer, specifically as follows Fig.14A and 14B shown.

[0172] The third insulating layer includes a first via hole V1 exposing the second electrode and a via hole exposing the initial signal line Vinit. The second insulating layer and the third insulating layer are provided with via holes exposing the first electrode. The first insulating layer, the second insulating layer and the third insulating layer are provided with via holes exposing the semiconductor layer.

[0173] Fig.14A This is a schematic diagram of the production of implementation mode 1. Fig. 14B This is a schematic diagram of the production of implementation method 2.

[0174] Step 400: depositing a metal film on the third insulating layer, processing the metal film by a composition process to form a third metal layer including source and drain electrodes of a plurality of transistors, depositing an insulating film on the third metal layer, processing the insulating film by a composition process to form a fourth insulating layer, such as Fig.15A and Fig. 15B shown.

[0175] The fourth insulating layer includes a first via hole V1 exposing the fifth transistor, a via hole exposing the second electrode of the sixth transistor, and a via hole exposing the first electrode of the fourth transistor.

[0176] It should be noted that Fig.15A This is a schematic diagram of the production of implementation mode 1. Fig. 15B This is a schematic diagram of the production of implementation method 2.

[0177] Step 500, depositing a metal film on the fourth insulating layer, processing the metal film by a composition process to form a fourth metal layer including a data line D, a power line VDD and a connecting electrode 61, depositing an insulating film on the fourth metal layer, processing the insulating film by a composition process to form a fifth insulating layer, coating a flat film on the fifth insulating layer, processing the flat film by a composition process to form a flat layer, specifically as follows Fig.16A and 16B shown.

[0178] Specifically, the fifth insulating layer and the planar layer are provided with via holes exposing the connection electrodes to emit light.

[0179] It should be noted that Fig.16A This is a schematic diagram of the production of implementation mode 1. Fig. 16B This is a schematic diagram of the production of implementation method 2.

[0180] Step 600, deposit a metal film on the flat layer, process the metal film through a composition process to form a fifth metal layer, coat an organic material film on the fifth metal layer, process the organic material film through a composition process to form an organic material layer, deposit a conductive film on the organic material layer, and process the conductive film through a composition process to form a cathode.

[0181] Based on the same inventive concept, an embodiment of the present application further provides a display device, wherein the display device includes: a display substrate.

[0182] Optionally, the display substrate is an OLED display substrate.

[0183] Specifically, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0184] Among them, the display substrate is the display substrate provided by the aforementioned embodiment, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0185] For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0186] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: The display substrate is provided with a gate line, a data line, a power line, a reset signal line, a light-emitting control line, an initial signal line and a plurality of sub-pixels, each of which includes a light-emitting device and a driving circuit for driving the light-emitting device to emit light, and the driving circuit includes a plurality of transistors and a storage capacitor; the display substrate includes a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer which are sequentially arranged on the substrate and insulated from each other; The semiconductor layer includes: an active layer of multiple transistors, the first metal layer includes: a gate line, a light emitting control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of multiple transistors, the second metal layer includes: an initial signal line and a second electrode of the storage capacitor; the third metal layer includes: source and drain electrodes of multiple transistors, the fourth metal layer includes: a data line and a power line, and the fifth metal layer includes: an anode of a light emitting device; The i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all the sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, and N is the total number of columns of sub-pixels.

2. The display substrate according to claim 1, characterized in that: The pixel structures of adjacent sub-pixels located in the same row are mirror-symmetric to each other about the center lines of the two sub-data lines located between the adjacent sub-pixels. The pixel structure of the sub-pixel located in the i-th row and j-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j+1-th column, and the pixel structure of the sub-pixel located in the i-th row and j+1-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j-th column.

3. The display substrate according to claim 1, characterized in that: Adjacent sub-pixels in the same column are connected to different sub-data lines; The i-th column of sub-pixels is also connected to the i-th column of power lines, and the i-th column of power lines is located between the first sub-data line and the second sub-data line in the i-th column of data lines; Two adjacent columns of power lines are mirror-symmetrical about a center line between the two adjacent columns of power lines.

4. The display substrate according to any one of claims 1 to 3, characterized in that: The i-th column of power lines includes: a plurality of interconnected sub-power lines, and the plurality of sub-power lines correspond one-to-one to all the sub-pixels in the i-th column of sub-pixels.

5. The display substrate according to claim 4, characterized in that: Each sub-power line includes: a first power supply unit, a second power supply unit and a third power supply unit; The second power supply unit is used to connect the first power supply unit and the third power supply unit, the first power supply unit and the third power supply unit are arranged in parallel with the data line, and the angle between the second power supply unit and the first power supply unit is greater than 90 degrees and less than 180 degrees; The third power supply part has a width smaller than that of the first power supply part.

6. The display substrate according to claim 5, characterized in that: The first power supply unit in the sub-power line corresponding to the sub-pixel is connected to the third power supply unit in the sub-power line corresponding to the sub-pixel in the previous row in the same column, and the third power supply unit in the sub-power line corresponding to the sub-pixel is connected to the first power supply unit in the sub-power line corresponding to the sub-pixel in the next row in the same column.

7. The display substrate according to claim 1, characterized in that: Each sub-pixel is divided into: a first area, a second area and a third area; The storage capacitor is located in the second area, the first area and the third area are respectively located on both sides of the second area, the initial signal line, gate line, and reset signal line connected to the sub-pixel are located in the first area, and the light emitting control line connected to the sub-pixel is located in the third area.

8. The display substrate according to claim 1, characterized in that: The display substrate further includes: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer; The first insulating layer is arranged between the semiconductor layer and the first metal layer, the second insulating layer is arranged between the first metal layer and the second metal layer, the third insulating layer is arranged between the second metal layer and the third metal layer, and the fourth insulating layer is arranged between the third metal layer and the fourth metal layer.

9. The display substrate according to claim 8, characterized in that: For each sub-pixel, the plurality of transistors include: a first transistor to a seventh transistor, and a first electrode of the fifth transistor is respectively connected to a power line and a second electrode of the storage capacitor.

10. The display substrate according to claim 9, characterized in that: The fourth insulating layer is provided with a first via hole exposing a portion of the first electrode of the fifth transistor, and the third insulating layer is provided with a second via hole exposing a portion of the second electrode of the storage capacitor; The power line connected to the sub-pixel is connected to the first electrode of the fifth transistor through the first via hole; the first electrode of the fifth transistor is connected to the second electrode of the storage capacitor through the second via hole.

11. The display substrate according to claim 10, characterized in that: For each sub-pixel, the number of the first via hole is one, and the number of the second via hole is at least one; When there are multiple second via holes, the multiple second via holes are arranged along the extending direction of the data line; The orthographic projection of the power line connected to the sub-pixel on the substrate covers the orthographic projection of the first via hole on the substrate, and the orthographic projection of the second electrode of the storage capacitor on the substrate covers the orthographic projection of the second via hole on the substrate.

12. The display substrate according to claim 9, characterized in that: The second electrodes of the storage capacitors in adjacent sub-pixels in the same row are in direct contact.

13. The display substrate according to claim 9, characterized in that: Every four consecutive sub-pixels constitute a pixel; In the jth pixel, four consecutive sub-pixels are arranged along the gate line in the order of the i-th sub-pixel, the i+1-th sub-pixel, the i+2-th sub-pixel and the i+3-th sub-pixel; The second electrode of the storage capacitor of the i-th sub-pixel in each pixel of one of the two adjacent rows of pixels is in direct contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is spaced from the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+3-th sub-pixel; The second electrode of the storage capacitor of the i-th sub-pixel in each pixel of the other row of two adjacent rows of pixels is spaced apart from the second electrode of the storage capacitor of the i+1-th sub-pixel, the second electrode of the storage capacitor of the i+1-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+2-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel is spaced apart from the second electrode of the storage capacitor of the i+3-th sub-pixel; Among them, i can take the value of 4j-3 in sequence, and j is a positive integer.

14. The display substrate according to claim 13, characterized in that: For each sub-pixel, an orthographic projection of the first electrode of the fifth transistor on the substrate and an orthographic projection of the data line connected to the sub-pixel on the substrate have an overlapping area.

15. The display substrate according to claim 13, characterized in that: For the j-th pixel, when the second electrode of the storage capacitor of the i-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+1-th sub-pixel, the first electrode of the fifth transistor in the i+1-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+2-th sub-pixel; In which, the second electrode of the storage capacitor in the i-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor in the i+3-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i+1-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+2-th sub-pixel.

16. The display substrate according to claim 13, characterized in that: For the j-th pixel, when the second electrode of the storage capacitor of the i+1-th sub-pixel is in direct contact with the second electrode of the storage capacitor of the i+2-th sub-pixel, the first electrode of the fifth transistor in the i-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+1-th sub-pixel, and the first electrode of the fifth transistor in the i+2-th sub-pixel is in direct contact with the first electrode of the fifth transistor in the i+3-th sub-pixel; Among them, the second electrode of the storage capacitor of the i-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor of the i+1-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+1-th sub-pixel, and the second electrode of the storage capacitor of the i+2-th sub-pixel located in the second metal layer is connected to the second electrode of the storage capacitor of the i+3-th sub-pixel located in the second metal layer through the first electrode of the fifth transistor in the i+2-th sub-pixel located in the third metal layer and the first electrode of the fifth transistor in the i+3-th sub-pixel.

17. The display substrate according to claim 8, characterized in that: The display substrate further comprises: a fifth insulating layer and a planar layer disposed between the fourth metal layer and the fifth metal layer, and an organic material layer and a cathode of the light emitting device disposed on a side of the fifth metal layer away from the substrate; The fifth insulating layer is arranged on a side of the planar layer close to the substrate; and the cathode is arranged on a side of the organic material layer away from the substrate.

18. A display device, characterized in that: It comprises the display substrate as claimed in any one of claims 1 to 17.

19. A method for manufacturing a display substrate, characterized in that: For manufacturing the display substrate according to any one of claims 1 to 17, the method comprises: providing a substrate; A mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer are sequentially formed on the substrate; wherein the semiconductor layer comprises: an active layer of multiple transistors, the first metal layer comprises: a gate line, a light emitting control line, a reset signal line, a first electrode of a storage capacitor and gate electrodes of multiple transistors, the second metal layer comprises: an initial signal line and a second electrode of a storage capacitor; the third metal layer comprises: source and drain electrodes of multiple transistors, the fourth metal layer comprises: a data line and a power line, and the fifth metal layer comprises: an anode of a light emitting device; the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines comprises: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data line in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, and all the sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line, 1≤i≤N, and N is the total number of columns of sub-pixels.

20. The method according to claim 19, characterized in that The step of sequentially forming a mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer on the substrate comprises: forming a semiconductor layer and a first insulating layer in sequence on the substrate; sequentially forming a first metal layer and a second insulating layer on the first insulating layer; forming a second metal layer and a third insulating layer in sequence on the second insulating layer; sequentially forming a third metal layer and a fourth insulating layer on the third insulating layer; sequentially forming a fourth metal layer, a fifth insulating layer and a planarization layer on the fourth insulating layer; A fifth metal layer, an organic light emitting layer of the light emitting device and a cathode of the light emitting device are sequentially formed on the planar layer.

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