FD-SOI device correction circuit and method

Abstract

A correction circuit for body bias includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal for receiving an oscillation signal from a ring oscillator. The phase detector provides an output signal representing a phase difference between the oscillation signal and a reference signal. The first voltage generator uses the output signal of the phase detector to generate a first reference voltage. The first voltage regulator uses the first reference voltage to generate a first regulated voltage as a first bias voltage. The second voltage generator uses the first reference voltage to generate a second reference voltage. The second voltage regulator uses the second reference voltage to generate a second regulated voltage as a second bias voltage. The first bias voltage provides a P-well for biasing a transistor of the ring oscillator. The second bias voltage provides an N-well for biasing a transistor of the ring oscillator.

Description

Technical Field

[0001] The present invention generally relates to a fully depleted-silicon on insulator (FD-SOI) device, and more particularly to a circuit and method for correcting body bias voltage. Background Art

[0002] Body biasing of forward body biasing (FBB) or reverse body biasing (RBB) is typically used in FD-SOI processes to correct the well bias voltage. However, during device operation, the performance of the device will inevitably degrade due to temperature and / or voltage changes. In addition, aging will also affect the performance of the device.

[0003] Circuits and methods to correct body bias of FD-SOI devices would be advantageous. Summary of the invention

[0004] This Summary is provided to introduce a selected, simplified version of the concepts that are detailed in the Detailed Description below. This Summary is not intended to identify key or essential features of the claims nor is it intended to limit the scope of the claims.

[0005] According to one embodiment, a correction circuit for body biasing includes:

[0006] a phase detector having an input configured to receive an oscillating signal from the ring oscillator, the phase detector configured to provide an output signal representative of a phase difference between the oscillating signal and a reference signal;

[0007] a first voltage generator configured to generate a first reference voltage using an output signal of the phase detector;

[0008] A first voltage regulator receives a first reference voltage and generates a first regulated voltage using the first reference voltage as a first bias voltage;

[0009] A second voltage generator configured to generate a second reference voltage using the first reference voltage;

[0010] The second voltage regulator receives a second reference voltage and uses the second reference voltage to generate a second regulated voltage as a second bias voltage.

[0011] Illustratively, the first bias voltage is provided for biasing a P-well of a transistor of the ring oscillator, and the second bias voltage is provided for biasing an N-well of a transistor of the ring oscillator.

[0012] Illustratively, the phase detector comprises a first output terminal and a second output terminal, wherein:

[0013] The first output signal at the first output terminal indicates that the frequency of the oscillation signal is higher than the frequency of the reference signal; and

[0014] The second output signal at the second output terminal indicates that the frequency of the oscillation signal is lower than the frequency of the reference signal.

[0015] By way of example, (i) the first voltage generator includes a first voltage source, a second voltage source, and an output terminal; (ii) a first output signal of the first output terminal of the phase detector couples the first voltage source of the first voltage generator to the output terminal to provide a first reference voltage; and (iii) a second output signal of the second output terminal of the phase detector couples the second voltage source of the first voltage generator to the output terminal to provide the first reference voltage.

[0016] Illustratively, the second reference voltage is the source voltage minus the first reference voltage.

[0017] Illustratively, the correction circuit further includes a compensation circuit coupled between the first voltage generator and the first voltage regulator.

[0018] Illustratively, the compensation circuit includes:

[0019] A first transistor coupled to a supply voltage;

[0020] A second transistor coupled to a supply voltage;

[0021] a third transistor coupled between the first transistor and ground;

[0022] a fourth transistor coupled between the second transistor and ground; and

[0023] The capacitor is coupled between a node between the first and third transistors and a node between the second and fourth transistors.

[0024] Illustratively, the first transistor is coupled as a source follower, and the second transistor is coupled as a source follower.

[0025] Illustratively, the first transistor and the second transistor are coupled to form a current source.

[0026] Illustratively, the output current of the first transistor is k times the output current of the second transistor, and the transconductance of the third transistor is k times the transconductance of the fourth transistor.

[0027] According to another embodiment, a method of correcting body bias of a ring oscillator, wherein the ring oscillator includes a plurality of transistors, includes:

[0028] The phase detector detects the phase difference between the oscillation signal of the ring oscillator and the reference signal, and provides a phase detector output signal representing the phase difference;

[0029] generating a first reference voltage by a first voltage generator using an output signal of the phase detector;

[0030] generating, by a first voltage regulator, a first regulated voltage as a first bias voltage using a first reference voltage;

[0031] generating a second reference voltage by a second voltage generator using the first reference voltage;

[0032] generating, by a second voltage regulator, a second regulated voltage using a second reference voltage as a second bias voltage;

[0033] For example, the method further comprises:

[0034] biasing a P-well of a transistor of the ring oscillator using a first bias voltage; and

[0035] The N-well of the transistor of the ring oscillator is biased using a second bias voltage.

[0036] Illustratively, detecting the phase difference and providing a phase detector output signal comprises:

[0037] providing a first output signal at a first output terminal of the phase detector, which indicates that the frequency of the oscillating signal is higher than the frequency of the reference signal; and

[0038] A second output signal is provided at a second output terminal of the phase detector, which indicates that the frequency of the oscillating signal is lower than the frequency of the reference signal.

[0039] Illustratively, generating the first reference voltage includes one of the following:

[0040] coupling a first voltage source to an output terminal of the first voltage generator using the first output signal to provide a first reference voltage; and

[0041] A second voltage source is coupled to the output terminal of the first voltage generator using the second output signal to provide a second reference voltage.

[0042] Illustratively, generating the second reference voltage includes subtracting the first reference voltage from the source voltage to generate the second reference voltage.

[0043] Illustratively, the method further includes: coupling a compensation circuit between the first voltage generator and the first voltage regulator.

[0044] For example, the coupling compensation circuit includes:

[0045] coupling the first transistor to a supply voltage;

[0046] coupling the second transistor to a supply voltage;

[0047] coupling the third transistor between the first transistor and ground;

[0048] coupling the fourth transistor between the second transistor and ground; and

[0049] A capacitor is coupled between a node between the first and third transistors and a node between the second and fourth transistors.

[0050] Illustratively, the method further includes: coupling the first transistor and the second transistor as a source follower.

[0051] By way of example, the method further includes: coupling the first transistor and the second transistor as a current source.

[0052] For example, the method further comprises:

[0053] configuring the output current of the first transistor to be k times the output current of the second transistor; and

[0054] The transconductance of the third transistor is configured to be k times the transconductance of the fourth transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0056] Figure 1 is an example block diagram of a ring oscillator and a correction circuit according to an embodiment of the present invention;

[0057] Figure 2 According to an exemplary embodiment of the present invention Figure 1 Block diagram of the reference voltage generator in FIG.

[0058] Figure 3 is an exemplary block diagram of a ring oscillator and a correction circuit according to another embodiment of the present invention;

[0059] Figure 4 yes Figure 3 Equivalent circuit diagram of the circuit in;

[0060] Figure 5 yes Figure 3 , Figure 4 Equivalent circuit diagram of the compensation circuit in;

[0061] Figure 6 is an exemplary circuit diagram of a compensation circuit according to another embodiment of the present invention; and

[0062] Figure 7 is an example block diagram of a ring oscillator according to an example embodiment of the present invention. DETAILED DESCRIPTION

[0063] Figure 1 1 is a block diagram of a ring oscillator 102 and a correction circuit 104 according to an exemplary embodiment of the present invention. The correction circuit 104 provides body bias signals NW and PW for the N-well and P-well of transistors in the ring oscillator 102, respectively. The correction circuit 104 includes a phase and frequency detector (PFD) 106, a reference voltage generator 108, a first voltage regulator 110, and a second voltage regulator 112.

[0064] The PFD 106 receives an oscillating signal from the ring oscillator 102 at a first input terminal A and receives a reference signal at a second input terminal B. The reference signal may include a clock signal provided by a crystal oscillator (not shown). The PFD 106 detects a difference in phase and frequency between the oscillating signal and the reference signal and generates an output signal representing the difference. The output signal from the PFD 106 indicates whether the frequency of the oscillating signal is higher or lower than the frequency of the reference signal. The output signal from the PFD 106 is provided to a reference voltage generator 108.

[0065] The reference voltage generator 108 generates first and second reference voltages in response to the output signal from the PFD 106, and provides the reference voltages to the first and second voltage regulators 110 and 112, respectively. The first and second voltage regulators 110 and 112 then use the respective first and second reference voltages to generate first and second bias signals (PW and NW).

[0066] Figure 2 is a block diagram of a reference voltage generator 108 according to an exemplary embodiment of the present invention. In a digital implementation, the reference voltage generator 108 includes a filter 202 and a digital-to-analog converter (DAC) 204. The filter 202 may be implemented as a digital filter, which receives the output signal from the PFD 106 and generates a filtered output signal for conversion by the DAC 204. The digital filter 202 performs a predetermined algorithm operation on the output signal from the PFD 106 to provide the required compensation and / or calculation to the output signal from the PFD 106. The DAC 204 receives the filtered output signal and converts it into a first reference voltage signal and / or a second reference voltage signal, which are provided to the first voltage regulator 110 and the second voltage regulator 112, respectively. However, the reference voltage generator 108 may be implemented as an analog circuit, which will be combined with the following Figure 3 Please explain.

[0067] The first and second voltage regulators 110 and 112 receive the first and second reference voltages, respectively, and generate the first and second regulated voltages (i.e., the first and second body bias signals). The first and second regulated voltages are provided to the ring oscillator 102 to serve as bias voltages for the N-well and P-well of transistors in the ring oscillator 102. Preferably, the first and second voltage regulators 110 and 112 are low dropout voltage regulators (Low Dropout Voltage Regulator, LDO).

[0068] As described above, the phase and frequency of the oscillation signal from the ring oscillator 102 are monitored. The detected differences / fluctuations in phase and frequency indicate that the bias voltages of the transistors of the ring oscillator 102 need to be adjusted to stabilize the operation of the oscillator 102. The output signals from the PFD 106 representing the differences are used to generate the adjusted bias voltages. The well bias voltages of the transistors are dynamically corrected to stabilize the performance of the ring oscillator.

[0069] Figure 3 FIG. 1 shows a ring oscillator 102 and a correction circuit 302 according to another embodiment of the present invention, wherein the reference voltage generator is implemented by an analog circuit. Figure 3 In, with Figure 1 The correction circuit 302 includes the PFD 106 , a first voltage generator 304 , a second voltage generator 306 , a first voltage regulator 110 , a second voltage regulator 112 , and a compensation circuit 308 .

[0070] The PFD 106 has a first output terminal QA and a second output terminal QB. The first output signal at the first output terminal QA indicates that the frequency of the oscillating signal is higher than the frequency of the reference signal, and the second output signal at the second output terminal QB indicates that the frequency of the oscillating signal is lower than the frequency of the reference signal.

[0071] The first voltage generator 304 includes a first voltage source 310, a second voltage source 312, and an output terminal 314. The first voltage generator 304 further includes a first switch SW1 and a second switch SW2, which are connected in series between the first and second voltage sources 310, 312. The output terminal 314 is coupled between the first switch SW1 and the second switch SW2. The first switch SW1 operates in response to the first output signal QA, and the second switch SW2 operates in response to the second output signal QB. When the first switch SW1 is closed in response to the first output signal QA from the PFD 106, the first voltage source 310 is coupled to the output terminal 314. When the second switch SW2 is closed in response to the second output signal QB from the PFD, the second voltage source 312 is coupled to the output terminal 314.

[0072] The second voltage generator 306 generates a second reference voltage from the first reference voltage. In this embodiment, the second reference voltage generated by the second voltage generator 306 is a portion of the source voltage, which is the source voltage minus the first reference voltage.

[0073] The compensation circuit 308 is coupled between the first voltage generator 304 and the first voltage regulator 110. The compensation circuit 308 is used to compensate for the pole caused by the first voltage regulator 110 and the second voltage regulator 112 in the loop. The compensation circuit 308 includes a first capacitor C0, which is coupled between the output terminal 314 of the first voltage generator 304 and the ground. The compensation circuit 308 further includes a first current source KI and a second current source I, both of which are coupled to the supply voltage VDD. In one embodiment, the first current source KI and the second current source I are implemented as a first transistor and a second transistor, both of which are connected as source followers. The output current of the first transistor KI is k times the output current of the second transistor I. The compensation circuit 308 includes a third transistor KM1 and a fourth transistor M1. The third transistor KM1 is coupled between the first transistor KI and the ground, and the fourth transistor M1 is coupled between the second transistor I and the ground. In this embodiment, the transconductance of the third transistor KM1 is k times the transconductance of the fourth transistor M1. The compensation circuit 308 further includes a second capacitor C1, one end of which is coupled to a node between the first transistor KI and the third transistor KM1, and a second end of which is coupled to a node between the second transistor I and the fourth transistor M1. In addition, the second end of the second capacitor C1 is also connected to the gates of the third transistor KM1 and the fourth transistor M1.

[0074] Figure 4 yes Figure 3 FIG. 1 is an equivalent circuit diagram of an amplifier system of the ring oscillator 102 and the correction circuit 302 in FIG. In the amplifier system, the other circuits except the compensation circuit 308 are equivalent to an amplifier gm1, which receives an input voltage V in And provide output voltage V out As described above, the first transistor KI provides the current KI, and the second transistor I provides the current I. The third transistor KM1 has a transconductance Kgm2, the fourth transistor M1 has a transconductance gm2, and the second capacitor C1 has a capacitance C.

[0075] Figure 5 yes Figure 3 and Figure 4 The equivalent circuit diagram of the compensation circuit 308 in FIG. Figure 5 In the equation, the equivalent current I X It can be defined as:

[0076] I X =(1+K)×gm2×V1;

[0077] Where V1 is the equivalent voltage of the circuit. The equivalent voltage V X The relationship between the equivalent input voltage V1 is given by:

[0078] V1=V X -gm2×V1×(1 / sC).

[0079] The equivalent output resistance of the circuit can be defined as:

[0080] V X / I X =1 / ((1+K)×gm2)+1 / ((1+K)×sC.

[0081] thereby, Figure 3 The output voltage of the circuit is given by:

[0082] V out =gm1×V in ×(1 / ((1+K)×gm2)+1 / ((1+K)×sC).

[0083] The above equation shows that the capacitance C of the second capacitor C1 is amplified by 1+K times. Therefore, the compensation circuit 308 provides a series resistance of 1 / ((1+K)×gm2) for compensation.

[0084] The second capacitor C1 is coupled between the first branch of the first transistor KI and the third transistor KM1 and the second branch of the second transistor I and the fourth transistor M1, and is amplified by 1+K times to compensate for the pole introduced by the first and second voltage regulators 110, 112. Thus, the second capacitor C1 itself does not need to be very large, thereby saving circuit area and design cost.

[0085] Now go to Figure 6, which shows a circuit diagram of a compensation circuit 602 according to another embodiment of the present invention. The compensation circuit 602 uses a two-stage amplifier circuit to amplify the capacitance of the second capacitor C1, which allows the capacitance to be amplified without the need for a very large transistor. The compensation circuit 602 includes a first transistor 604 marked as M2, a second transistor I1, a third transistor marked as K1M1, a fourth transistor M1, a fifth transistor 606 marked as M2, a sixth transistor M3, a seventh transistor marked as K2M2, and an eighth transistor marked as K2M3. The second transistor I1 is coupled as a current source to provide a current I1. The current I1 is amplified K1 times by the third transistor K1M1, so that the current flowing through the first transistor 604 marked as M2 is K1I1. The compensation circuit 602 also includes a fifth transistor 606, which is also marked as M2 because it is coupled as a mirror image of the first transistor 604 and is the same as the first transistor 604. The sixth transistor M3 is coupled between the fifth transistor 606 and the ground. The fifth transistor 606 mirrors the current K1I1, so that the current flowing through the sixth transistor M3 is K1I1. The compensation circuit 602 includes an additional amplifier stage, which includes a seventh transistor K2M2 and an eighth transistor K2M3. The current K1I1 flowing through the sixth transistor M3 is amplified by K2 times by the additional amplifier stage, so that the amplified current flowing through the seventh transistor K2M2 is K2K1I1. One end of the second capacitor C1 is coupled to the node between the seventh and eighth transistors K2M2 and K2M3, and the other end is coupled to the node between the second transistor I1 and the fourth transistor M2. According to the compensation circuit 602, the capacitance of the second capacitor C1 is amplified by 1+K1×K2 times. This two-stage amplification avoids the requirement to make the transistor particularly large when there is a greater need for amplification.

[0086] Figure 7 1 is a block diagram of a ring oscillator 102 according to an exemplary embodiment of the present invention. Generally, a ring oscillator includes a plurality of inverters connected in series, each inverter including a PMOS transistor and an NMOS transistor. Figure 7 In the embodiment shown, the ring oscillator 102 includes N physically dispersed parts. Each of the parts includes one or more transistor cells. The parts are electrically connected, for example, by wiring in a metal layer. The ring oscillator can be implemented as interlaced with other circuit cells. Necessary circuit cells can be arranged in the space between the parts of the ring oscillator to save layout area. This is particularly beneficial when considering that the transistors of the ring oscillator should be arranged far enough to avoid interference and well proximity effects.

[0087] The distributed configuration of the ring oscillator smoothes out differences in the silicon process. That is, it is understood that the temperature, IR drop, aging, etc. of the circuit vary from region to region in different applications, so that the ring oscillator portions in different physical locations, and in some cases portions associated with specific logic modules, will experience performance degradation, which will affect the operation of the ring oscillator portions to varying degrees. By combining the various ring oscillator portions into a complete ring oscillator, the operational differences can be averaged. By Figure 1 and Figure 3 The bias voltage generated by the correction circuit shown will reflect this effect and will adjust the well bias when applied to the oscillator section. Adjustment of the bias voltage is thereby facilitated.

[0088] According to various embodiments, correction circuit 104 detects phase and frequency variations of the oscillation signal of ring oscillator 102. Such variations reflect the need for body biasing. The detected variations are provided to generate adjusted body bias voltages for the N-well and P-well, respectively, in the transistors of ring oscillator 102. Since the bias voltages are generated in response to variations in the oscillation signal, the biasing will be accurate and dynamic.

[0089] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art to form a clear understanding of and implement the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0090] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and other positional relationships may be substituted when the orientation of the device changes during manufacture or operation. As mentioned above, those positional relationships are described only for the sake of clarity and are not limiting.

[0091] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and non-restrictive. In the drawings, the dimensions of the various elements may be exaggerated for illustrative purposes and may not be drawn to a specific scale. This description should also include discontinuous changes in tolerances and properties of various components and working methods. Various weakened implementations of the invention should also be included.

[0092] The word "comprising" as used in the present description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form such as "a", "an" is used to refer to a definite or indefinite element, the plural form of the element shall be included. Thus, the word "comprising" should not be understood as being limited to the items listed thereafter, nor should it be understood as excluding other elements or steps; the scope of the description "a device comprises items A and B" should not be limited to a device comprising only elements A and B. The description indicates that, for the purpose of this description, only elements A and B of the device are relevant.

[0093] It will be apparent to those skilled in the art that various detailed changes may be made without departing from the scope of the claims of the present invention.

Claims

1. A correction circuit for body bias, characterized in that include: a phase detector having an input configured to receive an oscillating signal from the ring oscillator, the phase detector configured to provide an output signal representative of a phase difference between the oscillating signal and a reference signal; a first voltage generator configured to generate a first reference voltage using an output signal of the phase detector; A first voltage regulator receives a first reference voltage and generates a first regulated voltage using the first reference voltage as a first bias voltage; A second voltage generator configured to generate a second reference voltage using the first reference voltage; a second voltage regulator receiving a second reference voltage and using the second reference voltage to generate a second regulated voltage as a second bias voltage; The first bias voltage is provided for biasing the P-well of the transistor of the ring oscillator, and the second bias voltage is provided for biasing the N-well of the transistor of the ring oscillator.

2. The correction circuit according to claim 1, characterized in that: The phase detector comprises a first output terminal and a second output terminal, wherein: The first output signal at the first output terminal indicates that the frequency of the oscillation signal is higher than the frequency of the reference signal; and The second output signal at the second output terminal indicates that the frequency of the oscillation signal is lower than the frequency of the reference signal.

3. The correction circuit according to claim 1, characterized in that: Further included is a compensation circuit coupled between the first voltage generator and the first voltage regulator.

4. The correction circuit according to claim 3, characterized in that: The compensation circuit includes: A first transistor coupled to a supply voltage; A second transistor coupled to a supply voltage; a third transistor coupled between the first transistor and ground; a fourth transistor coupled between the second transistor and ground; and The capacitor is coupled between a node between the first and third transistors and a node between the second and fourth transistors.

5. The correction circuit according to claim 4, characterized in that: The first transistor and the second transistor are coupled to form a current source.

6. A method for correcting body bias of a ring oscillator, characterized in that: The ring oscillator includes a plurality of transistors, and the method includes: The phase detector detects the phase difference between the oscillation signal of the ring oscillator and the reference signal, and provides a phase detector output signal representing the phase difference; generating a first reference voltage by a first voltage generator using an output signal of the phase detector; generating, by a first voltage regulator, a first regulated voltage as a first bias voltage using a first reference voltage; generating a second reference voltage by a second voltage generator using the first reference voltage; generating, by a second voltage regulator, a second regulated voltage using a second reference voltage as a second bias voltage; biasing a P-well of a transistor of the ring oscillator using a first bias voltage; and The N-well of the transistor of the ring oscillator is biased using a second bias voltage.

7. The method according to claim 6, characterized in that Detecting the phase difference and providing a phase detector output signal includes: providing a first output signal at a first output terminal of the phase detector, which indicates that the frequency of the oscillating signal is higher than the frequency of the reference signal; and A second output signal is provided at a second output terminal of the phase detector, which indicates that the frequency of the oscillating signal is lower than the frequency of the reference signal.

8. The method according to claim 6, characterized in that Further including: A compensation circuit is coupled between the first voltage generator and the first voltage regulator.

9. The method according to claim 8, characterized in that The coupling compensation circuit includes: coupling the first transistor to a supply voltage; coupling the second transistor to a supply voltage; coupling the third transistor between the first transistor and ground; coupling the fourth transistor between the second transistor and ground; and A capacitor is coupled between a node between the first and third transistors and a node between the second and fourth transistors.

10. The method according to claim 9, characterized in that Further including: The first transistor and the second transistor are coupled as a current source.

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