Display device

Abstract

A display device is provided. The display device includes an input sensing circuit. The input sensing circuit includes a plurality of sensors, a dummy line disposed on the periphery of the plurality of sensors, and a dummy pattern disposed between two adjacent sensors among the plurality of sensors. At least one of the plurality of sensors is a cut sensor having a partially cut shape compared to other sensors, and the dummy line and the dummy pattern are arranged adjacent to the cut sensor. The dummy line is electrically connected to the dummy pattern.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2018-0091199, filed on August 6, 2018, and all the benefits therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure herein relates to a display device having a partially curved display area, and more particularly, to a display device having an excellent capability of sensing an externally applied input. Background Art

[0003] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles, etc. Input devices of the display devices include keyboards and mice, etc. In addition, the display devices include input sensing circuits as input devices.

[0004] The display device can recognize a human finger or the like that contacts the screen through an input sensing circuit. A touch detection method for the input sensing circuit includes various methods such as a resistance method, an optical method, a capacitance method, an ultrasonic method, etc. Here, according to the capacitance method, it is determined whether a touch occurs by using a capacitance that changes when a touch generating device contacts the screen of the display device.

[0005] The display area of ​​the display device may have not only a rectangular shape but also a curved shape. Due to such a modified shape, some sensors included in the input sensing circuit are cut off. Therefore, a part of the input sensing circuit may have a different input detection sensitivity from another part. Summary of the invention

[0006] The present disclosure provides a display device including an input sensing circuit having uniform input sensing capability for each area.

[0007] Embodiments of the inventive concept provide a display device including a display panel in which a display area and a non-display area are defined, and an input sensing circuit disposed on the display panel.

[0008] In an embodiment, the input sensing circuit may include a plurality of sensors, a dummy line, and a plurality of dummy patterns.

[0009] In an embodiment, the plurality of sensors may include a plurality of first sensors and a plurality of second sensors respectively capacitively coupled to adjacent first sensors among the plurality of first sensors, wherein the plurality of sensors may overlap with the display area.

[0010] In an embodiment, the dummy line may be disposed on a periphery of the plurality of sensors, may extend along a portion of a boundary between the display area and the non-display area, and may be insulated from the plurality of sensors.

[0011] In an embodiment, each of the plurality of dummy patterns may be disposed between two adjacent sensors among the plurality of sensors, and at least a portion of the plurality of dummy patterns may be electrically connected to a dummy line.

[0012] In an embodiment, the dummy line may overlap the non-display area.

[0013] In an embodiment, an area of ​​at least one sensor among the plurality of sensors adjacent to a boundary between the display area and the non-display area may be about 10% to about 49% of areas of the other sensors.

[0014] In an embodiment, the display area may include: a first display area having a first area; a second display area having a second area smaller than the first area and extending from the first display area; and a third display area having a third area smaller than the first area, extending from the first display area and separated from the second display area.

[0015] In an embodiment, in the input sensing circuit, a first input sensing area overlapping the first display area, a second input sensing area overlapping the second display area, and a third input sensing area overlapping the third display area may be defined. A dummy line may be provided between the second input sensing area and the third input sensing area.

[0016] In an embodiment, the input sensing circuit may further include a connection line connecting one sensor disposed in the second input sensing region among the plurality of sensors to one sensor disposed in the third input sensing region among the plurality of sensors.

[0017] In an embodiment, the direction along which the connection line extends may be the same as the direction along which the dummy line extends.

[0018] In an embodiment, a dummy line may be disposed adjacent to a connection line.

[0019] In an embodiment, a dummy line may be provided between the connection line and the plurality of sensors.

[0020] In an embodiment, the dummy line may include molybdenum, and the plurality of sensors and the plurality of dummy patterns may include indium tin oxide.

[0021] In an embodiment of the inventive concept, a display device includes a display panel, a dummy line, an insulating layer, a sensor unit, and a plurality of dummy patterns.

[0022] In an embodiment, a display area and a non-display area may be defined in the display panel.

[0023] In an embodiment, the dummy line may be disposed on the display panel, may overlap the non-display area, and may extend along a portion of a boundary between the display area and the non-display area.

[0024] In an embodiment, an insulating layer may be disposed on the display panel while covering the dummy line, and may define a contact hole exposing a portion of the dummy line.

[0025] In an embodiment, the sensor unit may include a plurality of sensors arranged on an insulating layer, wherein each of the plurality of sensors may be capacitively coupled with other adjacent sensors.

[0026] In an embodiment, each of the plurality of dummy patterns may be disposed between adjacent first and second sensors among the plurality of sensors, and at least a portion of the plurality of dummy patterns may be electrically connected to a dummy line via a contact hole.

[0027] In an embodiment, the dummy line may be insulated from the plurality of sensors.

[0028] In an embodiment, the plurality of sensors may include: a plurality of first normal sensors, each of the plurality of first normal sensors having a first area; a plurality of second normal sensors, each of the plurality of second normal sensors having a second area that is half of the first area; and a plurality of atypical sensors, each of the plurality of atypical sensors having a third area that is different from the first area and the second area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept, and are included in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0030] Figure 1 is a perspective view showing a display device according to an embodiment of the inventive concept;

[0031] FIG. 2A to FIG. 2D is a cross-sectional view of a display device according to an embodiment of the inventive concept;

[0032] Figure 3 is a plan view showing a display panel according to an embodiment of the inventive concept;

[0033] Figure 4 is a diagram showing an equivalent circuit of a pixel according to an embodiment of the inventive concept;

[0034] Figure 5The example shows the application to Figure 4 The pixel signal;

[0035] Figure 6 is a cross-sectional view of a portion of a pixel according to an embodiment of the inventive concept;

[0036] Fig. 7A is a plan view showing an input sensing circuit according to an embodiment of the inventive concept;

[0037] Figure 7B yes Fig. 7A An enlarged view of portion AA shown in FIG.

[0038] Figure 7C yes Figure 7B An enlarged view of the portion BB shown in FIG.

[0039] Fig. 8A yes Fig. 7A An enlarged view of a portion of FF shown in FIG.

[0040] Figure 8B Shown along Fig. 8A A portion of the cross section taken along line II′;

[0041] Fig.9A yes Fig. 7A An enlarged view of a portion of EE shown in FIG.

[0042] Fig. 9B Shown along Fig.9A A portion of a cross section taken along line II-II′; and

[0043] Fig.10 and Fig.11 A display device according to an embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0045] In the drawings, proportions and sizes of elements are exaggerated for clarity of explanation.As used herein, the term "and / or" includes any combination that can be defined by the relevant elements.

[0046] It will be further understood that when the terms "include", "comprising", etc. are used in this specification, it means the presence of the stated features, numbers, steps, operations, elements, components or their combinations, but does not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components or their combinations.

[0047] Figure 1 is a perspective view illustrating a display device DD according to an embodiment of the inventive concept.

[0048] Figure 1 The display device DD is exemplarily shown as a smart phone. However, the display device DD is not limited thereto, and thus the display device DD may be a large-sized electronic device such as a TV or a monitor, or a small or medium-sized electronic device such as a mobile phone, a tablet computer, a car navigation system, a game console, or a smart watch.

[0049] A display area DA and a non-display area NDA may be defined in the display device DD.

[0050] The display area DA in which the image IM is displayed is parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display area DA (i.e., the thickness direction of the display device DD) is represented by the third direction axis DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each component are divided by the third direction axis DR3. However, the directions indicated by the first direction axis DR1 to the third direction axis DR3 are relative and can therefore be changed to other directions. In the following, the first direction to the third direction represented by the first direction axis DR1 to the third direction axis DR3 are represented by the same reference numerals.

[0051] The display area DA may include a first display area DA1 , a second display area DA2 , and a third display area DA3 .

[0052] In an embodiment of the inventive concept, a main image desired by a user may be displayed in the first display area DA1. Figure 1 A clock window and an icon are exemplarily shown as the main image.

[0053] The second display area DA2 may extend from the first display area DA1 and may display a sub image. Figure 1 An image corresponding to the reception state of the antenna is exemplarily shown as a sub-image displayed in the second display area DA2.

[0054] The third display area DA3 may extend from the first display area DA1, may be spaced apart from the second display area DA2, and may display a sub image. Figure 1 An image corresponding to the remaining capacity of the battery and an image corresponding to the current time are exemplarily shown as sub images displayed in the third display area DA3.

[0055] A portion of the second display area DA2 and a portion of the third display area DA3 may have a curved shape. Figure 1 It is exemplarily shown that a portion of the second display area DA2 close to the third display area DA3 has a curved shape, and a portion of the third display area DA3 close to the second display area DA2 has a curved shape. Figure 1The shape of the display area DA shown in may be referred to as a groove shape in the present disclosure.

[0056] In an embodiment of the inventive concept, an area of ​​the second display area DA2 and an area of ​​the third display area DA3 may be smaller than an area of ​​the first display area DA1.

[0057] Figure 1 The shape of the display area DA shown in FIG. 1 is exemplary and thus may be modified as needed.

[0058] The non-display area NDA is adjacent to the display area DA and does not display the image IM. A bezel area of ​​the display device DD may be defined by the non-display area NDA.

[0059] The non-display area NDA may surround the display area DA. However, embodiments of the inventive concept are not limited thereto, and thus the shape of the display area DA and the shape of the non-display area NDA may be relatively designed.

[0060] FIG. 2A to FIG. 2D is a cross-sectional view of a display device DD according to an embodiment of the inventive concept. FIG. 2A to FIG. 2D A cross section defined by the second direction axis DR2 and the third direction axis DR3 is shown. FIG. 2A to FIG. 2D The cross sections are simply shown to clarify the stacking of functional panels and / or functional components included in the display device DD.

[0061] like Figure 2A As shown in FIG. 1 , the display device DD may include a display panel DP, an input sensing circuit ISC, an anti-reflection member RPP, and a window member WP. The input sensing circuit ISC may be directly disposed on the display panel DP. The term “directly disposed” used herein means that no additional adhesive layer / adhesive member is disposed between the two components.

[0062] The display panel DP and the input sensing circuit ISC directly disposed on the display panel DP may be defined as a display module DM. An optically transparent adhesive member OCA is disposed between the display module DM and the anti-reflection member RPP and between the anti-reflection member RPP and the window member WP.

[0063] The display panel DP generates an image, and the input sensing circuit ISC obtains coordinate information of an external input (e.g., a touch event). Although not shown, the display module DM according to an embodiment of the inventive concept may further include a protective member disposed under the display panel DP. The protective member and the display panel DP may be bonded by an adhesive member. FIG. 2B to FIG. 2D The display device DD shown in FIG. 1 may further include a protection member.

[0064] The display panel DP according to an embodiment of the inventive concept may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. The display panel DP is described below as an organic light-emitting display panel.

[0065] The anti-reflection member RPP reduces reflectivity of external light incident on the window member WP. The anti-reflection member RPP according to an embodiment of the inventive concept may include a retarder and a polarizer.

[0066] The anti-reflection member RPP according to an embodiment of the inventive concept may include a color filter.

[0067] The window member WP according to an embodiment of the inventive concept includes a base film WP-BS and a light shielding pattern WP-BZ. The base film WP-BS may include a glass substrate and / or a synthetic resin film. The base film WP-BS is not limited to a single layer. The base film WP-BS may include two or more films bonded by an adhesive member.

[0068] The light blocking pattern WP-BZ partially overlaps the base film WP-BS. The light blocking pattern WP-BZ may be disposed on the rear surface of the base film WP-BS to define a bezel area (ie, a non-display area NDA) of the display device DD.

[0069] FIG. 2B to FIG. 2D The light shielding pattern WP-BZ and the base film WP-BS are not separately shown.

[0070] like Figure 2B As shown in , the display device DD may include a display panel DP, an input sensing circuit ISC, an anti-reflection member RPP, and a window member WP.

[0071] The display panel DP and the anti-reflection member RPP may be combined by an optically transparent adhesive member OCA. The anti-reflection member RPP and the input sensing circuit ISC may be combined by an optically transparent adhesive member OCA. The input sensing circuit ISC and the window member WP may be combined by an optically transparent adhesive member OCA.

[0072] Reference Figure 2C ,and Figure 2B Compared with the stacked structure shown in , the positions of the anti-reflection member RPP and the input sensing circuit ISC are exchanged with each other.

[0073] like Figure 2DAs shown in , the bonding member may not be provided in the display device DD, and the display panel DP, the input sensing circuit ISC, the anti-reflection member RPP and the window member WP may be formed by a continuous process. In another embodiment of the inventive concept, the stacking order of the input sensing circuit ISC and the anti-reflection member RPP may be changed.

[0074] The input sensing circuit ISC may be a touch sensing circuit for sensing a user's touch, or may be a fingerprint sensing circuit for sensing fingerprint information of a user's finger.

[0075] Figure 3 is a plan view showing a display panel DP according to an embodiment of the inventive concept.

[0076] The display panel DP includes a display area DP-DA and a non-display area DP-NDA in a plane. In this embodiment, the non-display area DP-NDA may be defined along an edge of the display area DP-DA. The display area DP-DA and the non-display area DP-NDA of the display panel DP may correspond to Figure 1 4 shows a display area DA and a non-display area NDA of the display device DD shown in FIG.

[0077] The display area DP-DA may include a first display area DP-DA1, a second display area DP-DA2, and a third display area DP-DA3.

[0078] The first display area DP-DA1 may correspond to Figure 1 The first display area DA1 and the second display area DP-DA2 may correspond to Figure 1 The second display area DA2 and the third display area DP-DA3 may correspond to Figure 1 The third display area DA3.

[0079] The display panel DP may include a scan driving unit 100, a data driving unit 200, a plurality of scan lines SL, a plurality of emission control lines ECL, a plurality of data lines DL, a plurality of power lines PL, and a plurality of pixels PX (hereinafter referred to as pixels). The pixels PX are arranged in the display area DP-DA. Each of the pixels PX includes an organic light emitting diode (OLED, see Figure 4 , hereinafter also referred to as "organic light emitting element") and a pixel circuit CC connected to the organic light emitting diode (see Figure 4 ).

[0080] The scan driving unit 100 may include a scan driving unit and an emission control driving unit.

[0081] The scan driving unit generates scan signals and sequentially outputs the generated scan signals to the scan lines SL. The emission control driving unit generates emission control signals and outputs the generated emission control signals to the emission control lines ECL.

[0082] In another embodiment of the inventive concept, the scan driving unit and the emission control driving unit may be constructed as a single circuit instead of being separated from each other in the scan driving unit 100 .

[0083] The scan driving unit 100 may include a plurality of thin film transistors formed by the same process as that for the driving circuit of the pixel PX, for example, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process.

[0084] The data driving unit 200 outputs a data signal to the data line DL. The data signal is an analog voltage corresponding to a grayscale value of a plurality of pieces of image data.

[0085] In an embodiment of the inventive concept, the data driving unit 200 may be mounted on the printed circuit board FPCB, and the printed circuit board FPCB may be connected to a pad (hereinafter, may also be referred to as a pad) arranged at one side of the data line DL. However, the embodiment of the inventive concept is not limited thereto, and therefore, the data driving unit 200 may be directly mounted on the display panel DP.

[0086] The scan lines SL may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0087] The emission control lines ECL may extend in the first direction DR1 and may be arranged in the second direction DR2. That is, each of the emission control lines ECL may be disposed in parallel with a corresponding scan line among the scan lines SL.

[0088] The data lines DL extend in the second direction DR2 and are arranged in the first direction DR1. The data lines DL may provide data signals to corresponding pixels PX.

[0089] The power lines PL extend in the second direction DR2 and are arranged in the first direction DR1. The power lines PL may supply the first power source ELVDD to the corresponding pixels PX.

[0090] Each of the pixels PX is connected to a corresponding scan line among the scan lines SL, a corresponding emission control line among the emission control lines ECL, a corresponding data line among the data lines DL, and a corresponding power line among the power lines PL.

[0091] Figure 4 is a diagram illustrating an equivalent circuit of a pixel PX according to an embodiment of the inventive concept. Figure 5The emission control signal Ei and the scan signals Si-1, Si, and Si+1 applied to the pixel PX are exemplarily shown. Figure 4 The pixel PX connected to the i-th scan line SLi and the i-th emission control line ECLi is exemplarily shown.

[0092] The pixel PX may include an organic light emitting element OLED and a pixel circuit CC. The pixel circuit CC may include a capacitor CP and a plurality of transistors T1 to T7. The pixel circuit CC controls the amount of current flowing through the organic light emitting element OLED in response to a data signal.

[0093] The organic light emitting element OLED may emit light of predetermined brightness according to the amount of current supplied from the pixel circuit CC. To this end, the level of the first power source ELVDD may be set higher than the level of the second power source ELVSS.

[0094] Each of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In the present disclosure, for convenience, one of the input electrode and the output electrode may be referred to as a first electrode, and the other may be referred to as a second electrode.

[0095] A first electrode of the first transistor T1 is connected to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode electrode of the organic light emitting element OLED via the sixth transistor T6. The first transistor T1 may be referred to as a driving transistor in the present disclosure.

[0096] The first transistor T1 controls the amount of current flowing through the organic light emitting element OLED in response to a voltage applied to the control electrode.

[0097] The second transistor T2 is connected between the data line DL and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the second transistor T2 is turned on to electrically connect the data line DL to the first electrode of the first transistor T1.

[0098] The third transistor T3 is connected between the control electrode of the first transistor T1 and the second electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the third transistor T3 is turned on to electrically connect the control electrode and the second electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is diode-connected.

[0099] The fourth transistor T4 is connected between the node ND and the initialization power generation unit (not shown). The control electrode of the fourth transistor T4 is connected to the (i-1)th scan line SLi-1. When the (i-1)th scan signal Si-1 is provided to the (i-1)th scan line SLi-1, the fourth transistor T4 is turned on to provide the initialization voltage Vint to the node ND.

[0100] The fifth transistor T5 is connected between the power line PL and the first electrode of the first transistor T1. A control electrode of the fifth transistor T5 is connected to the i-th emission control line ECLi.

[0101] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the organic light emitting element OLED. A control electrode of the sixth transistor T6 is connected to the i-th emission control line ECLi.

[0102] The seventh transistor T7 is connected between the initialization power generation unit (not shown) and the anode electrode of the organic light emitting element OLED. The control electrode of the seventh transistor T7 is connected to the (i+1)th scan line SLi+1. When the (i+1)th scan signal Si+1 is provided to the (i+1)th scan line SLi+1, the seventh transistor T7 is turned on to provide the initialization voltage Vint to the anode electrode of the organic light emitting element OLED.

[0103] The seventh transistor T7 can improve the black reproduction capability of the pixel PX. In detail, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the organic light emitting element OLED is discharged. Therefore, when black brightness is achieved, the organic light emitting element OLED does not emit light due to the leakage current from the first transistor T1, so the black reproduction capability can be improved.

[0104] In addition, although Figure 4 The control electrode of the seventh transistor T7 is shown as being connected to the (i+1)th scan line SLi+1, but embodiments of the inventive concept are not limited thereto. In another embodiment of the inventive concept, the control electrode of the seventh transistor T7 may be connected to the i-th scan line SLi or the (i-1)-th scan line SLi-1.

[0105] Figure 4 A PMOS transistor is exemplarily shown, but the embodiments of the inventive concept are not limited thereto. In another embodiment of the inventive concept, the pixel PX may be constructed using an NMOS. In another embodiment of the inventive concept, the pixel PX may be constructed using a combination of an NMOS and a PMOS.

[0106] The capacitor CP is connected between the power line PL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. The amount of current flowing through the first transistor T1 when the fifth transistor T5 and the sixth transistor T6 are turned on may be determined according to the voltage stored in the capacitor CP.

[0107] The structure of the pixel PX is not limited to Figure 4 In another embodiment of the inventive concept, the pixel PX may be configured in various forms that allow the organic light emitting element OLED to emit light.

[0108] Reference Figure 5 , the emission control signal Ei may have a high level E-HIGH or a low level E-LOW. Each of the scan signals SLi-1, SLi, and SLi+1 may have a high level S-HIGH or a low level S-LOW.

[0109] When the emission control signal Ei has a high level E-HIGH, the fifth transistor T5 and the sixth transistor T6 are turned off. When the fifth transistor T5 is turned off, the power line PL is electrically disconnected from the first electrode of the first transistor T1. When the sixth transistor T6 is turned off, the second electrode of the first transistor T1 is electrically disconnected from the anode electrode of the organic light emitting element OLED. Therefore, when the emission control signal Ei having a high level E-HIGH is provided to the i-th emission control line ECLi, the organic light emitting element OLED does not emit light.

[0110] Thereafter, when the (i-1)th scan signal Si-1 supplied to the (i-1)th scan line SLi-1 has a low level S-LOW, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the initialization voltage Vint is supplied to the node ND.

[0111] When the i-th scan signal Si supplied to the i-th scan line SLi has the low level S-LOW, the second transistor T2 and the third transistor T3 are turned on.

[0112] When the second transistor T2 is turned on, the data signal is provided to the first electrode of the first transistor T1. Here, since the node ND is initialized by the initialization voltage Vint, the first transistor T1 is turned on. When the first transistor T1 is turned on, a voltage corresponding to the data signal is provided to the node ND. Here, the capacitor CP stores a voltage corresponding to the data signal.

[0113] When the (i+1)th scan signal Si+1 supplied to the (i+1)th scan line SLi+1 has the low level S-LOW, the seventh transistor T7 is turned on.

[0114] When the seventh transistor T7 is turned on, the initialization voltage Vint is supplied to the anode electrode of the organic light emitting element OLED, so that the parasitic capacitor of the organic light emitting element OLED is discharged.

[0115] When the emission control signal Ei supplied to the i-th emission control line ECLi has a low level E-LOW, the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the first power source ELVDD is supplied to the first electrode of the first transistor T1. When the sixth transistor T6 is turned on, the second electrode of the first transistor T1 is electrically connected to the anode electrode of the organic light emitting element OLED. Therefore, the organic light emitting element OLED generates light of a predetermined brightness according to the amount of current supplied to the organic light emitting element OLED.

[0116] Figure 6 is a pixel PX according to an embodiment of the inventive concept (see Figure 4 ) is a cross-sectional view of a portion of ). Figure 6 The first transistor T1 and the second transistor T2 are exemplarily shown, but the structures of the first transistor T1 and the second transistor T2 are not limited thereto. Figure 6 The second electrode ED2 of the first transistor T1 is shown as if it is in direct contact with the anode electrode AE ​​of the pixel PX in the cross-sectional view, but the first transistor T1 may actually be connected to the anode electrode AE ​​of the pixel PX via the sixth transistor T6. Figure 4 However, embodiments of the inventive concept are not limited thereto, and thus, in another embodiment, the second electrode ED2 of the first transistor T1 may directly contact the anode electrode AE ​​of the pixel PX.

[0117] Display panel DP (see Figure 3 ) may include a base substrate BS, a buffer layer BFL, gate insulating layers GI1 and GI2, an interlayer dielectric layer ILD, a circuit insulating layer VIA, and a pixel defining layer PDL.

[0118] The buffer layer BFL is disposed on one surface of the base substrate BS.

[0119] The buffer layer BFL prevents impurities present in the base substrate BS from being introduced into the pixel PX during a manufacturing process. Specifically, the buffer layer BFL prevents the impurities from diffusing into active portions ACL of the first transistor T1 and the second transistor T2 included in the pixel PX.

[0120] Impurities may be introduced from the outside or may be generated due to thermal decomposition of the base substrate BS. The impurities may be gas or sodium exhausted from the base substrate BS. In addition, the buffer layer BFL blocks external moisture from being introduced into the pixel PX.

[0121] The active portions ACL of the first transistor T1 and the second transistor T2 are disposed on the buffer layer BFL. Each of the active portions ACL may include polysilicon or amorphous silicon. The active portion ACL may include a metal oxide semiconductor.

[0122] The active portion ACL may include a first ion doping region and a second ion doping region and a channel region serving as a passage through which electrons or holes move, the channel region being between the first ion doping region and the second ion doping region.

[0123] The first gate insulating layer GI1 covering the active portion ACL is disposed on the buffer layer BFL. The first gate insulating layer GI1 includes an organic film and / or an inorganic film. The first gate insulating layer GI1 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0124] The control electrode GE1 of the first transistor T1 and the control electrode GE1 of the second transistor T2 are arranged on the first gate insulating layer GI1. The control electrode GE1 of the first transistor T1 may be any one of the two electrodes included in the capacitor CP. Figure 3 ) and at least a portion of the scanning line SL (see Figure 3 ) may be disposed on the first gate insulating layer GI1.

[0125] The second gate insulating layer GI2 covering the control electrode GE1 is disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 includes an organic film and / or an inorganic film. The second gate insulating layer GI2 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0126] Capacitor CP (see Figure 4 ) may be disposed on the second gate insulating layer GI2. That is, the electrode GE1 disposed on the first gate insulating layer GI1 and the electrode GE2 disposed on the second gate insulating layer GI2 may be overlapped to form Figure 4 However, the structure in which the electrodes of the capacitor CP are arranged is not limited thereto.

[0127] The interlayer dielectric layer ILD covering the electrode GE2 is disposed on the second gate insulating layer GI2. The interlayer dielectric layer ILD includes an organic film and / or an inorganic film. The interlayer dielectric layer ILD may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0128] Power line PL (see Figure 3 ) and at least a portion of the data line DL (see Figure 3At least a portion of the first transistor T1 and the second transistor T2 may be disposed on the interlayer dielectric layer ILD. The first electrode ED1 and the second electrode ED2 of each of the first transistor T1 and the second transistor T2 may be disposed on the interlayer dielectric layer ILD.

[0129] The first and second electrodes ED1 and ED2 may be connected to corresponding active portions ACL via vias passing through the first and second gate insulating layers GI1 and GI2 and the interlayer dielectric layer ILD, respectively.

[0130] A circuit insulating layer VIA covering the first electrode ED1 and the second electrode ED2 is disposed on the interlayer dielectric layer ILD. The circuit insulating layer VIA includes an organic film and / or an inorganic film. The circuit insulating layer VIA may provide a flat surface.

[0131] Pixel defining layer PDL and organic light emitting element OLED (see Figure 4 ) is arranged on the circuit insulation layer VIA. For convenience, Figure 6 Only the anode electrode AE ​​of the organic light emitting element OLED is shown. Although not shown, the organic light emitting element OLED may further include a hole transport region, an emission layer, an electron transport region, and a cathode electrode in addition to the anode electrode AE. Although not shown, the display panel DP may include a thin film encapsulation layer for encapsulating the organic light emitting element OLED.

[0132] Fig. 7A is a plan view illustrating an input sensing circuit ISC according to an embodiment of the inventive concept. Figure 7B yes Fig. 7A An enlarged view of portion AA is shown in FIG. Figure 7C yes Figure 7B An enlarged view of portion BB is shown in FIG.

[0133] An input sensing area SA may be defined in the input sensing circuit ISC, wherein an external input may be sensed in the input sensing area SA. The input sensing area SA may include a first input sensing area SA1, a second input sensing area SA2, and a third input sensing area SA3.

[0134] The first input sensing area SA1 may correspond to Figure 1 The first display area DA1 and the second input sensing area SA2 may correspond to Figure 1 The second display area DA2 and the third input sensing area SA3 may correspond to Figure 1 That is, the first input sensing area SA1 can be connected to the third display area DA3. Figure 3 The second input sensing area SA2 may overlap with the first display area DP-DA1. Figure 3 The third input sensing area SA3 may overlap with the second display area DP-DA2. Figure 3 The third display area DP-DA3 is overlapped.

[0135] The input sensing circuit ISC may include a first sensor group IEG1 and a second sensor group IEG2. In the present disclosure, the first sensor group IEG1 and the second sensor group IEG2 may be defined as a sensor unit.

[0136] The first sensor groups IEG1 may extend in the first direction DR1 and may be arranged in the second direction DR2. Each of the first sensor groups IEG1 may include a plurality of first sensors IE1. For example, the first sensor IE1 may be an Rx sensor.

[0137] The second sensor groups IEG2 may extend in the second direction DR2 and may be arranged in the first direction DR1. Each of the second sensor groups IEG2 may include a plurality of second sensors IE2. For example, the second sensor IE2 may be a Tx sensor.

[0138] In an embodiment of the inventive concept, each of the first sensor IE1 and the second sensor IE2 may include indium tin oxide or indium zinc oxide. However, the embodiment of the inventive concept is not limited thereto, and thus each of the first sensor IE1 and the second sensor IE2 may include molybdenum (Mo).

[0139] In an embodiment of the inventive concept, each of the first sensors IE1 may be capacitively coupled with an adjacent second sensor IE2 among the second sensors IE2 to form capacitance. The input sensing circuit ISC may sense a change in capacitance formed between the first sensor IE1 and the second sensor IE2 to determine whether an input is externally applied.

[0140] The dummy pattern DMP may be arranged between the first sensor IE1 and the second sensor IE2. The dummy pattern DMP may be separated from the first sensor IE1 and the second sensor IE2. The dummy pattern DMP may be insulated from the first sensor IE1 and the second sensor IE2. Since the dummy pattern DMP is arranged, the visibility of the boundary area between the first sensor IE1 and the second sensor IE2 may be reduced.

[0141] In an embodiment of the inventive concept, the dummy pattern DMP may include indium tin oxide or indium zinc oxide.

[0142] In an embodiment of the inventive concept, each of the first and second sensors IE1 and IE2 may be defined as one of a first normal sensor NIE1, a second normal sensor NIE2, and an atypical sensor TIE according to an area of ​​each of the first and second sensors IE1 and IE2.

[0143] Among the first sensor IE1 and the second sensor IE2 , a sensor having a rhombus shape and a first area may be defined as a first normal sensor NIE1 .

[0144] Among the first sensor IE1 and the second sensor IE2 , a sensor having an isosceles triangle shape and a second area that is a half of the first area may be defined as a second normal sensor NIE2 .

[0145] Among the first sensor IE1 and the second sensor IE2, a sensor having a shape obtained by removing a portion of the first normal sensor NIE1 or a portion of the second normal sensor NIE2 may be defined as an atypical sensor TIE. The atypical sensor TIE may have a third area different from the first area and the second area. For example, the third area may be about 10% to about 49% of the first area. Alternatively, the third area may be about 10% to about 49% of the second area.

[0146] A sensor defined as an atypical sensor TIE among the first sensor IE1 and the second sensor IE2 may be arranged on the periphery of the sensor unit.

[0147] Figure 7B As shown in Fig. 7A The portion AA is defined as a unit area AA in which the input sensing circuit ISC senses external input. The unit area AA includes a left first sensor IE1-1, a right first sensor IE1-2, an upper second sensor IE2-1, and a lower second sensor IE2-2.

[0148] In the unit area AA, the left first sensor IE1 - 1 and the right first sensor IE1 - 2 form capacitances with the upper second sensor IE2 - 1 and the lower second sensor IE2 - 2 .

[0149] The left first sensor IE1 - 1 and the right first sensor IE1 - 2 may be electrically connected through the first connection portion CP1 .

[0150] The upper second sensor IE2-1 and the lower second sensor IE2-2 may be electrically connected through the second connection portion CP2. The second connection portion CP2 may include a plurality of patterns P1, P2, and P3.

[0151] Each of the first and second patterns P1 and P2 may electrically connect the third pattern P3 to the upper and lower second sensors IE2 - 1 and IE2 - 2 via the first contact holes CNT1 .

[0152] An opening CP1-OP is defined in the first connection portion CP1. A third pattern P3 is disposed inside the opening CP1-OP.

[0153] Although not shown, an antistatic pattern may be connected to each of the upper second sensor IE2-1 and the lower second sensor IE2-2. The antistatic pattern may guide static electricity to the apex thereof to prevent disconnection of the second connection portion CP2.

[0154] Fig. 8A yes Fig. 7A An enlarged view of the portion FF shown in FIG. Figure 8B Shown along Fig. 8A A portion of the cross section taken along line II′.

[0155] Reference Fig. 8A , the portion FF may include the second sensor IE2, the connection pattern CNP, the dummy line DML, the first signal line SSL1, the second signal line SSL2, the antistatic line ESD, and a portion of the sealing member CS. Here, the second sensor IE2 may be an atypical sensor TIE (see Fig. 7A ).

[0156] The dummy line DML may be used to prevent adjacent lines from coupling with each other. For example, a portion of the dummy line DML may prevent the first sensor IE1 and the second sensor IE2 (see Fig. 7A ) is coupled to the first signal line SSL1. In addition, a portion of the dummy line DML may prevent the first signal line SSL1 from being coupled to the second signal line SSL2.

[0157] At least one of the dummy lines DML may be provided between the first sensor IE1 and the second sensor IE2 (see Fig. 7A ) and can be arranged along the display area DA (see Figure 1 ) and non-display area NDA (see Figure 1 ) extends from a portion of the boundary between the non-display area NDA (see FIG. Figure 1 ) overlap.

[0158] A portion of at least one of the dummy lines DML may be disposed in the second input sensing area SA2 (see Fig. 7A ) and the third input sensing area SA3 (see Fig. 7A )between.

[0159] At least one of the dummy lines DML may be disposed adjacent to the second sensor IE2 on a plane defined by the first direction DR1 and the second direction DR2.

[0160] In an embodiment of the inventive concept, the dummy line DML may include molybdenum (Mo).

[0161] The first signal line SSL1 is electrically connected to the first sensor IE1 (see Fig. 7A ). In detail, Fig. 8A The first signal line SSL1 shown in FIG. 1 may be a line for connecting one of the first sensors IE1 arranged in the second input sensing area SA2 to one of the first sensors IE1 arranged in the third input sensing area SA3. In the present disclosure, Fig. 8A The first signal line SSL1 shown in FIG. 1 may be referred to as a connection line.

[0162] Fig. 8A A single first signal line SSL1 is exemplarily shown, but embodiments of the inventive concept are not limited thereto, and thus a plurality of first signal lines SSL1 may be provided.

[0163] The second signal line SSL2 can be electrically connected to the second sensor IE2 (see Fig. 7A ) in the corresponding second sensor IE2 (see Fig. 7A ).

[0164] Reference Fig. 8A , a direction along which a portion of the first signal line SSL1 extends, a direction along which a portion of the second signal line SSL2 extends, and a direction along which a portion of the dummy line DML extends may be substantially the same.

[0165] Reference Figure 8B , the dummy line DML, the first signal line SSL1, and the second signal line SSL2 may be arranged on the base portion SUB.

[0166] In an embodiment of the inventive concept, the base portion SUB may be a thin film encapsulation layer of the display panel DP. However, the base portion SUB is not limited thereto. Therefore, in another embodiment of the inventive concept, the base portion SUB may be a film including an organic material or an inorganic material, and may be an input sensing circuit ISC (see Fig. 7A ) component.

[0167] An insulating layer PVX covering the dummy line DML, the first signal line SSL1, and the second signal line SSL2 may be disposed on the base portion SUB. The insulating layer PVX may include an inorganic material or an organic material.

[0168] A second contact hole CNT2 exposing a portion of the second signal line SSL2 may be defined in the insulating layer PVX.

[0169] The second sensor IE2 may be disposed on the insulating layer PVX. Figure 8B Only the second sensor IE2 is shown, but in an embodiment of the inventive concept, the first sensor IE1 (see Fig. 7A ) can also be set on the insulating layer PVX.

[0170] The connection pattern CNP may extend from the second sensor IE2 and may be electrically connected to the second signal line SSL2 via the second contact hole CNT2.

[0171] An anti-static line ESD may be disposed on the periphery of the second signal line SSL2 to protect components of the input sensing circuit ISC from externally applied static electricity.

[0172] The sealing member CS may be disposed on the periphery of the anti-static line ESD to protect components of the input sensing circuit ISC from externally applied moisture or oxygen.

[0173] Fig.9A yes Fig. 7A An enlarged view of part EE is shown in FIG. Fig. 9B Shown along Fig.9A A portion of the cross section taken along line II-II′.

[0174] Fig.9A At least one of the first sensor IE1 and the second sensor IE2 shown in FIG. 1 may be defined as an atypical sensor TIE (see FIG. 1 ). Fig. 7A ) sensor.

[0175] At least one of the dummy patterns DMP disposed between the first sensor IE1 and the second sensor IE2 may be electrically connected to the dummy line DML. The dummy line DML electrically connected to the dummy pattern DMP may be a dummy line disposed closest to the second sensor IE2 among the dummy lines DML. The dummy line DML may be insulated from the first sensor IE1 and the second sensor IE2.

[0176] Reference Fig. 9B The dummy pattern DMP may be connected to the dummy line DML via the third contact hole CNT3 defined in the insulating layer PVX. Therefore, the parasitic capacitance generated between the dummy pattern DMP and the dummy line DML may be removed.

[0177] In addition, since the parasitic capacitance is removed, the capacitance between the first sensor IE1 and the second sensor IE2 can be increased. Therefore, the capacitance loss due to at least one of the first sensor IE1 and the second sensor IE2 being an atypical sensor TIE can be compensated.

[0178] When the capacitance of the atypical sensor TIE is compensated, the cell area AA of the atypical sensor does not exist (see Figure 7B ) and areas where atypical sensors exist can have similar input detection sensitivity.

[0179] Furthermore, when the dummy pattern DMP and the dummy line DML are electrically connected, the amount of capacitance to be controlled becomes smaller than the amount of capacitance before the connection, and thus compensation of capacitance can be simplified.

[0180] Fig.10 and Fig.11 A display device DD1, a display device DD2, and a display device DD3 according to an embodiment of the inventive concept are shown. Various types of display devices DD1 and DD2 may be applied in a vehicle.

[0181] Fig.10 A display device DD1 used as an embedded navigator and a display device DD2 provided near a gear lever are shown as examples.

[0182] The shapes of the display device DD1 and the display device DD2 of the vehicle may be changed according to the design of the vehicle. For example, the display device DD1 used as an embedded navigator may have rounded corners, and the display device DD2 disposed near the shift lever may have a notched upper portion.

[0183] Although not shown, the rounded display device may also be used in a dashboard of a vehicle.

[0184] Here, the above-mentioned input sensing circuit ISC may be applied to the display device DD1 and the display device DD2 to impart an excellent capability of sensing an external input.

[0185] Reference Fig.11 , the display device DD3 may be a wearable device worn on a part of the human body. Fig.11 A watch type device is exemplarily shown, but embodiments of the inventive concept are not limited thereto, and thus the display device DD3 may have various forms to be worn on a user's body.

[0186] The shape of the display area DD-DA of the wearable device can be changed as needed so that the wearable device can be worn on the body. Therefore, the input sensing circuit ISC described above can be applied to the display device DD3 to impart an excellent ability to sense external input.

[0187] According to an embodiment of the inventive concept, parasitic capacitance generated by sensors and other components of an input sensing circuit is removed, so that overall uniform capacitance can be formed between sensors.

[0188] Therefore, a display device including an input sensing circuit having uniform sensitivity can be provided.

[0189] Although exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present invention as claimed.

Claims

1. A display device, comprising: A display panel, wherein a display area and a non-display area are defined in the display panel; as well as An input sensing circuit is arranged on the display panel, Wherein, the input sensing circuit comprises: A plurality of sensors, including a plurality of first sensors and a plurality of second sensors, wherein the plurality of second sensors are capacitively coupled to adjacent first sensors among the plurality of first sensors, respectively, and the plurality of sensors overlap the display area; a plurality of dummy lines disposed on peripheries of the plurality of sensors, extending along a portion of a boundary between the display area and the non-display area, and insulated from the plurality of sensors; and a plurality of dummy patterns, each of the plurality of dummy patterns being disposed between two adjacent sensors among the plurality of sensors, the plurality of dummy patterns being insulated from the plurality of sensors, and at least a portion of the plurality of dummy patterns being electrically connected to at least one of the plurality of dummy lines, The dummy line electrically connected to at least a portion of the plurality of dummy patterns is a dummy line disposed closest to the second sensor among the plurality of dummy lines.

2. The display device according to claim 1, wherein: At least one of the plurality of dummy lines overlaps the non-display area.

3. The display device according to claim 1, wherein: An area of ​​at least one sensor among the plurality of sensors adjacent to the boundary between the display area and the non-display area is 10% to 49% of areas of the other sensors.

4. The display device according to claim 1, wherein: The display area includes: A first display region having a first area; a second display region having a second area smaller than the first area and extending from the first display region; and A third display region, having a third area smaller than the first area, extends from the first display region and is spaced apart from the second display region.

5. The display device according to claim 4, in, In the input sensing circuit, a first input sensing area overlapping the first display area, a second input sensing area overlapping the second display area, and a third input sensing area overlapping the third display area are defined, Wherein, at least one of the plurality of dummy lines is disposed between the second input sensing region and the third input sensing region.

6. The display device according to claim 5, wherein: The input sensing circuit further includes a connection line connecting one sensor disposed in the second input sensing region among the plurality of sensors to one sensor disposed in the third input sensing region among the plurality of sensors.

7. The display device according to claim 6, wherein: The direction along which the connection line extends is the same as the direction along which at least one of the plurality of dummy lines extends.

8. The display device according to claim 7, wherein: At least one of the plurality of dummy lines is disposed adjacent to the connection line.

9. The display device according to claim 8, wherein: At least one of the plurality of dummy lines is disposed between the connection line and the plurality of sensors.

10. The display device according to claim 1, wherein: At least one of the plurality of dummy lines includes molybdenum, and the plurality of sensors and the plurality of dummy patterns include indium tin oxide.

Images