Non-volatile memory

Abstract

The present disclosure provides a nonvolatile memory. A nonvolatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group, and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region, and a fourth region respectively below the first memory group, the second memory group, the third memory group, and the fourth memory group. The first region includes a drive circuit connected to a memory cell of one of the second memory group, the third memory group, and the fourth memory group through a specific word line and another drive circuit connected to a memory cell of the first memory group through a first bit line, wherein the specific word line and the first bit line extend in the same horizontal direction.

Description

Technical Field

[0001] The inventive concept relates to a memory device, and more particularly, to a memory device having a cell-on-periphery (COP) structure or a periphery-on-cell (POC) structure. Background Art

[0002] Contemporary electronic devices are subject to many competing demands. Physical size, data storage capacity, data processing speed, and user-friendliness are readily available examples of these demands. Contemporary storage devices must support functional diversity and provide high data storage capacity while maintaining an appropriate size for incorporation into electronic devices. In particular, the area occupied by the overall footprint of the storage device has become an important design consideration. The need to reduce the footprint has driven memory cell integration, which in turn has driven the complexity of the layout and wiring of the components that make up the storage device. Therefore, a storage device including a non-volatile storage device is sought that provides a high integration density with a relatively simple layout and wiring design. Summary of the invention

[0003] The inventive concept provides a nonvolatile memory device of a cell-on-periphery (COP) structure or a periphery-on-cell (POC) structure that can reduce the size of a peripheral circuit area and / or provide relatively simple wiring requirements.

[0004] According to one aspect of the inventive concept, a nonvolatile memory is provided, the nonvolatile memory comprising: a first semiconductor layer vertically stacked on a second semiconductor layer and comprising a first memory group, a second memory group, a third memory group and a fourth memory group, wherein the second semiconductor layer comprises a first region, a second region, a third region and a fourth region respectively below the first memory group, the second memory group, the third memory group and the fourth memory group, the first region comprises a driving circuit connected to a memory cell of one of the second memory group, the third memory group and the fourth memory group through a specific word line and another driving circuit connected to the memory cell of the first memory group through a first bit line, wherein the specific word line and the first bit line extend in the same horizontal direction.

[0005] According to another aspect of the inventive concept, a nonvolatile memory is provided, which includes: a first semiconductor layer, vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group, wherein the second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively below the first memory group, the second memory group, the third memory group and the fourth memory group, and the first region includes a driving circuit connected to the first memory group and another driving circuit connected to one of the second memory group, the third memory group and the fourth memory group and both of the first memory group, wherein each of the first memory group and the third memory group includes a word line extending in a first horizontal direction and a bit line extending in a second horizontal direction, and each of the second memory group and the fourth memory group includes a word line extending in the second horizontal direction and a bit line extending in the first horizontal direction.

[0006] According to another aspect of the inventive concept, a nonvolatile memory is provided, which includes: a first semiconductor layer, vertically stacked on a second semiconductor layer and including a first memory group and a second memory group, wherein the second semiconductor layer includes a first region below the first memory group, a second region below the second memory group, and a peripheral region, the first memory group includes word lines extending in a first horizontal direction and bit lines extending in a second horizontal direction, the second memory group includes word lines extending in the second horizontal direction and bit lines extending in the first horizontal direction, the first region includes a first driving circuit connected to the first memory group, the second region includes a second driving circuit connected to the second memory group and a third driving circuit connected to the first memory group, and the peripheral region includes a fourth driving circuit connected to the second memory group.

[0007] According to another aspect of the inventive concept, a nonvolatile memory is provided, the nonvolatile memory comprising: 2×2 horizontally arranged tiles in a first semiconductor layer, comprising a first tile including a first memory group, a second tile including a second memory group, a third tile including a third memory group, and a fourth tile including a fourth memory group; and 2×2 arranged regions in a second semiconductor layer, comprising a first region below the first tile, a second region below the second tile, a third region below the third tile, and a fourth region below the fourth tile, wherein the first region comprises a first row decoder and a first page buffer, the first row decoder having a length equal to a length of the fourth tile in a first horizontal direction, and the first page buffer having a length equal to a length of the fourth tile in a first horizontal direction. The first area includes a second row decoder and a second page buffer, the second row decoder has a width equal to the width of the first block in the second horizontal direction, and the second page buffer has a width equal to the width of the second block in the second horizontal direction. The third area includes a third row decoder and a third page buffer, the third row decoder has a length equal to the length of the second block in the first horizontal direction, and the third page buffer has a length equal to the length of the third block in the first horizontal direction. The fourth area includes a fourth row decoder and a fourth page buffer, the fourth row decoder has a width equal to the width of the third block in the second horizontal direction, and the fourth page buffer has a width equal to the width of the fourth block in the second horizontal direction.

[0008] According to another aspect of the inventive concept, a nonvolatile memory is provided, the nonvolatile memory comprising: 2×2 horizontally arranged blocks in a first semiconductor layer, comprising a first block including a first memory group, a second block including a second memory group, a third block including a third memory group, and a fourth block including a fourth memory group; and 2×2 arranged regions in a second semiconductor layer, comprising a first region below the first block, a second region below the second block, a third region below the third block, and a fourth region below the fourth block, wherein the first region comprises a first row decoder and a first page buffer, the first row decoder having a width equal to that of the first block in a second horizontal direction, and the first page buffer having a width equal to that of the first block in a second horizontal direction. The second area includes a second row decoder and a second page buffer, the second row decoder has a length in the first horizontal direction equal to the length of the second block, the second page buffer has a length in the first horizontal direction equal to the length of the third block, the third area includes a third row decoder and a third page buffer, the third row decoder has a width in the second horizontal direction equal to the width of the third block, the third page buffer has a width in the second horizontal direction equal to the width of the fourth block, the fourth area includes a fourth row decoder and a fourth page buffer, the fourth row decoder has a length in the first horizontal direction equal to the length of the fourth block, and the fourth page buffer has a length in the first horizontal direction equal to the length of the first block.

[0009] According to another aspect of the inventive concept, a nonvolatile memory is provided, the nonvolatile memory comprising: a first semiconductor layer comprising a first memory group, a second memory group, a third memory group and a fourth memory group; and a second semiconductor layer vertically stacked on the first semiconductor layer and comprising a first region, a second region, a third region and a fourth region respectively above the first memory group, the second memory group, the third memory group and the fourth memory group, wherein the first region comprises a driving circuit connected to memory cells of one of the second memory group, the third memory group and the fourth memory group through a first word line and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and the first bit line extend in the same horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the inventive concept;

[0012] Figure 2is a perspective view of a storage device according to an embodiment of the present inventive concept;

[0013] Figure 3 It is further shown in an example Figure 2 A perspective view of a storage group;

[0014] Figure 4 According to the embodiment of the present invention Figure 3 Equivalent circuit diagram of the memory block;

[0015] Figure 5 It is to further illustrate the embodiment according to the present invention. Figure 3 A perspective view of a memory block;

[0016] Figure 6 is a perspective view of a memory device including four memory groups arranged in a first semiconductor layer stacked over a second semiconductor layer according to an embodiment of the inventive concept;

[0017] Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 The various embodiments of the present invention are shown respectively. Figure 6 an upper surface of a second semiconductor layer;

[0018] Fig.12 is another perspective view of a memory device including two memory groups arranged in a first semiconductor layer according to an embodiment of the inventive concept;

[0019] Fig.13 The embodiment according to the present invention is shown Fig.12 an upper surface of a second semiconductor layer;

[0020] Fig.14 is another perspective view of a memory device including three memory groups arranged in a first semiconductor layer according to an embodiment of the inventive concept;

[0021] Fig.15 The embodiment according to the present invention is shown Fig.12 an upper surface of a second semiconductor layer;

[0022] Fig.16 is a perspective view of a storage assembly including a plurality of storage devices according to an embodiment of the present inventive concept;

[0023] Fig.17 and Fig.18 It further shows Fig.16 corresponding plan views of different examples of arrangement structures of the second semiconductor layer;

[0024] Fig.19 and Fig. 20 are corresponding plan views of different rectangular block arrangements that may be used to configure a storage device according to an embodiment of the inventive concept;

[0025] Fig.21 is a block diagram illustrating a solid state drive (SSD) system that may include a storage device or storage component according to an embodiment of the inventive concept;

[0026] Fig. 22 is a block diagram illustrating a memory system including a memory device including a resistive memory cell array according to some embodiments of the inventive concept;

[0027] Fig.23 In one embodiment, it is further shown Fig. 22 A block diagram of a storage device;

[0028] Fig.24 In one embodiment, it is further shown Fig. 22 and Fig.23 A block diagram of a resistive memory cell array;

[0029] Fig.25 illustrates an exemplary memory group including a plurality of memory cells according to an embodiment of the inventive concept;

[0030] Fig.26A , Fig.26B and Fig.26C The embodiments according to the present invention are shown respectively. Fig.25 Examples of possible implementation variations of a resistive memory cell;

[0031] Fig.27A It shows that Fig.25 a graph of the distribution of single level (SLC) resistive memory cells used in the examples of FIG.

[0032] Fig.27B It shows that Fig.25 a graph of the distribution of multi-level (MLC) resistive memory cells used in the examples of FIG.

[0033] Fig.28 is a perspective view of a storage device according to an embodiment of the present inventive concept;

[0034] Fig.29 is a perspective view of a memory device including a second semiconductor layer stacked over a first semiconductor layer including four memory groups according to an embodiment of the inventive concept; and

[0035] Fig.30 is a diagram showing a method according to some example embodiments Fig.29 A cross-sectional view of a storage device. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the inventive concept will be described in some additional details with reference to the accompanying drawings.

[0037] Certain embodiments and embodiment features will be described using spatial, relational, and / or geometric terms such as "above," "below," "on top of," "below," "vertical," "horizontally," "stacked on," "below," "first direction," "second direction," and the like. Those skilled in the art will recognize that these and similar terms may be used according to any assumed orientation to better describe embodiment features. The use of such spatial, relational, and / or geometric terms will generally be made with reference to one or more illustrated examples. It can be seen that as the assumed geometric orientation changes, the relative spatial, relational, and / or geometric descriptions may also change.

[0038] Figure 1 is a block diagram illustrating a memory device 10 according to an embodiment of the inventive concept.

[0039] Reference Figure 1 , the memory device 10 generally includes a memory cell array 100 and a peripheral circuit 200. As an example, the peripheral circuit 200 may include a row decoder 210, a page buffer unit 220, a control logic 230, and a voltage generator 240. Although not shown in Figure 1 , but the peripheral circuit 200 may also include data input and output (I / O) circuits, input / output interfaces, column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, a mobile area controller, a scheduler and / or various test and measurement circuits.

[0040] The memory cell array 100 may be connected to the page buffer unit 220 through one or more bit lines BL, and may be connected to the row decoder 210 through one or more word lines WL, string selection lines SSL, and / or ground selection lines GSL. The memory cell array 100 will typically include a large number of memory cells arranged to be accessed through word lines, bit lines, and / or strings, etc. (e.g., according to various row / column arrangements).

[0041] In certain embodiments of the present inventive concept, the memory cell may be a flash memory cell. Hereinafter, embodiments of the present inventive concept will be described assuming that the constituent memory cells of the memory cell array are NAND flash memory cells, but this need not be the case in every embodiment of the present inventive concept. On the contrary, as will be appreciated by those skilled in the art, certain embodiments of the present inventive concept may include a memory cell that is a resistive memory cell, such as a resistive random access memory (RAM) (ReRAM), a phase change RAM (PRAM), and / or a magnetic RAM (MRAM).

[0042] In some embodiments of the present inventive concept, the memory cell array 100 may include a three-dimensional memory cell array, such as a three-dimensional memory cell array including a plurality of NAND flash memory cell strings, wherein each NAND string includes memory cells respectively connected to word lines WL vertically stacked on a main substrate, as will be described below with reference to Figure 3 , Figure 4 and Figure 5 Various three-dimensional memory cell arrays are understood by those skilled in the art, such as those described by U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and published U.S. Patent Application No. 2011 / 0233648, the common subject matter of which is incorporated herein by reference.

[0043] In other embodiments of the inventive concept, the memory cell array 100 may alternatively or additionally include a two-dimensional memory cell array.

[0044] Figure 1 The control logic 230 may be used to provide various control signals that control (or define) the properties of various data access operations, such as read operations, programming (or writing) operations, and erase operations, as well as some other operations. In this regard, the generation and use of various control signals in the operation of the storage device 10 are well understood by those skilled in the art. Exemplary control signals include a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR, which may be generated by the control logic 230 in response to a command CMD, an address ADDR, and / or a control signal CTRL received from an external source (e.g., a memory controller, a processor, or a host device—not shown). One or more externally provided control signals may be applied to the storage device 10, and / or the control logic 230 may be used to control various operations of the storage device 10.

[0045] Figure 1The voltage generator 240 can be used to generate various voltages in response to (for example) the voltage control signal CTRL_vol provided by the control logic 230, which are also used to control (or define) the properties of the data access operation. For example, the voltage generator 240 can be used to generate various word line voltages VWL (such as read voltage, program voltage, pass voltage, erase voltage, program verification voltage, erase verification voltage, etc.) used during programming, reading and erasing operations, respectively. In addition, the voltage generator 240 can be used to generate a string selection voltage and / or a ground selection voltage in response to the voltage control signal CTRL_vol provided by the control logic 230.

[0046] exist Figure 1 In the embodiment of the present invention, the row decoder 210 may be used to select a memory block, a word line WL of a selected memory block and an unselected memory block, and / or a string selection line SSL in response to a row address X-ADDR provided by the control logic 230. The page buffer unit 220 may be used to select a bit line BL in response to a column address Y-ADDR. In this regard, the page buffer unit 220 may be used as a program (or write) driver and / or a sense amplifier according to various operation modes of the memory device 10.

[0047] like Figure 2 As conceptually shown in , some embodiments of the present inventive concept may include a memory cell array including two or more memory groups (e.g., MG1, MG2, MG3, and MG4). Various material layers, features, and / or structures forming the memory cell array 100 may be arranged on (or vertically stacked on) material layers, features, and structures forming the peripheral circuit 200. Hereinafter, for simplicity of description, the various material layers, features, and / or structures forming the memory cell array 100 will be referred to as a "first semiconductor layer", which is referred to as vertically stacked on a "second semiconductor layer" including various material layers, features, and / or structures forming the peripheral circuit 200. In this regard, it is possible that in some embodiments of the present inventive concept, some relatively small peripheral circuits may be arranged in the first semiconductor layer together with the memory cell array 100, but the main or relatively large peripheral circuits will generally be arranged in the second semiconductor layer. In this regard, the peripheral circuit 200 may be arranged adjacent to the main substrate, while the memory cell array 100 may be arranged further away from the main substrate.

[0048] In some embodiments of the present inventive concept, the memory cell array 100 may include a number of "memory groups", each of which includes a plurality of memory cells accessible by operation of one or more peripheral circuits (e.g., driver circuits) in the peripheral circuits 200. More specifically, in some embodiments of the present inventive concept, the corresponding driver circuits may be arranged in a spatial arrangement and / or relationship corresponding to one or more memory groups.

[0049] It should be noted here that the continued development of semiconductor processing technology allows the number of vertically stacked word lines in a three-dimensional memory cell array to increase. By vertically stacking memory groups and, in particular, the word lines WL that make up the memory groups above the associated peripheral circuits, embodiments of the inventive concept can reduce the lateral (or horizontal) area occupied by the memory device 10. Therefore, to the greatest extent that may be reasonable, the peripheral circuit 200 should be arranged below the lateral footprint of the memory groups in the memory cell array 100 in order to minimize the lateral area occupied by the memory device 10 (e.g., the footprint on the motherboard).

[0050] Consistent with the above and Figure 2 In the embodiments of the present invention, it is further shown that multiple memory groups (MG1, MG2, MG3, and MG4) can be arranged in the first semiconductor layer L1 to effectively utilize the available lateral area, while various peripheral circuits can be arranged in the second semiconductor layer L2 to be effectively below the memory groups. In addition, in certain embodiments of the present inventive concept, at least one drive circuit operably connected to a particular memory group (e.g., MG1) can be arranged in the second semiconductor layer L2 so that it is below a different (e.g., adjacent) memory group (e.g., MG2, MG3, or MG4). Examples of such arrangements will be described below with some additional details.

[0051] Therefore, refer to Figure 2 , the memory device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, wherein the first semiconductor layer L1 is stacked on the second semiconductor layer L2 in a vertical direction VD. Given this assumed orientation for the "vertical" direction, the first semiconductor layer L1 and the second semiconductor layer L2 may be understood to extend in corresponding "horizontal" directions (i.e., in the first horizontal direction HD1 and the second horizontal direction HD2). In some embodiments, the second semiconductor layer L2 may be disposed in whole or in part on a main and horizontally disposed substrate.

[0052] It should be noted here that the first semiconductor layer L1 may be directly disposed on the second semiconductor layer L2, or there may be an intervening layer between the first semiconductor layer L1 and the second semiconductor layer L2. For example, in some embodiments of the present inventive concept, the first semiconductor layer L1 may be disposed in whole or in part on an intervening second substrate.

[0053] It is recognized that some embodiments of the present inventive concept may include a Figure 1 The memory cell array 100 and the memory cell array 100 disposed in the second semiconductor layer L2 Figure 1 In the embodiment shown, although only a single "covering layer" (e.g., the first semiconductor layer L1) including a memory cell array (or a plurality of memory groups) is described, those skilled in the art will recognize that a plurality of memory cell layers can be vertically stacked on a semiconductor layer (e.g., the second semiconductor layer L2) that mainly includes peripheral circuits.

[0054] In this regard, the second semiconductor layer L2 may include a substrate and various circuits among the peripheral circuit 200, which are formed in the second semiconductor layer L2 by a combination of semiconductor devices (such as transistors and wiring patterns). After various circuits and wirings are formed in the second semiconductor layer L2, the first semiconductor layer L1 including the memory cell array 100 may be formed, including electronic devices and corresponding wirings (such as word lines WL and bit lines BL).

[0055] like Figure 2 As shown, the first to fourth memory groups MG1 to MG4 may be arranged in the first semiconductor layer L1, wherein the first memory group MG1 and the second memory group MG2 are adjacent in the first horizontal direction HD1, the third memory group MG3 and the fourth memory group MG4 are adjacent in the first horizontal direction HD1, the first memory group MG1 and the fourth memory group MG4 are adjacent in the second horizontal direction HD2, and the second memory group MG2 and the third memory group MG3 are adjacent in the second horizontal direction HD2. This particular configuration may be referred to as a 2×2 memory group arrangement. Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 Other embodiments are described that assume this particular configuration, but the scope of the inventive concept is not limited to only this configuration.

[0056] For example, only two memory groups may be arranged in the first semiconductor layer L1, as will be described with reference to Fig.12 and Fig.13 Optionally, three memory groups may be arranged in the first semiconductor layer L1, as will be described with reference to Fig.14 and Fig.15 In addition, in some embodiments, a plurality of memory devices 10 may be arranged (eg, cascaded) in the first semiconductor layer L1, as will be described with reference to Fig.16 and Fig.17Described with some additional detail.

[0057] Figure 3 is a perspective view showing a memory group MG according to an embodiment of the inventive concept. Here, the memory group MG may correspond to Figure 2 One (or each) of the first to fourth memory groups MG1 to MG4 are shown.

[0058] Reference Figure 3 , the memory group MG may include memory blocks BLK1 to BLKi, where "i" is a positive integer. Each of the memory blocks BLK1 to BLKi may have a three-dimensional (or vertical) structure. That is, each of the memory blocks BLK1 to BLKi may include a plurality of NAND strings extending in a vertical direction VD. The NAND strings may be separated from each other in a first horizontal direction HD1 and a second horizontal direction HD2. The memory blocks BLK1 to BLKi may be provided by a row decoder ( Figure 1 For example, the row decoder 210 may select a memory block corresponding to the block address among the memory blocks BLK1 to BLKi.

[0059] Figure 4 is an equivalent circuit diagram of a memory block BLK according to an embodiment of the inventive concept. For example, the memory block BLK may correspond to Figure 3 One of a plurality of memory blocks BLK1 to BLKi.

[0060] Reference Figure 4 , the memory block BLK may include NAND strings NS11 to NS33, word lines WL1 to WL8, bit lines BL1 to BL3, ground selection lines GSL1 to GSL3, string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND strings, word lines, bit lines, ground selection lines, and string selection lines may vary according to design choices.

[0061] NAND strings NS11, NS21, and NS31 are provided between a first bit line BL1 and a common source line CSL. NAND strings NS12, NS22, and NS32 are provided between a second bit line BL2 and a common source line CSL. NAND strings NS13, NS23, and NS33 are provided between a third bit line BL3 and a common source line CSL. Each NAND string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST.

[0062] The string selection transistor SST is connected to a corresponding one of the string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are connected to corresponding word lines WL1 to WL8, respectively. A ground selection transistor GST is connected to a corresponding one of the ground selection lines GSL1 to GSL3. The string selection transistor SST is connected to a corresponding one of the bit lines BL1 to BL3, and the ground selection transistor GST is connected to a common source line CSL.

[0063] according to Figure 4 In the illustrated embodiment, word lines having a given vertical height are commonly connected across a plurality of memory cell strings, string selection lines SSL1 to SSL3 are separated from each other, and ground selection lines GSL1 to GSL3 are separated from each other. Figure 4 , it is shown that three string selection lines SSL1 to SSL3 share a word line having the same height. However, the inventive concept is not limited thereto. For example, two string selection lines may share a word line having the same height. As another example, four string selection lines may share a word line having the same height.

[0064] Figure 5 In one embodiment, it is further shown Figure 4 A perspective view of the memory block BLK.

[0065] Reference Figure 5 , the memory block BLK is formed in a vertical direction relative to the main substrate SUB. The substrate SUB has a first conductivity type (e.g., P type), and a common source line CSL extending in a second horizontal direction HD2 and doped with impurities of a second conductivity type (e.g., N type) is provided on the substrate SUB. A plurality of insulating layers IL extending in the second horizontal direction HD2 are sequentially provided in a region of the substrate SUB between two adjacent common source lines CSL in a vertical direction VD. The plurality of insulating layers IL are separated from each other by a specific distance in the vertical direction VD. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

[0066] A plurality of pillars P are provided on a region of the substrate SUB between the two adjacent common source lines CSL, the plurality of pillars P being sequentially arranged in a first horizontal direction HD1 and passing through the plurality of insulating layers IL in a vertical direction VD. For example, the plurality of pillars P pass through the plurality of insulating layers IL and contact the substrate SUB. Here, a surface layer S of each pillar P may include a silicon material having a first type and may be used as a channel region. On the other hand, an inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0067] In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surface of the insulating layer IL, the pillar P and the substrate SUB. The charge storage layer CS may include a gate insulating layer (or referred to as a "tunneling insulating layer"), a charge trap layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between the two adjacent common source lines CSL, gate electrodes GE such as a ground selection line GSL and a string selection line SSL and word lines WL1 to WL8 are provided on the exposed surface of the charge storage layer CS.

[0068] Drains or drain contacts DR are respectively provided on the plurality of pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities having a second conductivity type. Bit lines BL1 to BL3 are provided on the drains or drain contacts DR, and the bit lines BL1 to BL3 extend in the first horizontal direction HD1 and are arranged to be spaced apart from each other by a certain distance in the second horizontal direction HD2.

[0069] Figure 6 is a perspective view showing a possible structure of a memory device 10a including a first semiconductor layer L1 and a second semiconductor layer L2 according to an embodiment of the inventive concept. The memory device 10a may correspond to Figure 1 and Figure 2 A storage device 10.

[0070] Reference Figure 6 , the first memory group MG1 includes a first word line WLa extending in the first horizontal direction HD1 and a first bit line BLa extending in the second horizontal direction HD2. The second memory group MG2 includes a second word line WLb extending in the second horizontal direction HD2 and a second bit line BLb extending in the first horizontal direction HD1. The third memory group MG3 includes a third word line WLc extending in the first horizontal direction HD1 and a third bit line BLc extending in the second horizontal direction HD2, and the fourth memory group MG4 includes a fourth word line WLd extending in the second horizontal direction HD2 and a fourth bit line BLd extending in the first horizontal direction HD1. Expressed in other terms according to the respective arrangements of the word lines and the bit lines, the first memory group MG1 and the third memory group MG3 can be understood as "A-type" memory groups, while the second memory group MG2 and the fourth memory group MG4 can be understood as "B-type" memory groups. It is worth noting that with regard to Figure 6 In the illustrated embodiment, the A-type and B-type memory groups are arranged so that each A-type memory group is horizontally adjacent to a B-type memory group (in the first horizontal direction HD1 or in the second horizontal direction HD2). However, this need not always be the case, and other arrangements of the A-type and B-type memory groups are possible for other embodiments of the inventive concept.

[0071] In other words, in some embodiments of the inventive concept, word lines of the A-type memory group extend in the same horizontal direction as bit lines of the B-type memory group, or bit lines of the A-type memory group extend in the same horizontal direction as word lines of the B-type memory group.

[0072] In addition, in certain embodiments of the present inventive concept, a corresponding set of word lines (e.g., WLa, WLb, WLc, and WLd) in a particular memory group (e.g., each of MG1, MG2, MG3, and MG4) is electrically isolated from other memory group lines (i.e., not electrically connected to word lines or bit lines outside the particular memory group). Similarly, in certain embodiments of the present inventive concept, a corresponding set of bit lines (e.g., BLa, BLb, BLc, and BLd) in a memory group (e.g., each of MG1, MG2, MG3, and MG4) is electrically isolated from other memory group lines (i.e., not electrically connected to additional word lines or bit lines outside the particular memory group).

[0073] about Figure 6 In the arrangement of memory groups shown, the second semiconductor layer L2 may include a first region R1 substantially below the first memory group MG1, a second region R2 substantially below the second memory group MG2, a third region R3 substantially below the third memory group MG3, and a fourth region R4 substantially below the fourth memory group MG4. Here, the limiting term "substantially" is used to identify the expected changes in the geometry of the memory groups relative to the corresponding peripheral circuit regions below. Those skilled in the art will recognize that a relatively small portion of the area below may extend beyond the boundaries of the corresponding memory group above, and / or a relatively small portion of the memory group may extend beyond the boundaries of the corresponding peripheral circuit region below. Nevertheless, such relatively small geometric mismatches are included in the terms "substantially below" and / or "substantially above" or more concisely "below" or "above" to avoid unnecessary and repeated use of well-known terms.

[0074] Therefore, refer to Figure 6 , the first region R1 is below the first memory group MG1 in the vertical direction VD and has a "size" substantially corresponding to the size of the first memory group MG1 (for example, a lateral area defined by a "length" measured in the second horizontal direction HD2 and a "width" measured in the first horizontal direction HD1). In a similar manner, the second region R2 is below the second memory group MG2 and has a size substantially corresponding to the size of the second memory group MG2; the third region R3 is below the third memory group MG3 and has a size substantially corresponding to the size of the third memory group MG3; and the fourth region R4 is below the fourth memory group MG4 and has a size substantially corresponding to the size of the fourth memory group MG4.

[0075] Figure 7 is a plan view (ie, a top view) illustrating an upper surface of the second semiconductor layer 30 according to an embodiment of the inventive concept. Here, the second semiconductor layer 30 may correspond to the second semiconductor layer L2 described previously.

[0076] Reference Figure 7 Consistent with the above, the second semiconductor layer 30 includes a first region R1 to a fourth region R4, and the first region R1 to the fourth region R4 may correspond to Figure 6 The first region R1 to the fourth region R4. Therefore, the first memory group MG1 to the fourth memory group MG4 can be arranged above the first region R1 to the fourth region R4, respectively. However, here each peripheral circuit region (i.e., each of the first region R1 to the fourth region R4) includes a row decoder RD and a page buffer PB, wherein each page buffer PB is connected to the memory cell of the corresponding (i.e., the above) memory group (e.g., via a bit line), and each row decoder RD is connected to the memory cell of the adjacent memory group (e.g., via a word line). Here, the term "corresponding memory group" refers to a memory group stacked vertically on a specific region, and the term "adjacent memory group" refers to a memory group stacked vertically on a region horizontally adjacent to a specific region.

[0077] Here, it should be noted that in some embodiments of the present inventive concept, the size of the page buffer PB may be larger than the size of the row decoder RD in at least one dimension (width and / or height). For example, the size of the page buffer PB in two horizontal dimensions may be larger than half the size of the corresponding region (e.g., the first region R1 to the fourth region R4).

[0078] Reference Figure 7 In the illustrated example, the first row decoder 311 and the first page buffer 321 may be arranged in the first region R1. The first row decoder 311 may be arranged in the first horizontal direction HD1 along which the first word line WLa extends, and may be arranged adjacent to the fourth region R4 in the second horizontal direction HD2. In addition, the first row decoder 311 may be arranged in the central portion of the second semiconductor layer 30 and between the first page buffer 321 and the fourth region R4.

[0079] The first row decoder 311 is connected to the memory cells of the fourth memory group MG4 (i.e., the adjacent memory group), and the first page buffer 321 is connected to the memory cells of the first memory group MG1 (i.e., the corresponding memory group). That is, the first page buffer 321 is connected to the first bit line BLa of the first memory group MG1 and can drive the first bit line BLa. The first row decoder 311 is connected to the fourth word line WLd of the fourth memory group MG4 and can drive the fourth word line WLd. Therefore, the fourth word line WLd driven by the first row decoder 311 is not included in the corresponding memory group (i.e., the first memory group MG1), but is included in the adjacent memory group (i.e., the fourth memory group MG4).

[0080] The second row decoder 312 and the second page buffer 322 are arranged in the second region R2, wherein the second row decoder 312 extends in the second horizontal direction HD2 between the second page buffer 322 and the first region R1. The second row decoder 312 is disposed in the central region of the second semiconductor layer 30 and is connected to the memory cells of the first memory group MG1, while the second page buffer 322 is connected to the memory cells of the second memory group MG2.

[0081] The third row decoder 313 and the third page buffer 323 are arranged in the third region R3, wherein the third row decoder 313 extends in the first horizontal direction HD1 between the third page buffer 323 and the second region R2. The third row decoder 313 is disposed in the central region of the second semiconductor layer 30 and is connected to the memory cells of the second memory group MG2, while the third page buffer 323 is connected to the memory cells of the third memory group MG3.

[0082] The fourth row decoder 314 and the fourth page buffer 324 are arranged in the fourth region R4, wherein the fourth row decoder 314 extends in the second horizontal direction HD2 between the fourth page buffer 324 and the third region R3. The fourth row decoder 314 is disposed in the central region of the second semiconductor layer 30 and is connected to the memory cells of the third memory group MG3, while the fourth page buffer 324 is connected to the memory cells of the fourth memory group MG4.

[0083] exist Figure 6 and Figure 7 In the aforementioned arrangement shown, each row decoder can be connected to the memory cell via a horizontally adjacent word line, and the corresponding page buffer can be connected to the memory cell via a corresponding bit line. In addition, each region (e.g., R1, R2, R3, and R4) can be electrically isolated from each other by one or more separation regions 350.

[0084] Figure 7The illustrated embodiments assume that the size of each row decoder RD and page buffer PB substantially occupies the corresponding area in at least one dimension (i.e., length or width). However, this need not always be the case, and other embodiments of the inventive concept may include driver circuits (e.g., row decoders and / or page buffers) having dimensions that are significantly smaller than the width or length of the corresponding area in the second semiconductor layer 30. However, it should be noted that in this regard, similar size dimensions (e.g., length and / or width) - such as between the various memory groups and the corresponding driver circuits - can enable the manufacture of storage devices with relatively straightforward (and therefore simple) wiring layouts. In contrast, mismatched size dimensions - such as between the various memory groups and the corresponding driver circuits - can require relatively complex wiring patterns. Nevertheless, recognizing this design trade-off, a person skilled in the art may select a smaller driver circuit in order to introduce additional peripheral circuits (e.g., portions of the control logic 230) into one or more peripheral circuit regions (e.g., R1 to R4).

[0085] Referring to the embodiments shown, in particular Figures 7 to 11 , Fig.13 , Fig.15 , Fig.17 and Fig.18 In the embodiments shown in FIG. 1 , the second semiconductor layer (eg Figure 7 The second semiconductor layer 30) may also include a pad area (PAD) 360. In many storage device layouts consistent with embodiments of the present invention, the pad area 360 may be arranged along at least a portion of an outer edge of the second semiconductor layer 30. A plurality of connection pads may be arranged differently in the pad area 360, wherein the corresponding pads may be used to electrically connect various peripheral circuits arranged in the first region R1 to the fourth region R4 to an external signal source (e.g., a memory controller, a processor, or a host device, not shown). In this regard, examples of externally provided signals include command signals CMD, address signals ADDR, and control signals CTRL. The pads of the pad area 360 may be arranged relatively close to various peripheral circuits that process externally provided signals and / or signals provided by one or more memory cell arrays 100. Here, the outer edge of the second semiconductor layer may extend in the first horizontal direction HD1 and / or the second horizontal direction HD2.

[0086] Similar to Figure 7 , Figures 8 to 11 2 are corresponding plan views illustrating an upper surface of a second semiconductor layer according to an embodiment of the inventive concept.

[0087] Reference Figure 8, the second semiconductor layer 30a may again include first to fourth regions R1 to R4 respectively below corresponding memory groups among the plurality of memory groups provided in the first semiconductor layer, and the first semiconductor layer is vertically stacked on the second semiconductor layer 30a. Again, each of the first to fourth regions R1 to R4 may include a row decoder and a page buffer. Only the detailed description will be given below. Figure 7 The embodiment shown is similar to Figure 8 Material differences between the embodiments shown.

[0088] Pay special attention to: Figure 8 Each row decoder shown in the embodiment is divided into a first part (e.g., 311a in the first region R1, 312a in the second region R2, 313a in the third region R3, and 314a in the fourth region R4) and a second part (e.g., 311b in the first region R1, 312b in the second region R2, 313b in the third region R3, and 314b in the fourth region R4).

[0089] exist Figure 8 In the embodiment of the present invention, the first region R1, the second region R2, the third region R3 and the fourth region R4 are arranged substantially in a rectangle having a central (or inner) region near the connection of the four (4) regions and having a peripheral (or outer) region surrounding the central region and near the outer edge of the rectangle. Assuming this arrangement, the corresponding first portions of the first row decoder 311, the second row decoder 312, the third row decoder 313 and the fourth row decoder 314 are centrally disposed in the rectangle, while the corresponding second portions of the first row decoder 311, the second row decoder 312, the third row decoder 313 and the fourth row decoder 314 extend from the corresponding first portions to the outer edge of the rectangle.

[0090] In addition, each first portion of the first row decoder 311, the second row decoder 312, the third row decoder 313, and the fourth row decoder 314 is connected to the memory cells of the corresponding memory group (e.g., via at least one word line), and each second portion of the first row decoder 311, the second row decoder 312, the third row decoder 313, and the fourth row decoder 314 is connected to the memory cells of the adjacent memory group (e.g., via at least one word line), similar to the previous description of Figure 7 In some embodiments, the second portion may be connected to adjacent memory cells of two or three memories.

[0091] Each page buffer (eg, a first page buffer 321 in the first region R1, a second page buffer 322 in the second region R2, a third page buffer 323 in the third region R3, and a fourth page buffer 324 in the fourth region R4) is similar to the previous description. Figure 7Connect in a similar manner as described.

[0092] Reference Fig. 9 , the second semiconductor layer 40 may again include first to fourth regions R1 to R4 respectively below corresponding memory groups among the memory groups provided in the first semiconductor layer, and the first semiconductor layer is vertically stacked on the second semiconductor layer 40. Here again, each of the first to fourth regions R1 to R4 includes a row decoder and a page buffer, and only the details will be described. Figure 7 and Figure 8 The embodiment shown is similar to Fig. 9 Material differences between the embodiments shown.

[0093] therefore, Fig. 9 The second semiconductor layer 40 includes first to fourth regions R1 to R4, each of which includes a row decoder RD and a page buffer PB. Figure 7 and Figure 8 Unlike the implementation of (which places the row decoder centrally between the corresponding page buffer and the horizontally adjacent region), Fig. 9 , Fig.10 and Fig.11 The embodiment of the present invention places the corresponding page buffer in the center, and thus places the corresponding row decoder on the outer edge of the memory device. In addition, in this configuration, each row decoder can be connected to the memory cell of the corresponding memory group, and each page buffer can be connected to the memory cell of the adjacent memory group.

[0094] Therefore, the size of each page buffer PB may be significantly larger than the size of the corresponding row decoder RD. That is, in some embodiments of the present inventive concept, the size of each page buffer PB may be larger than half of each corresponding region (eg, the first to fourth regions R1 to R4).

[0095] exist Fig. 9 , the first row decoder 411 and the first page buffer 421 may be arranged in the first region R1. The first row decoder 411 may be connected to the memory cells of the first memory group MG1 (e.g., via at least one word line), and the first page buffer 421 may be connected to the memory cells of the second memory group MG2 (e.g., via at least one bit line). Therefore, the first row decoder 411 may be connected to the first word line WLa and drive the first word line WLa, and the first page buffer 421 may be connected to the second bit line BLb of the second memory group MG2 and may drive the second bit line BLb.

[0096] In a similar manner, the second row decoder 412 and the second page buffer 422 may be arranged in the second region R2; the third row decoder 413 and the third page buffer 423 may be arranged in the third region R3, and the fourth row decoder 414 and the fourth page buffer 424 may be arranged in the fourth region R4.

[0097] However, here again, one driver circuit in a specific area is connected to memory cells of a corresponding memory group, while another driver circuit in the same specific area is connected to memory cells of a horizontally adjacent memory group.

[0098] Reference Fig. 9 and Fig.10 , Fig. 9 The embodiment shown may be Fig.10 As shown, the first page buffer is modified to include a page buffer divided into a first part and a second part in each region. Therefore, in the first region R1, the first page buffer includes a first part 521a and a second part 521b, wherein the first part 521a is connected to the memory cells of the corresponding memory group (i.e., the first memory group MG1), and the second part 521b is connected to the memory cells of the adjacent memory group (e.g., the second memory group MG2). Here, the first part 521a can be connected to the memory cells of the first memory group MG1 via one or more bit lines BLa1, and the second part 521b can be connected to the memory cells of the second memory group MG2 via one or more bit lines BLb2. In contrast, the first row decoder 511 (e.g., via one or more word lines WLa) is connected to the memory cells of the corresponding memory group.

[0099] exist Fig.10 A similar arrangement is shown in: a second row decoder 512 and a second page buffer (including a first part 522a and a second part 522b) in the second region R2; a third row decoder 513 and a third page buffer (including a first part 523a and a second part 523b) in the third region R3; and a fourth row decoder 514 and a fourth page buffer (including a first part 524a and a second part 524b) in the fourth region R4.

[0100] It is noted that, if so provided, each of the page buffers of its components may be disposed between a corresponding row decoder and an adjacent region such that each row decoder is disposed along an outer edge of the region.

[0101] like Fig.11 As further shown in FIG. 1 , each row decoder and page buffer disposed in a corresponding region can be electrically isolated from each other by selectively disposing or extending the separation region 350. The second semiconductor layer 50′ is formed in Fig.11. The first row decoder 511' and the first page buffer including the first part 521a' and the second part 521b' are arranged in the first region R1. The second row decoder 512' and the second page buffer including the first part 522a' and the second part 522b' are arranged in the second region R2. The third row decoder 513' and the third page buffer including the first part 523a' and the second part 523b' are arranged in the third region R3. The fourth row decoder 514' and the fourth page buffer including the first part 524a' and the second part 524b' are arranged in the fourth region R4.

[0102] As previously described, the peripheral circuit area of ​​the memory device according to the embodiment of the present invention may include various peripheral circuits that regularly communicate commands, addresses, and / or signals with the drive circuit and / or the memory group. In order to facilitate such communication of commands, addresses, and / or signals, a plurality of pads may be arranged in the pad area 360 provided with respect to the second semiconductor layer. For example, a plurality of pads may be used to externally connect one or more of the first region R1, the second region R2, the third region R3, and the fourth region R4.

[0103] Thus, column logic may be used to generate signals that drive one or more driver circuits (or driver circuit portions). A predecoder may generate signals that determine the timing of signals applied to or provided by one or more circuits. A voltage generator (e.g. Figure 1 The voltage generator 240 of the memory device 10 may be used to generate a voltage (e.g., a word line voltage, a bit line voltage, a reference voltage, a power supply voltage, etc.) applied to one or more drive circuits or peripheral circuits in the memory device 10. The temperature sensor may sense a specific temperature associated with the memory device 10 and output a control signal corresponding to the sensed temperature to one or more drive circuits and / or peripheral circuits. The command decoder may decode a command signal CMD received from an external source and set an operation mode of the memory device 10 according to the decoded command. The address decoder may decode an externally provided address signal ADDR, select a memory block in response to the address, and activate the memory block. The mobile area controller may control the operation of applying various memory cell string voltages included in the memory cell array 100. The scheduler may include a processor or a state machine and may generate a plurality of control signals at an appropriate timing according to a mode set by a command. The test and / or measurement circuit may be used to test and / or measure the characteristics of the memory device 10 so as to provide feature information or performance information about the memory device 10.

[0104] So far, Figures 6 to 11The illustrated embodiment assumes a 2×2 horizontal configuration of memory groups (MG1, MG2, MG3, and MG4) disposed in a first semiconductor layer L1, which is vertically stacked on a second semiconductor layer L2 including corresponding regions (R1, R2, R3, and R4). However, the scope of the inventive concept is not limited to such a 2×2 horizontal configuration of memory groups and corresponding regions.

[0105] exist Fig.12 and Fig.13 In the illustrated embodiment, a memory device 10 b according to an embodiment of the inventive concept may include first and second memory groups MG1 and MG2 horizontally adjacent to each other in a first semiconductor layer L1 and first and second regions R1 and R2 disposed in a second semiconductor layer L2 and respectively below the first and second memory groups MG1 and MG2 .

[0106] More specifically, regarding Fig.13 The illustrated embodiment shows the upper surface of the second semiconductor layer 60. The first region R1 includes a first driving circuit (i.e., a first page buffer 621) connected to the memory cells of the corresponding memory group (i.e., the first memory group MG1) (e.g., through at least one bit line BLa). The second region R2 includes a second driving circuit (i.e., a second page buffer 622) connected to the memory cells of the corresponding memory group (i.e., the second memory group MG2) (e.g., through at least one bit line BLb) and a third driving circuit (i.e., a first row decoder 611) connected to the memory cells of the adjacent memory group (i.e., the first memory group MG1).

[0107] In addition, the second semiconductor layer 60 includes a peripheral region (PERI) 370 extending across the length (or width) of both the first region R1 and the second region R2. The peripheral region 370 includes a fourth driving circuit (i.e., a second row decoder 612) connected to the memory cells of the adjacent memory group (i.e., the second memory group MG2). Here, the second semiconductor layer 60 may also include the pad region 360 described previously.

[0108] Fig.14 Another memory device 10 c according to an embodiment of the inventive concept is shown, which includes three (3) memory groups ( MG1 , MG2 , and MG3 ) arranged in the first semiconductor layer L1 .

[0109] Reference Fig.14 The first memory group MG1, the second memory group MG2 and the third memory group MG3 are similar to those previously described. Figure 6The first memory group MG1 is arranged in the first semiconductor layer L1 in a manner similar to that described above, wherein the first memory group MG1 is horizontally adjacent to the second memory group MG2 in the first horizontal direction HD1, and the first memory group MG1 is horizontally adjacent to the third memory group MG3 in the second horizontal direction HD2. Figure 6 In contrast to the embodiment of , the fourth memory group MG4 is not provided.

[0110] like Fig.15 As shown, the second semiconductor layer 70 may include a first region R1, a second region R2, and a third region R3 as well as a peripheral region 370 and a pad region 360. As described above, the first region R1, the second region R2, and the third region R3 are respectively under the first memory group MG1, the second memory group MG2, and the third memory group MG3. Fig.15 In the illustrated embodiment, the first memory group MG1 may be an A-type memory group, the second memory group MG2 may be a B-type memory group, and the third memory group MG3 may also be a B-type memory group.

[0111] The first region R1 includes a first row decoder 711 connected to memory cells of an adjacent memory group (i.e., the third memory group MG3) and a first page buffer 721 connected to memory cells of the corresponding memory group (i.e., the first memory group MG1). The second region R2 includes a second row decoder 712 connected to memory cells of an adjacent memory group (i.e., the first memory group MG1) and a second page buffer 722 connected to memory cells of the corresponding memory group (i.e., the second memory group MG2). The fourth region R4 includes a third page buffer 723 connected to memory cells of the corresponding memory group (i.e., the third memory group MG3). The peripheral region 370 includes a third row decoder 713 connected to memory cells of an adjacent memory group (i.e., the second memory group MG2).

[0112] With this configuration, a substantial portion of the peripheral region 370 may include one or more peripheral circuit types as described above. Fig.14 and Fig.15 The embodiment provides some additional flexibility for including various peripheral circuits in the second semiconductor layer L2 below the first semiconductor layer L1.

[0113] Fig.16 is a perspective view illustrating a memory assembly 21 including two or more memory devices similar to the previously described memory devices. Consistent with the foregoing embodiments of the present inventive concept, the memory assembly 21 may include a second semiconductor layer L2 below the first semiconductor layer L1.

[0114] Reference Fig.16, the first storage device MD1, the second storage device MD2 and the third storage device MD3 can be understood as a lateral arrangement (eg, lateral cascade) of corresponding 2×2 horizontal storage devices, similar to the previous description of Figures 6 to 11 In addition, Fig.16 The storage component 21 may include a fourth storage device MD4, similar to the previous description of Fig.14 and Fig.15 Those described in the embodiments of the present invention.

[0115] Fig.17 and Fig.18 yes Fig.16 The corresponding plan view of the storage assembly 21 is shown. Fig.17 In the embodiment, each of the first storage device MD1, the second storage device MD2, the third storage device MD3 and the fourth storage device MD4 may include the same Figure 6 , Figure 7 and Figure 8 The word lines and bit lines are arranged in a manner consistent with the described embodiments. Fig.18 In the embodiment, each of the first storage device MD1, the second storage device MD2, the third storage device MD3 and the fourth storage device MD4 may include the same Fig. 9 , Fig.10 and Fig.11 The described embodiments arrange the word lines and bit lines in a consistent manner.

[0116] about Fig.16 , Fig.17 and Fig.18 The storage component 21, each of the constituent storage devices (e.g., the first storage device MD1, the second storage device MD2, the third storage device MD3, and the fourth storage device MD4) can operate independently in response to one or more commands, addresses, and / or control signals. For example, the first storage device MD1 can perform a programming operation, while the second storage device MD2 and the third storage device MD3 each perform a corresponding read operation, and the fourth storage device MD4 remains idle or performs a housekeeping operation. In this regard, the first storage device MD1, the second storage device MD2, the third storage device MD3, and the fourth storage device MD4 of the storage component 21 can share an I / O bus, an address bus, a command bus, a control signal, and / or a signal connection pad.

[0117] In various embodiments of the present invention, the first memory group MG1 to the fourth memory group MG4 can be defined separately and arbitrarily according to the word line length (or word line width) and the bit line width (or bit line length). Here, the length and width obtained can be equal to or different from each other. In this regard, the word line length (or word line width) can be represented by the shortest word line, the longest word line, or the middle word line in the word line arrangement (e.g., the vertical stacking arrangement of the word lines). Similarly, the bit line length (or bit line width) can be represented by the shortest bit line, the longest bit line, or the middle bit line in the bit line arrangement.

[0118] Regardless of the geometric definition or description, each memory group (e.g., MG1, MG2, MG3, and MG4) can be understood as corresponding to a tile for certain embodiments of the present inventive concept. In this context, a "tile" can be regarded as a lateral area (i.e., a memory group) including a memory cell array and corresponding wiring (e.g., an area measured according to a first horizontal direction and a second horizontal direction).

[0119] For example, by including a first word line, a first bit line, and a first memory cell in different portions of the first semiconductor layer L1, the first block may include a first memory group MG1. Consistent with the aforementioned embodiment, the first region R1 under the first block may include a first memory cell connected to a corresponding memory group (e.g. Figure 6 and Figure 7 In the context of the first memory group MG1) of FIG. 1 , a first driver circuit of a memory cell and a first driver circuit connected to an adjacent memory group (eg Figure 6 and Figure 7 In this exemplary context, the first region R1 is below a first block including the first memory group MG1, and the second region R2 is below a second block including the second memory group MG2.

[0120] Fig.19 is a conceptual diagram showing an exemplary rectangular (or straight line) arrangement of blocks, each block including a corresponding memory group. For the sake of clarity of description, it is assumed that the first block T1 includes Figure 7 The first memory group MG1 and the second block T2 include Figure 7 The second memory group MG2, the third block T3 includes Figure 7 The third memory group MG3, the fourth block T4 includes Figure 7 The fourth memory group MG4.

[0121] Reference Fig.19, the first block T1, the second block T2, the third block T3, and the fourth block T4 are arranged in a rectangular pattern with aligned outer edges and a central void area. Recognizing that it is desirable to directly wire between the drive circuits and the memory cells of the connected memory groups, for example, the second row decoder disposed below the second block T2 may have a width in the second horizontal direction HD2 that is substantially equal to the width of the first memory group MG1 in the first block T1. In a similar manner, the first page buffer disposed below the first block T1 may have a length in the first horizontal direction HD1 that is substantially equal to the length of the first memory group MG1. Such substantially identical widths and lengths between the memory groups and the connected drive circuits result in a relatively simple wiring layout and efficient use of the available lateral area.

[0122] Fig. 20 The illustrated embodiment shows another rectangular (or straight line) arrangement of the blocks. Fig. 20 is another conceptual view showing an exemplary arrangement of blocks, each block including a corresponding memory group. However, it is assumed here that the first block T1 includes Fig. 9 The first memory group MG1 and the second block T2 include Fig. 9 The second memory group MG2, the third block T3 includes Fig. 9 The third memory group MG3, the fourth block T4 includes Fig. 9 The fourth memory group MG4.

[0123] Reference Fig. 20 , the first block T1, the second block T2, the third block T3 and the fourth block T4 are arranged in a rectangular pattern with aligned inner edges. Again recognizing the desire to directly wire between the drive circuit and the memory cells of the connected memory groups, the second page buffer disposed under the second block T2 may have a length equal to the length of the third memory group MG3 in the first horizontal direction HD1. In a similar manner, the first page buffer disposed under the first block T1 may have a width equal to the width of the second memory group MG2 in the second horizontal direction HD2.

[0124] Fig.21 is a block diagram illustrating a solid state drive (SSD) system 1000 according to an embodiment of the inventive concept, which may include one or more memory devices consistent with the aforementioned embodiments.

[0125] Reference Fig.21, the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 sends and receives signals to and from the host 1100 through a signal connector, and receives power through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memories 1230, 1240, and 1250. The memories 1230, 1240, and 1250 may be the SSD controller 1210, an auxiliary power supply 1220, and memories 1230, 1240, and 1250 described above. Figures 1 to 18 Describes a type of vertically stacked NAND flash memory.

[0126] So far, an exemplary memory device and memory system assuming the use of flash memory cells have been described. However, as previously described, the inventive concept includes a range of memory devices and memory systems.

[0127] For example, Fig. 22 A memory system 10A is generally shown including a nonvolatile memory device 101 and a memory controller 201 , wherein the nonvolatile memory device 101 may include a memory cell array 102 including resistive memory cells.

[0128] Here, in addition to the memory cell array 102, the memory device 101 may further include control logic 103 and a voltage generator 130. The memory cell array 102 may include an arrangement (eg, a matrix) of resistive memory cells. Therefore, the memory device 101 may be referred to as a resistive memory device.

[0129] The memory controller 201 may be used to control the overall operation of the resistive memory device 101 during read, write, and erase operations in response to various commands received from a host (not shown). That is, the memory controller 201 may control the read, write, and erase operations performed by the resistive memory device 101 by providing one or more addresses ADDR, commands CMD, and / or control signals CTRL to the resistive memory device 101. In addition, program (or write) data DT and / or read data DT may be communicated (i.e., sent and / or received) between the memory controller 201 and the resistive memory device 101.

[0130] As can be understood by those skilled in the art, the memory cell array 102 can arrange resistive memory cells respectively with respect to a plurality of word lines and a plurality of bit lines. In this regard, the resistive memory device 101 can be referred to as a cross-point memory. During a memory access operation (e.g., a write operation), the parasitic resistance of the selected (or target) memory cell may be different depending on its position within the resistive memory cell array 102. Specifically, the length of the conductive line between the selected memory cell and the driving circuit (e.g., a word line selection switch or a bit line selection switch) can be different depending on the relative position of the selected memory cell, thereby changing the corresponding parasitic resistance.

[0131] In certain embodiments of the present inventive concept, the memory cells of the resistive memory cell array 102 may include a variable resistance element. For example, when the variable resistance element includes a phase change material (Ge-Sb-Te (GST)) and has a resistance that changes according to temperature, the memory device 101 may be a phase change random access memory (PRAM). As another example, when the variable resistance element includes an upper electrode, a lower electrode, and a composite metal oxide therebetween, the memory device 101 may be a resistance random access memory (ReRAM). As another example, when the variable resistance element includes a magnetic upper electrode, a magnetic lower electrode, and a dielectric therebetween, the memory device 101 may be a magnetic random access memory (MRAM). Hereinafter, an embodiment in which the memory device 101 is a PRAM will be described as a more detailed example.

[0132] The control logic 103 may generate a programming voltage control signal CTRL_VPGM suitable for adjusting the programming voltage of the selected memory cell in response to the write command and the address ADDR. In one example, the control logic 103 may generate a programming voltage control signal CTRL_VPGM corresponding to the address of the selected memory cell, which is indicated by a mapping table MT associated with the control logic 103. For example, the mapping table MT may define a parasitic resistance corresponding to the address ADDR for each memory cell in the resistive memory cell array 102. That is, the mapping table MT may be stored in a register of the control logic 103. However, embodiments of the inventive concept are not limited thereto. For example, the mapping table MT may be stored outside the control logic 103.

[0133] Refer again Fig. 22 , the voltage generator 130 may generate a programming voltage having a first programming voltage level based on the programming voltage control signal CTRL_VPGM, the first programming voltage level being one of a plurality of programming voltage levels. The plurality of programming voltage levels may correspond to a plurality of predetermined parasitic resistances. Therefore, the number of programming voltage levels may correspond to the number of parasitic resistances stored in the mapping table MT. In this way, the voltage generator 130 may generate a programming voltage corresponding to a first programming voltage level among the programming voltage levels based on the position information of the selected memory cell among the memory cells and the cell resistance distribution of the memory cells. In one embodiment, the voltage generator 130 may generate a programming voltage before the programming operation of the memory cell array 102 starts. In other words, the programming voltage may be set before the programming current is applied to the selected memory cell.

[0134] In some embodiments, the storage system 10A may be implemented as an internal memory embedded in an electronic device. For example, the storage system 10A may be a universal flash memory (UFS) storage device, an embedded multimedia card (eMMC), or a solid-state drive (SSD), as described in detail in relation to Fig.21 As described. In some embodiments, the storage system 10A can be implemented by an external memory that is detachable from the electronic device. For example, the storage system 10A can be implemented as a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro secure digital (micro-SD) card, a mini secure digital (mini-SD) card, an extreme digital (xD) card, or a memory stick.

[0135] Fig.23 In one embodiment, it is further shown Fig. 22 A block diagram of a storage device 101 is shown.

[0136] Reference Fig.23 In addition to the resistive memory cell array 102 , the memory device 101 may include a control logic 103 , a voltage generator 130 , a row decoder 140 , a column decoder 150 , and a write circuit 160 .

[0137] The resistive memory cell array 102 may be connected to the row decoder 140 via word lines WL, and may be connected to the column decoder 150 via bit lines BL. The memory cells of the resistive memory cell array 102 may be further arranged in a plurality of memory groups. And, as will be appreciated by those skilled in the art, each respective memory group may be differently defined to include one or more banks, bays, tiles, sub-tiles, etc.

[0138] The control logic 103 can be used to output various control signals (e.g., programming voltage control signal CTRL_VPGM, row address X_ADDR, column address Y_ADDR, and write control signal CTRL_W, etc.), so that the program data to be programmed into the resistive memory cell array 102, the read data retrieved from the resistive memory cell array 102, and / or the erase data stored in the resistive memory cell array 102 can be identified according to the received command CMD, address ADDR, and / or control signal CTRL. In this way, the control logic 103 can be used to control the overall operation of the storage device 101.

[0139] Consistent with the previously described embodiments, for example, Fig. 22 and Fig.23The control logic 103 may be used to generate a connection control signal CTRL_CON for activating the voltage generator 130 in response to a write command. Therefore, the control logic 103 may provide the connection control signal CTRL_CON to the voltage generator 130, and then provide the programming voltage control signal CTRL_VPGM to the voltage generator 130. When the connection control signal CTRL_CON is activated, the current path in the voltage generator 130 may be activated.

[0140] Based on various voltage control signals received from the control logic 103, the voltage generator 130 may generate various types of voltages for performing programming, reading, and erasing operations on the memory cell array 102. Specifically, the voltage generator 130 may generate a word line voltage VWL, such as a program voltage, a read voltage, a pass voltage, an erase verification voltage, or a program verification voltage.

[0141] The row decoder 140 may select one of the plurality of word lines WL in response to the row address X_ADDR. For example, the row decoder 140 may include a plurality of word line selection switches or row selection switches respectively connected to the plurality of word lines WL. The row selection switch may be driven in response to the row address X_ADDR. The row decoder 140 may be configured to provide a programming voltage to a selected word line connected to a selected memory cell among the word lines WL.

[0142] The column decoder 150 may select one of the plurality of bit lines BL in response to the column address Y_ADDR. For example, the column decoder 150 may include a plurality of bit line selection switches or column selection switches respectively connected to the plurality of bit lines BL. The column selection switch may be driven in response to the column address X_ADDR. The column decoder 150 may be configured so that a selected bit line connected to a selected memory cell among the bit lines BL is electrically connected to the write circuit 160.

[0143] The write circuit 160 may be configured to receive a write control signal CTRL_W from the control logic 103 and provide a programming current to the selected bit line in response to the write control signal CTRL_W. In one embodiment, the programming current may have a fixed value. In this regard, the write circuit 160 may be referred to as a write driver. Although not shown, the storage device 101 may also include a read circuit. The read circuit may include a sense amplifier that amplifies the data read from the selected memory cell.

[0144] Fig.24 In one embodiment, it is further shown Fig. 22 and Fig.23 1 is a block diagram of a resistive memory cell array 102.

[0145] Reference Fig.24, the resistive memory cell array 102 may include a plurality of memory banks BK1, BK2, ..., and BKm. For example, the memory banks BK1, BK2, ..., and BKm may be arranged in one direction of the resistive memory cell array 102. For example, the resistive memory cell array 102 may include "m" memory banks, where "m" is an integer greater than 1. Each of the memory banks BK1, BK2, ..., and BKm may include a plurality of blocks TL. In certain embodiments of the present inventive concept, the corresponding memory groups described previously may correspond to specific memory banks of the resistive memory cell array 102, or to blocks or partitions within the resistive memory cell array 102, where the term "partition" represents a plurality of blocks.

[0146] Fig.25 An exemplary memory group 111 including a plurality of memory cells according to an embodiment of the inventive concept is shown.

[0147] Reference Fig.25 , the memory group 111 is arranged in relation to a plurality of word lines WL1 to WLa and a plurality of bit lines BL1 to BLb, and includes a plurality of resistive memory cells MC. The resistive memory cells MC may be arranged in regions where the word lines WL1 to WLa and the bit lines BL1 and BLb cross each other, respectively. Assuming such descriptive terms are used for word lines and bit lines, variables "a" and "b" may be the same or different.

[0148] The memory group 111 may be disposed close to (e.g., adjacent to) the row decoder 141 in a first direction (e.g., X direction) and close to the column decoder 151 in a second direction (e.g., Y direction). In this way, the memory group 111 operatively accessed by using the row decoder 141 and the column decoder 151 is defined as a "block". That is, a particular block may be defined based on the row decoder 141 connections of the word lines WL1 to WLa and the column decoder 151 connections of the bit lines BL1 to BLb. The parasitic resistance of the resistive memory cell MC will vary depending on its location within the memory group 111.

[0149] exist Fig.25 In the memory group 111 shown, the first memory cell MC1 is arranged in the region where the first word line WL1 and the first bit line BL1 intersect each other, and the second memory cell MC2 is arranged in the region where the a-th word line WLa and the first bit line BL1 intersect each other. Here, the relative distances between the first and second memory cells MC1 and MC2 and the row decoder 141 may be substantially the same. However, the distance between the second memory cell MC2 and the column decoder 151 is substantially greater than the distance between the first memory cell MC1 and the column decoder 151. Therefore, during a programming (or writing) operation, the parasitic resistance of the second memory cell MC2 may be greater than the parasitic resistance of the first memory cell MC1.

[0150] Refer again Fig.25 , the third memory cell MC3 is disposed in a region where the a-th word line WLa and the b-th bit line BLb cross each other. In this case, the distances between the second and third memory cells MC2 and MC3 and the column decoder 151 may be substantially the same, but the distance between the third memory cell MC3 and the row decoder 141 is greater than the distance between the second memory cell MC2 and the row decoder 141. Therefore, during a programming (or writing) operation, the parasitic resistance of the third memory cell MC3 may be greater than the parasitic resistance of the second memory cell MC2.

[0151] Fig.26A , Fig.26B and Fig.26C The embodiments according to the present invention are shown respectively. Fig.25 Examples of possible implementation variations of the resistive memory cell MC.

[0152] Reference Fig.26A , the memory cell MC may include a variable resistance element R, a selection element SW, and a heating element H. The variable resistance element R may be referred to as a variable resistor or a variable resistance material, and the selection element SW may be referred to as a switching element. In addition, the heating element H may be referred to as a heating electrode or a heating electrode layer.

[0153] In one embodiment, the variable resistance element R may be connected between the selection element SW and the heating element H. The selection element SW may be connected to the bit line BL. The heating element H may be connected to the word line WL. In other words, one end of the selection element SW may be connected to the bit line BL, and the other end of the selection element SW may be connected to the variable resistance element R. In addition, one end of the heating element H may be connected to the word line WL, and the other end of the heating element H may be connected to the variable resistance element R.

[0154] The variable resistance element R can be changed into one of a plurality of resistance states by an applied electric pulse (e.g., a programming current). The variable resistance element R may include a phase change material whose crystalline state changes according to the amount of current. The phase change material may use various types of materials, such as GaSb, InSb, InSe, Sb2Te3, and GeTe (two elements are combined), GeSbTe (GST), GaSeTe, InSbTe, SnSb2Te4, and InSbGe (three elements are combined), and AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81Ge15Sb2S2 (four elements are combined).

[0155] Phase change material can have an amorphous state and a crystalline state, the amorphous state has a relatively high resistance, and the crystalline state has a relatively low resistance. The phase of the phase change material can be changed by the Joule heat generated according to the amount of current. Data can be written and stored in association with different material phases. For example, by defining a high resistance state or a reset state as "0" and defining a low resistance state or a set state as "1", data can be stored in the variable resistance element R.

[0156] In other embodiments, the variable resistance element R may include a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material instead of a phase change material.

[0157] The selection element SW can control the current supply to the variable resistance element R according to the voltage or current applied to the connected word line WL. The selection element SW can be a bidirectional threshold switch (OTS) including a chalcogenide. The bidirectional threshold switch can include a material including arsenic (AS), germanium (Ge), selenium (Se), tellurium (Te), silicon (Si), bismuth (Bi), sulfur (S) and antimony (Sb). Specifically, the bidirectional threshold switch can include a six-element material in which selenium (Se) and sulfur (S) are added to a compound including germanium (Ge), silicon (Si), arsenic (As) and tellurium (Te).

[0158] The heating element H may heat the variable resistance element R during a data programming (or writing) operation (e.g., an operation to define a reset or set state). The heating element H may include a conductive material capable of generating sufficient heat to phase-change the variable resistance element without reacting with the variable resistance element R. For example, the heating element H may include a carbon-based conductive material.

[0159] In example embodiments, the heating element H may include a high melting point metal or a nitride thereof, such as TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), carbonitride (CN), titanium carbonitride (TiCN), and tantalum carbonitride (TaCN).

[0160] Reference Fig.26B , the memory cell MCa may include a variable resistance element Ra, and the variable resistance element Ra may be connected between the bit line BL and the word line WL. The memory cell MCa may store data by a programming current applied by the bit line BL. In addition, the data stored in the memory cell MCa may be read by a read current applied by the word line WL.

[0161] Reference Fig.26C , the memory cell MCb may include a variable resistance element Rb and a bidirectional diode Db. The variable resistance element Rb may include a resistance material for storing data. The bidirectional diode Db may be connected between the variable resistance element Rb and the bit line BL, and the variable resistance element Rb may be connected to the word line WL and the bidirectional diode Db. The bidirectional diode Db may block leakage current flowing through an unselected resistive memory cell.

[0162] Fig.27A It shows that Fig.25 FIG. 4 is a graph showing the distribution of single-level cell (SLC) resistive memory cells MC used in the example of FIG.

[0163] Reference Fig.27A , the horizontal axis represents the memory cell resistance, and the vertical axis represents the number of resistive memory cells MC. For example, when the memory cell MC is a single-level resistive memory cell, it can be programmed to a low resistance state LRS (set state) or a high resistance state HRS (reset state), wherein, for example, the low resistance state LRS and the high resistance state HRS can correspond to the assigned data states "0" and "1", respectively.

[0164] The operation of switching a memory cell MC from a high resistance state HRS to a low resistance state LRS by applying an appropriate programming current to the resistive memory cell MC may be referred to as a set operation or a set write operation. The operation of switching a memory cell MC from a low resistance state LRS to a high resistance state HRS by applying an appropriate programming current to the memory cell MC may be referred to as a reset operation or a reset write operation.

[0165] Fig.27B It shows that Fig.25 FIG. 4 is a graph showing the distribution of multi-level cell (MLC) resistive memory cells MC used in the example of FIG.

[0166] Reference Fig.27B , the multi-layer resistive memory cell MC can be used to program 2 data bits according to one of the first resistance state RS1, the second resistance state RS2, the third resistance state RS3, and the fourth resistance state RS4. However, the embodiments of the inventive concept are not limited thereto. In one or more embodiments, the plurality of memory cells may include a triple-layer cell (TLC), each capable of storing 3 bits of data and may therefore have one of eight resistance states. In one or more embodiments, the plurality of memory cells may include memory cells each capable of storing 4 bits or more of data.

[0167] Each of the resistance states RS1, RS2, RS3, and RS4 may correspond to one of data "00", data "01", data "10", and data "11". In one embodiment, the resistance level (R) may increase in the order of data "11", data "01", data "00", and data "10". That is, the first resistance state RS1 may correspond to data "11", the second resistance state RS2 may correspond to data "01", the third resistance state RS3 may correspond to data "00", and the fourth resistance state RS4 may correspond to data "10".

[0168] Fig.28 is a perspective view of a storage device 10 d according to an embodiment of the inventive concept. Fig.29 is a perspective view of a memory device 10 d including a second semiconductor layer stacked over a first semiconductor layer including four memory groups according to an embodiment of the inventive concept.

[0169] Reference Fig.28 and Fig.29 , the memory device 10d may include a first semiconductor layer L1' and a second semiconductor layer L2', wherein the second semiconductor layer L2' is stacked on the first semiconductor layer L1' in a vertical direction VD. Given this assumed orientation for the "vertical" direction, the first semiconductor layer L1' and the second semiconductor layer L2' may be understood to extend in respective "horizontal" directions (i.e., in the first horizontal direction HD1 and the second horizontal direction HD2).

[0170] According to some embodiments, Figure 1 The memory cell array 100 may be disposed in the first semiconductor layer L1'. Figure 1 The peripheral circuit 200 may be disposed in the second semiconductor layer L2'. Such an embodiment may be understood as having a "peripheral on cell" (POC) structure. In this regard, the first semiconductor layer L1' may include a substrate and a memory cell array 100, and the second semiconductor layer L2' may include various circuits among the substrate and the peripheral circuit 200, which are formed in the second semiconductor layer L2' by combining semiconductor devices such as transistors and wiring patterns. After the memory cell array 100 including electronic devices and corresponding wiring (e.g., word lines WL and bit lines BL) is formed in the first semiconductor layer L1' and various circuits and wiring are formed in the second semiconductor layer L2', the first semiconductor layer L1' and the second semiconductor layer L2' may be joined together.

[0171] like Fig.29As shown, the first to fourth memory groups MG1 to MG4 may be arranged in the first semiconductor layer L1', wherein the first memory group MG1 and the second memory group MG2 are adjacent in the first horizontal direction HD1, the third memory group MG3 and the fourth memory group MG4 are adjacent in the first horizontal direction HD1, the first memory group MG1 and the fourth memory group MG4 are adjacent in the second horizontal direction HD2, and the second memory group MG2 and the third memory group MG3 are adjacent in the second horizontal direction HD2. This particular configuration may be referred to as a 2×2 memory group arrangement. Referring to Figure 7-Figure 17 Any of the foregoing descriptions provided in one or more may be applied in the present embodiment.

[0172] Fig.30 is a diagram showing a method according to some example embodiments Fig.29 sectional view of a storage device 10d.

[0173] Reference Fig.30 , the first semiconductor layer L1 ′ may include a first substrate SUB1 , and the second semiconductor layer L2 ′ may include a second substrate SUB2 . Figure 1 The memory cell array 110 may be disposed in the first semiconductor layer L1'. A plurality of word lines WL may be stacked over the first substrate SUB1 and may be connected to corresponding pads PD1 through corresponding contact plugs CP1. Figure 1 The peripheral circuit 200 may be disposed in the second semiconductor layer L2'. Each of the first substrate SUB1 and the second substrate SUB2 may be a semiconductor substrate including a semiconductor material such as crystalline silicon or crystalline germanium, and may be manufactured from a silicon wafer.

[0174] A plurality of semiconductor devices (e.g., transistors TR) may be provided on the second substrate SUB2 included in the second semiconductor layer L2' and may be electrically connected to the contact pads PD2 through corresponding contact plugs CP2, metal lines M1, M2, and M3. For example, the semiconductor devices provided in the second semiconductor layer L2' may configure circuits corresponding to the first to fourth row decoders 311 to 314 and the first to fourth page buffers 321 to 324.

[0175] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

[0176] This application claims the benefit of Korean Patent Application No. 10-2018-0097561 filed in the Korean Intellectual Property Office on August 21, 2018, the subject matter of which is incorporated herein by reference.

Claims

1. A non-volatile memory, comprising: a first semiconductor layer vertically stacked on the second semiconductor layer and comprising a first memory group, a second memory group, a third memory group, and a fourth memory group, wherein the second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively below the first memory group, the second memory group, the third memory group and the fourth memory group, and The first region includes a row decoder and a page buffer, the row decoder is connected to the memory cells of one of the second memory group, the third memory group and the fourth memory group through a specific word line, and the page buffer is connected to the memory cells of the first memory group through a first bit line, wherein the specific word line and the first bit line extend in the same horizontal direction.

2. The nonvolatile memory according to claim 1, wherein each of the first memory group and the third memory group includes a word line extending in a first horizontal direction and a bit line extending in a second horizontal direction, and Each of the second memory group and the fourth memory group includes a word line extending in the second horizontal direction and a bit line extending in the first horizontal direction.

3. The nonvolatile memory of claim 2 , wherein the row decoder is a first row decoder connected to the specific word line of the one of the second memory group, the third memory group, and the fourth memory group, and the page buffer is a first page buffer connected to the first bit line of the first memory group.

4. The nonvolatile memory of claim 3 , wherein the first row decoder is disposed in the first region, between one of the second region, the third region, and the fourth region and the first page buffer, and the one of the second region, the third region, and the fourth region is below the one of the second memory group, the third memory group, and the fourth memory group.

5. The nonvolatile memory of claim 4, wherein the first row decoder extends along the entire length of a boundary between the first region and the one of the second region, the third region, and the fourth region, and the first page buffer occupies more than half of the first region.

6. The nonvolatile memory of claim 3, wherein the first memory group and the second memory group are adjacent in the first horizontal direction, the third memory group and the fourth memory group are adjacent in the first horizontal direction, the first memory group and the fourth memory group are adjacent in the second horizontal direction, and the second memory group and the third memory group are adjacent in the second horizontal direction.

7. The nonvolatile memory of claim 6, wherein the first row decoder is connected to word lines of the fourth memory group including the specific word line, and the first page buffer is connected to bit lines of the first memory group including the first bit line, The second region includes a second row decoder connected to the word lines of the first memory group and a second page buffer connected to the bit lines of the second memory group, The third region includes a third row decoder connected to the word lines of the second memory group and a third page buffer connected to the bit lines of the third memory group, and The fourth region includes a fourth row decoder connected to word lines of the third memory group and a fourth page buffer connected to bit lines of the fourth memory group.

8. The nonvolatile memory of claim 7, wherein the first row decoder is disposed in the first region and between the first page buffer and the fourth region, the second row decoder is disposed in the second region and between the second page buffer and the first region, the third row decoder is disposed in the third region and between the third page buffer and the second region, and the fourth row decoder is disposed in the fourth region and between the fourth page buffer and the third region.

9. The nonvolatile memory of claim 8, wherein the first row decoder extends along the entire length of a boundary between the first region and the fourth region, and the first page buffer occupies more than half of the first region, The second row decoder extends along the entire length of a boundary between the second region and the first region, and the second page buffer occupies more than half of the second region, The third row decoder extends along the entire length of a boundary between the third region and the second region, and the third page buffer occupies more than half of the third region, and The fourth row decoder extends along an entire length of a boundary between the fourth region and the third region, and the fourth page buffer occupies more than half of the fourth region.

10. The nonvolatile memory according to claim 2, wherein the first area, the second area, the third area, and the fourth area are arranged in a rectangular shape, and the nonvolatile memory further comprises: The pad area includes a plurality of pads and extends across at least a portion of an outer edge of the rectangle.

11. The nonvolatile memory of claim 2, wherein word lines of the first memory group, the second memory group, the third memory group, and the fourth memory group are isolated from each other, and bit lines of the first memory group, the second memory group, the third memory group, and the fourth memory group are isolated from each other, respectively.

12. The nonvolatile memory of claim 1 , wherein the first memory group and the second memory group are adjacent in a first horizontal direction, the third memory group and the fourth memory group are adjacent in the first horizontal direction, the first memory group and the fourth memory group are adjacent in a second horizontal direction, and the second memory group and the third memory group are adjacent in the second horizontal direction, The first memory group includes a first word line extending in the first horizontal direction and a first bit line extending in the second horizontal direction, the second memory group includes a second word line extending in the second horizontal direction and a second bit line extending in the first horizontal direction, The third memory group includes a third word line extending in the first horizontal direction and a third bit line extending in the second horizontal direction, and The fourth memory group includes a fourth word line extending in the second horizontal direction and a fourth bit line extending in the first horizontal direction.

13. The nonvolatile memory of claim 3 , wherein the first area, the second area, the third area, and the fourth area are arranged in a rectangular shape, and the first row decoder comprises: a first portion, centrally disposed in the rectangle and connected to at least one word line of the first memory group, and A second portion extends from the first portion of the first row decoder to an outer edge of the rectangle and is connected to the word line of at least one of the second memory group, the third memory group, and the fourth memory group.

14. The nonvolatile memory of claim 13, wherein the second portion of the first row decoder is connected to a word line of the fourth memory group.

15. The non-volatile memory of claim 14, wherein The second area includes: a second row decoder and a second page buffer connected to the bit lines of the second memory group, the second row decoder comprising a first portion and a second portion, the first portion being centrally disposed in the rectangle and connected to at least one word line of the second memory group, the second portion extending from the first portion of the second row decoder to an outer edge of the rectangle and connected to the word line of the first memory group; The third area includes: a third row decoder and a third page buffer connected to the bit lines of the third memory group, the third row decoder comprising a first portion and a second portion, the first portion being centrally disposed in the rectangle and connected to at least one word line of the third memory group, the second portion extending from the first portion of the third row decoder to an outer edge of the rectangle and connected to the word line of the second memory group; and The fourth area includes: A fourth row decoder and a fourth page buffer connected to the bit lines of the fourth memory group, the fourth row decoder comprising a first portion and a second portion, the first portion being centrally disposed in the rectangle and connected to at least one word line of the fourth memory group, the second portion extending from the first portion of the fourth row decoder to an outer edge of the rectangle and connected to the word line of the third memory group.

16. A non-volatile memory comprising: a first semiconductor layer vertically stacked on the second semiconductor layer and comprising a first memory group, a second memory group, a third memory group, and a fourth memory group, wherein the second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively below the first memory group, the second memory group, the third memory group and the fourth memory group, and The first region includes a first page buffer connected to a bit line of one of the second memory group, the third memory group, and the fourth memory group, and a first row decoder connected to a word line of the first memory group.

17. The nonvolatile memory of claim 16, wherein each of the first memory group and the third memory group includes a word line extending in a first horizontal direction and a bit line extending in a second horizontal direction, and Each of the second memory group and the fourth memory group includes a word line extending in the second horizontal direction and a bit line extending in the first horizontal direction.

18. The nonvolatile memory of claim 17, wherein the first page buffer is disposed in the first area and between one of the second area, the third area, and the fourth area and the first row decoder, and the one of the second area, the third area, and the fourth area is below the one of the second memory group, the third memory group, and the fourth memory group.

19. The nonvolatile memory of claim 18, wherein the first page buffer extends along and is adjacent to a boundary between the one region below the one of the second memory group, the third memory group, and the fourth memory group in the second region, the third region, and the fourth region and the first region.

20. The nonvolatile memory of claim 1 or 16, wherein the nonvolatile memory is one of a vertical NAND flash memory device (VNAND) and a phase change random access memory (PRAM).

21. A non-volatile memory comprising: a first semiconductor layer vertically stacked on the second semiconductor layer and comprising a first memory group, a second memory group, a third memory group, and a fourth memory group, wherein the second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively below the first memory group, the second memory group, the third memory group and the fourth memory group, and The first region includes one driving circuit connected to the first memory group and another driving circuit connected to both of the first memory group and one of the second memory group, the third memory group, and the fourth memory group, Wherein each of the first memory group and the third memory group includes a word line extending in a first horizontal direction and a bit line extending in a second horizontal direction, and each of the second memory group and the fourth memory group includes a word line extending in the second horizontal direction and a bit line extending in the first horizontal direction.

22. The nonvolatile memory of claim 21, wherein the one driving circuit is a row decoder connected to a word line of the first memory group, and The other driving circuit is a page buffer including a first page buffer portion connected to the bit line of the first memory group and a second page buffer portion connected to at least one bit line of the one of the second memory group, the third memory group, and the fourth memory group.

23. The nonvolatile memory of claim 22, wherein the first region includes a first outer edge extending in the first horizontal direction and a second outer edge extending in the second horizontal direction, The row decoder is arranged along the second outer edge, and The second page buffer portion is disposed along the first outer edge.

24. The non-volatile memory of claim 23, further comprising: A separation region extends in the second horizontal direction between the row decoder and the page buffer.

25. A non-volatile memory comprising: a first semiconductor layer vertically stacked on the second semiconductor layer and including a first memory group and a second memory group, wherein the second semiconductor layer includes a first region below the first memory group, a second region below the second memory group, and a peripheral region, The first memory group includes word lines extending in a first horizontal direction and bit lines extending in a second horizontal direction, the second memory group includes word lines extending in the second horizontal direction and bit lines extending in the first horizontal direction, The first region includes a first driving circuit connected to the first memory group, the second region includes a second driving circuit connected to the second memory group and a third driving circuit connected to the first memory group, and The peripheral region includes a fourth driving circuit connected to the second memory group.

26. The nonvolatile memory of claim 25, wherein the first driving circuit is a page buffer connected to the bit lines of the first memory group, The second driving circuit is another page buffer connected to the bit lines of the second memory group, The third driving circuit is a row decoder connected to the word lines of the first memory group, The fourth driving circuit is another row decoder connected to the word lines of the second memory group.

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