Electronic device and method for load balancing in multi-core processor

Abstract

The present invention provides an electronic device and a method for load balancing in a multi-core processor, the method comprising: the electronic device divides a first task and at least one second task into a plurality of task jobs; the electronic device determines at least one core configuration for each of the plurality of task jobs; the electronic device schedules each of the plurality of task jobs on at least one core of the multi-core processor based on the at least one core configuration to generate an execution schedule; and the multi-core processor executes the plurality of task jobs according to the execution schedule.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian Provisional Patent Application No. 201841031838 filed in the Indian Intellectual Property Office on August 24, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to load balancing in a multi-core environment, and more particularly, to a method and electronic device for an energy-aware real-time load balancer for 5th Generation (5G) and beyond 5th Generation (B5G) multi-core user equipment. Background Art

[0004] The 3rd Generation Partnership Project (3GPP) has developed a new 5G New Radio (5GNR). th 5G NR) is a new generation of radio technology to provide enhanced mobile broadband (eMBB) with higher throughput and ultra-reliable low latency communications (URLLC). Incorporating a multi-core architecture into the user equipment (UE) has been considered as a suitable solution to provide the increased computing associated with 5G NR. For example, the multi-core architecture may include a multi-core processor (MP) architecture (e.g., symmetric multi-processing (SMP) or asymmetric multi-processing (AMP)).

[0005] Supporting multi-core architectures involves some challenges, such as software partitioning and data synchronization for maximizing or improving multi-core utilization. Real-time Operating Systems (RTOS) are used with multi-core architectures by enabling programmers to control the binding of tasks to specific cores or by enabling the RTOS to control the binding of tasks to specific cores (e.g., by executing software instructions). Compared to the widespread adoption of multi-core architectures, there have been few improvements in automated software partitioning and data synchronization techniques when moving from single-core architectures to multi-core architectures.

[0006] Although compile-time techniques (such as Open Multi-Processing (OpenMP)) that allow programmers to write code that is suitable for multi-core architectures are available, such compile-time techniques are largely platform dependent. In order to achieve high performance of multi-core processors, each core should be utilized at its maximum efficiency or high efficiency. This can be achieved by using a load balancer (LB) that distributes tasks evenly across cores. The load balancer performs task allocation statically through offline analysis of the workload or in real time through online analysis of the workload.

[0007] The architecture for the multi-core processor system 100 is shown in Figure 1 . The multi-core processor system 100 includes N number of cores 102 (e.g., core 1, core 2 ... core N) and executes an RTOS. The RTOS is configured to schedule various tasks 108 (e.g., task 1, task 2 ... task M). Each task has three main characteristics: task priority, core affinity, and resource availability / allocation. The multi-core processor system 100 includes an operating system (OS) scheduler 104, which is configured to dispatch tasks to cores of the cores 102 based on the characteristics. The multi-core processor system 100 includes a load balancer 106, which is configured to keep track of the execution order and dependencies of the tasks 108. The load balancer 106 is configured to dynamically control the core affinity of various tasks so as to complete (e.g., process) the workload based on the execution order and / or dependencies of the tasks 108.

[0008] Upgrading legacy software for use with multi-core architectures involves analysis, redesign, and development of software. In Long Term Evolution (LTE) and New Radio (NR) modem baseband software (BBS) and protocol stack (PS) development, each of the tasks is designed to handle processing in the Non Access Stratum (NAS) layer, Radio Resource Control (RRC) layer, Packet Data Convergence Protocol (PDCP) layer, Radio Link Control (RLC) layer, Medium Access Control (MAC) layer, or physical layer. Single-core implementations cannot be extended for higher-order Multiple Input Multiple Output (MIMO) technologies with Carrier Aggregation (CA). Single-core implementations involve stabilizing and correcting the multi-core software architecture to achieve optimal or required performance. Performance is defined in terms of total execution time and energy consumption, and achieving optimality or improvement is a difficult, iterative, and time-consuming task. Therefore, it is expected that time-consuming tasks can be reduced by supporting the adoption of multi-core architectures without requiring a lot of work from BBS and PS software developers.

[0009] It would therefore be desirable to address the above-mentioned or other disadvantages or at least provide a useful alternative. Summary of the invention

[0010] Some exemplary embodiments provide methods for energy-aware load balancing in multi-core processor systems for 5G and B5G networks in real time.

[0011] Some exemplary embodiments provide for dividing each of a plurality of tasks into a plurality of task jobs.

[0012] Some exemplary embodiments provide for scheduling each of task jobs on at least one core of a multi-core processor system based on at least one core configuration.

[0013] Some exemplary embodiments provide for aggregating the output of each of the task jobs.

[0014] Some example embodiments provide for obtaining profile data for at least one task.

[0015] Therefore, some exemplary embodiments provide a method for load balancing in a multi-core processor of an electronic device. The method includes: dividing a first task and at least one second task into a plurality of task jobs by an electronic device; determining at least one core configuration for each of the plurality of task jobs by the electronic device; scheduling each of the plurality of task jobs on at least one core of the multi-core processor based on the at least one core configuration to generate an execution schedule by the electronic device; and executing the plurality of task jobs according to the execution schedule by the multi-core processor.

[0016] In some exemplary embodiments, dividing a first task and at least one second task into multiple task jobs includes: obtaining, by an electronic device, profile data of the first task and at least one second task, the profile data including at least one of the following: individual entry points of the first task and at least one second task, individual exit points of the first task and at least one second task, individual execution times of the first task and at least one second task, individual preemption states of the first task and at least one second task, an inter-task communication type between the first task and at least one second task, an inter-task communication metric or an interaction metric between the first task and at least one second task; and dividing, by the electronic device, the first task and at least one second task into multiple task jobs based on the profile data.

[0017] The partitioning further includes analyzing the execution flow of the first task and the at least one second task, wherein the execution flow includes at least one of the following: the execution time of the first task and the at least one second task and / or the consumption execution of the first task and the at least one second task. The partitioning also includes analyzing the profile data of the first task and the at least one second task, and partitioning the first task and the at least one second task into a plurality of task tasks based on the profile data analysis and the execution flow analysis.

[0018] In some exemplary embodiments, the method for load balancing further includes performing, by the electronic device, at least one of the following operations: aggregating multiple task jobs to form at least one new task based on profile data of the multiple task jobs, or aggregating a first task and at least one second task to form at least one new task based on profile data.

[0019] In some exemplary embodiments, the profile data includes an interaction metric and an inter-task communication metric, the interaction metric being an interaction cost, and the inter-task communication metric being an inter-task communication cost between the first task and at least one second task.

[0020] In some exemplary embodiments, determining at least one core configuration for each of a plurality of task jobs includes: determining, by an electronic device, a utilization level of each of a plurality of cores of a multi-core processor; determining, by the electronic device, an individual interaction metric between two or more task jobs among the plurality of task jobs and an individual communication metric between two or more task jobs; determining, by the electronic device, a total execution time for each of the plurality of task jobs; and determining, by the electronic device, at least one core configuration based on the utilization level, the individual interaction metric, the individual communication metric, and the total execution time for each of the plurality of task jobs.

[0021] In some exemplary embodiments, at least one of the core configurations identifies a plurality of task jobs and at least one core of a multi-core processor on which the plurality of task jobs are to be scheduled and executed.

[0022] In some exemplary embodiments, the individual interaction metric is the individual interaction cost between two or more task works, and the individual communication metric is the individual communication cost between two or more task works, and determining at least one core configuration includes: determining the individual task work with the highest dependency among the multiple task works based on the individual interaction metric and the individual communication metric; and specifying the individual task work and the task work on which the individual task work depends among the multiple task works to be executed on a single core among the multiple cores.

[0023] Some exemplary embodiments provide an electronic device including a multi-core environment for load balancing. The electronic device includes: a multi-core processor configured to execute a plurality of task jobs according to an execution schedule; and a processing circuit configured to divide a first task and at least one second task into the plurality of task jobs, determine at least one core configuration for each of the plurality of task jobs, and schedule each of the plurality of task jobs on at least one core of the multi-core processor based on the at least one core configuration to generate an execution schedule.

[0024] These and other aspects of some exemplary embodiments will be better understood and appreciated when considered in conjunction with the following description and accompanying drawings. However, it should be understood that the following description, while indicating some exemplary embodiments and many of their specific details, is given by way of illustration and is not limiting. Many changes and modifications may be made within the scope of some exemplary embodiments without departing from the spirit of the exemplary embodiments, and some exemplary embodiments include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Some exemplary embodiments are shown in the accompanying drawings, and the same reference numerals indicate corresponding components in the various figures throughout the accompanying drawings. Some exemplary embodiments of the present invention will be better understood according to the following description with reference to the drawings, in which:

[0026] Figure 1 is a block diagram of a conventional multi-core processor architecture with a load balancer and an OS scheduler.

[0027] Figure 2 is a block diagram of an electronic device for load balancing in a multi-core processor of the electronic device according to some exemplary embodiments.

[0028] Figure 3 is a block diagram of a multi-core processor for load balancing according to some exemplary embodiments.

[0029] Figure 4 is a schematic diagram illustrating a task work model according to some exemplary embodiments.

[0030] Figure 5 is a diagram illustrating an exemplary calculation of execution time of task work according to some exemplary embodiments.

[0031] Figure 6 is a directed acyclic graph (DAG) illustrating the runtime and communication costs of various task jobs according to some exemplary embodiments.

[0032] Figure 7 is a DAG illustrating the calculation of d-values ​​for task work, according to some exemplary embodiments.

[0033] Figure 8 is a DAG illustrating grouping of task work according to some exemplary embodiments. DETAILED DESCRIPTION

[0034] Some exemplary embodiments herein and their various features and advantageous details are explained with reference to non-limiting embodiments, which are shown in the accompanying drawings and described in detail in the following description. The description of well-known components and processing techniques may be omitted to avoid unnecessary confusion of some exemplary embodiments. In addition, some exemplary embodiments described herein are not necessarily mutually exclusive, because some exemplary embodiments may be combined with one or more other exemplary embodiments to form new embodiments. Unless otherwise indicated, the term "or" as used herein refers to non-exclusive or. The examples used herein are intended only to promote the understanding of the practical modes of some exemplary embodiments herein, and further enable those skilled in the art to practice some exemplary embodiments. Therefore, examples should not be construed as limiting the scope of some exemplary embodiments.

[0035] As is conventional in the art, some exemplary embodiments may be described and illustrated in terms of blocks that perform one or more functions described. These blocks, which may be referred to herein as managers, units, modules, hardware components, or the like, may be physically implemented by processing circuitry. The term 'processing circuitry' as used in the present disclosure may refer to hardware including, for example, logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. According to some exemplary embodiments, blocks may be physically implemented by analog and / or digital circuits and / or may be optionally driven by firmware and software, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, fixed-line circuits and / or the like. For example, the circuit may be implemented in one or more semiconductor chips and / or on a substrate support such as a printed circuit board and / or the like. The circuits constituting the blocks may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuits) or by a combination of dedicated hardware to perform some functions of the blocks and processors, thereby performing other functions of the blocks. Each described and / or illustrated block may be physically separated into two or more than two interactive and discrete blocks without departing from the scope of the present disclosure. Similarly, the described and / or illustrated blocks may be physically combined into more complex blocks without departing from the scope of the present disclosure.

[0036] The accompanying drawings are used to help easily understand various technical features, and it should be understood that some exemplary embodiments presented herein are not limited by the accompanying drawings. Thus, except for those specifically described in the accompanying drawings, the present disclosure should be understood to extend to any variations, equivalents, and substitutions. Although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are generally used only to distinguish one element from another element.

[0037] Therefore, some exemplary embodiments provide a method for load balancing in a multi-core processor. The method includes dividing at least one task into a plurality of task jobs. The method further includes determining at least one core configuration for each of the task jobs. The method also includes scheduling each of the task jobs on at least one core of the multi-core processor system based on the at least one core configuration. The method further includes aggregating outputs of each of the task jobs.

[0038] Unlike conventional methods, the proposed load balancer for RTOS running on MP minimizes or reduces energy consumption while maintaining an average or balanced computational load on multiple cores. According to some exemplary embodiments, the load balancer is configured to ensure the optimal or desired distribution of tasks on the available cores in a manner that makes the computational load balanced among the cores and the energy consumption of the cores is minimized or low. The energy consumption of the cores is proportional to the total runtime of the tasks. Therefore, minimizing or reducing the total runtime of all tasks causes minimizing or reducing energy consumption.

[0039] Now refer to the diagram, and more specifically, to Figures 2 to 8 ), some exemplary embodiments are shown.

[0040] Figure 2 2 is a block diagram of an electronic device 200 according to some exemplary embodiments. In some exemplary embodiments, the electronic device 200 includes a memory 210, a multi-core processor 220, and / or a communicator 230. The multi-core processor 220 includes a plurality of cores (e.g., core-1 220A, core-2 220B, ... core-N 220N). The multi-core processor 220 is configured to execute instructions stored in the memory 210 and perform various processes. The communicator 230 is configured to communicate internally between internal hardware components and / or communicate with external devices via one or more networks.

[0041] Memory 210 may be configured to store instructions to be executed by multi-core processor 220. Memory 210 may include non-volatile storage elements. Examples of such non-volatile storage elements may include magnetic hard disks, optical disks, floppy disks, flash memory, and / or various forms of erasable programmable memories (EPROM) and / or electrically erasable and programmable read only memories (EEPROM). In addition, in some examples, memory 210 may be considered a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not implemented in a carrier wave or propagating signal. However, the term "non-transitory" should not be interpreted to mean that memory 210 is non-removable. In some examples, memory 210 may be configured to store a larger amount of information than memory (e.g., over time, memory 210 may store an amount of data that exceeds the capacity of memory 210 by deleting previously stored data and storing new data). In some examples, non-transitory storage media may store data that may change over time (eg, in random access memory (RAM) and / or cache memory).

[0042] In some exemplary embodiments, the electronic device 200 may include processing circuitry configured to perform energy-aware load balancing in real time.

[0043] Although Figure 2 Various hardware components of the electronic device 200 are shown, but it should be understood that some exemplary embodiments are not limited thereto. In some exemplary embodiments, the electronic device 200 may include fewer or more components. In addition, the identification or names of the components are used only for illustrative purposes and do not limit the scope of some exemplary embodiments.

[0044] Figure 3is a block diagram of a load balancer for balancing tasks. According to some exemplary embodiments, the load balancer 300 may be included in the electronic device 200. According to some exemplary embodiments, the load balancer 300 may be included in the multi-core processor 220. According to some exemplary embodiments, the task may be a software process, a thread, an operation, etc. The load balancer 300 may be configured to balance the load on the multi-core processor 220 for efficient work. The load balancer 300 includes a task divider 310, a task profiler 320, a profiler analyzer 330, and / or a task work scheduler 340. In some exemplary embodiments, the multi-core processor 220 includes (e.g., receives and / or stores) several tasks for execution. The task divider 310 may divide the task into a plurality of task works based on the profile data of the task. According to some example embodiments, the task work may be a sub-process of the task, such as a software loop, a function, a mathematical calculation, etc. The profile data may be obtained by the task profiler 320. The profiler analyzer 330 may generate a graph showing (e.g., organizing) a plurality of task works based on the profile data. According to some exemplary embodiments, the operations described herein may be performed by the processing circuitry as they are performed by the electronic device 200, the load balancer 300, the task divider 310, the task profiler 320, the profiler analyzer 330, and / or the task work scheduler 340.

[0045] After generating the graph, the task work scheduler 340 may schedule the tasks onto multiple cores (e.g., core-1 220A, core-2 220B, ... core-N 220N) for efficient execution. In some exemplary embodiments, the load balancer 300 may determine at least one core configuration for each of the task work. In some exemplary embodiments, the load balancer 300 may form a new dynamic task for each task work, wherein two or more task works from the same parent task or similar parent tasks are allocated on different cores. According to some exemplary embodiments, the load balancer 300 may determine a utilization level of each of the cores of the multi-core processor, determine an interaction metric (e.g., an interaction cost between multiple task works) and a communication metric (e.g., a communication cost between multiple task works), determine a total execution time for each of the task works, and determine at least one core configuration (e.g., at least one core on which the multiple task works will be scheduled and executed) based on the utilization level, the interaction metric, the communication metric, and the total execution time. According to some exemplary embodiments, the load balancer 300 may determine an individual task work with the highest dependency among multiple task works based on interaction metrics and communication metrics, and determine at least one core configuration so that the individual task work with the highest dependency (e.g., the task work with the highest number of other task works on which it depends) and the task work on which the individual task work depends are executed on the same core or similar cores.

[0046] Figure 4 is a schematic diagram of the task work model. Figure 4 As can be seen in , a task can be divided into a plurality of task jobs: job-1, job-2 ... job-K by the task divider 310. In some exemplary embodiments, profile data for each task, each of which will be divided into a plurality of task jobs, can be obtained by the task profiler 320. The profile data to be obtained may include an entry point of a task, an exit point of a task, an execution time of a task, a preemption state of a task, an inter-task communication type between a task and another task, an inter-task communication metric (e.g., an inter-task communication cost) and / or an interaction metric (e.g., an interaction cost between a task and another task) for communication between tasks. The inter-task communication cost may correspond to the time for a task and another task to communicate between tasks. After obtaining the profile data, the profiler analyzer 330 may perform a profiler analysis on the obtained profile data. Based on the profiler analysis, the task divider 310 may divide the task into a plurality of task jobs.

[0047] In some exemplary embodiments, the profiler analyzer 330 may generate a directed acyclic graph (DAG) based on the profile data. The load balancer 300 may calculate task work metrics based on the generated DAG. The task work metrics may include start times and / or communication times between multiple task works. Based on the values ​​in the DAG, the load balancer 300 may calculate task work execution times and / or inter-task work communication times for multiple task works. The task work execution time and / or inter-task work communication time may be calculated by the load balancer 300 based on the start time of the current task work (the time when the communication between the current task work and the next task work is triggered) and / or the start time of the next task work (e.g., as provided in the DAG).

[0048] Figure 5 FIG. 1 is a schematic diagram showing an example of calculating the execution time of a task work according to some exemplary embodiments. Figure 5 As seen in FIG. 1 , task work T1 starts at time 't1=0' microseconds (us) and sends message M12 to task work T2 at time 't2=150' microseconds. T2 then starts at time 't3=200' microseconds. Therefore, the execution time for T1=(t2-t1)=150 microseconds, and the inter-task work communication time between T1 and T2 is (t3-t2)=50 microseconds. Based on the execution time of the task work and the inter-task work communication time, the task work scheduler 340 can schedule multiple task works to one or more cores of the multi-core processor 220.

[0049] In some exemplary embodiments, an epoch is defined for the generated DAG. An epoch is a predefined or defined single unit of time during which the load balancer 300 is operable.

[0050] Figure 6 A DAG showing the calculation of runtime (eg, execution time) and communication cost (eg, inter-task worker communication time) for various task workers is depicted according to some exemplary embodiments. Figure 6 In the above example, V is the set of nodes and E is the set of edges. At each node, T u Indicates the task work identifier. u The value of represents the running time μ(u) of the task work corresponding to the task work identifier. u With T v The interaction metric or communication cost between is represented by the edge γ(u,v). A directed edge means that the task work T v Can only work in task T u Completed and waiting for task work T v The use of data is ready (e.g., dependencies). In addition, the value on the edge γ(u,v) indicates when Tu and T v The communication cost when the two processes are on different cores (e.g., executed by different cores). When T u and T v When on the same core or similar cores, the communication cost γ(u,v) is scaled down by a constant factor α depending on the underlying processor architecture, where 0≤α≤1.

[0051] In addition, if the communication cost between two task jobs is sufficiently higher than the total execution time of the two task jobs (e.g., a high threshold), the task job scheduler 340 may not schedule the two task jobs on different cores (e.g., for parallelization). The DAG may be partitioned into as many groups (e.g., partitions) as the number of cores so that: all groups have the same or nearly the same execution time, and the communication cost between groups is reduced to a minimum or low cost.

[0052] The example DAG is shown in Figure 6 In DAG, there are root nodes and sink nodes. The root node is a task that does not have any parent. For example, in Figure 6 In , T1 and T2 are root nodes. A sink node is a task that has a parent but no children. For example, in Figure 6 In the example, T8, T9, and T10 are sink nodes. In addition, the start time of a task is the longest path from the root node to itself. Mathematically, assuming that s(v) is T v The start time of is given by equation (1).

[0053] s(v)=max{s(u)+μ(u)+γ(u,v)|(u,v)∈E} Equation (1)

[0054] Given a task job T v The d value d(v) is obtained from T v The longest path to the sink node in the current partition. Given a task job T v The t value t(v) is the value of the given task work T when it is part of the current partition. v The total time taken to complete the execution. Mathematically, assume that t(v) is defined as given in equation (2).

[0055] t(v)=s(v)+d(v) Equation (2)

[0056] First, for each node T in the graph v, s(v), d(v), and t(v) are calculated (e.g., by the task work scheduler 340). The task work scheduler 340 groups the task work into a given cluster (e.g., group and / or partition) based on t(v) for the task work. The task work scheduler 340 may begin by placing each host node v into its own group (e.g., partition and / or cluster). Subsequently, the task work scheduler 340 may consider grouping each such node u, all of whose direct descendants have been assigned to a group. Such nodes are referred to as new task work. For each new task work u, d(u) may be calculated as provided in equation (3), where v represents each direct descendant task work of the new task work u.

[0057] d(u)=max{μ(u)+γ(u,v)+d(v)} Equation (3)

[0058] The direct children that define d(u) are called the best children and can be used by the task job scheduler 340 when grouping. In some exemplary embodiments, two or more new task jobs may have the same dominant children or similar dominant children. After calculating the d values ​​d(u) for all new task jobs, the corresponding t values ​​are calculated.

[0059] Figure 7 A schematic diagram showing the calculation of the d value for a new task job is shown. Figure 7 , T2 and T3 are new task jobs because all their children are already grouped. However, T1 is not a new task job because its child T3 is still not grouped. The d value of T2 can be calculated as max{μ(T2)+γ(T2, T4)+d(T4),μ(T2)+γ(T2, T5)+d(T5)}=max{50+40+170,50+90+80}=260. Individually, for new task job T2, it is determined that the direct child task job T5 is the best child. After calculating the t values ​​of all new task jobs, the new task jobs are arranged in descending order of their t values.

[0060] For a new task job u, assume v is the best child under the maximum (e.g., highest) t(u). In addition, assume v is a member of group G v If the assignment will reduce d(u) or d(G v ) (referred to herein as condition (A)), but both will not be increased, and the t value of the combined group will not exceed a threshold value (e.g., the threshold value determined using equation (4)), then the task work scheduler 340 may assign the new task work u to group G v In equation (4), N is the number of cores on the multi-core processor.

[0061]

[0062] If the above two conditions (i.e., condition (A) and equation (4)) are not met, then the task work scheduler 340 may assign the new task work u to the group completely independently. When a new task work is added to a group, the communication cost between the new task work and the group is scaled down by a factor α. Consider the example of grouping new task work, where α = 0.5. From Figure 7 , it is observed that if T3 is merged into T4's group, then d(T3) decreases from 320 to 285. Furthermore, d(T4) remains unchanged. However, s(T4) decreases from 330 to 300. Similarly, T2 may not be merged into T4's group because the merger will increase d(T2). Figure 8 Draws the merged groups.

[0063] The process of scheduling task work, merging groups, and processing the DAG as discussed above may continue until all nodes of the graph are processed. According to some exemplary embodiments, once a new task work is assigned to a group, the parent task work of the most recently assigned task work may become the new task work, and the process may be repeated with respect to the new task work. According to some exemplary embodiments, the load balancer 300 (e.g., the profiler analyzer 330) may aggregate two or more task works to form at least one new task based on analysis of profile data of the two or more task works.

[0064] In some exemplary embodiments, the number of groups output by the proposed method may be greater than the number of cores. In such cases, the groups may be merged. Assume that group G1 has the smallest or lowest workload among all groups, and group G2 also has the smallest or lowest workload, or the second lowest workload, among all groups, then in this case, group G1 and group G2 may be merged. Therefore, some exemplary embodiments provide a load balancer configured to split software tasks configured for a single-core processor into groups of subtasks for execution on a multi-core processor, thereby providing an average or nearly average load across the cores of the multi-core processor. By providing an average or nearly average load across the cores of the multi-core processor, the load balancer reduces the processing time of the multi-core processor while reducing the energy consumption of the multi-core processor.

[0065] Some of the exemplary embodiments disclosed herein may be implemented using processing circuitry.For example, some of the exemplary embodiments disclosed herein may be implemented using at least one software program running on at least one hardware device and performing network management functions to control elements.

[0066] The foregoing description of some exemplary embodiments will fully disclose the general nature of the exemplary embodiments so that by utilizing current knowledge, others can easily modify these exemplary embodiments and / or adapt these exemplary embodiments to various applications without departing from the general concept, and therefore, these adaptations and modifications should and are intended to be included in the meaning and scope of equivalents of some exemplary embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation. Therefore, although some exemplary embodiments herein have been described in terms of examples, those skilled in the art will recognize that some exemplary embodiments may be practiced with modifications within the spirit and scope of some exemplary embodiments as described herein.

Claims

1. A method for load balancing in a multi-core processor of an electronic device, the method comprising: The electronic device divides the first task and at least one second task into a plurality of task tasks; determining, by the electronic device, at least one core configuration for each of the plurality of task jobs; The electronic device schedules each of the plurality of task jobs on at least one core of the multi-core processor based on the at least one core configuration to generate an execution schedule; as well as The multi-core processor executes the multiple tasks according to the execution schedule, Wherein determining at least one core configuration comprises: determining, by the electronic device, a utilization level of each of a plurality of cores of the multi-core processor; determining, by the electronic device, individual interaction metrics between two or more task tasks among the plurality of task tasks and individual communication metrics between the two or more task tasks; determining, by the electronic device, a total execution time of each of the plurality of task jobs; and The at least one core configuration is determined by the electronic device based on the utilization level, the individual interaction metrics, the individual communication metrics, and the total execution time of each of the plurality of task jobs.

2. The method according to claim 1, wherein the partitioning comprises: Obtaining, by the electronic device, profile data of the first task and the at least one second task, the profile data comprising at least one of the following: individual entry points of the first task and the at least one second task, individual exit points of the first task and the at least one second task, individual execution times of the first task and the at least one second task, individual preemption states of the first task and the at least one second task, an inter-task communication type between the first task and the at least one second task, an inter-task communication metric between the first task and the at least one second task, or an interaction metric; as well as The first task and the at least one second task are divided into the plurality of task tasks by the electronic device based on the profile data.

3. The method according to claim 1, further comprising: At least one of the following is performed by the electronic device: aggregating the plurality of task jobs to form at least one new task based on the profile data of the plurality of task jobs, or The first task and the at least one second task are aggregated based on the profile data to form the at least one new task.

4. The method of claim 2, wherein the profile data comprises the interaction metric and the inter-task communication metric, the interaction metric being an interaction cost, and the inter-task communication metric being an inter-task communication cost between the first task and the at least one second task.

5. The method of claim 1, wherein the at least one core configuration identifies the plurality of task jobs and the at least one core of the multi-core processor on which the plurality of task jobs are to be scheduled and executed.

6. The method according to claim 1, wherein The individual interaction metric is an individual interaction cost between the two or more task jobs, and the individual communication metric is an individual communication cost between the two or more task jobs; and Determining the at least one core configuration comprises: determining, based on the individual interaction metric and the individual communication metric, an individual task work having the highest dependency among the plurality of task works, and The individual task work and a task work among the plurality of task works on which the individual task work depends are specified to be executed on a single core among the plurality of cores.

7. An electronic device comprising a multi-core environment for load balancing, the electronic device comprising: A multi-core processor configured to execute multiple tasks according to an execution schedule; as well as The processing circuit is configured as follows: dividing the first task and at least one second task into the plurality of task tasks, determining at least one core configuration for each of the plurality of task jobs, and scheduling each of the plurality of tasks on at least one core of the multi-core processor based on the at least one core configuration to generate the execution schedule, The processing circuit is configured to determine at least one core configuration for each of the plurality of task jobs by: determining a utilization level of each of a plurality of cores of the multi-core processor; determining individual interaction metrics between two or more task works among the plurality of task works and individual communication metrics between the two or more task works; determining a total execution time for each of the plurality of task jobs; as well as The at least one core configuration is determined based on the utilization level, the individual interaction metrics, the individual communication metrics, and the total execution time of each of the plurality of task jobs.

8. The electronic device according to claim 7, wherein the processing circuit is configured to divide the first task and the at least one second task into a plurality of task tasks by: obtaining profile data of the first task and the at least one second task, the profile data comprising at least one of: individual entry points of the first task and the at least one second task, individual exit points of the first task and the at least one second task, individual execution times of the first task and the at least one second task, individual preemption states of the first task and the at least one second task, an inter-task communication type between the first task and the at least one second task, an inter-task communication metric between the first task and the at least one second task, or an interaction metric; and The first task and the at least one second task are divided into the plurality of task tasks based on the profile data.

9. The electronic device of claim 7, wherein the processing circuit is configured to perform at least one of the following: aggregating the plurality of task works to form at least one new task based on the profile data of the plurality of task works; or A plurality of tasks are aggregated based on profiler data of the plurality of tasks to form the at least one new task.

10. The electronic device of claim 8, wherein the profile data comprises the interaction metric and the inter-task communication metric, the interaction metric being an interaction cost, and the inter-task communication metric being an inter-task communication cost between the first task and the at least one second task.

11. The electronic device of claim 7, wherein the at least one core configuration identifies the plurality of task jobs and the at least one core of the multi-core processor on which the plurality of task jobs are to be scheduled and executed.

12. The electronic device according to claim 7, wherein The individual interaction metric is an individual interaction cost between the two or more task jobs, and the individual communication metric is an individual communication cost between the two or more task jobs; and Determining the at least one core configuration comprises: determining, based on the individual interaction metric and the individual communication metric, an individual task work having the highest dependency among the plurality of task works, and The individual task work and a task work among the plurality of task works on which the individual task work depends are specified to be executed on a single core among the plurality of cores.

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