Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes a mounting substrate including at least one bonding pad, a first semiconductor chip disposed on the mounting substrate and including a first protrusion on an upper surface of the first semiconductor chip, a first spacer ball electrically connected to the first semiconductor chip, a first bump ball electrically connected to the first spacer ball, and a first wiring electrically connecting the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wiring includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0099332, filed on August 24, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The apparatus and method according to exemplary embodiments of the present invention relate to a semiconductor package including a folded loop and a normal loop. Background Technology

[0004] Recently, semiconductor chips have increased in size while requiring high-performance components. Furthermore, to meet the demands for multifunctionality and high capacity in semiconductor packages, a multi-chip semiconductor package has been developed, in which multiple semiconductor chips are stacked within a single package.

[0005] However, as electronic devices using semiconductor packages become thinner, the size of these packages tends to decrease. To meet this trend of shrinking electronic device size, various researches are being conducted on methods that can reduce the size of semiconductor packages. Summary of the Invention

[0006] Various embodiments of the present invention provide a miniaturized semiconductor package that improves product reliability.

[0007] However, the inventive concept is not limited to the embodiments described herein; rather, various other embodiments will become apparent to those skilled in the art upon which the inventive concept pertains from the detailed description of these embodiments.

[0008] According to some embodiments of the present invention, a semiconductor package is provided, which may include: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate and including a first protrusion on an upper surface of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first convex ball electrically connected to the first spacer ball; and a first wiring that electrically connects the first convex ball and the bonding pad without contacting the first protrusion, wherein the first wiring includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad.

[0009] According to some embodiments of the inventive concept, there is provided a semiconductor package, which can include at least one bonding pad, a first semiconductor chip including a first chip pad connected to the bonding pad and a first protrusion protruding from an upper surface of the first chip pad, a first spacer ball on the first chip pad, a first bump ball on the first spacer ball, a first wire connecting the first bump ball with the bonding pad without contacting the first protrusion, a second semiconductor chip disposed on the first semiconductor chip and including a second chip pad connected to the bonding pad and a second protrusion protruding from an upper surface of the second chip pad, a second bump ball directly connected to the second chip pad, and a second wire connecting the second bump ball and the bonding pad without contacting the second protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad, and the second wire does not extend in the direction away from the bonding pad.

[0010] According to some embodiments of the inventive concept, there is provided a semiconductor package, which can include a mounting substrate including at least one bonding pad, a first semiconductor chip disposed on the mounting substrate and including a first chip pad and a first protrusion protruding from the first chip pad, a second semiconductor chip disposed on the first semiconductor chip and including a second chip pad and a second protrusion protruding from an upper surface of the second chip pad, a third semiconductor chip disposed on the second semiconductor chip and including a third chip pad and a third protrusion protruding from an upper surface of the third chip pad, and a first wire, a second wire, and a third wire connecting the first chip pad, the second chip pad, and the third chip pad to the bonding pad, respectively, wherein the second wire is connected to the second chip pad by a second spacer ball disposed on the second chip pad and a second bump ball disposed on the second spacer ball, wherein the first chip pad and the third chip pad do not overlap the second semiconductor chip in a vertical direction, wherein the second chip pad overlaps the first semiconductor chip and the third semiconductor chip in the vertical direction, and wherein the second wire includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects and features of the inventive concept will become clearer from the following detailed description of exemplary embodiments thereof, taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram illustrating a semiconductor package according to some embodiments;

[0013] Figure 2 is a schematic diagram for describing a wafer including a semiconductor chip region according to some embodiments;

[0014] Figure 3A and Figure 3B is a schematic diagram for explaining a process of forming a protrusion of a semiconductor chip according to some embodiments;

[0015] Figure 4 is an enlarged view of the area A shown in Figure 1 enlarged manner according to some embodiments;

[0016] Figure 5 is a schematic diagram showing a semiconductor package in which semiconductor chips are vertically stacked according to some embodiments;

[0017] Figure 6 is a schematic diagram showing a semiconductor package according to some embodiments;

[0018] Figure 7 is a schematic diagram showing a semiconductor package according to some embodiments; and

[0019] Figures 8 to 16 is a schematic diagram for explaining a process of manufacturing a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0020] The embodiments provided herein are all examples and do not limit the inventive concept. The embodiments provided in the following description do not preclude the combination of one or more features with one or more other features provided in the same embodiment or in another embodiment provided herein or not provided herein but consistent with the inventive concept. For example, unless otherwise stated in the description, what is described in a particular example can be understood as relating or combining with a different example even if it is not described in the different example.

[0021] It should be understood that when an element or layer is referred to as being “on”, “above”, “over”, “connected to” or “coupled to” another element or layer, it can be directly on, above, over, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being “directly on”, “directly above”, “directly over”, “directly connected to”, or “directly coupled to” another element or layer, then there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0022] Figure 1 is a schematic diagram showing a semiconductor package according to some embodiments.

[0023] Referring toFigure 1 The semiconductor package can include a mounting substrate 100, a first semiconductor chip 120a, a first adhesive film 121, a first spacer ball 150a, a first convex ball 160a, a first wiring 170a, and a first molding resin 180.

[0024] The first semiconductor chip 120a can be disposed on the mounting substrate 100. The first adhesive film 121 can be disposed between the first semiconductor chip 120a and the mounting substrate 100. For example, the first semiconductor chip 120a can be fixed to the mounting substrate 100 by the first adhesive film 121. For example, the first adhesive film 121 can be a die attach film (DAF).

[0025] The mounting substrate 100 can include a first bonding pad 110a on a surface on which the first semiconductor chip 120a is disposed. The first semiconductor chip 120a can include a first chip pad 130a on a surface opposite to the surface connected to the mounting substrate 100.

[0026] The first spacer ball 150a can be disposed on the first semiconductor chip 120a. For example, the first spacer ball 150a can be connected to the first chip pad 130a of the first semiconductor chip 120a. The first convex ball 160a can be disposed on the first spacer ball 150a. For example, the first convex ball 160a can be connected to the first spacer ball 150a.

[0027] The first wiring 170a can electrically connect the first semiconductor chip 120a and the mounting substrate 100. For example, the first wiring 170a can connect the first chip pad 130a of the first semiconductor chip 120a and the first bonding pad 110a of the mounting substrate 100, thereby electrically connecting the first semiconductor chip 120a and the mounting substrate 100.

[0028] The first molding resin 180 can be formed on the mounting substrate 100 to cover the first semiconductor chip 120a, the first adhesive film 121, the first bonding pad 110a, the first spacer ball 150a, the first convex ball 160a, and the first wiring 170a. The first molding resin 180 can protect internal constituent elements of the semiconductor package. For example, the first molding resin 180 can prevent or reduce external impact from being transmitted to the mounting substrate 100, the first semiconductor chip 120a, the first adhesive film 121, the first bonding pad 110a, the first spacer ball 150a, the first convex ball 160a, and the first wiring 170a. For example, the first molding resin 180 can be an epoxy molding compound (EMC), but embodiments are not limited thereto.

[0029] According to some embodiments, the mounting substrate 100 can be a package substrate, and can be, for example, a printed circuit board (PCB), a ceramic substrate, or the like. On a lower surface of the mounting substrate 100, that is, on a surface opposite to a mounting surface on which the first semiconductor chip 120a is disposed, external terminals (e.g., solder balls or a lead frame) that electrically connect the semiconductor package to external devices can be formed. The first bonding pad 110a can be electrically connected to the external terminals (to the external devices), and can supply an electrical signal to the first semiconductor chip 120a. Alternatively, the first bonding pad 110a can be, for example, a ground pad, and can be electrically connected to a ground line in the mounting substrate 100. The first bonding pad 110a is shown, for example, as being disposed in a housing of the mounting substrate 100, but embodiments are not limited thereto.

[0030] According to some embodiments, for example, the first semiconductor chip 120a can be a memory chip, a logic chip, or the like. When the first semiconductor chip 120a is a logic chip, various designs can be made in consideration of operations to be performed. When the first semiconductor chip 120a is a memory chip, the memory chip can be, for example, a non-volatile memory chip. For example, the first semiconductor chip 120a can be a flash memory chip. For example, the first semiconductor chip 120a can be one of a NAND flash memory chip and a NOR flash memory chip. However, the form of the memory device according to the technical idea of the present inventive concept is not limited thereto. In some embodiments, the first semiconductor chip 120a can be one of a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), and a resistive random access memory (RRAM).

[0031] According to some embodiments, the first chip pad 130a of the first semiconductor chip 120a can be electrically connected to a semiconductor element within the first semiconductor chip 120a. Accordingly, the electrical signal received by the first bonding pad 110a can be transmitted to the first chip pad 130a of the first semiconductor chip 120a through the first wiring 170a. The electrical signal transmitted to the first chip pad 130a of the first semiconductor chip 120a can be transmitted to the semiconductor element within the first semiconductor chip 120a.

[0032] According to some embodiments, the first semiconductor chip 120a can include a first protrusion 140a. The first protrusion 140a can include a portion protruding in a vertical direction Z from an upper surface 120a_us of the first semiconductor chip. In some drawings, the first protrusion 140a is shown as a rectangular portion protruding in the vertical direction Z from the upper surface 120a_us of the first semiconductor chip, but embodiments are not limited thereto. For example, the first protrusion 140a can have various shapes such as a triangle or an inclined triangle. Reference will be made to FIGS. 2A and 2B for a detailed description of the first protrusion 140a. Figure 2 、 Figure 3A and Figure 3BA process of generating the first protrusion 140a of the first semiconductor chip 120a is described.

[0033] Figure 2 is a schematic diagram for describing a wafer including a semiconductor chip region according to some embodiments. Figure 3A and Figure 3B is a schematic diagram for explaining a process of forming a protrusion of a semiconductor chip according to some embodiments.

[0034] Referring to Figure 2 , the wafer 200 can include a first semiconductor chip region 20 and a second semiconductor chip region 21. For example, the first semiconductor chip region 20 and the second semiconductor chip region 21 can be arranged on the wafer 200 in planar directions X, Y. A cutting region 22 can be disposed between the first semiconductor chip region 20 and the second semiconductor chip region 21. Each of the first semiconductor chip region 20 and the second semiconductor chip region 21 can include internal circuitry required to drive a semiconductor chip.

[0035] Referring to Figure 3A and Figure 3B , by separating the first semiconductor chip region 20 and the second semiconductor chip region 21 along the cutting region 22, corresponding semiconductor chips (20_chip, 21_chip) can be generated. For example, the first semiconductor chip region 20 and the second semiconductor chip region 21 can be separated in the x direction and the -x direction based on the cutting region 22. The semiconductor chips (20_chip, 21_chip) formed by separating the first semiconductor chip region 20 and the second semiconductor chip region 21 can include protrusions 20_pt, 21_pt, respectively. At this time, the protrusions 20_pt, 21_pt can be generated due to characteristics of a material constituting the semiconductor chips (20_chip, 21_chip). Alternatively, the protrusions 20_pt, 21_pt can be generated due to external stress generated when the first semiconductor chip region 20 and the second semiconductor chip region 21 are separated along the cutting region 22. However, embodiments are not limited to these reasons for generating the protrusions 20_pt, 21_pt. In addition to the above reasons, each of the semiconductor chips (20_chip, 21_chip) can include the protrusions 20_pt, 21_pt due to various reasons.

[0036] Referring again to Figure 1 , for example, the first wiring 170a can include gold, copper, aluminum, or the like. The first wiring 170a can be formed by, for example, a capillary tube, but embodiments are not limited thereto. An example of a process of forming the first wiring 170a will be described later.

[0037] According to some embodiments, the first wiring 170a can be formed as a folded ring having a hook shape. The hook shape means a shape including a portion extending in a direction away from the first bonding pad 110a and a portion extending in a direction close to the first bonding pad 110a. The folded ring means that the wiring adjacent to a portion in which the first wiring 170a is connected to the first bump 160a has a pleated shape. For explanatory purposes, reference will be made to Figure 4 A description is provided.

[0038] Figure 4 is an enlarged view of the area A shown in Figure 1 an enlarged view of the area A.

[0039] Referring to Figure 4 , the first wiring 170a can include a first portion 170a1 extending in a direction away from the first bonding pad 110a and a second portion 170a2 extending in a direction close to the first bonding pad 110a. In other words, the first wiring 170a can have a hook shape. Further, the first wiring 170a can have a shape in which a portion adjacent to a portion connected to the first bump 160a is pleated downward. In other words, the first wiring 170a can be formed as a folded ring having a hook shape.

[0040] According to some embodiments, since the first wiring 170a is formed as a folded ring, the height H1 of the first wiring can be smaller than that of a general bonding wire. In a case in which another semiconductor chip is vertically stacked on the first semiconductor chip 120a, since the height H1 of the first wiring is smaller than that of a general bonding wire, more chips can be stacked in the same area. Thus, by forming the first wiring 170a as a folded ring, the semiconductor package can be miniaturized.

[0041] According to some embodiments, the first wiring 170a does not contact the first protrusion 140a of the first semiconductor chip 120a. When the first wiring 170a contacts the first protrusion 140a of the first semiconductor chip 120a, defective operation of the first semiconductor chip 120a can occur. Thus, according to some embodiments, by interposing the first spacer ball 150a between the first bump 160a and the first chip pad 130a of the first semiconductor chip 120a, short-circuiting between the first wiring 170a and the first protrusion 140a of the first semiconductor chip 120a can be prevented. The height of the first spacer ball 150a can vary based on the height of the first protrusion 140a.

[0042] According to some embodiments, since the first wiring 170a does not contact the first protrusion 140a of the first semiconductor chip 120a, the reliability of the semiconductor package can be improved. In addition, since the height H1 of the first wiring is reduced and more semiconductor chips can be stacked, the integration of the semiconductor package can be improved.

[0043] Figure 5 is a schematic diagram illustrating a semiconductor package in which semiconductor chips are vertically stacked according to some embodiments.

[0044] Referring to Figure 5 , a semiconductor package according to some embodiments can include a mounting substrate 100, a first semiconductor chip 120a, a second semiconductor chip 120b, a third semiconductor chip 120c, a first spacer ball 150a, a second spacer ball 150b, a first bump ball 160a, a second bump ball 160b, a third bump ball 160c, a first wiring 170a, a second wiring 170b, a third wiring 170c, a first adhesive film 121, a second adhesive film 122, a third adhesive film 123, and a molding resin 180.

[0045] Figure 5 Each of the constituent elements shown can be similar to those described above Figure 1 . Thus, a repeated description will be omitted or simply explained. According to some embodiments, the first semiconductor chip 120a can include a first chip pad 130a and a first protrusion 140a protruding from an upper surface 120a_us of the first semiconductor chip. The second semiconductor chip 120b can include a second chip pad 130b and a second protrusion 140b protruding from an upper surface of the second semiconductor chip 120b. The third semiconductor chip 120c can include a third chip pad 130c and a third protrusion 140c protruding from an upper surface of the third semiconductor chip 120c.

[0046] The first semiconductor chip 120a can be disposed on the mounting substrate 100. For example, the first semiconductor chip 120a can be attached to the mounting substrate 100 via the first adhesive film 121.

[0047] The first spacer ball 150a can be connected to the first chip pad 130a of the first semiconductor chip 120a. The first bump ball 160a can be connected to the first spacer ball 150a. The first wiring 170a can be connected to the first bump ball 160a and the first bonding pad 110a. In other words, the first chip pad 130a and the first bonding pad 110a can be electrically connected by the first wiring 170a. That is, the first semiconductor chip 120a and the mounting substrate 100 can be electrically connected to each other via the first wiring 170a. In some embodiments, the first wiring 170a can be formed as a folded ring having a hook shape.

[0048] According to some embodiments, the first wiring 170a does not contact the first protrusion 140a of the first semiconductor chip 120a. Also, the first wiring 170a does not contact the second semiconductor chip 120b. When the first wiring 170a contacts the first protrusion 140a of the first semiconductor chip 120a and the second semiconductor chip 120b, defective operation can occur in the semiconductor package. Accordingly, according to some embodiments, by inserting the first spacer ball 150a between the first bump ball 160a of the first semiconductor chip 120a and the first chip pad 130a in a case where the first wiring 170a is formed to have a folded ring with a hook shape, short circuit of the first wiring 170a with the first protrusion 140a of the first semiconductor chip 120a and the second semiconductor chip 120b can be prevented. The height of the first spacer ball 150a can be changed in consideration of the height of the first protrusion 140a and the distance between the first semiconductor chip 120a and the second semiconductor chip 120b.

[0049] According to some embodiments, since the first wiring 170a does not contact the first protrusion 140a of the first semiconductor chip 120a and the second semiconductor chip 120b, the reliability of the semiconductor package can be improved. Also, since the height H1 of the first wiring is reduced, and more semiconductor chips can be stacked, the integration of the semiconductor package can be improved.

[0050] The second semiconductor chip 120b can be disposed on the first semiconductor chip 120a. For example, the second semiconductor chip 120b can be attached to the first semiconductor chip 120a via the second adhesive film 122. In other words, the second adhesive film 122 can be disposed between the first semiconductor chip 120a and the second semiconductor chip 120b.

[0051] The first adhesive film 121 and the second adhesive film 122 can be, for example, a die attach film (DAF), and can be a material through which a wiring can penetrate. The thickness of the first adhesive film 121 and the thickness of the second adhesive film 122 can be different according to the position of attachment. The adhesive film through which the wiring can penetrate (for example, the second adhesive film 122 through which the first wiring 170a penetrates) can be, for example, thicker than the first adhesive film 121, so that the first wiring 170a can be protected. Here, the expression "wiring penetrating an adhesive film" means that even if the adhesive film is disposed on the wiring, the shape of the wiring remains unchanged since the adhesive film surrounds the wiring.

[0052] The second spacer ball 150b can be connected to the second chip pad 130b of the second semiconductor chip 120b. The second bump ball 160b can be connected to the second spacer ball 150b. The second wire 170b can be connected to the second bump ball 160b and the first bonding pad 110a. In other words, the second chip pad 130b and the first bonding pad 110a can be electrically connected to each other through the second wire 170b. That is, the second semiconductor chip 120b and the mounting substrate 100 can be electrically connected to each other through the second wire 170b. The second wire 170b can be formed as a folded loop having a hook shape. In the same manner as described above, the second wire 170b does not contact the second protrusion 140b of the second semiconductor chip 120b and the third semiconductor chip 120c.

[0053] The third semiconductor chip 120c can be disposed on the second semiconductor chip 120b. For example, the third semiconductor chip 120c can be attached to the second semiconductor chip 120b through a third adhesive film 123. In other words, the third adhesive film 123 can be disposed between the second semiconductor chip 120b and the third semiconductor chip 120c. The third adhesive film 123 can also be a DAF.

[0054] The third bump ball 160c can be directly connected to the third chip pad 130c of the third semiconductor chip 120c. In other words, a spacer ball can not be disposed on the third semiconductor chip 120c. The third wire 170c can be connected to the third bump ball 160c and the first bonding pad 110a. In other words, the third chip pad 130c and the first bonding pad 110a can be electrically connected to each other through the third wire 170c. The third wire 170c can be formed as a normal loop. In some embodiments, the normal loop can be a wrinkle-free form. In addition, the third wire 170c can be referred to as a normal loop when the third wire 170c does not extend in a direction away from the first bonding pad 110a. The normal loop according to some embodiments can be a forward loop or a reverse loop. A loop is referred to as a forward loop when the starting point of the wire bond is the chip pad of the semiconductor chip. On the other hand, a loop is referred to as a reverse loop when the starting point of the wire bond is the bonding pad of the mounting substrate. According to some embodiments, the third wire 170c does not contact the third protrusion 140c of the third semiconductor chip 120c.

[0055] According to some embodiments, as for the third semiconductor chip 120c, another semiconductor chip can not be stacked on top of it. Accordingly, the third semiconductor chip 120c can be connected to the first bonding pad 110a by a third wire 170c having a normal ring form. In some embodiments, the height H2 of the third wire can be higher than the height H1 of the first wire. Accordingly, even if a spacer ball is not formed on the third chip pad 130c of the third semiconductor chip 120c, the third wire 170c can not contact the third protrusion 140c.

[0056] The first chip pad 130a of the first semiconductor chip 120a, the second chip pad 130b of the second semiconductor chip 120b, and the third chip pad 130c of the third semiconductor chip 120c are electrically connected to semiconductor elements inside the first semiconductor chip 120a, the second semiconductor chip 120b, and the third semiconductor chip 120c, respectively. Since the first chip pad 130a, the second chip pad 130b, and the third chip pad 130c are electrically connected to the first bonding pad 110a, the first chip pad 130a, the second chip pad 130b, and the third chip pad 130c must be pads performing the same role in the corresponding semiconductor chip. Accordingly, the first semiconductor chip 120a, the second semiconductor chip 120b, and the third semiconductor chip 120c according to some embodiments can be semiconductor chips having the same configuration.

[0057] According to some embodiments, the first semiconductor chip 120a to the third semiconductor chip 120c can be uniformly stacked. In other words, assuming that the first semiconductor chip 120a to the third semiconductor chip 120c are semiconductor chips of the same size, the first semiconductor chip 120a to the third semiconductor chip 120c can be stacked in a vertical direction. In other words, the first chip pad 130a of the first semiconductor chip 120a can vertically overlap the second semiconductor chip 120b and the third semiconductor chip 120c. In addition, the second chip pad 130b of the second semiconductor chip 120b can vertically overlap the first semiconductor chip 120a and the third semiconductor chip 120c. Furthermore, the third chip pad 130c of the third semiconductor chip 120c can vertically overlap the first semiconductor chip 120a and the second semiconductor chip 120b.

[0058] Figure 6 is a schematic diagram illustrating a semiconductor package according to some embodiments.

[0059] Referring to Figure 6A semiconductor package according to some embodiments can include a mounting substrate 100, a first semiconductor chip 120a, a second semiconductor chip 120b, a third semiconductor chip 120c, a first spacer ball 150a, a second spacer ball 150b, a first convex ball 160a, a second convex ball 160b, a third convex ball 160c, a first wiring 170a, a second wiring 170b, a third wiring 170c, a first adhesive film 121, a second adhesive film 122, a third adhesive film 123, and a molding resin 180.

[0060] Figure 6 Each of the constituent elements shown can be similar to those described above Figure 1 and Figure 5 Thus, overlapping descriptions will be omitted or simply explained.

[0061] According to some embodiments, the mounting substrate 100 can include a first bonding pad 110a and a second bonding pad 110b. The first bonding pad 110a and the second bonding pad 110b can be electrically connected to external terminals (connected to external devices), respectively. For example, the first bonding pad 110a can be electrically connected to a first solder ball (not shown), and the second bonding pad 110b can be electrically connected to a second solder ball (not shown). Alternatively, the first bonding pad 110a and the second bonding pad 110b can be, for example, ground pads, and can be electrically connected to a ground wire in the mounting substrate 100. The first bonding pad 110a and the second bonding pad 110b are shown, for example, as being disposed in the housing of the mounting substrate 100, but embodiments are not limited thereto.

[0062] According to some embodiments, the first semiconductor chip 120a and the second semiconductor chip 120b can be connected to the first bonding pad 110a. In addition, the third semiconductor chip 120c can be connected to the second bonding pad 110b. According to some embodiments, the first semiconductor chip 120a and the second semiconductor chip 120b can be semiconductor chips of the same configuration, and the first semiconductor chip 120a and the third semiconductor chip 120c can be semiconductor chips of different configurations. However, embodiments are not limited thereto.

[0063] Figure 6 A configuration in which the first semiconductor chip 120a and the second semiconductor chip 120b are connected to the first bonding pad 110a and the third semiconductor chip 120c is connected to the second bonding pad 110b is shown, but embodiments are not limited thereto. For example, the first semiconductor chip 120a can be connected to the first bonding pad 110a, and the second semiconductor chip 120b and the third semiconductor chip 120c can be connected to the second bonding pad 110b. A person of ordinary skill in the technical field to which the inventive concept pertains can implement semiconductor packages including semiconductor chips having various arrangements.

[0064] Figure 7is a schematic diagram illustrating a semiconductor package according to some embodiments.

[0065] Referring to Figure 7 , a semiconductor package according to some embodiments can include a mounting substrate 100, a first semiconductor chip 120a, a second semiconductor chip 120b, a third semiconductor chip 120c, a fourth semiconductor chip 120d, a fifth semiconductor chip 120e, a second spacer ball 150b, a fourth spacer ball 150d, a first bump ball 160a, a second bump ball 160b, a third bump ball 160c, a fourth bump ball 160d, a fifth bump ball 160e, a first wiring 170a, a second wiring 170b, a third wiring 170c, a fourth wiring 170d, a fifth wiring 170e, a first adhesive film 121, a second adhesive film 122, a third adhesive film 123, a fourth adhesive film 124, a fifth adhesive film 125, and a molding resin 180.

[0066] Figure 7 Each of the constituent elements illustrated can be similar to those of the above Figure 1 , Figure 5 and Figure 6 . Thus, the repeated description will be omitted or simply explained.

[0067] According to some embodiments, the first semiconductor chip 120a can be disposed on the mounting substrate 100. The mounting substrate 100 and the first semiconductor chip 120a can be attached to each other via the first adhesive film 121. The second semiconductor chip 120b can be disposed on the first semiconductor chip 120a. The first semiconductor chip 120a and the second semiconductor chip 120b can be attached to each other via the second adhesive film 122. The third semiconductor chip 120c can be disposed on the second semiconductor chip 120b. The second semiconductor chip 120b and the third semiconductor chip 120c can be attached to each other via the third adhesive film 123. The fourth semiconductor chip 120d can be disposed on the third semiconductor chip 120c. The third semiconductor chip 120c and the fourth semiconductor chip 120d can be attached to each other via the fourth adhesive film 124. The fifth semiconductor chip 120e can be disposed on the fourth semiconductor chip 120d. The fourth semiconductor chip 120d and the fifth semiconductor chip 120e can be attached to each other via the fifth adhesive film 125.

[0068] The first semiconductor chip 120a to the fifth semiconductor chip 120e can be stacked in a zigzag shape. In other words, the first chip pad 130a of the first semiconductor chip 120a and the third chip pad 130c of the third semiconductor chip 120c can not contact the second adhesive film 122 and the fourth adhesive film 124, respectively. However, the second chip pad 130b of the second semiconductor chip 120b and the fourth chip pad 130d of the fourth semiconductor chip 120d can contact the third adhesive film 123 and the fifth adhesive film 125, respectively.

[0069] In other words, the first chip pad 130a of the first semiconductor chip 120a, the third chip pad 130c of the third semiconductor chip 120c, and the fifth chip pad 130e of the fifth semiconductor chip 120e can not be vertically overlapped with the second semiconductor chip 120b and the fourth semiconductor chip 120d. Also, the second chip pad 130b of the second semiconductor chip 120b and the fourth chip pad 130d of the fourth semiconductor chip 120d can be overlapped with the first semiconductor chip 120a, the third semiconductor chip 120c, and the fifth semiconductor chip 120e in the vertical direction.

[0070] According to some embodiments, the first bump 160a, the third bump 160c, and the fifth bump 160e can be directly connected to the first chip pad 130a of the first semiconductor chip 120a, the third chip pad 130c of the third semiconductor chip 120c, and the fifth chip pad 130e of the fifth semiconductor chip 120e, respectively. In other words, the spacer bumps can be connected to the top of the first semiconductor chip 120a, the top of the third semiconductor chip 120c, and the top of the fifth semiconductor chip 120e without being separated.

[0071] The first wire 170a, the third wire 170c, and the fifth wire 170e can be connected to the first bump 160a, the third bump 160c, and the fifth bump 160e, respectively. Since the first chip pad 130a of the first semiconductor chip 120a is not overlapped with the second semiconductor chip 120b in the vertical direction, the first wire 170a can be formed as a normal ring. In other words, since the first chip pad 130a of the first semiconductor chip 120a has a sufficient height to form a normal ring at the top thereof, the first wire 170a can be formed as a normal ring. Similarly, the third wire 170c and the fifth wire 170e can be formed as normal rings.

[0072] According to some embodiments, the second spacer bump 150b and the fourth spacer bump 150d can be disposed on the second chip pad 130b of the second semiconductor chip 120b and the fourth chip pad 130d of the fourth semiconductor chip 120d, respectively. Also, the second spacer bump 150b and the fourth spacer bump 150d can be connected to the second bump 160b and the fourth bump 160d, respectively.

[0073] The second wire 170b and the fourth wire 170d can be connected to the second bump 160b and the fourth bump 160d, respectively. Since the second chip pad 130b of the second semiconductor chip 120b and the third semiconductor chip 120c overlap in the vertical direction, the second wire 170b can be formed as a folded ring having a hook shape. In other words, since the second chip pad 130b of the second semiconductor chip 120b does not have a sufficient height to form a normal ring at the top, the second wire 170b can be formed as a folded ring. Similarly, the fourth wire 170d can be formed as a folded ring having a hook shape.

[0074] Even though Figure 7 It is shown that the first wire 170a to the fifth wire 170e are connected to the first bonding pad 110a, but embodiments are not limited thereto. For example, at least one of the first wire 170a to the fifth wire 170e can be connected to a bonding pad different from the first bonding pad 110a.

[0075] Figures 8 to 16 is an intermediate stage diagram for explaining a method of manufacturing a semiconductor package according to some embodiments. Repetitive or similar descriptions with regard to the above embodiments will be omitted or simply explained.

[0076] Referring to Figure 8 The first semiconductor chip 120a is disposed on the mounting substrate 100. The first semiconductor chip 120a can be attached to the mounting substrate 100 by the first adhesive film 121. Next, the first spacer ball 150a having a suitable size (for example, such that the first wire 170a to be formed on the first spacer ball 150a does not come into contact with the first protrusion 140a of the first semiconductor chip 120a and the second semiconductor chip 120b) is formed on the first chip pad 130a of the first semiconductor chip 120a. A person of ordinary skill in the technical field of the present inventive concept can change the size of the first spacer ball 150a as necessary.

[0077] Referring to Figure 9 and Figure 10 The capillary 920 can form the first free air ball (FAB) 910. By moving the capillary 920 in the first direction 1001 to press the first free air ball 910, the first bump 160a can be formed on the first spacer ball 150a.

[0078] Referring to Figure 11 and Figure 12 By moving the capillary 920 in the second direction 1101 away from the first bonding pad 110a, the first portion of the first wire 170a (the first wire 170a excluding the second portion of the first wire 170a) can be formed. Figure 4(170a1). Next, by moving the capillary 920 in the third direction 1102, the fourth direction 1103, and the fifth direction 1104 near the first bonding pad 110a, a second portion of the first wiring 170a can be formed. Figure 4 (170a2). That is to say, it can be achieved through Figures 9 to 12 The process creates a hook-shaped folded ring.

[0079] Reference Figure 13 A second semiconductor chip 120b is disposed on the first semiconductor chip 120a. The second semiconductor chip 120b can be attached to the first semiconductor chip 120a via a second adhesive film 122. Next, a second spacer ball 150b of suitable size is formed on the second chip pad 130b of the second semiconductor chip 120b. Those skilled in the art can change the size of the second spacer ball 150b as needed.

[0080] Reference Figure 14 The second convex ball 160b and the second wiring 170b are formed in a manner similar to that described above. In some embodiments, the second wiring 170b may be formed as a hook-shaped folded loop.

[0081] Reference Figure 15 and Figure 16 A third semiconductor chip 120c is disposed on the second semiconductor chip 120b. The third semiconductor chip 120c can be attached to the second semiconductor chip 120b via a second adhesive film 122. Unlike the first semiconductor chip 120a and the second semiconductor chip 120b, no spacer balls are formed on the third chip pad 130c of the third semiconductor chip 120c. After forming a second free air ball 1510 in the capillary 920 and pressing the second free air ball 1510 relative to the third chip pad 130c of the third semiconductor chip 120c to form a third convex ball 160c, wiring is formed in a direction close to the first bonding pad 110a to form a third wiring 170c. In some embodiments, the third wiring 170c may be formed as a regular ring. Even Figure 15 and Figure 16 The third wiring 170c, which is a normal ring, is shown to be formed as a positive ring, but the embodiments are not limited to this.

[0082] Then, it is manufactured by filling the mounting substrate 10 and the first semiconductor chip 120a to the third semiconductor chip 120c with molding resin 180. Figure 5 Semiconductor packaging components.

[0083] Although reference Figures 8 to 16 Describes manufacturing Figure 5The present application relates to a method of manufacturing a semiconductor package, but embodiments are not limited thereto. A person of ordinary skill in the art of the technical field of the present inventive concept can manufacture a semiconductor package including the technical idea of the present inventive concept by adding, changing, or deleting certain processes as necessary.

[0084] While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present inventive concept is to be determined not with reference to the above description but with reference to the appended claims.

Claims

1. A semiconductor package comprising: a mounting substrate including at least one bond pad; a first semiconductor chip disposed on the mounting substrate and including a first chip pad connected to the bond pad and a first protrusion on an upper surface of the first semiconductor chip; a first spacer ball electrically connected to the first chip pad of the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; a first wire electrically connecting the first bump ball and the bond pad; a second semiconductor chip attached on the first semiconductor chip via an adhesive film, wherein the first chip pad of the first semiconductor chip is in contact with the adhesive film and vertically overlaps with the second semiconductor chip, the first wire penetrates into the adhesive film, and wherein a portion of the first wire connected to the first bump ball includes a first portion extending in a direction away from the bond pad and a second portion extending in a direction approaching the bond pad, such that the portion of the first wire is formed as a folded ring having a hook shape, so that the first wire does not contact both the first protrusion and the second semiconductor chip.

2. The semiconductor package of claim 1, further comprising: a second bump ball directly connected to the second semiconductor chip; and a second wire electrically connecting the second bump ball and the mounting substrate without contacting a second protrusion, wherein the second semiconductor chip includes a second protrusion on an upper surface of the second semiconductor chip. the second bump ball is electrically connected to the bond pad.

3. The semiconductor package of claim 2, wherein, the first semiconductor chip and the second semiconductor chip have the same structure.

4. The semiconductor package of claim 3, wherein, the bond pad includes a first bond pad and a second bond pad, and 5. The semiconductor package of claim 2, wherein, wherein the second bump ball is electrically connected to the second bond pad. the first semiconductor chip and the second semiconductor chip have different structures.

6. The semiconductor package of claim 5, wherein, the second wire does not extend in a direction away from the bond pad.

7. The semiconductor package of claim 2, wherein, 8. The semiconductor package of claim 1, further comprising a molding resin covering the first semiconductor chip and the mounting substrate.

9. A semiconductor package comprising: at least one bond pad; a first semiconductor chip including a first chip pad connected to the bond pad and a first protrusion protruding from an upper surface of the first chip pad; a first spacer ball on the first chip pad; a first bump ball on the first spacer ball; a first wire connecting the first bump ball and the bond pad; a second semiconductor chip attached on the first semiconductor chip via an adhesive film and including a second chip pad connected to the bond pad and a second protrusion protruding from an upper surface of the second chip pad; a second bump ball directly connected to the second chip pad; and a second wire connecting the second bump ball and the bond pad without contacting the second protrusion, wherein the first chip pad of the first semiconductor chip is in contact with the adhesive film and vertically overlaps with the second semiconductor chip, the first wire penetrates into the adhesive film, and ​ wherein a portion of the first wiring connected to the first bump includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad, such that the portion of the first wiring is formed as a folded ring having a hook shape, so that the first wiring does not contact both the first protrusion and the second semiconductor chip, and wherein the second wiring does not extend in a direction away from the bonding pad.

10. The semiconductor package of claim 9, further comprising: a third semiconductor chip including a third chip pad connected to the bonding pad and a third protrusion protruding from an upper surface of the third chip pad; a second spacer ball on the third chip pad; a third bump on the second spacer ball; and a third wiring connecting the third bump with the bonding pad without contacting the third protrusion, wherein the third semiconductor chip is disposed between the first semiconductor chip and the second semiconductor chip, and wherein the third wiring includes a third portion extending in a direction away from the bonding pad and a fourth portion extending in a direction approaching the bonding pad. the bonding pad includes a plurality of bonding pads, and 11. The semiconductor package of claim 10, wherein, wherein each of the first wiring, the second wiring, and the third wiring is connected to at least one of the bonding pads. the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip have the same structure.

12. The semiconductor package of claim 11, wherein, one or two of the first wiring, the second wiring, and the third wiring are connected to one of the bonding pads, and the remaining one or two of the first wiring, the second wiring, and the third wiring are connected to another of the bonding pads.

13. The semiconductor package of claim 11, wherein, the first semiconductor chip and the third semiconductor chip have the same structure, and 14. The semiconductor package of claim 10, wherein, wherein a structure of the second semiconductor chip is different from a structure of the first semiconductor chip.

15. The semiconductor package of claim 9, further comprising a molding resin covering the first semiconductor chip and the second semiconductor chip.

16. A semiconductor package comprising: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate and including a first chip pad and a first protrusion protruding from an upper surface of the first chip pad; a second semiconductor chip attached to the first semiconductor chip via a first adhesive film and including a second chip pad and a second protrusion protruding from an upper surface of the second chip pad; a third semiconductor chip attached to the second semiconductor chip via a second adhesive film and including a third chip pad and a third protrusion protruding from an upper surface of the third chip pad; and first, second, and third wirings connecting the first, second, and third chip pads to the bonding pad, respectively, wherein the second wiring is connected to the second chip pad by a second spacer ball disposed on the second chip pad and a second bump disposed on the second spacer ball, wherein the third wiring is connected to the third chip pad by a third spacer ball disposed on the third chip pad and a third bump disposed on the third spacer ball, and wherein the first, second, and third wirings are connected to different ones of the bonding pads. wherein the first chip pad and the third chip pad do not overlap the second semiconductor chip in a vertical direction, wherein the second chip pad overlaps the first semiconductor chip and the third semiconductor chip in the vertical direction, wherein the second chip pad of the second semiconductor chip is in contact with the second adhesive film, the second wire penetrates into the second adhesive film, and wherein a portion of the second wire connected to the second bump includes a first portion extending in a direction away from the bonding pad and a second portion extending in a direction approaching the bonding pad, such that the portion of the second wire is formed as a folded loop having a hook shape, so that the second wire does not contact both the second protrusion and the third semiconductor chip.

17. The semiconductor package of claim 16, wherein, the first wire does not extend in a direction away from the bonding pad, and wherein the third wire does not extend in a direction away from the bonding pad.

18. The semiconductor package of claim 16, further comprising: a first bump directly connected to the first chip pad and the first wire; and a third bump directly connected to the third chip pad and the third wire. ​

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