Fuse testing circuit and method, integrated circuit

Abstract

The present disclosure relates to a fuse test circuit and method, and an integrated circuit. The fuse test circuit includes a fuse and a latch circuit, wherein the latch circuit is connected to the fuse, and the latch circuit has a signal receiving end, and the signal receiving end is used to receive a trigger signal, so that the current in the latch circuit increases and the fuse can be blown. When blowing multiple fuses, it is only necessary to trigger the latch circuit corresponding to one fuse and then trigger the latch circuit corresponding to another fuse, thereby avoiding the problem of long test time and low test efficiency caused by waiting for one fuse to blow and then blowing another fuse in the related art.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a fuse testing circuit and method, and an integrated circuit. Background Art

[0002] With the development and progress of technology, integrated circuits are used more and more widely. When designing and manufacturing integrated circuits, they need to be tested.

[0003] When testing integrated circuits, it is often necessary to test the fuses in the integrated circuits. Currently, when testing integrated circuits, if multiple fuses need to be tested, one fuse usually needs to be blown before the next fuse is blown. The entire testing process is time-consuming and the testing efficiency is low.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a fuse testing circuit and method, and an integrated circuit, thereby overcoming the problems of time-consuming testing process and low testing efficiency in related technologies in fuse testing, at least to a certain extent.

[0006] According to a first aspect of the present disclosure, there is provided a fuse testing circuit, comprising:

[0007] Fuse;

[0008] A latch circuit is connected to the fuse, and the latch circuit has a signal receiving end, and the signal receiving end is used to receive a trigger signal, so that the current in the latch circuit increases.

[0009] According to an embodiment of the present disclosure, the latch circuit includes:

[0010] A first parasitic transistor, wherein a first emitter and a second emitter receive a first power supply signal, a collector receives a second power supply signal, and a base receives a first trigger signal;

[0011] A second parasitic transistor, whose collector is connected to the base of the first parasitic transistor, the collector receives a first power supply signal, the base is connected to the collector of the first parasitic transistor, the base receives a second trigger signal, and the first emitter and the second emitter receive a second power supply signal.

[0012] According to an embodiment of the present disclosure, the fuse is connected to the first emitter of the first parasitic transistor.

[0013] According to an embodiment of the present disclosure, the fuse is connected to the second emitter of the first parasitic transistor.

[0014] According to an embodiment of the present disclosure, the fuse is connected to a first emitter of the second parasitic transistor.

[0015] According to an embodiment of the present disclosure, the fuse is connected to the second emitter of the second parasitic transistor.

[0016] According to an embodiment of the present disclosure, the latch circuit includes:

[0017] a third parasitic transistor, an emitter of which receives the first power supply signal, a collector of which receives the second power supply signal, and a base of which receives the first trigger signal;

[0018] A fourth parasitic transistor, whose collector is connected to the base of the third parasitic transistor, the collector receives the first power supply signal, the base is connected to the collector of the third parasitic transistor, the base receives the second trigger signal, and the emitter receives the second power supply signal.

[0019] According to an embodiment of the present disclosure, the fuse is connected to the emitter of the third parasitic transistor.

[0020] According to an embodiment of the present disclosure, the fuse is connected to the emitter of the fourth parasitic transistor.

[0021] According to an embodiment of the present disclosure, the fuse test circuit includes:

[0022] A plurality of fuses are respectively connected to latch circuits. The fuses and the latch circuits connected thereto form a detection unit. One end of the detection unit is connected to a first power supply and the other end is connected to a second power supply. The plurality of detection units are connected in parallel.

[0023] According to a second aspect of the present disclosure, a fuse testing method is provided, comprising:

[0024] The latch circuit receives a trigger signal;

[0025] The latch circuit outputs a fusing current;

[0026] The fusing current flows through the fuse to blow the fuse.

[0027] According to one embodiment of the present disclosure, the testing method further includes:

[0028] Detecting whether the fuse is blown;

[0029] If the fuse is blown, a first signal is output;

[0030] If the fuse is not blown, a second signal is output.

[0031] According to a third aspect of the present disclosure, an integrated circuit is provided, comprising the fuse testing circuit provided by the present disclosure.

[0032] The present invention provides a fuse test circuit, which connects a fuse and a latch circuit, receives a trigger signal through a signal receiving end on the latch circuit, and when the latch circuit is triggered, the current in the latch circuit gradually increases, so that the fuse can be blown. When blowing multiple fuses, it is only necessary to trigger the latch circuit corresponding to one fuse and then trigger the latch circuit corresponding to another fuse, thereby avoiding the problem of waiting for one fuse to blow before blowing another fuse in the related art, resulting in long test time and low test efficiency.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0035] Figure 1 A schematic diagram of a first fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0036] Figure 2 A schematic diagram of the structure of a CMOS device provided for an exemplary embodiment of the present disclosure;

[0037] Figure 3 A circuit diagram of a second fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0038] Figure 4 A circuit diagram of a third fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0039] Figure 5 A circuit diagram of a fourth fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0040] Figure 6 A circuit diagram of a fifth fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram of the structure of another CMOS device provided for an exemplary embodiment of the present disclosure;

[0042] Figure 8 A circuit diagram of a sixth fuse test circuit provided for an exemplary embodiment of the present disclosure;

[0043] Fig. 9 A circuit diagram of a seventh fuse testing circuit provided by an exemplary embodiment of the present disclosure.

[0044] Fig.10 A first latch circuit trigger signal diagram provided for an exemplary embodiment of the present disclosure;

[0045] Fig.11 A second latch circuit trigger signal diagram provided for an exemplary embodiment of the present disclosure;

[0046] Fig.12 A third latch circuit trigger signal diagram provided for an exemplary embodiment of the present disclosure;

[0047] Fig.13 A fourth latch circuit trigger signal diagram provided for an exemplary embodiment of the present disclosure;

[0048] Fig.14 A flowchart of a fuse testing method provided for an exemplary embodiment of the present disclosure.

[0049] Fig.15 A flow chart of another fuse testing method provided for an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0051] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0052] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0053] In this exemplary embodiment, a fuse test circuit is first provided. Figure 1 As shown, the fuse test circuit includes a fuse Fu and a latch circuit LC;

[0054] The latch circuit LC is connected to the fuse Fu, and the latch circuit LC has a signal receiving end, and the signal receiving end is used to receive a trigger signal, so that the current in the latch circuit LC increases.

[0055] The fuse Fu may be a fuse arranged in an integrated circuit, such as a fuse, etc. The latch circuit LC may be generated by a latch effect of a CMOS device, and the signal receiving end of the latch circuit LC may be a plurality of receiving ends, and the plurality of receiving ends receive a trigger signal, so that the current in the latch circuit LC increases, and the fuse Fu connected to the latch circuit LC is melted.

[0056] The present disclosure provides a fuse test circuit, which connects a fuse Fu and a latch circuit LC, receives a trigger signal through a signal receiving end on the latch circuit LC, and when the latch circuit LC is triggered, the current in the latch circuit LC gradually increases, so that the fuse Fu can be blown. When blowing multiple fuses Fu, it is only necessary to trigger the latch circuit LC corresponding to one fuse Fu, and then trigger the latch circuit LC corresponding to another fuse Fu, thereby avoiding the problem of long test time and low test efficiency caused by waiting for one fuse Fu to blow and then blowing another fuse Fu in the related art.

[0057] Furthermore, the fuse test circuit provided by the embodiment of the present disclosure may include multiple fuses, and the multiple fuses are respectively connected to latch circuits. The fuses and the latch circuits connected thereto form a detection unit, one end of the detection unit is connected to a first power supply, and the other end is connected to a second power supply, and the multiple detection units are connected in parallel. During the detection process, the multiple parallel detection units can trigger the latch circuit in sequence. In the latch circuit, when the latch circuit is triggered, the current in the latch circuit will gradually increase until the fuse is burned. Therefore, it is only necessary to trigger the latch circuit during detection. Since the triggering time of the latch circuit is less than the melting time of the fuse, the test time is saved and the test efficiency is improved.

[0058] The fuse test circuit provided in the embodiment of the present disclosure is described in detail below:

[0059] In a feasible implementation of the present disclosure, Figure 3 As shown, the latch circuit LC may include a first parasitic transistor Q1 and a second parasitic transistor Q2;

[0060] The first parasitic transistor Q1 has a first emitter and a second emitter receiving a first power supply signal, a collector receiving a second power supply signal, and a base receiving a first trigger signal; the second parasitic transistor Q2 has a collector connected to the base of the first parasitic transistor Q1, a collector receiving the first power supply signal, a base connected to the collector of the first parasitic transistor Q1, a base receiving a second trigger signal, and a first emitter and a second emitter receiving a second power supply signal. The first power supply signal may be a high level, and the second power supply signal may be a low level.

[0061] The first parasitic transistor Q1 and the second parasitic transistor Q2 are both parasitic transistors in the CMOS device, which can be connected as follows: Figure 2 The structure shown produces a first parasitic transistor Q1 and a second parasitic transistor Q2. Figure 2 As shown, the CMOS includes a substrate Su, on which NMOS and PMOS are arranged. The NMOS includes a P-type silicon substrate Su with a low doping concentration, namely, the P well PW shown in the figure, on which two heavily doped N+ regions and one heavily doped P+ region are made. The PMOS includes an N-type silicon substrate Su with a low doping concentration, namely, the N well NW shown in the figure, on which two heavily doped P+ regions and one heavily doped N+ region are made.

[0062] In CMOS, due to the latch effect, a first parasitic transistor Q1 and a second parasitic transistor Q2 are formed. The first emitter and the second emitter of the first parasitic transistor Q1 are connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal. The collector of the second parasitic transistor Q2 is connected to the base of the first transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives a second trigger signal, and the first emitter and the second emitter are connected to a low level, forming a latch circuit LC. In the latch circuit LC, when the trigger signal is received, the current in the latch circuit LC gradually increases.

[0063] The first emitter of the first parasitic transistor Q1 corresponds to the source of the PMOS in the COMS, and the second emitter of the first parasitic transistor Q1 corresponds to the drain of the PMOS in the COMS. The first emitter of the second parasitic transistor Q2 corresponds to the source of the NMOS in the COMS, and the second emitter of the second parasitic transistor Q2 corresponds to the drain of the NMOS in the COMS.

[0064] Figure 3 for Figure 2 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 3 As shown, the fuse Fu can be connected to the first emitter of the first parasitic transistor Q1, one end of the fuse Fu is connected to the first emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of the PMOS. When the latching effect of the CMOS is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0065] Figure 4 for Figure 2 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 4 As shown, the fuse Fu can be connected to the second emitter of the first parasitic transistor Q1. One end of the fuse Fu is connected to the second emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the drain of the PMOS. When the latching effect of the CMOS is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0066] Figure 5 for Figure 2 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 5 As shown, the fuse Fu can be connected to the first emitter of the second parasitic transistor Q2. One end of the fuse Fu is connected to the first emitter of the second parasitic transistor Q2, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of NMOS. When the latch effect of CMOS is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0067] Figure 6 for Figure 2 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 6 As shown, the fuse Fu can be connected to the second emitter of the second parasitic transistor Q2. One end of the fuse Fu is connected to the second emitter of the second parasitic transistor Q2, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the drain of NMOS. When the latch effect of CMOS is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0068] In another feasible embodiment of the present disclosure, as Figure 8 As shown, the latch circuit LC may include: a third parasitic transistor Q3 and a fourth parasitic transistor Q4.

[0069] The emitter of the third parasitic transistor Q3 receives the first power supply signal, the collector receives the second power supply signal, and the base receives the first trigger signal; the collector of the fourth parasitic transistor Q4 is connected to the base of the third parasitic transistor Q3, the collector receives the first power supply signal, the base is connected to the collector of the third parasitic transistor Q3, the base receives the second trigger signal, and the emitter receives the second power supply signal.

[0070] The third parasitic transistor Q3 and the fourth parasitic transistor Q4 can be Figure 7 The structure shown produces Figure 7 As shown, the structure includes a substrate Su, on which an N-type region and a P-type region, namely, an N-well NW and a P-well PW, are arranged. Heavily doped P+ and N+ are made on the N-well NW, and heavily doped P+ and N+ are made on the P-well PW. A third parasitic transistor Q3 and a fourth parasitic transistor Q4 are formed on the structure, wherein the emitter of the third parasitic transistor Q3 is connected to a high level, the collector is connected to a low level, and the base receives a first trigger signal; the collector of the fourth parasitic transistor Q4 is connected to the base of the third transistor, the collector is connected to a high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives a second trigger signal, and the emitter is connected to a low level, forming a latch circuit LC. In the latch circuit LC, when the trigger signal is received, the current in the latch circuit LC gradually increases.

[0071] Figure 8 for Figure 7 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Figure 8 As shown, the fuse Fu can be connected to the emitter of the third parasitic transistor Q3. One end of the fuse Fu is connected to the emitter of the third parasitic transistor Q3, and the other end is connected to the power supply. Correspondingly, the P+ end on the N-type region. When the latch effect is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0072] Fig. 9 for Figure 7 The equivalent circuit diagram of the parasitic circuit and the fuse Fu is as follows: Fig. 9 As shown, the fuse Fu can be connected to the emitter of the fourth parasitic transistor Q4. One end of the fuse Fu is connected to the emitter of the fourth parasitic transistor Q4, and the other end is connected to the power supply. Correspondingly, the N+ end on the P-type region. When the latching effect is triggered, the current in the latch circuit LC continues to increase, and the current flowing through the fuse Fu also continues to increase, and finally the fuse Fu is blown.

[0073] like Figures 3 to 6In the fuse Fu test circuit shown in the figure, the latch circuit LC signal receiving end may include multiple receiving ends, for example, it may include four receiving ends as shown in the figure, wherein the first receiving end G1 is set at the base of the second parasitic transistor Q2, the second receiving end G2 is set at the base of the first parasitic transistor Q1, the third receiving end G3 is set at the high level end, and the fourth receiving end G4 is set at the low level end. Figure 8 and Fig. 9 In the fuse Fu test circuit shown, in the signal receiving end of the latch circuit LC, the first receiving end G1 is set at the base of the fourth parasitic transistor Q4, the second receiving end G2 is set at the base of the third parasitic transistor Q3, the third receiving end G3 is set at the high level end, and the fourth receiving end G4 is set at the low level end.

[0074] In the fuse Fu test circuit provided by the embodiment of the present disclosure, after the latching effect is triggered, the current in the latch circuit LC continues to increase, and the fuse Fu is blown. The latch circuit LC can be triggered in the following manner.

[0075] In a first feasible implementation manner provided by the present disclosure, as Fig.10 As shown, an overshoot signal is input to the first receiving terminal G1, the emitter-base of the second parasitic transistor Q2 is forward biased, and the current is fed back to the first parasitic transistor Q1, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form positive feedback, and the current continues to increase until the fuse Fu is blown.

[0076] In a second feasible implementation of the present disclosure, as Fig.11 As shown, an undershoot signal is input at the second receiving end G2, the emitter-base of the first parasitic transistor Q1 is forward biased, and the current is fed back to the second parasitic transistor Q2, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form positive feedback, and the current continues to increase until the fuse Fu is blown.

[0077] In a third feasible implementation of the present disclosure, as Fig.12 As shown, an overshoot signal is input to the third receiving terminal G3, the emitter-base of the first parasitic transistor Q1 is forward biased, and the current is fed back to the second parasitic transistor Q2, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form positive feedback, and the current continues to increase until the fuse Fu is blown.

[0078] In a fourth feasible implementation of the present disclosure, as Fig.13As shown, an undershoot signal is input to the fourth receiving terminal G4, the emitter-base of the second parasitic transistor Q2 is forward biased, and the current is fed back to the first parasitic transistor Q1, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form positive feedback, and the current continues to increase until the fuse Fu is blown.

[0079] This example implementation also provides a fuse testing method, such as Fig.14 As shown, the fuse testing method includes the following steps:

[0080] Step S1, the latch circuit receives a trigger signal;

[0081] Step S2, the latch circuit outputs a fusing current;

[0082] Step S3: the fusing current flows through the fuse to blow the fuse.

[0083] By triggering the latch effect of the latch circuit, the fuse current output by the latch circuit is continuously increased, thereby quickly blowing the fuse, saving detection time. When multiple fuses are tested, it is only necessary to sequentially trigger the latch circuit to ensure the blowing of the fuses, avoiding the need to detect the current fuse before blowing another fuse in the related art, saving detection time and improving detection efficiency.

[0084] Optional, such as Fig.15 As shown, the integrated circuit chip fuse detection method provided by the embodiment of the present disclosure may further include, after step S3:

[0085] Step S4, detecting whether the fuse is blown;

[0086] Step S5, if the fuse is blown, outputting a first signal;

[0087] Step S6: if the fuse is not blown, output a second signal.

[0088] In step S4, whether the fuse is blown can be detected by a circuit breaking detection device, such as a latching circuit; in step S5, if the fuse is blown, the entire circuit is open, and the circuit breaking detection device outputs a first signal to indicate that the fuse has been blown; in step S6, if the fuse is blown, a second signal is output, and the second signal is used to indicate that the fuse is unqualified or the circuit is faulty.

[0089] By detecting whether the fuse is blown, and outputting a first signal when the fuse is blown, and outputting a second signal when the fuse is not blown, the fuse test result is easy to obtain, avoiding the problem that the fuse test result cannot be directly obtained due to the fuse being located inside the integrated circuit chip.

[0090] This exemplary embodiment also provides an integrated circuit, including the fuse test circuit provided in the embodiment of the present disclosure. In practical applications, the integrated circuit may also include capacitors, resistors, and other transistors, etc., which are all prior art and will not be described in detail in the embodiment of the present disclosure.

[0091] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A fuse test circuit, characterized in that: include: Fuse; A latch circuit connected to the fuse, the latch circuit having a signal receiving end, the signal receiving end being used to receive a trigger signal so that the current in the latch circuit increases; The latch circuit comprises: A first parasitic transistor, wherein a first emitter and a second emitter receive a first power supply signal, a collector receives a second power supply signal, and a base receives a first trigger signal; a second parasitic transistor, wherein the collector of the second parasitic transistor is connected to the base of the first parasitic transistor, the collector receives a first power supply signal, the base is connected to the collector of the first parasitic transistor, the base receives a second trigger signal, and the first emitter and the second emitter receive a second power supply signal; The fuse is connected to the first emitter of the first parasitic transistor or the second emitter of the first parasitic transistor; or the fuse is connected to the first emitter of the second parasitic transistor or the second emitter of the second parasitic transistor; The triggering time of the latch circuit is shorter than the blowing time of the fuse.

2. The fuse testing circuit according to claim 1, characterized in that: The fuse testing circuit comprises: A plurality of fuses are respectively connected to the latch circuits. The fuses and the latch circuits connected thereto form a detection unit. One end of the detection unit is connected to a high level and the other end is connected to a low level. The plurality of detection units are connected in parallel.

3. A fuse testing method, characterized in that: include: The latch circuit receives a trigger signal; The latch circuit outputs a fusing current; The fusing current flows through the fuse to blow the fuse; The latch circuit comprises: A first parasitic transistor, wherein a first emitter and a second emitter receive a first power supply signal, a collector receives a second power supply signal, and a base receives a first trigger signal; A second parasitic transistor, whose collector is connected to the base of the first parasitic transistor, the collector receives a first power supply signal, the base is connected to the collector of the first parasitic transistor, the base receives a second trigger signal, and the first emitter and the second emitter receive a second power supply signal.

4. The testing method according to claim 3, characterized in that: Also includes: Detecting whether the fuse is blown; If the fuse is blown, a first signal is output; If the fuse is not blown, a second signal is output.

5. An integrated circuit, characterized in that: Comprising the fuse testing circuit as claimed in claim 1.

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