Display Devices

Abstract

A display device is provided, comprising: a substrate; a first layer of power supply lines arranged on the substrate in a peripheral area, the peripheral area surrounding a display area in which an image is displayed; a first insulating layer located on the substrate on which the first layer of power supply lines are arranged; a second layer of power supply lines arranged on the first insulating layer and the first layer of power supply lines and in contact with the first layer of power supply lines; a second insulating layer located on the first insulating layer on which the second layer of power supply lines are arranged; and a light emitting structure arranged on the second insulating layer and comprising a first electrode, a light emitting layer, and a second electrode electrically connected to the second layer of power supply lines.

Description

Technical Field

[0001] Exemplary embodiments of the invention relate to a display device. More particularly, exemplary embodiments of the invention relate to a display device including a power supply line in a peripheral area. Background Art

[0002] Recently, display devices with light weight and small size have been manufactured. Cathode ray tube ("CRT") display devices have been used due to high performance and competitive price. However, CRT display devices have weaknesses including size or portability. Therefore, display devices such as plasma display devices, liquid crystal display devices, and organic light emitting display devices have attracted much attention due to their small size, light weight, and low power consumption.

[0003] Generally, a display device includes a display area in which an image is displayed and a peripheral area which is a non-display area and surrounds the display area. For the convenience of users, efforts have been made to reduce the peripheral area and improve the brightness of the display device. Summary of the invention

[0004] One or more exemplary embodiments of the invention provide a display device capable of reducing the size of a peripheral area and increasing brightness and improving display quality.

[0005] According to an exemplary embodiment of the invention, a display device includes: a substrate; a first layer of power supply lines, which are arranged on the substrate in a peripheral area, and the peripheral area surrounds a display area in which an image is displayed; a first insulating layer, which is located on the substrate on which the first layer of power supply lines are arranged; a second layer of power supply lines, which are arranged on the first insulating layer and the first layer of power supply lines and are in contact with the first layer of power supply lines; a second insulating layer, which is located on the first insulating layer on which the second layer of power supply lines are arranged; and a light emitting structure, which is arranged on the second insulating layer and includes a first electrode, a light emitting layer, and a second electrode electrically connected to the second layer of power supply lines.

[0006] In an exemplary embodiment, the display device may include a circuit portion thin film transistor ("TFT") disposed in a circuit portion region between the first layer power supply line and the display region. The second layer power supply line may extend to the circuit portion region.

[0007] In an exemplary embodiment, the uneven structure is provided on an upper surface of a portion of the second layer power supply line in the circuit portion region.

[0008] In an exemplary embodiment, an uneven structure may be provided on an upper surface of a portion of the first insulating layer contacting the second layer power supply line. The uneven structure of the second layer power supply line may correspond to the uneven structure of the first insulating layer.

[0009] In exemplary embodiments, the first insulating layer and the second insulating layer may include an organic insulating material.

[0010] In an exemplary embodiment, a voltage level of -3 volts (V) or less may be applied to the second electrode.

[0011] In an exemplary embodiment, an uneven structure may be provided on the second layer power supply line.

[0012] In an exemplary embodiment, the display device may further include a plurality of protrusions disposed between the first layer power supply line and the second layer power supply line. The plurality of protrusions may be disposed in the same layer as the first insulating layer.

[0013] In an exemplary embodiment, the display device may further include a thin film encapsulation layer including: a first inorganic layer disposed on the second electrode; a second inorganic layer disposed on the first inorganic layer; and an organic layer disposed between the first inorganic layer and the second inorganic layer.

[0014] In an exemplary embodiment, the display device may further include: a first insulating barrier disposed on the second layer power supply line; and a second insulating barrier spaced apart from the first insulating barrier and having a height higher than that of the first insulating barrier.

[0015] In an exemplary embodiment, the display device may further include a pixel defining layer, wherein the first insulating barrier and the second insulating barrier may include the same layer as any one or more of the first insulating layer, the second insulating layer, and the pixel defining layer.

[0016] In an exemplary embodiment, the power supply line may include a first layer power supply line and a second layer power supply line.The power supply line may extend along the peripheral area.

[0017] In an exemplary embodiment, an uneven structure may be provided on the first layer power supply line.

[0018] In an exemplary embodiment, the display device may further include an uneven structure insulating pattern disposed between the first layer power supply line and the substrate. The uneven structure may be disposed on the uneven structure insulating pattern, the uneven structure insulating pattern contacts the first layer power supply line, and the uneven structure of the first layer power supply line corresponds to the uneven structure of the uneven structure insulating pattern.

[0019] In an exemplary embodiment, the display device may further include: a buffer layer disposed on the substrate; a circuit portion active pattern of the circuit portion TFT disposed on the buffer layer in the peripheral region; a gate insulating layer disposed on the buffer layer, the circuit portion active pattern disposed on the buffer layer; a gate pattern disposed on the gate insulating layer and including a gate electrode of the circuit portion TFT; an insulating intermediate layer disposed on the gate insulating layer, the gate pattern disposed on the gate insulating layer; and a first data pattern disposed on the insulating intermediate layer and including a first layer power supply line.

[0020] In an exemplary embodiment, the display device may further include a third insulating barrier disposed on the buffer layer and contacting the gate insulating layer and the insulating interlayer.

[0021] In an exemplary embodiment, the second layer power supply line may overlap the circuit part TFT.

[0022] According to an exemplary embodiment of the invention, a display device includes: a substrate; an uneven structure insulating pattern, which is arranged on the substrate in a peripheral area, and the peripheral area surrounds a display area in which an image is displayed; a power supply line, which is arranged on the uneven structure insulating pattern; a first insulating layer, which is arranged on the substrate on which the power supply line is arranged; and a light-emitting structure, which is arranged on the first insulating layer and includes a first electrode, a light-emitting layer and a second electrode electrically connected to the power supply line.

[0023] In exemplary embodiments, an uneven structure corresponding to the uneven structure of the uneven structure insulation pattern may be disposed on a portion of the power supply line contacting the uneven structure insulation pattern.

[0024] According to an exemplary embodiment of the invention, a display device includes: a substrate; a first layer power supply line disposed on the substrate in a peripheral area, the peripheral area surrounding a display area in which an image is displayed; a first insulating layer located on the substrate on which the first layer power supply line is disposed; a second layer power supply line disposed on the first insulating layer and the first layer power supply line and in contact with the first layer power supply line; a second insulating layer located on the first insulating layer on which the second layer power supply line is disposed; and a light emitting structure disposed on the second insulating layer and including a first electrode, a light emitting layer, and a second electrode electrically connected to the second layer power supply line. An uneven structure is disposed on the first layer power supply line or the second layer power supply line.

[0025] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the invention will become more apparent by describing in detail exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a plan view showing an exemplary embodiment of a display device according to the invention;

[0028] Figure 2 It is shown Figure 1 An equivalent circuit diagram of an exemplary embodiment of a pixel shown in FIG.

[0029] Figure 3A It is along Figure 1 A cross-sectional view taken along line II';

[0030] Figure 3B Is the display device in Figure 2 A cross-sectional view of a portion corresponding to a pixel;

[0031] Figure 4A is a cross-sectional view showing an exemplary embodiment of a display device according to the invention;

[0032] Figure 4B Is the display device in Figure 4A A cross-sectional view of a portion corresponding to a pixel;

[0033] Figure 5A is a cross-sectional view showing an exemplary embodiment of a display device according to the invention;

[0034] Figure 5B Is the display device in Figure 5A A cross-sectional view of a portion corresponding to a pixel;

[0035] Fig. 6A is a cross-sectional view showing an exemplary embodiment of a display device according to the invention;

[0036] Figure 6B Is the display device in Fig. 6A A cross-sectional view of a portion corresponding to a pixel;

[0037] Fig. 7A is a cross-sectional view showing an exemplary embodiment of a display device according to the invention;

[0038] Figure 7B Is the display device in Fig. 7A A cross-sectional view of a portion corresponding to a pixel;

[0039] Figure 8 is a block diagram illustrating an exemplary embodiment of an electronic device;

[0040] Fig. 9A It shows that Figure 8 FIG. 1 is a diagram of an example in which the electronic device is implemented as a television; and

[0041] Fig. 9B It shows that Figure 8The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0042] Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

[0043] It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0044] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0045] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. Unless the content clearly states otherwise, as used herein, the singular forms "one", "an" and "said" are also intended to include plural forms including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be further understood that when the terms "include" and / or "comprise" or their variations are used in this specification, the description indicates the presence of the described features, regions, entireties, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or their groups.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used here to describe the relationship of one element to another (other) element as shown in the drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in one of the drawings in the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the drawings in the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. The exemplary terms "below..." or "below..." can therefore include both "above..." and "below..." orientations.

[0047] For ease of description, spatially relative terms such as "under," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature relative to another (other) element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Therefore, the exemplary term "under" may include both above and below orientations. The device may be positioned otherwise (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0048] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an ideal or overly formal sense unless explicitly defined as such herein.

[0050] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized exemplary embodiments. As such, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but will include deviations in shapes, for example, caused by manufacturing. For example, a region shown or described as being flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0051] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the invention.

[0052] Reference Figure 1 The display device may include a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA may include a peripheral area PA disposed adjacent to the display area DA and a driver area DR disposed adjacent to the peripheral area PA and below the display area DA.

[0053] The display device may include a plurality of pixels (not shown) disposed in the display area DA. The display device may include a driver and a power supply unit, the driver being used to drive the pixels disposed in the display area DA, and the power supply unit being used to supply power to the pixels. The display device may further include a wiring portion connecting the pixels and the driver. In an exemplary embodiment, for example, the driver may be disposed in the driver area DR, and the power supply unit may be disposed in the peripheral area PA and the driver area DR.

[0054] Each pixel PXL is the smallest unit for displaying an image, and may be provided in plurality. The pixel PXL may include a display element that emits colored light. In an exemplary embodiment, the display element may be, for example, any one of a liquid crystal display ("LCD") device, an electrophoretic display ("EPD") device, an electrowetting display ("EWD") device, and an organic light emitting diode ("OLED") device. Hereinafter, for convenience, an OLED device is explained as an example of a display element.

[0055] Each pixel PXL may emit one color among red, green, and blue, but is not limited thereto. In an exemplary embodiment, each pixel PXL may emit a color such as cyan, magenta, yellow, and white. Figure 2 and Figure 3B Describe the pixel in detail.

[0056] The power supply unit may include at least one power supply line. In an exemplary embodiment, the power supply unit may include, for example, a first power supply line PL1 and a second power supply line PL2. The first power supply line PL1 and the second power supply line PL2 may supply power to the pixel. The first power supply line PL1 may supply a first power source ELVDD to the pixel, and the second power supply line PL2 may supply a second power source ELVSS to the pixel.

[0057] The first power supply line PL1 may be disposed in the peripheral area PA disposed under the display area DA and may extend in the first direction D1.

[0058] The second power lines PL2 may be disposed in the peripheral area PA disposed at upper, left, and right sides of the display area DA. The second power lines PL2 may be disposed along the peripheral area PA in a first direction D1 and a second direction D2 crossing the first direction D1.

[0059] The wiring portion may provide a signal of a driver to a pixel, and may include, for example, a scan line, a data line, an emission control line, a power supply line, and an initialization power supply line.

[0060] Figure 2 It is shown Figure 1 An equivalent circuit diagram of an exemplary embodiment of a pixel is shown in FIG. Figure 2 In the figure, for convenience of explanation, a pixel connected to an m-th data line Dm and an i-th scan line S1i is shown, wherein m and i are natural numbers.

[0061] Reference Figure 2 , a pixel according to an exemplary embodiment of the invention is provided with an OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst.

[0062] The anode of the OLED is connected to the first transistor T1 via the sixth transistor T6, and the cathode of the OLED is connected to the second power source ELVSS. Such an OLED generates light of a certain brightness corresponding to the amount of current supplied by the first transistor T1.

[0063] The first power source ELVDD may be set to a voltage higher than that of the second power source ELVSS so that current may flow to the OLED.

[0064] The seventh transistor T7 is connected between the initialization power supply Vint and the anode of the OLED. In addition, the gate electrode of the seventh transistor T7 is connected to the i+1 scan line S1i+1. When the scan signal is supplied to the i+1 scan line S1i+1, such a seventh transistor T7 is turned on and the voltage of the initialization power supply Vint is supplied to the anode of the OLED. Here, the initialization power supply Vint can be set to a voltage lower than the data signal. However, exemplary embodiments are not limited thereto. For example, in another embodiment, the gate electrode of the seventh transistor T7 can be connected to the i-1 scan line Sli-1.

[0065] The sixth transistor T6 is connected between the first transistor T1 and the OLED. In addition, the gate electrode of the sixth transistor T6 is connected to the i-th light emitting control line E1i. When the light emitting control signal is supplied to the i-th light emitting control line E1i, such a sixth transistor T6 is turned off, and in other cases, the sixth transistor T6 is turned on.

[0066] The fifth transistor T5 is connected between the first power source ELVDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 is connected to the i-th light emitting control line E1i. When the light emitting control signal is supplied to the i-th light emitting control line E1i, such a fifth transistor T5 is turned off, and in other cases, the fifth transistor T5 is turned on.

[0067] A first electrode of the first transistor T1 (driving transistor) is connected to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode of the OLED via the sixth transistor T6. In addition, a gate electrode of the first transistor T1 is connected to the first node N1. Such a first transistor T1 controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the OLED in response to the voltage of the first node N1.

[0068] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 is connected to the i-th scan line S1i. When the scan signal is supplied to the i-th scan line S1i, such a third transistor T3 is turned on and electrically connects the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode form. That is, when the third transistor T3 is turned on, the first node N1 is electrically connected to the second node N2.

[0069] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. In addition, the gate electrode of the fourth transistor T4 is connected to the i-1th scan line S1i-1. When the scan signal is supplied to the i-1th scan line S1i-1, such a fourth transistor T4 is turned on and supplies the voltage of the initialization voltage Vint to the first node N1.

[0070] The second transistor T2 is connected between the mth data line Dm and the first electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 is connected to the i-th scan line S1i. When the scan signal is supplied to the i-th scan line S1i, such a second transistor T2 is turned on and electrically connects the mth data line Dm and the first electrode of the first transistor T1.

[0071] The storage capacitor Cst is connected between the first power source ELVDD and the first node N1. Such a storage capacitor Cst stores a data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

[0072] Figure 3A It is along Figure 1 A cross-sectional view taken along line II'. Figure 3B Is the display device in Figure 2 A cross-sectional view of the portion corresponding to the pixel.

[0073] Reference Figure 3B , in the display area DA, the display device may include a substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer 190.

[0074] The substrate 100 including a transparent insulating material or an opaque insulating material may be provided. In an exemplary embodiment, the substrate 100 may include, for example, a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. In an alternative exemplary embodiment, the substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate).

[0075] The buffer layer 110 may be disposed on the substrate 100. The buffer layer 110 may be disposed on the entire substrate 100. The buffer layer 110 may prevent metal atoms and / or impurities from diffusing from the substrate 100 into the active pattern ACT. In addition, the buffer layer 110 may control the rate of heat transfer in a crystallization process for forming the active pattern ACT, thereby obtaining a substantially uniform active pattern ACT.

[0076] The active pattern ACT may be disposed on the buffer layer 110. The active pattern ACT may include amorphous silicon or polycrystalline silicon. In some exemplary embodiments, the active pattern ACT may include an oxide of at least one substance selected from the group including, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active pattern ACT may include a source region S and a drain region D doped with impurities and a channel region C disposed between the source region S and the drain region D.

[0077] The gate insulating layer 120 may be disposed on the buffer layer 110. The gate insulating layer 120 may be uniformly disposed on the buffer layer 110 along the contour of the active pattern ACT. In an exemplary embodiment, the gate insulating layer 120 may include, for example, a silicon compound, a metal oxide, or the like.

[0078] The gate pattern may be disposed on the gate insulating layer 120. The gate pattern may include a gate electrode GE and a signal line such as a gate line. In an exemplary embodiment, the gate pattern may be disposed using, for example, metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.

[0079] The insulating interlayer 130 may be disposed on the gate insulating layer 120 on which the gate pattern is disposed. In an exemplary embodiment, the insulating interlayer 130 may be uniformly disposed on the gate insulating layer 120 along the contour of the gate pattern. Here, the insulating interlayer 130 may have a substantially small thickness so that a step portion may be provided at a portion of the insulating interlayer 130 adjacent to the gate pattern. In some exemplary embodiments, the insulating interlayer 130 may have a relatively large thickness for sufficiently covering the gate pattern so that the insulating interlayer 130 may have a substantially horizontal surface. The insulating interlayer 130 may include a silicon compound or a metal oxide, etc. The insulating interlayer 130 may include a plurality of layers.

[0080] The first data pattern may be disposed on the insulating interlayer 130. The first data pattern may include the source electrode SE and the drain electrode DE of the thin film transistor TFT, the first layer second power supply line PL2a of the first layer power supply line (see FIG. 1 ). Figure 3A ) and signal lines such as data lines. The first data pattern may be provided using metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In an exemplary embodiment, the first data pattern may be a stacked structure including, for example, a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti).

[0081] The active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may form a thin film transistor TFT. In an exemplary embodiment, the thin film transistor TFT may be a first transistor to a seventh transistor included in a pixel (refer to Figure 2 Any one of T1 to T7).

[0082] The first insulating layer 140 may be disposed on the insulating interlayer 130 on which the first data pattern is disposed. The first insulating layer 140 may have a single-layer structure or a multi-layer structure including at least two insulating films. The first insulating layer 140 may be provided using an organic material. In an exemplary embodiment, the first insulating layer 140 may include, for example, a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, etc.

[0083] The second data pattern may be disposed on the first insulating layer 140. The second data pattern may include a second layer second power supply line PL2b (see Figure 3A ) and a signal line such as a data line. In an exemplary embodiment, the second data pattern may be provided using, for example, a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In an exemplary embodiment, the second data pattern may be a stacked structure including, for example, a first layer including titanium (Ti), a second layer including aluminum (Al), and a third layer including titanium (Ti).

[0084] The second insulating layer 150 may be disposed on the first insulating layer 140 on which the second data pattern is disposed. The second insulating layer 150 may have a single-layer structure or a multi-layer structure including at least two insulating films. The second insulating layer 150 may be provided using an organic material. In an exemplary embodiment, the first insulating layer 140 may include, for example, a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, etc. In some exemplary embodiments, the second insulating layer 150 may be provided using an inorganic material such as, for example, a silicon compound, a metal, or a metal oxide.

[0085] The light emitting structure 180 may include a first electrode 181 , an emission layer 182 , and a second electrode 183 .

[0086] The first electrode 181 may be disposed on the second insulating layer 150. Depending on the emission type of the display device, the first electrode 181 may include a reflective material or a transmissive material. In an exemplary embodiment, the first electrode 181 may be provided using, for example, aluminum, an alloy including aluminum, aluminum nitride, silver, an alloy including silver, tungsten, tungsten nitride, copper, an alloy including copper, nickel, an alloy including nickel, chromium, chromium nitride, molybdenum, an alloy including molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. They may be used alone or in combination. In an exemplary embodiment, the first electrode 181 may have a single-layer structure or a multi-layer structure, and the first electrode 181 may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0087] The pixel defining layer PDL may be disposed on the second insulating layer 150 on which the first electrode 181 is disposed. The pixel defining layer PDL may be disposed using an organic material. In an exemplary embodiment, the pixel defining layer PDL may include, for example, a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, and the like. In some exemplary embodiments, the opening exposing the first electrode 181 may be defined by etching the pixel defining layer PDL. The light-emitting area and the non-light-emitting area of ​​the display device may be defined by the opening of the pixel defining layer PDL. In an exemplary embodiment, for example, the portion where the opening of the pixel defining layer PDL is located may correspond to the light-emitting area, and the non-light-emitting area may correspond to the portion adjacent to the opening of the pixel defining layer PDL.

[0088] The light-emitting layer 182 may be disposed on the first electrode 181 exposed by the opening of the pixel defining layer PDL. In addition, the light-emitting layer 182 may extend on the sidewall of the opening of the pixel defining layer PDL. In some exemplary embodiments, the light-emitting layer 182 may include an organic light-emitting layer ("EL"), a hole injection layer ("HIL"), a hole transport layer ("HTL"), an electron transport layer ("ETL"), an electron injection layer ("EIL"), etc. In some exemplary embodiments, in addition to the organic light-emitting layer (EL), the HIL, HTL, ETL and EIL may be provided together to correspond to a plurality of pixels. In some exemplary embodiments, a plurality of ELs may be provided using light-emitting materials for generating light of different colors such as red light, green light and blue light according to the color pixels of the display device. In some exemplary embodiments, the EL of the light-emitting layer 182 may include a plurality of stacked light-emitting materials for generating red light, green light and blue light, thereby emitting white light. Here, the elements of the light-emitting layer 182 are provided together to correspond to a plurality of pixels, and each pixel may be divided by a color filter layer.

[0089] The second electrode 183 may be disposed on the pixel defining layer PDL and the light emitting layer 182. The second electrode 183 may include a transmissive material or a reflective material according to the emission type of the display device. In an exemplary embodiment, the second electrode 183 may be provided using, for example, aluminum, an alloy including aluminum, aluminum nitride, silver, an alloy including silver, tungsten, tungsten nitride, copper, an alloy including copper, nickel, an alloy including nickel, chromium, chromium nitride, molybdenum, an alloy including molybdenum, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, etc. They may be used alone or in combination. In an exemplary embodiment, the second electrode 183 may also have a single-layer structure or a multilayer structure, and the second electrode 183 may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0090] The thin film encapsulation layer 190 may be disposed on the second electrode 183. The thin film encapsulation layer 190 may prevent moisture and oxygen from penetrating from the outside. The thin film encapsulation layer 190 may include a first inorganic layer 191, an organic layer 192, and a second inorganic layer 193. The first inorganic layer 191, the organic layer 192, and the second inorganic layer 193 may be sequentially stacked on the second electrode 183.

[0091] Here, the thin film encapsulation layer 190 may include at least one organic layer and at least one inorganic layer alternately stacked with each other. In the illustrated exemplary embodiment, the thin film encapsulation layer 190 includes first and second inorganic layers 191 and 193 and one organic layer 192 therebetween, but the invention is not limited thereto.

[0092] Reference Figure 3A , in the peripheral area PA, the display device may include a substrate 100, a buffer layer 110, a driver active pattern ACTa, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a first insulating barrier DM1, a second insulating barrier DM2, a third insulating barrier DM3 and a thin film encapsulation layer 190.

[0093] The buffer layer 110 may be disposed to an edge (left side of the drawing) of the substrate 100 . The driver active pattern ACTa may be disposed on the buffer layer 110 .

[0094] The gate insulating layer 120 may be disposed on the buffer layer 110 on which the driver active pattern ACTa is disposed. The gate insulating layer 120 may not be disposed to the edge of the substrate 100 but may be disposed only to the third insulating barrier DM3.

[0095] The gate pattern may be disposed on the gate insulating layer 120. The gate pattern may further include a driver gate electrode GEa.

[0096] The insulating interlayer 130 may be disposed on the gate insulating layer 120 on which the gate pattern is disposed. The insulating interlayer 130 may not be disposed to the edge of the substrate 100 but may be disposed only to the third insulating barrier DM3.

[0097] The third insulating barrier DM3 may be disposed on the buffer layer 110 on which the insulating interlayer 130 is disposed. The third insulating barrier DM3 is for preventing cracks from being transmitted to the display area DA through the inorganic film layer due to physical damage caused by external impact (refer to Figure 1 The third insulating barrier DM3 may be disposed in the same layer as the first insulating layer 140 or the second insulating layer 150. The third insulating barrier DM3 may contact the insulating interlayer 130 and the gate insulating layer 120.

[0098] The first data pattern may be disposed on the insulating interlayer 130. The first data pattern may further include a driver source electrode SEa and a driver drain electrode DEa of the circuit portion thin film transistor TFTa and a first layer second power supply line PL2a.

[0099] The first insulating layer 140 may be disposed on the insulating interlayer 130 on which the first data pattern is disposed.

[0100] The second data pattern may be disposed on the first insulating layer 140. The second data pattern may further include a second-layer second power supply line PL2b. The first-layer second power supply line PL2a is not completely covered by the first insulating layer 140, and a portion of the first-layer second power supply line PL2a may be exposed so that the first-layer second power supply line PL2a may contact the second-layer second power supply line PL2b. That is, the first-layer second power supply line PL2a and the second-layer second power supply line PL2b may contact each other in the peripheral area PA, and a double wiring may be formed. Therefore, the width of the second power supply line PL2 may be reduced, and the wiring resistance of the second power supply line PL2 may be reduced while reducing the width of the peripheral area PA.

[0101] Specifically, in the prior art, when the absolute value of the voltage applied to the second power supply line is increased to increase the brightness of the display device, the power consumption increases and the problem of degradation of the display quality due to the wiring resistance of the second power supply line is significant. According to the illustrated exemplary embodiment, since the width of the peripheral area PA can be reduced while reducing the wiring resistance of the second power supply line PL2, the display quality can be improved.

[0102] Table 1 below is a simulation value and an actual value, showing that when the brightness of the display device increases from about 420 nits to about 700 nits, the absolute value of the desired second power supply voltage level is large.

[0103]

[0104]

[0105] Here, it can be seen that since the wiring resistance of the second power supply line PL2 having a double wiring structure can be reduced, the influence caused by the second power supply voltage level being lower (the absolute value being larger) and the increased power consumption in the second power supply line PL2 can be reduced. According to an exemplary embodiment, the wiring resistance of the second power supply line PL2 can be reduced.

[0106] The second insulating layer 150 may be disposed on the first insulating layer 140 on which the second data pattern is disposed. The second electrode 183 may be disposed on the second insulating layer 150 and the second layer second power supply line PL2b to be electrically connected to the second layer second power supply line PL2b.

[0107] The first insulating barrier DM1 may be disposed on the second-layer second power supply line PL2b. The second insulating barrier DM2 may be disposed on the first-layer second power supply line PL2a and the insulating interlayer 130. The second insulating barrier DM2 is separated from the first insulating barrier DM1 and has a height higher than that of the first insulating barrier DM1, and the second insulating barrier DM2 may be disposed adjacent to the first-layer second power supply line PL2a on the insulating interlayer 130. The first insulating barrier DM1 may be arranged to surround the display area DA. The second insulating barrier DM2 may be separated from the first insulating barrier DM1 and arranged to surround the first insulating barrier DM1.

[0108] The first and second insulating barriers DM1 and DM2 may be disposed in the same layer as any one or more of the first insulating layer 140 , the second insulating layer 150 , and the pixel defining layer PDL.

[0109] In an exemplary embodiment, the first insulating barrier DM1 may include, for example, a first portion DM1a and a second portion DM1b disposed on the first portion DM1a. The first portion DM1a may be disposed in the same layer as the second insulating layer 150, and the second portion DM1b may be disposed in the same layer as the pixel defining layer PDL.

[0110] In an exemplary embodiment, the second insulating barrier DM2 may include, for example, a first portion DM2a, a second portion DM2b disposed on the first portion DM2a, and a third portion DM2c disposed on the second portion DM2a. The first portion DM2a may be disposed in the same layer as the first insulating layer 140, the second portion DM2b may be disposed in the same layer as the second insulating layer 150, and the third portion DM2c may be disposed in the same layer as the pixel defining layer PDL.

[0111] The first insulating barrier DM1 and the second insulating barrier DM2 can prevent the organic material of the organic layer 192 of the thin film encapsulation layer 190 that seals the display area DA from flowing in the edge direction of the substrate 100. Therefore, the formation of an edge tail of the organic material can be prevented. Here, the edge tail means that the edge of the organic layer is set to flow outward beyond the edge of the inorganic layer. Generally, in order to form the thin film encapsulation layer 190, when the organic layer and the inorganic layer are set, the pattern is set by placing a mask corresponding to the layer on the substrate. At this time, the organic layer penetrates into the gap between the mask and the substrate, and the edge tail is well formed. In this case, oxygen or moisture can penetrate into the structure in the display area DA through the edge tail, thereby deteriorating the display quality.

[0112] A thin film encapsulation layer 190 including a first inorganic layer 191, an organic layer 192, and a second inorganic layer 193 may be disposed on the substrate 100 on which the second electrode 183 is disposed. The organic layer 192 may be disposed from the display area DA to the first insulating barrier DM1.

[0113] The circuit portion thin film transistor TFTa may be disposed in a circuit portion region CA between the first layer second power supply line PL2a and the display region DA. The circuit portion region CA may be disposed adjacent to the display region DA. The peripheral region PA may include the circuit portion region CA. In addition to the circuit portion thin film transistor TFTa, a circuit and wiring for driving the display device may also be disposed in the circuit portion region CA.

[0114] According to the exemplary embodiment shown, the second power line PL2 may be set as a double wiring by the first data pattern and the second data pattern, so that the width of the second power line PL2 may be reduced and the wiring resistance of the second power line PL2 may be reduced while reducing the width of the peripheral area PA.

[0115] Specifically, in the prior art, when the absolute value of the voltage applied to the second power supply line increases to increase the brightness of the display device, power consumption increases, and the problem of display quality degradation due to the wiring resistance of the second power supply line is significant. According to the illustrated exemplary embodiment, since the width of the peripheral area PA can be reduced while reducing the wiring resistance of the second power supply line PL2, the display quality can be improved.

[0116] In particular, when a voltage level of -3 volts (V) or less is applied to the second electrode 183 of the light emitting structure 180, an influence due to wiring resistance is minimized, so that display quality may be improved compared to a conventional structure.

[0117] Although not shown, the first power supply line PL1 may have a similar structure to the second power supply line PL2 .

[0118] Figure 4A is a cross-sectional view showing a display device according to an exemplary embodiment of the invention. Figure 4B Is the display device in Figure 4A Since the display device is connected to the second power supply line PL2b in addition to the second layer second power supply line PL2b, Figure 3A and Figure 3B The display devices are basically the same, so repeated descriptions will be omitted.

[0119] Reference Figure 4A and Figure 4B , in the display area DA (refer to Figure 1 ), the display device may include a substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer 190.

[0120] The first data pattern may include the circuit portion source electrode SEa and the circuit portion drain electrode DEa of the circuit portion thin film transistor TFTa and the first layer second power supply line PL2a. The second data pattern may include the second layer second power supply line PL2b.

[0121] Here, the second layer second power supply line PL2b may extend into the circuit portion area CA where the circuit portion thin film transistor TFTa is disposed. Therefore, a portion of the second layer second power supply line PL2b may be disposed in the circuit portion area CA to overlap the circuit portion thin film transistor TFTa.

[0122] According to the illustrated exemplary embodiment, since the second power supply line PL2 forms a double wiring and further extends to the circuit portion area CA, the wiring resistance reduction effect can be further increased.

[0123] Figure 5A is a cross-sectional view showing a display device according to an exemplary embodiment of the invention. Figure 5B Is the display device in Figure 5A In addition to the uneven structure of the second layer second power supply line PL2b, the display device is similar to Figure 4A and Figure 4B The display devices are basically the same, so repeated descriptions will be omitted.

[0124] Reference Figure 5A and Figure 5B, in the display area DA, the display device may include a substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer 190.

[0125] In the peripheral area PA, the display device may include a substrate 100, a buffer layer 110, a circuit portion active pattern ACTa, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a first insulating barrier DM1, a second insulating barrier DM2, a third insulating barrier DM3 and a thin film encapsulation layer 190.

[0126] The first data pattern may include the circuit portion source electrode SEa and the circuit portion drain electrode DEa of the circuit portion thin film transistor TFTa and the first layer second power supply line PL2a. The second data pattern may include the second layer second power supply line PL2b.

[0127] Here, the second layer second power supply line PL2b may extend into the circuit portion area CA where the circuit portion thin film transistor TFTa is disposed. Therefore, a portion of the second layer second power supply line PL2b may be disposed in the circuit portion area CA to overlap the circuit portion thin film transistor TFTa.

[0128] An uneven structure may be provided on the second layer second power supply line PL2b in the circuit portion area CA. Thus, a plurality of grooves may be defined in the upper and lower surfaces of the second layer second power supply line PL2b so that the upper and lower surfaces may form an uneven surface. Thus, the area of ​​the second layer second power supply line PL2b is increased, thereby further reducing the wiring resistance.

[0129] At this time, an uneven structure is provided on the upper surface of the first insulating layer 140 contacting the second layer second power supply line PL2 b and the uneven structure of the second layer second power supply line PL2 b may be provided corresponding to the uneven structure on the upper surface of the first insulating layer 140 .

[0130] The uneven structure on the upper surface of the first insulating layer 140 can be set by various methods. In an exemplary embodiment, when the first insulating layer 140 is set, for example, a photoresist material can be used. During the manufacturing process, by using a slit mask or a halftone mask in various parts of the first insulating layer 140 whose top surface is still substantially flat to change the amount of exposure, specific parts are etched relatively more than other parts. Here, the more etched part can be understood as a recess on the upper surface of the first insulating layer 140. The method used when manufacturing the display device according to the exemplary embodiment shown is not limited to such a method. In an exemplary embodiment, a first insulating layer 140 with a substantially flat top surface can be set, and then only a specific part can be removed by, for example, a dry etching method, etc.

[0131] According to the illustrated exemplary embodiment, since the second power supply line PL2 forms a double wiring and further extends to the circuit portion area CA, and an uneven structure is provided on the second power supply line PL2, the wiring resistance reduction effect may be further increased.

[0132] Fig. 6A is a cross-sectional view showing a display device according to an exemplary embodiment of the invention. Figure 6B Is the display device in Fig. 6A In addition to the uneven structure of the second layer second power supply line PL2b, the display device is similar to Figure 3A and Figure 3B The display devices are basically the same, so repeated descriptions will be omitted.

[0133] Reference Fig. 6A and Figure 6B , in the display area DA, the display device may include a substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer 190.

[0134] In the peripheral area PA, the display device may include a substrate 100, a buffer layer 110, a circuit portion active pattern ACTa, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a first data pattern, a first insulating layer 140, a second data pattern, a second insulating layer 150, a first insulating barrier DM1, a second insulating barrier DM2, a third insulating barrier DM3 and a thin film encapsulation layer 190.

[0135] The first data pattern may include the circuit portion source electrode SEa and the circuit portion drain electrode DEa of the circuit portion thin film transistor TFTa and the first layer second power supply line PL2a. The second data pattern may include the second layer second power supply line PL2b.

[0136] The second-layer second power supply line PL2b may be provided with an uneven structure. In other words, a plurality of grooves may be defined in the upper and lower surfaces of the second-layer second power supply line PL2b, so that the upper and lower surfaces of the second-layer second power supply line PL2b may form an uneven surface. Therefore, the area of ​​the second-layer second power supply line PL2b is increased, thereby further reducing the wiring resistance.

[0137] At this time, a plurality of protrusions 142 may be provided between the first-layer second power supply line PL2a and the second-layer second power supply line PL2b. The plurality of protrusions 142 may be spaced apart from each other and may be patterned by the same layer as the first insulating layer 140. The plurality of protrusions 142 may form an uneven surface on the first-layer second power supply line PL2a, thereby forming an uneven structure on the second-layer second power supply line PL2b. That is, the uneven structure of the second-layer second power supply line PL2b may be provided corresponding to the protrusions.

[0138] Fig. 7A is a cross-sectional view showing a display device according to an exemplary embodiment of the invention. Figure 7B Is the display device in Fig. 7A The display device is similar to the pixel corresponding to the portion of FIG. 1 . In addition to the data pattern and the uneven structure insulating pattern 135 for forming the uneven structure of the second power supply line being provided as one layer, Fig. 6A and Figure 6B The display devices are basically the same, so repeated descriptions will be omitted.

[0139] Reference Fig. 7A and Figure 7B , in the display area DA, the display device may include a substrate 100, a buffer layer 110, an active pattern ACT, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a data pattern, a first insulating layer 140, a pixel defining layer PDL, a light emitting structure 180 and a thin film encapsulation layer 190.

[0140] In the peripheral area PA, the display device may include a substrate 100, a buffer layer 110, a circuit portion active pattern ACTa, a gate insulating layer 120, a gate pattern, an insulating interlayer 130, a data pattern, a first insulating layer 140, a first insulating barrier DM1, a second insulating barrier DM2, a third insulating barrier DM3 and a thin film encapsulation layer 190.

[0141] The data pattern may include the circuit portion source electrode SEa and the circuit portion drain electrode DEa of the circuit portion thin film transistor TFTa and the second power supply line PL2 .

[0142] An uneven structure may be provided on the second power supply line PL2. That is, a plurality of grooves may be defined in the upper and lower surfaces of the second power supply line PL2 so that the upper and lower surfaces may form uneven surfaces. Therefore, the area of ​​the second power supply line PL2 increases and wiring resistance may be reduced.

[0143] At this time, an uneven structure insulating pattern 135 may be disposed between the insulating interlayer 130 and the second power supply line PL2. The uneven structure insulating pattern 135 may have an uneven structure on its upper surface to form an uneven surface. The uneven structure insulating pattern 135 may be disposed by various methods. In an exemplary embodiment, when the uneven structure insulating pattern 135 is disposed, for example, a photoresist material may be used, and the uneven structure insulating pattern 135 may be disposed by using a slit mask or a halftone mask, etc. to change the exposure amount so that a specific portion is etched (removed) relatively more than other portions. That is, the second power supply line PL2 contacting the uneven structure insulating pattern 135 may have an uneven structure disposed corresponding to the uneven structure of the uneven structure insulating pattern 135.

[0144] Figure 8 is a block diagram illustrating an electronic device according to an exemplary embodiment. Fig. 9A It shows that Figure 8 The electronic device is implemented as an example of a television. Fig. 9B It shows that Figure 8 The electronic device is implemented as an example of a smart phone.

[0145] Reference Figures 8 to 9B , the electronic device 500 may include a processor 510, a memory device 520, a storage device 530, an input / output ("I / O") device 540, a power supply 550, and a display device 560. Here, the display device 560 may be connected to Figure 1 In addition, the electronic device 500 may also include multiple ports for communicating with a video card, a sound card, a memory card, a universal serial bus ("USB") device, other electronic devices, etc. In an exemplary embodiment, as Fig. 9A As shown in , the electronic device 500 may be implemented as a television. In another exemplary embodiment, as Fig. 9BAs shown in , the electronic device 500 may be implemented as a smart phone. However, the electronic device 500 is not limited thereto. In an exemplary embodiment, the electronic device 500 may be implemented as, for example, a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer ("PC"), a car navigation system, a computer monitor, a portable computer, a head mounted display ("HMD"), etc.

[0146] The processor 510 may perform various computing functions. The processor 510 may be a microprocessor, a central processing unit ("CPU"), an application processor ("AP"), etc. The processor 510 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 510 may be coupled to an expansion bus such as a peripheral component interconnect ("PCI") bus. The memory device 520 may store data for operating the electronic device 500. In an exemplary embodiment, for example, the memory device 520 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.). In an exemplary embodiment, the storage device 530 may include, for example, a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. In an exemplary embodiment, for example, I / O device 540 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and output devices such as a printer, a speaker, etc. Power supply 550 may provide power for operation of electronic device 500 .

[0147] The display device 560 may be coupled to other components via a bus or other communication links. In some exemplary embodiments, the display device 560 may be included in the I / O device 540. As described above, according to the display device 560, by reducing the wiring resistance of the power supply line while reducing the width of the peripheral area as the non-display area, the display quality can be improved even when the brightness of the display device 560 is increased. However, since these have been described above, their repeated description will be omitted.

[0148] The invention can be applied to organic light-emitting display devices and various electronic devices including organic light-emitting display devices. In an exemplary embodiment, the invention can be implemented as, for example, a cellular phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer monitor, a portable computer, an HMD, etc.

[0149] The foregoing is an illustration of the invention and should not be construed as a limitation of the invention. Although some exemplary embodiments of the invention have been described, it will be readily appreciated by those skilled in the art that many modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the invention. Therefore, all such changes are intended to be included within the scope of the invention as defined in the claims. In the claims, the means-plus-function statement is intended to cover structures that perform the functions as described herein, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of the invention and is not to be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the claims. The invention is defined by the claims and the equivalents of the claims included therein.

Claims

1. A display device, comprising: substrate; a first layer of power supply lines disposed on the substrate in a peripheral region surrounding a display region in which an image is displayed; a first insulating layer, located on the substrate on which the first layer of power supply wires is arranged; A second layer of power supply lines, disposed on the first insulating layer and the first layer of power supply lines, and in contact with the first layer of power supply lines to form a double wiring structure; a second insulating layer, located on the first insulating layer on which the second layer of power supply wires is arranged; as well as a light emitting structure, disposed on the second insulating layer, and comprising a first electrode, a light emitting layer and a second electrode directly contacting the second layer power supply line, wherein the second electrode, the first layer power supply line and the second layer power supply line overlap each other in the peripheral area, The power supply lines include the first layer of power supply lines and the second layer of power supply lines, and the power supply lines extend along the peripheral area.

2. The display device according to claim 1, further comprising: A circuit portion thin film transistor is disposed in a circuit portion region, wherein the circuit portion region is located between the first layer power supply line and the display region, and Wherein, the second layer power supply line extends to the circuit part area.

3. The display device according to claim 2, wherein: An uneven structure is provided on an upper surface of a portion of the second layer power supply line in the circuit portion region.

4. The display device according to claim 3, wherein: An uneven structure is provided on an upper surface of a portion of the first insulating layer that contacts the second-layer power supply line, and The uneven structure of the second-layer power supply line corresponds to the uneven structure of the first insulating layer.

5. The display device according to claim 4, wherein: The first insulating layer and the second insulating layer include an organic insulating material.

6. The display device according to claim 5, wherein: A voltage level of -3 volts or less is applied to the second electrode.

7. The display device according to claim 1, wherein: The uneven structure is arranged on the second-layer power supply line.

8. The display device according to claim 7, further comprising: a plurality of protrusions disposed between the first layer power supply line and the second layer power supply line, and The plurality of protrusions are disposed in the same layer as the first insulating layer.

9. The display device according to claim 1, further comprising: A thin film encapsulation layer includes: a first inorganic layer disposed on the second electrode; a second inorganic layer disposed on the first inorganic layer; and an organic layer disposed between the first inorganic layer and the second inorganic layer.

10. The display device according to claim 9, further comprising: A first insulating barrier is arranged on the second layer power supply line; as well as The second insulating barrier is spaced apart from the first insulating barrier and has a height greater than that of the first insulating barrier.

11. The display device according to claim 10, further comprising a pixel defining layer, wherein: The first insulating barrier and the second insulating barrier include the same layer as any one or more layers of the first insulating layer, the second insulating layer, and the pixel defining layer.

12. The display device according to claim 1, wherein: The uneven structure is arranged on the first layer of power supply lines.

13. The display device according to claim 12, further comprising: An uneven structure insulating pattern is disposed between the first layer power supply line and the substrate, and The uneven structure is disposed on the uneven structure insulation pattern, the uneven structure insulation pattern contacts the first-layer power supply line, and the uneven structure of the first-layer power supply line corresponds to the uneven structure of the uneven structure insulation pattern.

14. The display device according to claim 1, further comprising: A buffer layer is disposed on the substrate; A circuit portion active pattern of a circuit portion thin film transistor is disposed on the buffer layer in the peripheral region; A gate insulating layer is disposed on the buffer layer, and the circuit part active pattern is disposed on the buffer layer; A gate pattern, disposed on the gate insulating layer and including a gate electrode of the thin film transistor of the circuit portion; an insulating intermediate layer, disposed on the gate insulating layer, and the gate pattern is disposed on the gate insulating layer; as well as The first data pattern is disposed on the insulating intermediate layer and includes the first layer power supply line.

15. The display device according to claim 14, further comprising: A third insulating barrier is disposed on the buffer layer and is in contact with the gate insulating layer and the insulating interlayer.

16. The display device according to claim 14, wherein: The second-layer power supply line overlaps the thin-film transistor of the circuit portion.

17. A display device, comprising: substrate; a first layer of power supply lines disposed on the substrate in a peripheral region surrounding a display region in which an image is displayed; a first insulating layer, located on the substrate on which the first layer of power supply wires is arranged; A second layer of power supply lines, disposed on the first insulating layer and the first layer of power supply lines, and in contact with the first layer of power supply lines to form a double wiring structure; a second insulating layer, located on the first insulating layer on which the second layer of power supply wires is arranged; as well as a light emitting structure, disposed on the second insulating layer, and comprising a first electrode, a light emitting layer and a second electrode directly contacting the second layer power supply line, wherein the second electrode, the first layer power supply line and the second layer power supply line overlap each other in the peripheral area, wherein the uneven structure is arranged on the first layer power supply line or the second layer power supply line, and The power supply lines include the first layer of power supply lines and the second layer of power supply lines, and the power supply lines extend along the peripheral area.

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