Display device

Abstract

A display device is disclosed, which includes a substrate, a semiconductor layer on the substrate, a first insulating layer on the semiconductor layer, a first conductive layer on the semiconductor layer, a second insulating layer on the first conductive layer, a first contact hole penetrating the first insulating layer and the second insulating layer, a second conductive layer on the second insulating layer, and a third insulating layer on the second conductive layer, wherein the second conductive layer is connected to the semiconductor layer through the first contact hole and includes a hydrogen barrier material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0095944, filed on August 17, 2018 in the Korean Intellectual Property Office and entitled “DISPLAY DEVICE,” is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to a display device. Background Art

[0004] With the development of multimedia, the importance of display devices has increased. Accordingly, various types of display devices such as liquid crystal displays ("LCDs") and organic light emitting displays ("OLEDs") have been used. Among these display devices, an organic light emitting display device displays an image by using an organic light emitting element that generates light by recombination of electrons and holes. Summary of the invention

[0005] An embodiment relates to a display device, which includes a substrate, a semiconductor layer located on the substrate, a first insulating layer located on the semiconductor layer, a first conductive layer located on the semiconductor layer, a second insulating layer located on the first conductive layer, a first contact hole penetrating the first insulating layer and the second insulating layer, a second conductive layer located on the second insulating layer, and a third insulating layer located on the second conductive layer, wherein the second conductive layer is connected to the semiconductor layer through the first contact hole and includes a hydrogen barrier material.

[0006] An embodiment also relates to a display device, which includes a substrate, a semiconductor layer located on the substrate, a first insulating layer located on the semiconductor layer, a first conductive layer located on the semiconductor layer, a second insulating layer located on the first conductive layer, a first contact hole penetrating the first insulating layer and the second insulating layer to expose the semiconductor layer, a second conductive layer located on the second insulating layer and connected to the semiconductor layer through the first contact hole, a third insulating layer located on the second conductive layer, a second contact hole penetrating the third insulating layer to expose the second conductive layer and overlapping with the first contact hole, and a third conductive layer located on the third insulating layer and connected to the second conductive layer through the second contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A block diagram showing a display device according to an example embodiment is shown;

[0009] Figure 2 Shown in the display included Figure 1 A circuit diagram of an example of a pixel in a display device;

[0010] Figure 3 and Figure 4 Shown Figure 1 An example layout diagram of a display device;

[0011] Figure 5 Shown along Figure 4 A cross-sectional view taken along line AA', line BB' and line CC';

[0012] Figure 6 Shown in the display included Figure 5 A cross-sectional view of an example of a second conductive layer in a display device;

[0013] Figure 7 and Figure 8 Shown is a diagram for explaining the Figure 5 A cross-sectional view of hydrogenation and dehydrogenation of a semiconductor layer in a display device;

[0014] Fig. 9 Shown Figure 1 A layout diagram of another example of a display device; and

[0015] Fig.10 Shown Fig. 9 A cross-sectional view of an example of a display device. DETAILED DESCRIPTION

[0016] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey example implementations to those skilled in the art. In the figures, the dimensions of layers and regions may be exaggerated for clarity. The same reference numerals represent the same elements throughout.

[0017] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the inventive concept. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. It should also be understood that when the words "comprise" and / or "comprising" are used in this specification, they indicate the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof.

[0018] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] It should be understood that although the words first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these words. These words are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the teaching of the concept of the present invention.

[0020] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0021] Figure 1 is a block diagram of a display device according to example embodiments.

[0022] Reference Figure 1 According to an example embodiment, the display device 1 includes a display unit 10 including pixels PX (or reference pixels and unit pixels), a scan driver 20, a data driver 30, a light emission control driver 40, and a controller 50. The display unit 10 includes pixels PX (or reference pixels and unit pixels).

[0023] The display device 1 (or the display unit 10) may include scan lines SL11 to SL1n and SL21 to SL2n (n is an integer of 2 or more), data lines DL1 to DLm (m is an integer of 2 or more), and light emission control lines EL1 to ELn. Pixels PX may be arranged in intersections of the scan lines SL11 to SL1n and SL21 to SL2n, the data lines DL1 to DLm, and the light emission control lines EL1 to ELn. The pixel PX may be a display unit of a minimum unit for displaying an image or color. The pixel PX will be referred to below. Figure 2 Give a description.

[0024] The scan lines SL11 to SL1n and SL21 to SL2n may extend substantially in a row direction (or a first direction between the left and right sides). The light emission control lines EL1 to ELn may extend substantially in a row direction. The data lines DL1 to DLm may extend substantially in a column direction (or a second direction between the upper side and the lower side). The row direction and the column direction may be switched to each other.

[0025] The display device 1 may include an initialization voltage wiring (or an initialization voltage supply line), a first power supply voltage wiring (or a first power supply voltage supply line), and a second power supply voltage wiring (or a second power supply voltage supply line).

[0026] The initialization voltage wiring may supply the initialization voltage VINT, and may be branched for each row and extend in the row direction. The first power supply voltage wiring is a wiring that supplies the first power supply voltage ELVDD, and may be branched for each column and extend in the column direction. The second power supply voltage wiring is a wiring that supplies a second power supply voltage ELVSS different from the first power supply voltage ELVDD, and may be arranged in a grid form. In another example embodiment, the extension direction of the initialization voltage wiring and the extension direction of the first power supply voltage wiring may be modified differently.

[0027] The pixel PX may be connected to two scan lines, one data line, one light emission control line, one initialization voltage wiring, and one first power supply voltage wiring. For example, a pixel PX (hereinafter referred to as the 11th pixel) located at the first row (or the first pixel row) and the first column (or the first pixel column) may be connected to the 11th scan line SL11 and the 21st scan line SL21, the first data line DL1, the first light emission control line EL1, one initialization voltage wiring, and one first power supply voltage wiring.

[0028] The scan driver 20 may generate a first scan signal and a second scan signal, and may provide the first scan signal and the second scan signal to the pixel PX through the scan lines SL11 to SL1n and SL21 to SL2n. The first scan signal and the second scan signal will be referred to below. Figure 2 Give a description.

[0029] The data driver 30 may provide data signals to the pixels PX through the data lines DL1 to DLm. For example, when the first scan signal is provided to the pixel PX of the first row and the first column (eg, the 11th pixel), the data signal may be provided to the 11th pixel.

[0030] The light emission control driver 40 generates a light emission control signal and transmits the light emission control signal to the pixel PX through the light emission control lines EL1 to ELn. The light emission control driver 40 (or the display device 1) controls the light emission time of the pixel PX based on the light emission control signal. Although the light emission control driver 40 is shown in the figure as being implemented separately from the scan driver 20, the light emission control driver 40 may be included in the scan driver 20 and integrated with the scan driver 20. As another example, the light emission control driver 40 may be omitted depending on the circuit configuration of the pixel PX.

[0031] The controller 50 may convert video signals R, G, and B transmitted from the outside (or an external device such as an application processor) into video data signals DR, DG, and DB, and may transmit the video data signals DR, DG, and DB to the data driver 30. The controller 50 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, may generate control signals for controlling the operation (or driving) of the scan driver 20, the data driver 30, and the light emission control driver 40, and may provide the control signals to the scan driver 20, the data driver 30, and the light emission control driver 40, respectively. The control signals may include a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and a light emission drive control signal ECS for controlling the light emission control driver 40.

[0032] The display device 1 may include a power supply unit. The power supply unit may generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT, and may provide the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage VINT to the pixel PX through a first power supply voltage wiring, a second power supply voltage wiring, and an initialization voltage wiring, respectively. The first power supply voltage ELVDD may be a predetermined high level voltage, the second power supply voltage ELVSS may be a predetermined low level voltage, and the voltage level of the second power supply voltage ELVSS may be lower than the voltage level of the first power supply voltage ELVDD. The power supply unit may be implemented as an external voltage source.

[0033] In response to the data signals transmitted through the data lines DL1 to DLm, the pixels PX may emit light of predetermined brightness based on the driving current supplied to the organic light emitting elements.

[0034] Figure 2 Is the display included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0035] Reference Figure 2 , the pixel PX includes a light emitting element (or an organic light emitting diode OLED) EL, a first transistor T1 to a seventh transistor T7, and a capacitor Cst. The pixel PX may be provided with a data signal DATA, a first scan signal GW, and a second scan signal GI. The second scan signal GI may be the same as the previous first scan signal GW or the first scan signal GW of the previous row. For example, the second scan signal GI[n] provided to the pixel PX of the nth row may be the same as the first scan signal GW[n-1] provided to the pixel PX of the (n-1)th row.

[0036] Each of the first to seventh transistors T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other of them may be a drain electrode.

[0037] Each of the first to seventh transistors T1 to T7 may be a thin film transistor. Each of the first to seventh transistors T1 to T7 may be any one of a PMOS transistor and an NMOS transistor. Hereinafter, it is assumed that the first to seventh transistors T1 to T7 are PMOS transistors.

[0038] The light emitting element EL may include a pixel electrode and a cathode electrode. The pixel electrode of the light emitting element EL may be connected to the fourth node N4, and the cathode electrode thereof may be connected to the second power supply voltage wiring (ie, wiring for transmitting the second power supply voltage ELVSS).

[0039] The first transistor T1 (or driving transistor) may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor T1 may provide a driving current Id to the light emitting element EL based on a voltage of the third node N3 (or a data voltage stored in the capacitor Cst to be described below).

[0040] The second transistor T2 (or the switching transistor) may include a first electrode connected to the data line (or receiving the data signal DATA), a second electrode connected to the first node N1, and a first electrode connected to the first scan line (eg, Figure 1 The second transistor T2 may be turned on in response to the first scan signal GW and may transmit the data signal DATA to the first node N1.

[0041] The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first scan line or receiving the first scan signal GW. The third transistor T3 may be turned on in response to the first scan signal GW and may transmit the data signal DATA to the third node N3.

[0042] The capacitor Cst may be connected or formed between the third node N3 and the first power source voltage ELVDD. The capacitor Cst may store or hold the supplied data signal DATA.

[0043] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the initialization voltage wiring or receiving the initialization voltage VINT, and a second electrode connected to the second scan line (eg, Figure 1 The 21st scan line SL21 shown in FIG. 8 or the gate electrode receiving the second scan signal GI.

[0044] Before the data signal DATA is stored in the capacitor Cst (or after the light emitting element EL emits light), the fourth transistor T4 may be turned on in response to the second scan signal GI and may initialize the third node N3 (or the capacitor Cst) using the initialization voltage VINT.

[0045] In an embodiment, the third transistor T3 and the fourth transistor T4 may be implemented as a double transistor (ie, a transistor component in the form of a combination of two transistors). In this case, leakage current of the third transistor T3 and the fourth transistor T4 and degradation of display quality caused by the leakage current may be prevented or mitigated.

[0046] The fifth transistor T5 and the sixth transistor T6 (or the first and second light emission control transistors) may be connected between the first power supply voltage wiring and the light emitting element EL, and may form a current path through which the drive current Id generated by the first transistor T1 moves.

[0047] The fifth transistor T5 may include a first electrode connected to the first power voltage wiring to receive the first power voltage ELVDD, a second electrode connected to the first node N1, and a second electrode connected to the light emitting control signal line (eg, Figure 1 ) or a gate electrode receiving a light emitting control signal EM.

[0048] Similarly, the sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4 (or the pixel electrode of the light emitting element EL), and a second electrode connected to the light emitting control signal line (eg, Figure 1 ) or a gate electrode receiving a light emitting control signal EM.

[0049] The fifth transistor T5 and the sixth transistor T6 may be turned on in response to the light emission control signal EM. In this case, the driving current Id may be supplied to the light emitting element EL, and the light emitting element EL may emit light having brightness corresponding to the driving current Id.

[0050] The seventh transistor T7 may include a first electrode connected to the fourth node N4, a second electrode connected to the initialization voltage wiring (or the initialization voltage VINT), and a second electrode connected to the second scan signal line (eg, Figure 1 The 21st scan line SL21 shown in FIG. 8 or the gate electrode receiving the second scan signal GI.

[0051] Before the light emitting element EL emits light (or after the light emitting element EL emits light), the seventh transistor T7 may be turned on in response to the second scan signal GI, and the pixel electrode of the light emitting element EL may be initialized using the initialization voltage VINT. The light emitting element EL may have a parasitic capacitor between the pixel electrode and the cathode electrode (or the second power supply voltage ELVSS). The parasitic capacitor may be charged when the light emitting element EL emits light to allow the pixel electrode of the light emitting element EL to have a specific voltage. Therefore, the light emitting element may be initialized by the seventh transistor T7.

[0052] Despite Figure 2 , the seventh transistor T7 is shown to receive the second scan signal GI, but the seventh transistor T7 may receive a third scan signal, such as the second scan signal GI[n+1] at the (n+1)th time, instead of the second scan signal GI[n] at the nth time.

[0053] Figure 3 and Figure 4 It is a display Figure 1 A layout diagram of an example of a display device. Figure 5 is along Figure 4 Cross-sectional views taken along lines AA', BB' and CC'. Figure 6 Is the display included in Figure 5 A cross-sectional view of an example of a second conductive layer in a display device.

[0054] In the following example implementation, although some components are similar to Figure 1 and Figure 2 The components mentioned in the drawings are substantially the same, but new reference numerals will be given to facilitate description of the arrangement and coupling relationship between the elements.

[0055] Reference Figures 2 to 6 , the pixel PX may include first to seventh transistors T1 to T7, a storage capacitor Cst, and a light emitting element EL.

[0056] The first to seventh transistors T1 to T7 may include a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. Top gate type transistors (in which a gate electrode is arranged above a semiconductor layer) may be used as the first to seventh transistors T1 to T7.

[0057] The display device 1 (or the display unit 10) may include a substrate 910, a buffer layer 920, a semiconductor layer 100, a first insulating layer 710, a first conductive layer 200, a second insulating layer 720, a second conductive layer 300, a third insulating layer 730, a third conductive layer 400, a fourth insulating layer 740, a fourth conductive layer 500, and a fifth insulating layer 750. The substrate 910, the buffer layer 920, the semiconductor layer 100, the first insulating layer 710, the first conductive layer 200, the second insulating layer 720, the second conductive layer 300, the third insulating layer 730, the third conductive layer 400, the fourth insulating layer 740, the fourth conductive layer 500, and the fifth insulating layer 750 may be sequentially arranged and stacked. The display device 1 may further include a display element layer 800 and an encapsulation layer.

[0058] Each of the above-mentioned layers may be formed of a single film, but may also be formed of a laminated film including a plurality of films. Another layer may be further arranged between the respective layers.

[0059] The substrate 910 supports layers arranged thereon. When the display device 1 is a rear or double-sided emission type, a transparent substrate may be used as the substrate 910. When the display device 1 is a front emission type, a semi-transparent or opaque substrate as well as a transparent substrate may be used as the substrate 910.

[0060] The substrate 910 may be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of polymer resins include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose acetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. The substrate 910 may include a metal material.

[0061] The substrate 910 may be a rigid substrate or a flexible substrate capable of being bent, folded, rolled, etc. An example of a material constituting the flexible substrate 910 is polyimide (PI).

[0062] The buffer layer 920 may be located on the entire surface of the substrate 910. The buffer layer 920 may prevent the diffusion of impurity ions, may prevent the penetration of moisture or external air, and may perform a surface planarization function. The buffer layer 920 may include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of the substrate 910, process conditions, etc., the buffer layer 920 may be omitted.

[0063] The semiconductor layer 100 is an active layer and may form channels of the first to seventh transistors T1 to T7 .

[0064] For each pixel PX, the semiconductor layers 100 may be separated from each other, or, for example, as shown in FIG. Figure 3As shown in , pixels arranged in the second direction D2 (or column direction) may share the semiconductor layer 100 .

[0065] The semiconductor layer 100 may include a horizontal portion extending substantially in the first direction D1, a first vertical portion (or a left vertical portion) and a second vertical portion (or a right vertical portion) extending substantially in the second direction D2, and a bent portion extending in a zigzag form.

[0066] The horizontal portion may connect the middle portion of the first vertical portion with the middle portion of the second vertical portion. Figure 4 As shown in , the horizontal portion may connect the first vertical portion and the second vertical portion at the shortest distance, but may include a left curved portion and a right curved portion. The total length of the horizontal portion may be increased by bending the horizontal portion multiple times. The horizontal portion may be provided with a channel 1111 of the first transistor T1.

[0067] The first vertical portion may be arranged adjacent to the left side of the pixel PX (or a pixel region where one pixel PX is arranged), and the second vertical portion may be arranged adjacent to the right side of the pixel PX. The first vertical portion and the second vertical portion may be spaced apart from each other. The length of the second vertical portion in the column direction may be longer than the length of the first vertical portion in the column direction.

[0068] The channel 1211 of the second transistor T2 may be arranged in the upper portion of the first vertical portion, and the channel 1511 of the fifth transistor T5 may be arranged in the lower portion of the second vertical portion. The channel 1321 of the 32nd transistor T3_2 may be arranged in the upper portion of the second vertical portion, and the channel 1611 of the sixth transistor T6 and the channel 1711 of the seventh transistor T7 may be arranged in the lower portion of the second vertical portion.

[0069] The bent portion may include a first sub-bend portion extending from the upper end of the first vertical portion to the left side thereof, a second sub-bend portion bent and extending to the upper side of the first vertical portion, and a third sub-bend portion bent and extending to the left and upper side of the first vertical portion, and may be connected to the second vertical portion (or the second vertical portion positioned in the previous pixel region). The first sub-bend portion may be provided with a channel 1311 of the 31st transistor T3_1, the second sub-bend portion may be provided with a channel 1411 of the 41st transistor T4_1, and the third sub-bend portion may be provided with a channel 1421 of the 42nd transistor T4_2. The 31st transistor T3_1 and the 32nd transistor T3_2 may be included in the third transistor T3, and the 41st transistor T4_1 and the 42nd transistor T4_2 may be included in the fourth transistor T4.

[0070] The semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization methods include rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), sequential lateral solidification (SLS), etc. In an embodiment, the semiconductor layer 100 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, etc.

[0071] In the semiconductor layer 100, a region (eg, an electrode region or a source / drain region) connected to a source / drain electrode of each of the first to seventh transistors T1 to T7 may be doped with impurity ions. A trivalent dopant such as boron (B) may be used as the p-type impurity ions.

[0072] The first insulating layer 710 may be located on the semiconductor layer 100, and may be disposed substantially over the entire surface of the substrate 910. The first insulating layer 710 may be a gate insulating film having a gate insulating function.

[0073] The first insulating layer 710 may include a silicon compound or a metal oxide. For example, the first insulating layer 710 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. These compounds may be used alone or in combination of two or more. The first insulating layer 710 may be a single film or a multilayer film formed by stacked films of different materials. For example, the first insulating layer 710 may include silicon nitride (SiN x ) and silicon dioxide (SiO 2 ) and can use silane gas (SiH 4 ) is formed by chemical vapor deposition (CVD).

[0074] The first conductive layer 200 is located on the first insulating layer 710. The first conductive layer 200 may include a first scan line 210, a second scan line 220, a light emitting control line 230, and a first gate electrode 240.

[0075] The first scan line 210 may transmit the second scan signal GI. The first scan line 210 may extend along the second direction D2, and may extend to an adjacent pixel beyond a boundary of the pixel PX.

[0076] In a plan view, the first scan line 210 may be positioned above the pixel PX. The first scan line 210 may overlap with a curved portion of the semiconductor layer 100. The gate electrode of the 41st transistor T4_1 may be formed in a 41st overlapping region where the first scan line 210 overlaps with the second sub-bending portion of the semiconductor layer 100, and the gate electrode of the 42nd transistor T4_2 may be formed in a 42nd overlapping region where the first scan line 210 overlaps with the third sub-bending portion of the semiconductor layer 100. A portion 1412 of the semiconductor layer 100 positioned below the 41st overlapping region may be formed as a first electrode region (or a region where the first electrode is formed) of the 41st transistor T4_1, and a portion 1413 of the semiconductor layer 100 positioned above the 41st overlapping region may be formed as a second electrode region of the 41st transistor T4_1. Similarly, a portion 1422 of the semiconductor layer 100 positioned above the 42nd overlapping region may be formed as a first electrode region of the 42nd transistor T4_2, and a portion 1423 of the semiconductor layer 100 positioned below the 42nd overlapping region may be formed as a second electrode region of the 42nd transistor T4_2.

[0077] The first scan line 210 may overlap with the lower side of the second vertical portion of the semiconductor layer 100. The gate electrode of the seventh transistor T7 may be formed in a seventh overlapping region where the first scan line 210 overlaps with the second vertical portion of the semiconductor layer 100. A portion 1712 of the semiconductor layer 100 positioned below the seventh overlapping region may be formed as a first electrode region of the seventh transistor T7, and a portion 1713 of the semiconductor layer 100 positioned above the seventh overlapping region may be formed as a second electrode region of the seventh transistor T7.

[0078] The second scan line 220 may transmit the first scan signal GW. The second scan line 220 may extend along the second direction D2, and may extend to an adjacent pixel beyond a boundary of the pixel PX.

[0079] In a plan view, the second scan line 220 may be positioned in the middle of the pixel PX. The second scan line 220 may overlap the upper side of the first vertical portion of the semiconductor layer 100, the first sub-bending portion, and the upper side of the second vertical portion. Figure 4 As shown in FIG. 2 , the second scan line 220 may include a protrusion protruding in the first direction D1 , and the protrusion may overlap the first sub-bending portion of the semiconductor layer 100 .

[0080] The gate electrode of the second transistor T2 may be formed in a second overlapping region where the second scan line 220 overlaps the first vertical portion of the semiconductor layer 100. A portion 1212 of the semiconductor layer 100 positioned above the second overlapping region may be formed as a first electrode region of the second transistor T2, and a portion 1213 of the semiconductor layer 100 positioned below the second overlapping region may be formed as a second electrode region of the second transistor T2.

[0081] The gate electrode of the 31st transistor T3_1 may be formed in the 31st overlapping region where the second scan line 220 overlaps the first sub-bending portion of the semiconductor layer 100. A portion 1312 of the semiconductor layer 100 positioned on the left side of the 31st overlapping region may be formed as a first electrode region of the 31st transistor T3_1, and a portion 1313 of the semiconductor layer 100 positioned on the right side of the 31st overlapping region may be formed as a second electrode region of the 31st transistor T3_1.

[0082] The gate electrode of the 32nd transistor T3_2 may be formed in a 32nd overlapping region where the second scan line 220 overlaps the first vertical portion of the semiconductor layer 100. A portion 1322 of the semiconductor layer 100 positioned above the 32nd overlapping region may be formed as a first electrode region of the 32nd transistor T3_2, and a portion 1323 of the semiconductor layer 100 positioned below the 32nd overlapping region may be formed as a second electrode region of the 32nd transistor T3_2.

[0083] The light emitting control line 230 may transmit the light emitting control signal EM. The light emitting control line 230 may extend along the second direction D2, and may extend to an adjacent pixel beyond a boundary of the pixel PX.

[0084] In a plan view, the light emission control line 230 may be positioned below the pixel PX. The light emission control line 230 may overlap a lower side of the first vertical portion and a lower side of the second vertical portion of the semiconductor layer 100.

[0085] The gate electrode of the fifth transistor T5 may be formed in a fifth overlapping region where the light emission control line 230 overlaps the first vertical portion of the semiconductor layer 100. A portion 1512 of the semiconductor layer 100 positioned below the fifth overlapping region may be formed as a first electrode region of the fifth transistor T5, and a portion 1513 of the semiconductor layer 100 positioned above the fifth overlapping region may be formed as a second electrode region of the fifth transistor T5.

[0086] Similarly, the gate electrode of the sixth transistor T6 may be formed in a sixth overlapping region where the light emission control line 230 overlaps the second vertical portion of the semiconductor layer 100. A portion 1612 of the semiconductor layer 100 positioned above the sixth overlapping region may be formed as a first electrode region of the sixth transistor T6, and a portion 1613 of the semiconductor layer 100 positioned below the sixth overlapping region may be formed as a second electrode region of the sixth transistor T6.

[0087] The first gate electrode 240 is a gate electrode of the first transistor T1 and may be positioned at the center of the pixel PX. In a plan view, the first gate electrode 240 may be arranged between the second scan line 220 and the light emission control line 230. The first gate electrode 240 may be separated for each pixel PX and may be arranged in an island shape.

[0088] The first gate electrode 240 may overlap the horizontal portion of the semiconductor layer 100. A portion 1112 of the semiconductor layer 100 positioned on the left side of a first overlapping region where the first gate electrode 240 overlaps the horizontal portion of the semiconductor layer 100 may be formed as a first electrode region of the first transistor T1, and a portion 1113 of the semiconductor layer 100 positioned on the right side of the first overlapping region may be formed as a second electrode region of the first transistor T1.

[0089] The first conductive layer 200 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 200 may be a single-layer film or a multi-layer film.

[0090] The second insulating layer 720 may be located on the first conductive layer 200, and may be disposed over the entire surface of the substrate 910. The second insulating layer 720 may serve to insulate the first conductive layer 200 from the second conductive layer 300, and may be an interlayer insulating film.

[0091] The second insulating layer 720 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or may include an organic insulating material such as polyacrylate resin, epoxy resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The second insulating layer 720 may be a single-layer film or a multi-layer film formed of stacked films of different materials.

[0092] The second conductive layer 300 is positioned on the second insulating layer 720. The second conductive layer 300 may include an electrode line 310 of the storage capacitor Cst.

[0093] In a plan view, the electrode line 310 of the storage capacitor Cst may cross the center of the pixel PX and may be arranged between the second scan line 220 and the light emission control line 230. The electrode line 310 of the storage capacitor Cst may be arranged to overlap with the first gate electrode 240 with the second insulating layer 720 therebetween. The first gate electrode 240 may become a first electrode of the storage capacitor Cst, an extended region of the electrode line 310 of the storage capacitor Cst overlapping with the first gate electrode 240 may become a second electrode of the storage capacitor Cst, and the second insulating layer 720 interposed therebetween may be a dielectric of the storage capacitor Cst.

[0094] The electrode line 310 of the storage capacitor Cst may extend along the second direction D2 and may extend to an adjacent pixel beyond the boundary of the pixel PX. The width of the electrode line 310 of the storage capacitor Cst in the region overlapping the first gate electrode 240 may be extended. The extension region of the electrode line 310 of the storage capacitor Cst may include an opening overlapping the first conductive pattern 420 to be described below.

[0095] The third insulating layer 730 may be located on the second conductive layer 300 to cover the second conductive layer 300. The third insulating layer 730 may include a silicon compound or a metal oxide. For example, the third insulating layer 730 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide. They may be used alone or in combination. The third insulating layer 730 may be a single-layer film or a multi-layer film formed of stacked films of different materials.

[0096] The third insulating layer 730 may include the first contact hole CNT1, and the first contact hole CNT1 may include 11th to 17th contact holes CNT11 to CNT17. The 11th to 17th contact holes CNT11 to CNT17 will be described together with the third conductive layer 400.

[0097] The third conductive layer 400 is positioned on the second insulating layer 720. The third conductive layer 400 may include an initialization voltage line 410 for transmitting an initialization voltage VINT, a first conductive pattern 420, a second conductive pattern 430, a third conductive pattern 440, and a fourth conductive pattern 450.

[0098] In a plan view, the initialization voltage line 410 may be arranged between the first scan line 210 and the second scan line 220, and may extend along the second direction D2 to an adjacent pixel beyond the boundary of the pixel PX. In a region where the initialization voltage line 410 and the semiconductor layer 100 overlap each other, a 13th contact hole CNT13 penetrating the first insulating layer 710, the second insulating layer 720, and the third insulating layer 730 to expose the semiconductor layer 100 may be formed, and the initialization voltage line 410 may contact the semiconductor layer 100 through the 13th contact hole CNT13.

[0099] The first conductive pattern 420 may be arranged to overlap the first gate electrode 240 and extend in the first direction D1 to overlap the bent portion of the semiconductor layer 100 .

[0100] In a region where the first conductive pattern 420 and the first gate electrode 240 overlap each other, an 11th contact hole CNT11 penetrating the second insulating layer 720 and the third insulating layer 730 to expose the first gate electrode 240 may be formed, and the first conductive pattern 420 may contact the first gate electrode 240 through the 11th contact hole CNT11. Similarly, in a region where the first conductive pattern 420 and the bent portion of the semiconductor layer 100 overlap each other, a 12th contact hole CNT12 penetrating the first insulating layer 710, the second insulating layer 720, and the third insulating layer 730 to expose the semiconductor layer 100 may be formed, and the first conductive pattern 420 may contact the semiconductor layer 100 through the 12th contact hole CNT12. Therefore, the first conductive pattern 420 may electrically connect the gate electrode of the first transistor T1 (and the first electrode of the storage capacitor Cst) to the first electrode of the first transistor T1.

[0101] The 11th contact hole CNT11 may be formed on the opening of the electrode line 310 of the storage capacitor Cst. In the 11th contact hole CNT11, the first conductive pattern 420 and the storage capacitor Cst adjacent thereto may be insulated from each other by the third insulating layer 730.

[0102] The second conductive pattern 430 may be arranged to an upper end of the first vertical portion of the semiconductor layer 100. The second conductive pattern 430 may be arranged to overlap with a data line 510 to be described below.

[0103] In a region where the second conductive pattern 430 overlaps the upper end of the first vertical portion of the semiconductor layer 100, a 14th contact hole CNT14 penetrating the first insulating layer 710, the second insulating layer 720, and the third insulating layer 730 to expose the semiconductor layer 100 may be formed, and the second conductive pattern 430 may contact the semiconductor layer 100 through the 14th contact hole CNT14. The second conductive pattern 430 may be electrically connected to the data line 510 through a 21st contact hole CNT21 to be described below, and the 14th contact hole CNT14 may not overlap with the 21st contact hole CNT21.

[0104] The third conductive pattern 440 may overlap the electrode line 310 of the storage capacitor Cst, and may overlap the lower end of the first vertical portion of the semiconductor layer 100. The third conductive pattern 440 may be arranged to overlap the power supply voltage wiring 520 to be described below.

[0105] In the area where the third conductive pattern 440 overlaps with the electrode line 310 of the storage capacitor Cst, a 15th contact hole CNT15 penetrating the third insulating layer 730 to expose the electrode line 310 of the storage capacitor Cst may be formed, and the third conductive pattern 440 may contact the electrode line 310 of the storage capacitor Cst through the 15th contact hole CNT15.

[0106] In the region where the third conductive pattern 440 overlaps with the lower end of the first vertical portion of the semiconductor layer 100, a 16th contact hole CNT16 penetrating the first insulating layer 710, the second insulating layer 720, and the third insulating layer 730 to expose the semiconductor layer 100 may be formed, and the third conductive pattern 440 may contact the lower end of the first vertical portion of the semiconductor layer 100 through the 16th contact hole CNT16. The third conductive pattern 440 may be electrically connected to the power supply voltage wiring 520 through the 22nd contact hole CNT22 to be described below. Therefore, the third conductive pattern 440 may electrically connect the electrode line 310 of the storage capacitor Cst and the first electrode of the fifth transistor T5 to the power supply voltage wiring 520.

[0107] The fourth conductive pattern 450 may overlap a lower side of the second vertical portion of the semiconductor layer 100. The fourth conductive pattern 450 may be arranged to overlap a through electrode 530 to be described below.

[0108] In the region where the fourth conductive pattern 450 overlaps with the lower side of the second vertical portion of the semiconductor layer 100, a 17th contact hole CNT17 penetrating the first insulating layer 710, the second insulating layer 720, and the third insulating layer 730 to expose the semiconductor layer 100 may be formed, and the fourth conductive pattern 450 may contact the lower side of the second vertical portion of the semiconductor layer 100 through the 17th contact hole CNT17. The fourth conductive pattern 450 may be electrically connected to the through electrode 530 through the 23rd contact hole CNT23 to be described below. Therefore, the fourth conductive pattern 450 may electrically connect the second electrode of the sixth transistor T6 (and the second electrode of the seventh transistor T7) to the first electrode of the light emitting element EL.

[0109] The third conductive layer 400 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 400 may be a single-layer film or a multi-layer film. For example, the third conductive layer 400 may be formed to have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0110] In example embodiments, the third conductive layer 400 may include a hydrogen barrier material (or hydrogen diffusion preventing material) or a hydrogen barrier layer (or hydrogen diffusion preventing layer). A hydrogen barrier material refers to a material that is resistant to hydrogen (or hydrogen ions (H + )) is a material having a barrier property, and examples thereof include titanium (Ti), tin (Sn), nickel (Ni), and indium oxides such as indium zinc oxide (IZO) and indium tin oxide (ITO). The hydrogen barrier layer refers to a layer through which hydrogen cannot pass or diffuse, and may be a layer including a hydrogen barrier material such as titanium (Ti).

[0111] In example embodiments, the third conductive layer 400 may include an alloy of titanium (Ti) and any one of aluminum (Al) and molybdenum (Mo).

[0112] Reference Figure 6 , the third conductive layer 400 may include a metal conductive layer 401 and a hydrogen barrier layer 402 .

[0113] The metal conductive layer 401 can be directly arranged on Figure 5 On the third insulating layer 730 shown in FIG. 4 , the hydrogen barrier layer 402 may be directly disposed on the metal conductive layer 401 . Therefore, the hydrogen barrier layer 402 may cover (or cap) the metal conductive layer 401 .

[0114] The metal conductive layer 401 may include the above metal (for example, molybdenum (Mo) or aluminum (Al)), the hydrogen barrier layer 402 may include titanium (Ti), and the metal conductive layer 401 may have a stacked structure of, for example, Mo / Ti. Considering signal transmission, the metal conductive layer 401 may have or greater, and the hydrogen barrier layer 402 may have a thickness of or less thickness.

[0115] Despite Figure 6 4 shows that the hydrogen barrier layer 402 is located on the metal conductive layer 401, but the hydrogen barrier layer 402 may be arranged below the metal conductive layer 401 (between the metal conductive layer 401 and the third insulating layer 730). As another example, the third conductive layer 400 may have a stacked structure of Ti / Al / Ti.

[0116] Refer again Figures 3 to 5 , the fourth insulating layer 740 may be located on the third conductive layer 400, and may be arranged over the entire surface of the substrate 910. The fourth insulating layer 740 may insulate the third conductive layer 400 from the fourth conductive layer 500. The fourth insulating layer 740 may include the same material as the third insulating layer 730, or may include at least one material selected from the materials exemplified as the constituent material of the third insulating layer 730. The fourth insulating layer 740 may be a single-layer film or a multi-layer film formed of stacked films of different materials.

[0117] The fourth insulating layer 740 may include the second contact hole CNT2, and the second contact hole CNT2 may include 21st to 23rd contact holes CNT21 to CNT23. The 21st to 23rd contact holes CNT21 to CNT23 will be described together with the fourth conductive layer 500.

[0118] The fourth conductive layer 500 is located on the fourth insulating layer 740. The fourth conductive layer 500 may include a data line 510, a power supply voltage wiring 520, and a through electrode 530.

[0119] In an embodiment, the fourth conductive layer 500 may include a hydrogen barrier material or a hydrogen barrier layer, similar to the third conductive layer 400. In this case, the possibility of hydrogen diffusion through the fourth conductive layer 500 and the second contact hole CNT2 may be further reduced.

[0120] The data line 510 may be located on the left side of the pixel PX, may extend in the first direction D1, and may extend to an adjacent pixel beyond a boundary of the pixel PX.

[0121] The data line 510 may overlap the first vertical portion of the semiconductor layer 100 , and may overlap the second and third conductive patterns 430 and 440 .

[0122] In a region where the data line 510 overlaps the second conductive pattern 430 , a 21st contact hole CNT21 penetrating the fourth insulating layer 740 to expose the second conductive pattern 430 may be formed, and the data line 510 may be connected to the second conductive pattern 430 through the 21st contact hole CNT21 .

[0123] In an embodiment, the 21st contact hole CNT21 may be arranged to be spaced apart from the 14th contact hole CNT14 by a reference distance without overlapping the 14th contact hole CNT14. The reference distance may be a distance that limits the diffusion of hydrogen through the third conductive layer 400. The reference distance may be equal to or greater than a distance (or spacing) between wirings (e.g., between the data line 510 and the power supply voltage wiring 520). For example, the reference distance may be 2 μm to 6 μm or 3 μm to 4 μm.

[0124] like Figure 3 and Figure 4 As shown in , the 21st contact hole CNT21 may be arranged below the 14th contact hole CNT14.

[0125] The power supply voltage wiring 520 may be arranged at the center of the pixel PX, may extend along the first direction D1, and may extend to an adjacent pixel beyond the boundary of the pixel PX. The power supply voltage wiring 520 may overlap with the third transistor T3 (or the 31st transistor T3_1 and the 32nd transistor T3_2), and the width of the power supply voltage wiring 520 may be relatively widened in the corresponding overlapping area.

[0126] The power supply voltage wiring 520 may overlap the second sub-bending portion of the semiconductor layer 100. In the region where the power supply voltage wiring 520 overlaps the second sub-bending portion of the semiconductor layer 100, a 22nd contact hole CNT22 penetrating the fourth insulating layer 740 to expose the third conductive pattern 440 may be formed, and the power supply voltage wiring 520 may be connected to the third conductive pattern 440 through the 22nd contact hole CNT22.

[0127] In an embodiment, the 22nd contact hole CNT22 may be arranged to be spaced apart from the 15th and 16th contact holes CNT15 and CNT16 by a reference distance without overlapping the 15th and 16th contact holes CNT15 and CNT16.

[0128] Despite Figure 3 and Figure 4 22nd contact hole CNT22 is shown to be positioned relatively adjacent to the 16th contact hole CNT16, but the 22nd contact hole CNT22 may be spaced apart from the 15th contact hole CNT15 and the 16th contact hole CNT16 by the same distance. As another example, the 22nd contact hole CNT22 may be positioned relatively adjacent to the 15th contact hole CNT15 (e.g., adjacent to the first transistor T1).

[0129] The through electrode 530 may overlap the fourth conductive pattern 450. In a region where the through electrode 530 overlaps the fourth conductive pattern 450, a 23rd contact hole CNT23 penetrating the fourth insulating layer 740 to expose the fourth conductive pattern 450 may be formed, and the through electrode 530 may be connected to the fourth conductive pattern 450 through the 23rd contact hole CNT23.

[0130] In an embodiment, the 23rd contact hole CNT23 may be arranged to be spaced apart from the 17th contact hole CNT17 by a reference distance without overlapping the 17th contact hole CNT17 .

[0131] The fourth conductive layer 500 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 500 may be a single-layer film or a multi-layer film. For example, the fourth conductive layer 500 may be formed to have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0132] The fifth insulating layer 750 (or protective film) may be located on the fourth conductive layer 500 and may be arranged over the entire surface of the substrate 910. The fifth insulating layer 750 may insulate the fourth conductive layer 500 from the light emitting element EL. The fifth insulating layer 750 may include an organic insulating material such as polyacrylic resin or polyimide resin. The upper surface of the fifth insulating layer 750 may be substantially flat.

[0133] The display element layer 800 may be located on the fifth insulating layer 750. The display element layer 800 may include a first electrode layer 810, a pixel defining layer PDL, a light emitting layer 820, and a second electrode layer 830.

[0134] The first electrode layer 810 may be located on the fifth insulating layer 750 and may include a pixel electrode (or an anode electrode) of the light emitting element EL. The pixel electrode may overlap with the through electrode 530.

[0135] The pixel electrodes may be arranged in a pentile matrix structure, for example. For example, the pixel electrode 810a of the red pixel R and the pixel electrode 810c of the blue pixel B may be arranged alternately in the second direction D2, the pixel electrode 810a of the red pixel R and the pixel electrode 810b of the green pixel G may be arranged alternately in one diagonal direction, and the pixel electrode 810c of the blue pixel B and the pixel electrode 810b of the green pixel G may be arranged alternately in another diagonal direction. In other implementations, the arrangement structures of the pixel electrodes 810a, 810b, and 810c may be changed differently.

[0136] In a region where the pixel electrode overlaps the through electrode 530 , a through hole CNT3 penetrating the fifth insulating layer 750 to expose the through electrode 530 may be formed, and the pixel electrode may be connected to the through electrode 530 through the through hole CNT3 .

[0137] The pixel electrode may be arranged to overlap the third transistor T3 and the fourth transistor T4. In this case, the pixel electrode may block the inflow of external light from above the third transistor T3 and the fourth transistor T4.

[0138] The pixel defining layer PDL may be arranged along an edge of the pixel electrode. The pixel defining layer PDL may include an opening exposing the pixel electrode in a region overlapping the pixel electrode.

[0139] The light emitting layer 820 may be located on the first electrode layer 810. The light emitting layer 820 may be positioned in the opening of the pixel defining layer PDL. The light emitting layer 820 may include an organic light emitting material or an inorganic light emitting material.

[0140] The second electrode layer 830 may be located on the light emitting layer 820. The second electrode layer 830 is a common electrode, and the common electrode may be formed on the pixel defining layer PDL to extend over a plurality of pixels.

[0141] The cathode electrode of the first electrode layer 810, the light emitting layer 820, and the common electrode of the second electrode layer 830 may constitute the light emitting element EL.

[0142] The encapsulation layer (or thin film encapsulation layer) may be located on the display element layer 800. The encapsulation layer may prevent moisture and air introduced from the outside from penetrating into the light emitting element EL. The encapsulation layer may be a thin film encapsulation layer, and may include at least one organic film and at least one inorganic film. For example, the organic film may include any one selected from epoxy resin, acrylate, and urethane acrylate, and the inorganic film may include any one selected from silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON x ) at least one of.

[0143] As reference Figures 3 to 6 As described above, the display device 1 (or the display unit 10) includes a third conductive layer 400 containing a hydrogen barrier material or capping the metal conductive layer 401 with a hydrogen barrier layer 402, which can help prevent hydrogen from diffusing into the semiconductor layer 100 through the first contact hole CNT1 (for example, the 13th contact hole CNT13 or the 17th contact hole CNT17) when forming the fourth insulating layer 740, and can reduce changes in the electrical characteristics of the transistors T1 to T7 including the semiconductor layer 100.

[0144] In an example embodiment of the display device 1, the second contact hole CNT2 (e.g., the 23rd contact hole CNT23) is spaced apart from the first contact hole CNT1 (e.g., the 17th contact hole CNT17). Therefore, the first conductive pattern 420, the second conductive pattern 430, and the third conductive pattern 440 may be configured in the form of a bridge. This structure may remove a hydrogen diffusion path of the semiconductor layer 100 and help reduce variations in electrical characteristics of the transistors T1 to T7.

[0145] Figure 7 and Figure 8 is used to explain the Figure 5 Cross-sectional view of hydrogenation and dehydrogenation of a semiconductor layer in a display device. Figure 7 and Figure 8 is with Figure 5 The corresponding cross-sectional view of the display device 1 .

[0146] First, refer to Figure 7 , the semiconductor layer 100 , the first insulating layer 710 , the first conductive layer 200 , the second insulating layer 720 , the second conductive layer 300 , and the third insulating layer 730 may be sequentially stacked.

[0147] As described above, the first insulating layer 710 may include silicon nitride (SiN x) and silicon dioxide (SiO 2 ) and can use silane gas (SiH 4 ) is formed by chemical vapor deposition (CVD). In this case, the semiconductor layer 100 including a silicon semiconductor may be hydrogenated by a chemical reaction using a silane gas.

[0148] Then, the 13th contact hole CNT13 and the 17th contact hole CNT17 (as well as the 12th contact hole CNT12, the 14th contact hole CNT14 and the 16th contact hole CNT16) can be formed to penetrate the first insulating layer 710 to the third insulating layer 730 to expose the semiconductor layer 100, and the 11th contact hole CNT11 can be formed to penetrate the second insulating layer 720 and the third insulating layer 730 to expose the first conductive layer 200.

[0149] After forming the 11th contact hole CNT11, the 13th contact hole CNT13, and the 17th contact hole CNT17, an annealing process may be performed, and the semiconductor layer 100 may be dehydrogenated during the annealing process. Figure 7 As shown in , most of the reduced hydrogen can flow out through the 13th contact hole CNT13 and the 17th contact hole CNT17, and a portion of the reduced hydrogen can flow out through the first conductive layer 200 (eg, the first scan line 210, the first gate electrode 240, and the 11th contact hole CNT11).

[0150] When the conditions of the annealing process are controlled, the degree of hydrogenation of the semiconductor layer 100 may be controlled, and if necessary, the electrical characteristics (eg, driving range) of the transistors T1 to T7 may be controlled.

[0151] After the annealing process, the third conductive layer 400 may be formed on the third insulating layer 730, and the fourth insulating layer 740 may be formed on the third conductive layer 400. Similar to the first insulating layer 710, the fourth insulating layer 740 may include silicon nitride (SiN x ) and silicon dioxide (SiO 2 ), and can be formed by chemical vapor deposition (CVD) technology using silane gas. In this case, the hydrogen component in the silane gas can diffuse into the semiconductor layer 100 through the 13th contact hole CNT13 and the 17th contact hole CNT17 (or through the third conductive layer 400), and thus the semiconductor layer 100 can be hydrogenated again.

[0152] Then, a reference can be formed Figure 5The second contact holes CNT2 (i.e., the 21st to 23rd contact holes CNT21 to CNT23) are described, and an annealing process may be performed, thereby performing dehydrogenation of the semiconductor layer 100. However, depending on the positions of the second contact holes CNT2 and the number of the second contact holes CNT2, dehydrogenation of the entire semiconductor layer 100 may be difficult, and it may be difficult to uniformly control the degree of hydrogenation of the transistors T1 to T7.

[0153] Therefore, in the display device 1, the third conductive layer 400 (i.e., the third conductive layer 400 formed before forming the fourth insulating layer 740) may include a hydrogen barrier material, or the metal conductive layer 401 of the third conductive layer 400 may be capped with the hydrogen barrier layer 402. Therefore, re-hydrogenation of the semiconductor layer 100 may be prevented, and the degree of hydrogenation of the semiconductor layer 100 may be controlled only by an annealing process when forming the first contact hole CNT1.

[0154] In Table 1, the driving range (DR) of the transistors (i.e., transistors T1 to T7) with respect to the materials (and stacked structures) included in the third conductive layer 400 is shown. "Before deposition" refers to the transistor (or semiconductor layer 100) before the fourth insulating layer 740 is formed, and "after deposition" refers to the transistor after the fourth insulating layer 740 is formed.

[0155] [Table 1]

[0156]

[0157] Referring to Table 1, when the third conductive layer 400 has a single-layer structure of molybdenum (Mo), the driving range of the transistor is about 3.4V before the fourth insulating layer 740 is formed, but after the fourth insulating layer 740 is formed, the driving range of the transistor is significantly changed to about 2.65V by re-hydrogenation of the semiconductor layer 100.

[0158] When the third conductive layer 400 has a stacked structure of Ti / Al / Ti or Mo / Ti, the driving range of the transistor is approximately 3.2V to 3.4V before forming the fourth insulating layer 740, and the driving range of the transistor is approximately 3.3V to 3.4V after forming the fourth insulating layer 740, which is almost unchanged.

[0159] Therefore, when the third conductive layer 400 includes a hydrogen barrier material or is capped with the hydrogen barrier layer 402, the electrical characteristics of the transistor may be controlled to a desired level.

[0160] The second contact holes CNT2 (i.e., the 21st contact hole CNT21, the 22nd contact hole CNT22 and the 23rd contact hole CNT23) are spaced apart from the adjacent first contact holes CNT1 (i.e., the 14th contact hole CNT14, the 16th contact hole CNT16 and the 17th contact hole CNT17) by a reference distance so that the hydrogen diffusion path (or hydrogenation / dehydrogenation path) can be more reliably removed, the electrical characteristics of the transistor can be easily controlled, the variation of the electrical characteristics of the transistor can be reduced or the variation of the electrical characteristics of the transistor can be made more uniform, and the display quality of the display device 1 can be improved.

[0161] Fig. 9 It is a display Figure 1 A layout diagram of another example of a display device. Fig.10 It is a display Fig. 9 A cross-sectional view of an example of a display device. Fig.10 is with Figure 5 Corresponding cross-sectional view of display device 1_1.

[0162] Reference Figures 3 to 5 , Fig. 9 and Fig.10 In addition to the third conductive layer 400_1 and the second contact hole CNT2_1, the display device 1_1 can be similar to the reference Figures 3 to 5 The display devices 1 described are substantially the same or similar. Therefore, a redundant description will not be repeated.

[0163] The third conductive layer 400_1 and the reference Figures 3 to 5 The third conductive layer 400 is described differently in that it does not include a hydrogen barrier material and includes a second conductive pattern 430_1 .

[0164] The third conductive layer 400_1 may not include a hydrogen barrier material, and may include a dehydrogenation material (ie, a hydrogen diffusion material). For example, the third conductive layer 400_1 may not include titanium (Ti), and may have a single layer structure of molybdenum (Mo).

[0165] The second conductive pattern 430_1 may overlap with the upper end of the first vertical portion of the semiconductor layer 100 and may not overlap with the second scan line 220. Fig. 9 and Fig.10 The second conductive pattern 430_1 has a smaller Figures 3 to 5 The size of the second conductive pattern 430 is shown in FIG. 4 , but the size may be changed.

[0166] The second contact hole CNT2_1 and the reference Figures 3 to 5 The second contact hole CNT2 described is different in that the second contact hole CNT2_1 includes a 21st contact hole CNT21_1 and a 23rd contact hole CNT23_1.

[0167] The 23rd contact hole CNT23_1 may be arranged to overlap with the 17th contact hole CNT17. Therefore, the 17th contact hole CNT17 and the 23rd contact hole CNT23_1 may constitute a direct contact hole (direct CNT) connecting the fourth conductive layer 500 and the semiconductor layer 100 on a vertical line (or penetrating the first insulating layer 710 to the fourth insulating layer 740 in one vertical line). In this case, even if the semiconductor layer 100 is rehydrogenated when the third insulating layer 730 is formed, dehydrogenation of the semiconductor layer 100 may be performed through the direct contact hole. Therefore, changes in the electrical characteristics of the transistor due to the formation of the third insulating layer 730 may be limited.

[0168] Similarly, the 21st contact hole CNT21_1 may be arranged to overlap the 14th contact hole CNT14. Therefore, the 14th contact hole CNT14 and the 21st contact hole CNT21_1 may constitute a direct contact hole (direct CNT) connecting the fourth conductive layer 500 and the semiconductor layer 100 on a vertical line.

[0169] As reference Fig. 9 and Fig.10 As described above, the display device 1_1 includes a direct contact hole (direct CNT) connecting the fourth conductive layer 500 and the semiconductor layer 100 on a vertical line, which can easily perform dehydrogenation of the semiconductor layer 100 and reduce changes and variations in electrical characteristics (eg, driving range) of the transistor.

[0170] By way of summary and review, an organic light-emitting display device may include a plurality of transistors that provide a driving current to an organic light-emitting element. As the resolution of a display device increases, a pixel area forming a pixel decreases, and thus the number of layers for arranging circuit elements, wiring, etc. in the pixel area may increase. In the pixel area, a signal wiring may be located on the transistor, an insulating layer may be interposed between the signal wirings, and the signal wiring may be connected to the semiconductor layer of the transistor through a contact hole that penetrates the insulating layer. When the insulating layer is formed using a chemical vapor deposition technique, the semiconductor layer of the transistor may be hydrogenated by a deposition gas, but may be dehydrogenated by performing annealing after the formation of the contact hole, and may be hydrogenated again by the stacking of additional insulating layers, and thus the electrical characteristics of the transistor may be changed.

[0171] Embodiments provide a display device that can prevent variations in electrical characteristics of a transistor.

[0172] According to example embodiments, a display device includes a metal conductive layer including a hydrogen barrier material, or includes a metal conductive layer capped with a hydrogen barrier layer, so that hydrogen (or hydrogen ions) can be prevented or mitigated from diffusing into the semiconductor layer through a first contact hole connecting the metal conductive layer to a semiconductor layer positioned therebelow, and changes in electrical characteristics of a transistor including the semiconductor layer can be limited.

[0173] In the display device according to the embodiment, the second contact hole exposing the conductive layer is spaced apart from the first contact hole. Therefore, a hydrogen diffusion path for the semiconductor layer can be removed, and variations in electrical characteristics of a transistor including the semiconductor layer can be reduced.

[0174] Example embodiments have been disclosed herein, and although specific wording is employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as this application is submitted, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Accordingly, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: substrate; a semiconductor layer, wherein the semiconductor layer is located on the substrate; a first insulating layer, wherein the first insulating layer is located on the semiconductor layer; a first conductive layer, wherein the first conductive layer is located on the semiconductor layer; a second insulating layer, the second insulating layer being located on the first conductive layer; a first contact hole, the first contact hole penetrating the first insulating layer and the second insulating layer; a second conductive layer, the second conductive layer being located on the second insulating layer, connected to the semiconductor layer through the first contact hole, and comprising a hydrogen barrier material; a third insulating layer, the third insulating layer being located on the second conductive layer; a second contact hole, the second contact hole penetrating the third insulating layer to expose the second conductive layer, the second contact hole overlapping the first contact hole; as well as a third conductive layer, the third conductive layer being located on the third insulating layer and connected to the second conductive layer through the second contact hole, and The first contact hole is wider than the second contact hole.

2. The display device according to claim 1, wherein: The third insulating layer includes silicon nitride and silicon dioxide, and The second conductive layer includes at least one of titanium, tin, nickel, indium zinc oxide and indium tin oxide.

3. The display device according to claim 1, wherein: The second conductive layer comprises: a metal conductive layer, the metal conductive layer being located on the second insulating layer and connected to the semiconductor layer through the first contact hole; and A hydrogen barrier layer is located on the metal conductive layer and includes the hydrogen barrier material.

4. The display device according to claim 1, wherein: The second conductive layer comprises: a first hydrogen barrier layer, the first hydrogen barrier layer being located on the second insulating layer; a metal conductive layer, the metal conductive layer being located on the first hydrogen barrier layer; and A second hydrogen barrier layer is located on the metal conductive layer.

5. The display device according to claim 1, wherein: The third conductive layer includes the hydrogen barrier material, the first conductive layer includes a gate electrode of a transistor, the second conductive layer includes a first electrode of the transistor, and the first electrode of the transistor is connected to the semiconductor layer through the first contact hole.

6. The display device according to claim 5, wherein: The third conductive layer includes a signal wiring electrically connected to the first electrode of the transistor through the second contact hole.

7. The display device according to claim 6, wherein: The semiconductor layer includes a first portion extending in a first direction, and the signal wiring extends in the first direction and overlaps the first portion of the semiconductor layer.

8. The display device according to claim 5, further comprising: a fourth insulating layer, the fourth insulating layer being located on the third conductive layer; as well as A display element layer, the display element layer is located on the fourth insulating layer and includes a light emitting element, wherein the third conductive layer includes a through electrode electrically connected to the first electrode of the transistor through the second contact hole, and The light emitting element is electrically connected to the through electrode through a third contact hole penetrating the fourth insulating layer to expose the through electrode.

9. The display device according to claim 5, wherein: The third conductive layer further comprises: a second electrode of the capacitor overlapping the first electrode of the capacitor and a conductive pattern connecting the first electrode of the transistor to the second electrode of the capacitor; and A signal wiring is electrically connected to the conductive pattern through the second contact hole.

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