A DC comparator

Abstract

A DC comparator includes: a pair of openable and closable main iron cores, an exciting coil and a secondary feedback coil wound outside the main iron cores, and a signal processing circuit. The signal processing circuit includes a modulation circuit, and a demodulation circuit, a signal amplification circuit and a signal feedback circuit connected in sequence. The main iron cores are coated with a multiferroic material thin film, and the multiferroic material thin film is connected to a zero adjustment circuit. In the present invention, the main iron cores are coated with a multiferroic material thin film, the zero adjustment circuit is connected to the multiferroic material thin film, and by applying a voltage to the piezoelectric layer in the multiferroic material thin film, the magnetic permeability of the ferromagnetic layer (multiferroic material thin film) is changed to suppress the asymmetry of the main iron cores, thereby fundamentally solving the zero point problem caused by the asymmetry and difference of the iron cores and improving the accuracy of the DC comparator.

Description

Technical Field

[0001] The present invention belongs to the technical field of current measurement, and particularly relates to a DC comparator. Background Art

[0002] As a calibration instrument for DC current, a DC comparator needs to have high precision, and the zero point of the DC comparator limits the precision of the small range of the DC comparator to a certain extent. The DC comparator is generally modulated by two or more magnetic cores. Due to the asymmetry and difference between each iron core, a zero point will occur. The asymmetry and difference of the iron core can only be minimized through quality control during the production of the iron core, but it is impossible to completely avoid them. How to solve the difference and asymmetry of the iron core has become the main problem restricting the zero adjustment and precision of the DC comparator.

[0003] Figure 1 For the circuit schematic diagram of the DC comparator, as Figure 1 shown, the currently commonly used method for adjusting the zero point of the DC comparator is to add a zero adjustment circuit at the adjustment point (one or more of points a, b, c, and d) on the negative feedback circuit loop ( Figure 1 the circuit within the center dotted line box) of the DC comparator, and use the zero adjustment circuit to increase the bias current or bias voltage to adjust the DC zero point. However, this adjustment method does not fundamentally solve the zero point problem caused by the difference and asymmetry existing in the iron core itself. Moreover, due to the inconsistent differences of each iron core, the compensation points and compensation methods of each instrument need to be debugged one by one, resulting in high labor and time costs. At the same time, because one or more zero adjustment circuits need to be added, the variables of the system increase, which will affect the stability of the negative feedback under certain conditions. Summary of the Invention

[0004] The purpose of the present invention is to provide a DC comparator that can achieve precise zero adjustment and has high precision.

[0005] In order to achieve the above purpose, the present invention adopts the following technical solution:

[0006] A DC comparator includes: a pair of openable and closable main iron cores, an excitation coil and a secondary feedback coil wound outside the main iron cores, and a signal processing circuit. The signal processing circuit includes a modulation circuit and a demodulation circuit, a signal amplification circuit, and a signal feedback circuit connected in sequence. The main iron core is coated with a multiferroic material thin film, and the multiferroic material thin film is connected to a zero adjustment circuit.

[0007] More specifically, the multiferroic material thin film includes a ferromagnetic layer formed by a magnetic material and a piezoelectric layer formed by a piezoelectric material.

[0008] More specifically, the initial permeability of the magnetic material is greater than 1000 and the magnetostriction coefficient is greater than 10 ppm.

[0009] More specifically, the magnetic material is Ni or Fe or Co or an alloy thereof.

[0010] More specifically, the electrostrictive coefficient of the piezoelectric material is greater than 500 ppm.

[0011] More specifically, the piezoelectric material is PZT or PZN-PT or PMN-PT or AlN or HfO 2 。

[0012] More specifically, the multiferroic material thin film includes: a substrate, a first conductive layer formed on the substrate, a piezoelectric layer and a ferromagnetic layer formed on the first conductive layer, an insulating layer formed on the ferromagnetic layer, and a second conductive layer formed on the insulating layer. Zero-adjusting connection points connected to the zero-adjusting circuit are respectively arranged on the first conductive layer and the second conductive layer.

[0013] More specifically, the modulation circuit includes a current-driven iron core and a first amplifier. A primary coil and a secondary coil are wound around the current-driven iron core; one end of the primary coil is grounded, and the other end is connected to the output end of the first amplifier. The inverting input end of the first amplifier is connected to the output end of the first amplifier through a resistor R1 and is simultaneously grounded through a capacitor C1; the non-inverting input end of the first amplifier is connected to the output end of the first amplifier through a resistor R3 and is simultaneously grounded through a resistor R2; the secondary coil of the current-driven iron core is connected to the exciting coil of the main iron core.

[0014] More specifically, the demodulation circuit is connected to the taps on the secondary coil of the current-driven iron core and the taps on the exciting coil of the main iron core in the DC comparator; the demodulation circuit includes a first diode, a second diode and a potentiometer. The positive electrode of the first diode and the negative electrode of the second diode are connected together and then connected to the tap of the coil. The negative electrode of the first diode is connected to one end of the resistor in the potentiometer through a resistor R4, and a capacitor C2 is connected in parallel with the resistor R4; the positive electrode of the second diode is connected to the other end of the resistor in the potentiometer through a resistor R5, and a capacitor C3 is connected in parallel with the resistor R5; the sliding contact of the potentiometer is connected to the signal amplification circuit and is simultaneously grounded through a capacitor C4.

[0015] More specifically, the signal amplification circuit includes a second amplifier. The non-inverting input end of the second amplifier is connected to the demodulation circuit through a resistor R7, the inverting input end is connected to the output end of the second amplifier through a resistor R9 and is simultaneously grounded through a resistor R8, and the output end of the second amplifier is connected to the signal feedback circuit.

[0016] More specifically, the signal feedback circuit includes a third amplifier, a first triode, a second triode, a third diode, and a fourth diode; the inverting input terminal of the third amplifier is connected to the signal amplification circuit via a resistor R10, and at the same time is connected to the secondary feedback coil of the main iron core via a resistor R12. The non-inverting input terminal of the third amplifier is grounded via a resistor R1. The output terminal is respectively connected to the base of the first triode and the base of the second triode. The collector of the first triode is connected to the power supply VCC terminal, and the emitter is connected to the secondary feedback coil of the main iron core; the collector of the second triode is connected to the power supply VEE terminal, and the emitter is connected to the secondary feedback coil of the main iron core; the cathode of the third diode is connected to the power supply VCC terminal, and the anode is connected to the secondary feedback coil of the main iron core; the anode of the fourth diode is connected to the power supply VEE terminal, and the cathode is connected to the secondary feedback coil of the main iron core.

[0017] As can be seen from the above technical solutions, in the present invention, a multi-ferroic material thin film is coated on the main iron core of the current comparator. Utilizing the characteristics of the multi-ferroic material, the voltage of the zero-adjusting circuit is applied to the multi-ferroic material thin film to reduce the difference and asymmetry of the main iron core by changing the magnetic permeability of the multi-ferroic material thin film, realizing the compensation of the zero point and improving the accuracy of the DC comparator. Moreover, only one zero-adjusting circuit needs to be set on the multi-ferroic material thin film for adjustment, which not only simplifies the steps of the zero-adjusting operation, but also minimizes the system variables as much as possible, ensuring the stability of the signal feedback. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is the circuit schematic diagram of the DC comparator;

[0020] Figure 2 is the circuit diagram of the zero-adjusting circuit in the embodiment of the present invention;

[0021] Figure 3 is the schematic diagram of the magnetoelectric effect of the multi-ferroic material;

[0022] Figures 4a to 4e is the schematic diagram of the preparation process of the multi-ferroic material thin film in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following specifically lists the embodiments of the present invention and, in conjunction with the accompanying drawings, makes a detailed description as follows.

[0024] The DC comparator mainly includes a pair of main iron cores. The main iron cores are composed of a pair of separable magnetic cores. The two magnetic cores are arranged opposite to each other. The magnetic cores can be made of conventional magnetic materials such as silicon steel sheets, permalloys, and nanocrystals. The main iron cores are coated with a layer of multiferroic material thin film. An exciting coil is wound around the main iron cores coated with the multiferroic material thin film. The main iron cores wound with the exciting coil are placed in an insulating secondary shell (not shown), and a secondary feedback coil is wound outside the insulating secondary shell with an enameled wire.

[0025] As Figure 1 shown, an exciting coil P and a secondary feedback coil Q are wound around the main iron core L2 coated with the multiferroic material thin film. One end of the secondary feedback coil Q is connected to a secondary resistor R13, and the other end is connected to a signal processing unit (current feedback circuit C). The other end of the secondary resistor R13 is grounded. The signal processing unit includes a modulation circuit A, a demodulation circuit B, a signal amplification circuit C, and a signal feedback circuit D.

[0026] The modulation circuit A includes a current-driven iron core L1 and a first amplifier U1A. A primary coil M and a secondary coil N are wound around the current-driven iron core L1. One end of the primary coil M is grounded, and the other end is connected to the output terminal of the first amplifier U1A. The inverting input terminal of the first amplifier U1A is connected to the output terminal of the first amplifier U1A through a resistor R1 and is simultaneously grounded through a capacitor C1. The non-inverting input terminal of the first amplifier U1A is connected to the output terminal of the first amplifier U1A through a resistor R3 and is simultaneously grounded through a resistor R2. The primary coil M of the current-driven iron core L1 is the input terminal of the current-driven iron core L1. The square wave self-excited by the first amplifier U1A is input into the current-driven iron core L1. The secondary coil N of the current-driven iron core L1 is connected to the exciting coil P of the main iron core L2 to drive the main iron core L2 and increase the driving current.

[0027] A tap is provided on the secondary coil N of the current-driven iron core L1, and another tap is provided on the exciting coil P of the main iron core L1. The tap of the secondary coil N of the current-driven iron core L1 and the tap of the exciting coil P of the main iron core L1 are connected to the demodulation circuit B. The demodulation circuit B includes a first diode D1, a second diode D2, a resistor R4, a resistor R5, a potentiometer R6, a capacitor C2, a capacitor C3, and a capacitor C4. After the positive electrode of the first diode D1 and the negative electrode of the second diode D2 are connected together, they serve as the input terminal of the demodulation circuit B and are connected to the tap of the coil. The negative electrode of the first diode D1 is connected to one end of the resistor in the potentiometer R6 through a resistor R4, and the capacitor C2 is connected in parallel with the resistor R4. The positive electrode of the second diode D2 is connected to the other end of the resistor in the potentiometer R6 through a resistor R5, and the capacitor C3 is connected in parallel with the resistor R5. The sliding contact of the potentiometer R6 is connected to the signal amplification circuit C, and the sliding contact is simultaneously grounded through a capacitor C4.

[0028] The signal amplification circuit C includes a second amplifier U1B. The non-inverting input terminal of the second amplifier U1B is connected to the demodulation circuit B via a resistor R7. The inverting input terminal is connected to the output terminal of the second amplifier U1B via a resistor R9 and is also grounded via a resistor R8. The output terminal of the second amplifier U1B is connected to the signal feedback circuit D.

[0029] The signal feedback circuit D includes a third amplifier U1C, a first triode Q1, a second triode Q2, a third diode V1, and a fourth diode V2. The inverting input terminal of the third amplifier U1C is connected to the signal amplification circuit C via a resistor R10 and is also connected to the secondary feedback coil Q of the main iron core L1 via a resistor R12. The non-inverting input terminal of the third amplifier U1C is grounded via a resistor R1. The output terminal is connected to the base of the first triode Q1 and the base of the second triode Q2 respectively. The collector of the first triode Q1 is connected to the power supply VCC terminal, and the emitter is connected to the secondary feedback coil Q of the main iron core L1. The collector of the second triode Q2 is connected to the power supply VEE terminal, and the emitter is connected to the secondary feedback coil Q of the main iron core L1. The negative electrode of the third diode V1 is connected to the power supply VCC terminal, and the positive electrode is connected to the secondary feedback coil Q of the main iron core L1. The positive electrode of the fourth diode V2 is connected to the power supply VEE terminal, and the negative electrode is connected to the secondary feedback coil Q of the main iron core L1.

[0030] As Figure 2 shown, the zero-adjusting circuit of this embodiment includes a potentiometer R16 and resistors R14, R15, and R17. One end of the resistor in the potentiometer R16 is connected to the power supply VEE terminal via a resistor R14, and the other end is connected to the power supply VCC terminal via a resistor R15. The sliding contact of the potentiometer R16 is electrically connected to the multiferroic material thin film coated outside the main iron core L2 via a resistor R17. In other embodiments, if higher-precision debugging is required, the zero-adjusting circuit can use a reference chip for debugging. The debugging process of the zero-adjusting circuit is a prior art and will not be elaborated here.

[0031] As Figure 3 shown, the multiferroic material is a material with ferroelectric (P-E) characteristics and magnetoelectric (M-H) characteristics, and there is a magneto-electric cross-regulation effect, that is, the polarization (P) can be regulated by the magnetic field (H), or the magnetization (M) can be regulated by the electric field (E). Under the action of electric polarization, the magnetic domain angle can be changed, that is, by applying a voltage to the multiferroic material, the saturation magnetic field magnitude and permeability of the multiferroic material itself can be changed. The multiferroic material thin film of this embodiment mainly includes a ferromagnetic layer and a piezoelectric layer. The ferromagnetic layer is formed by magnetic materials such as Ni, Fe, Co and their alloys. The initial permeability of the magnetic material is greater than 1000 and the magnetostriction coefficient is greater than 10 ppm. The piezoelectric layer is composed of PZT or PZN-PT or PMN-PT or AlN or HfO 2It is formed of piezoelectric materials, and the electrostrictive coefficient of the piezoelectric materials is greater than 500 ppm. When a voltage is applied to the piezoelectric layer, based on the characteristics of the piezoelectric materials, the piezoelectric layer will deform under the action of the voltage, and this deformation will be further transmitted to the ferromagnetic layer, causing the magnetic permeability of the ferromagnetic layer to change accordingly due to its own deformation (under the action of a large voltage, the magnetic permeability of the ferromagnetic layer will increase), thereby affecting the distribution of the external magnetic field.

[0032] In the present invention, by applying a voltage to the piezoelectric layer in the multiferroic material thin film, the magnetic permeability of the ferromagnetic layer (multiferroic material thin film) is changed to suppress the asymmetry of the main iron core (excitation iron core), thereby fundamentally solving the zero-point problem caused by the asymmetry and difference of the iron core and improving the accuracy of the DC comparator.

[0033] The following further describes the preparation method of the multiferroic material thin film of the present invention with a specific embodiment:

[0034] As Figure 4a shown, a substrate 21 is provided. The surface of the substrate 1 is flat and has good insulation performance. The substrate 1 is pretreated. The pretreatment steps include: ultrasonically cleaning the substrate 21 with acetone, alcohol and deionized water for 5 min, then drying it with N2, and baking it in an oven at 115 °C for 20 min; the substrate in this embodiment is a Si substrate;

[0035] A first predefined pattern is formed on the substrate 21 by photolithography technology, and a first conductive layer 22 corresponding to the shape of the first predefined pattern is deposited on the substrate 1 by magnetron sputtering thin film growth technology. The first conductive layer 22 can be formed of conductive non-magnetic materials such as Cu and Au. The thickness of the first conductive layer 22 is about 10 nm to 50 nm. The first conductive layer 22 is used to form the lower electrode. After removing the photoresist with acetone, the lower electrode is formed on the substrate 21, as Figure 4b shown;

[0036] A second predefined pattern is formed on the first conductive layer 22 by photolithography technology, and a magnetoelectric composite layer 23 composed of a piezoelectric layer and a ferromagnetic layer is deposited on the first conductive layer 22 in sequence with a piezoelectric material and a ferromagnetic material, as Figure 4c shown, that is, a multi-layer structure of substrate - lower electrode - piezoelectric layer - ferromagnetic layer is formed; the thickness of the magnetoelectric composite layer 23 is related to the size of the actual device and can be 500 nm to 5000 nm;

[0037] Remove the photoresist with acetone, and form a third predefined pattern on the magnetoelectric composite layer 23 by photolithography technology;

[0038] As Figure 4dAs shown, an insulating layer 24 is grown on the magnetoelectric composite layer 23. The thickness of the insulating layer 24 is greater than that of the magnetoelectric composite layer 23. Generally, the thickness of the insulating layer 24 can be about 50 nm thicker than that of the magnetoelectric composite layer 23. The insulating layer 24 can be formed of insulating materials such as SiO 2 、Al 2 O 3 and so on;

[0039] The photoresist is removed with acetone, and a fourth predefined pattern is formed on the insulating layer 24 through photolithography technology;

[0040] As Figure 4e shown, a second conductive layer 25 is grown on the insulating layer 24. The second conductive layer is used to form the upper electrode. The material of the second conductive layer 25 is the same as that of the first conductive layer 22; the upper electrode and the lower electrode serve as zero-adjusting connection points, and the zero-adjusting connection points are connected to the zero-adjusting circuit through leads;

[0041] Clean with acetone to remove the photoresist, and a multiferroic material thin film is obtained.

[0042] In the foregoing steps, the method for forming the predefined pattern is as follows: After dropping the photoresist on the substrate, first rotate at a rate of 600 revolutions per minute for 10 s on a spin coater so that the photoresist covers the Si wafer, and then rotate at a rate of 4000 revolutions per minute for 40 s to make the thickness of the photoresist uniform; Place the Si substrate spin-coated with photoresist in an oven and heat it at 115 °C for 20 min to completely cure the photoresist; The photoresist layer is exposed to ultraviolet light through a mask of the predefined pattern; Develop to remove the excess photoresist and leave the predefined pattern on the Si substrate.

[0043] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DC comparator, comprising: a pair of openable and closable main iron cores, an exciting coil and a secondary feedback coil wound outside the main iron cores, and a signal processing circuit, the signal processing circuit comprising a modulation circuit and a demodulation circuit, a signal amplification circuit and a signal feedback circuit connected in sequence; characterized in that: the main iron core is coated with a multiferroic material thin film, and the multiferroic material thin film is connected to a zero adjustment circuit; the multiferroic material thin film comprises a substrate, a first conductive layer formed on the substrate, a piezoelectric layer and a ferromagnetic layer formed on the first conductive layer, an insulating layer formed on the ferromagnetic layer, and a second conductive layer formed on the insulating layer, and zero adjustment connection points connected to the zero adjustment circuit are respectively arranged on the first conductive layer and the second conductive layer; when a voltage is applied to the piezoelectric layer, the piezoelectric layer will deform under the action of the voltage, and the deformation will be further transmitted to the ferromagnetic layer, so that the magnetic permeability of the ferromagnetic layer changes accordingly due to its own deformation, suppressing the asymmetry of the main iron core.

2. The DC comparator according to claim 1, characterized in that: the ferromagnetic layer is formed of a magnetic material, and the initial magnetic permeability of the magnetic material is greater than 1000 and the magnetostrictive coefficient is greater than 10 ppm.

3. The DC comparator according to claim 2, characterized in that: the magnetic material is Ni or Fe or Co or an alloy thereof.

4. The DC comparator according to claim 1, characterized in that: the piezoelectric layer is formed of a piezoelectric material, and the electrostrictive coefficient of the piezoelectric material is greater than 500 ppm.

5. The DC comparator according to claim 4, characterized in that: The piezoelectric material is PZT or PZN-PT or PMN-PT or AlN or HfO 2 .

6. The DC comparator according to claim 1, characterized in that: the modulation circuit comprises a current-driven iron core and a first amplifier, and a primary coil and a secondary coil are wound outside the current-driven iron core; one end of the primary coil is grounded, and the other end is connected to the output end of the first amplifier. The inverting input end of the first amplifier is connected to the output end of the first amplifier through a resistor R1 and is grounded through a capacitor C1 at the same time; the non-inverting input end of the first amplifier is connected to the output end of the first amplifier through a resistor R3 and is grounded through a resistor R2 at the same time; the secondary coil of the current-driven iron core is connected to the exciting coil of the main iron core.

7. The DC comparator according to claim 6, characterized in that: A tap is provided on the secondary side coil, and another tap is provided on the exciting coil. The demodulation circuit is connected to the tap on the secondary side coil and the tap on the exciting coil. The demodulation circuit includes a first diode, a second diode and a potentiometer. The positive electrode of the first diode and the negative electrode of the second diode are connected together and then connected to the tap on the secondary side coil and the tap on the exciting coil. The negative electrode of the first diode is connected to one end of the resistor in the potentiometer through a resistor R4, and a capacitor C2 is connected in parallel with the resistor R4. The positive electrode of the second diode is connected to the other end of the resistor in the potentiometer through a resistor R5, and a capacitor C3 is connected in parallel with the resistor R5. The sliding contact of the potentiometer is connected to the signal amplification circuit, and the sliding contact is grounded through a capacitor C4 at the same time.

8. The DC comparator according to claim 1, characterized in that: the signal amplification circuit includes a second amplifier. The non-inverting input terminal of the second amplifier is connected to the demodulation circuit through a resistor R7, the inverting input terminal is connected to the output terminal of the second amplifier through a resistor R9 and is grounded through a resistor R8 at the same time, and the output terminal of the second amplifier is connected to the signal feedback circuit.

9. The DC comparator according to claim 1, characterized in that: the signal feedback circuit includes a third amplifier, a first triode, a second triode, a third diode and a fourth diode. The inverting input terminal of the third amplifier is connected to the signal amplification circuit through a resistor R10 and is connected to the secondary feedback coil of the main iron core through a resistor R12 at the same time. The non-inverting input terminal of the third amplifier is grounded through a resistor R1, and the output terminal is connected to the base of the first triode and the base of the second triode respectively. The collector of the first triode is connected to the power supply VCC terminal, and the emitter is connected to the secondary feedback coil of the main iron core. The collector of the second triode is connected to the power supply VEE terminal, and the emitter is connected to the secondary feedback coil of the main iron core. The negative electrode of the third diode is connected to the power supply VCC terminal, and the positive electrode is connected to the secondary feedback coil of the main iron core. The positive electrode of the fourth diode is connected to the power supply VEE terminal, and the negative electrode is connected to the secondary feedback coil of the main iron core.

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