Signal detection device, signal detection method and radar system

Abstract

The present invention relates to the field of radar technology, and in particular to a signal detection device, a signal detection method and a radar system. The signal detection device provided by the present invention includes a ring register link, which is used to update the value of the corresponding data bit in the indication data according to each signal edge of the signal to be detected, and the frequency of the signal to be detected changes linearly within the detection interval; and a processing circuit, which is used to obtain a measurement value according to the starting value and the ending value of the indication data within the detection interval, and obtain the detection result data according to the offset between the measurement value and the preset expected value corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected within the detection interval meets the expected range. The radar system, signal detection device and signal detection method provided by the present disclosure can monitor the frequency of the signal to be detected in real time, so as to determine whether the signal to be detected is in a normal state.

Description

Technical Field

[0001] The present invention relates to the field of radar technology, and more specifically, to a signal detection device, a signal detection method and a radar system. Background Art

[0002] In the radar system, the frequency difference between the echo signal and the transmitted signal can be obtained by transmitting and receiving frequency modulated continuous waves, and then the distance, speed and other information of the target can be obtained according to the frequency difference. This modulation method using frequency modulated continuous waves has outstanding advantages such as simple structure, simple signal processing process, low cost and low power, so it has been widely used in fields such as vehicle-mounted radar.

[0003] Since the frequency of the FM continuous wave changes continuously during the operation of the radar system, the frequency state of the FM continuous wave can be used to determine whether modules such as the phase-locked loop in the radar system are in a normal working state.

[0004] Based on this, it is expected to provide a frequency detection scheme of a frequency modulated continuous wave to determine whether the radar system is in a normal operating state. Summary of the invention

[0005] In order to solve the problems existing in the above-mentioned prior art, the present invention provides a radar system, a signal detection method and a signal detection device, which can monitor the frequency of the signal to be detected in real time, so as to determine whether the frequency change of the signal to be detected is in a normal state.

[0006] According to a first aspect of an embodiment of the present invention, a signal detection device is provided, comprising: a ring register link, for updating the value of a corresponding data bit in indication data according to each signal edge of a signal to be detected, the frequency of the signal to be detected changing linearly within a detection interval; and a processing circuit, for obtaining a measurement value according to a starting value and an ending value of the indication data within the detection interval, and obtaining detection result data according to an offset between the measurement value and a preset expected value corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected within the detection interval satisfies an expected range.

[0007] Optionally, each rising edge and / or each falling edge of the signal to be detected is the signal edge, and for each of the detection intervals, the ring register link is suitable for: cyclically updating the values ​​of each data bit of the indication data in sequence under the triggering of each of the signal edges; and updating the value of a corresponding data bit in the indication data under the triggering of each of the signal edges.

[0008] Optionally, the ring register link includes a plurality of registers cascaded in sequence, each stage of the registers being respectively used to provide different data bits in the indication data, and each stage of the registers being suitable for providing an output signal of the register at that stage according to the signal to be detected and the input signal of the register, and providing corresponding data bits in the indication data according to the signal to be detected and the input signal of the register at that stage and / or according to the output signal of the register, wherein, in the plurality of registers cascaded in sequence: the first stage register obtains the input signal of the first stage register according to the inverted signal of the output signal provided by the last stage register; and each stage of registers other than the first stage register obtains the input signal of the register at that stage according to the output signal provided by the register cascaded at the previous stage.

[0009] Optionally, the register at each level updates the corresponding first data bit in the indication data according to the rising edge of the signal to be detected, and updates the corresponding second data bit in the indication data according to the falling edge of the signal to be detected.

[0010] Optionally, each level of the register includes: a cascaded sampling and holding module chain, including at least a first-level sampling and holding module and a second-level sampling and holding module, the first-level sampling and holding module samples the input signal of the register of this level in a sampling state to generate a transfer signal, and the second-level sampling and holding module samples the transfer signal in a sampling state to generate an output signal of the register of this level; and a buffer module, providing the first data bit according to the transfer signal, and providing the second data bit according to the output signal, wherein the first-level sampling and holding module and the second-level sampling and holding module alternately enter the sampling state according to the level state of the signal to be detected.

[0011] Optionally, the detection result data includes a first bit result value, and the processing circuit includes: a sampling unit, used to sample the indication data at the start time and the end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval; a storage unit, used to pre-store a relationship lookup table to indicate the sequence numbers corresponding to multiple state values ​​of the indication data under the output logical order of the ring register link, the multiple state values ​​include the start value and the end value, and the sequence number includes a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judgment unit, used to obtain the measurement value according to the difference between the first sequence number and the second sequence number, and judge whether the offset is greater than a first threshold value, if so, the first judgment unit sets the first bit result value to a valid state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not meet the expected range, if not, the first judgment unit sets the first bit result value to an invalid state to indicate that the average value of the frequency of the signal to be detected in the detection interval meets the expected range.

[0012] Optionally, the preset expected value is: based on the total number of the multiple state values ​​and the expected number of occurrences of the signal edge of the signal to be detected in the detection interval, the obtained data value is calculated.

[0013] Optionally, for each detection interval: the measured value is equal to the difference, the preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, and the set value is equal to the product of the expected average value of the frequency of the signal to be detected within the detection interval and the duration of the detection interval.

[0014] Optionally, the processing circuit also includes: a counter, used to provide a count value based on the first-bit result value, the counter responds to the first-bit result value in a valid state to add 1 to the count value, and responds to the first-bit result value in an invalid state to reset the count value to an initial value; and a comparator, used to determine whether the count value is greater than a second threshold value, if so, the comparator sets the second-bit result value of the detection result data to a valid state to characterize that the frequency change of the signal to be detected is in an abnormal state, if not, the comparator sets the second-bit result value to an invalid state to characterize that the frequency change of the signal to be detected is in a normal state.

[0015] Optionally, the signal to be detected is a frequency modulated continuous wave signal with a frame period, the signal to be detected changes linearly within a linear interval of each frame period and is reset to an initial level within a waiting interval of each frame period, each detection interval is included in the corresponding linear interval, and for each detection interval, the processing circuit samples the signal to be detected according to a sampling clock signal to obtain the starting value and the ending value of the indication data in the detection interval, and the starting time and the ending time of the detection interval respectively correspond to two adjacent and same-direction clock edges in the sampling clock signal.

[0016] Optionally, the signal detection device also includes: a frequency reduction circuit, cascaded before the ring register link, for reducing the frequency of the signal to be detected according to a set division ratio; and / or a shaping circuit, cascaded before the ring register link, for shaping the signal to be detected into a square wave, and the ring register link provides the indication data based on the signal to be detected after frequency reduction, the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

[0017] According to a second aspect of an embodiment of the present invention, a radar system is provided, comprising: a phase-locked loop structure, comprising a voltage-controlled oscillator, the voltage-controlled oscillator generating a swept frequency signal according to a frequency control voltage, the frequency of the swept frequency signal varying with the voltage value of the frequency control voltage; a signal detection device as disclosed in any embodiment of the present invention, used to use the swept frequency signal or the clock signal as the signal to be detected, the frequency of the clock signal being in a set ratio to the frequency of the swept frequency signal; and a radar transceiver, providing a transmission signal and / or processing an echo signal according to the swept frequency signal.

[0018] For example, when the calculated offset is less than / equal to the first threshold, the signal detection device disclosed in the embodiment of the present invention can determine that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; and in order to improve the accuracy of the judgment, the signal detection device disclosed in the embodiment of the present invention can perform judgment processing for multiple detection intervals respectively, and only in all or a preset proportion of the detection intervals, the offset is less than / equal to the above-mentioned first threshold, and at the same time shows a certain regular change or the change amplitude is small, the phase-locked loop structure is judged to be in a normal working state. Among them, the judgment of the change amplitude can be set based on the actual accuracy requirements.

[0019] In addition, for a phase-locked loop structure in an abnormal working state, the signal detection device provided in an embodiment of the present invention can also determine whether the phase-locked loop structure is in a locked state or an unstable state by further analyzing and judging the change law of the offset obtained in different detection intervals (that is, in the embodiment of the present application, the abnormal working state may include a locked state and an unstable state). For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or changes by a large amplitude, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it can be considered that some components in the phase-locked loop structure may be damaged at this time; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

[0020] According to the third aspect of an embodiment of the present invention, a signal detection method is also provided, comprising: providing a signal to be detected, the frequency of the signal to be detected changes linearly within a detection interval; providing indication data having multiple data bits, and updating corresponding data bits in the indication data according to the signal edge of the signal to be detected; sampling the indication data at the start time and the end time of the detection interval to obtain the start value and the end value of the indication data within the detection interval; and for each of the detection intervals, obtaining a measurement value according to the start value and the end value of the indication data within the detection interval, and obtaining detection result data according to the offset between a preset expected value corresponding to the detection interval and the measurement value, wherein the detection result data characterizes whether the average value of the frequency of the signal to be detected within the detection interval meets the expected range.

[0021] Optionally, each rising edge and / or each falling edge of the signal to be detected is the signal edge, and the step of updating the corresponding data bit in the indication data according to the signal edge of the signal to be detected includes: cyclically updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and updating the value of a corresponding data bit in the indication data under the triggering of each signal edge.

[0022] Optionally, for each of the detection intervals, a measurement value is obtained according to the starting value and the ending value of the indication data in the detection interval, and a step of obtaining detection result data according to an offset between a preset expected value corresponding to the detection interval and the measurement value includes: obtaining a relationship lookup table, the relationship lookup table indicating sequence numbers corresponding to multiple state values ​​of the indication data in an output logical order, the multiple state values ​​including the starting value and the ending value, the sequence numbers including a first sequence number corresponding to the starting value and a second sequence number corresponding to the ending value; obtaining the measurement value according to a difference between the first sequence number and the second sequence number; judging whether the offset is greater than a first threshold value, and if so, setting the first bit result value of the detection result data to a valid state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not satisfy the expected range, and if not, setting the first bit result value to an invalid state to indicate that the average value of the frequency of the signal to be detected in the detection interval satisfies the expected range.

[0023] Optionally, the signal detection method provided by the embodiment of the present invention further includes: calculating the preset expected value based on the total number of the multiple state values ​​and the expected number of occurrences of the signal edge of the signal to be detected within the detection interval.

[0024] Optionally, for each detection interval: the measured value is equal to the difference, the preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, and the set value is equal to the product of a preset frequency average value of the signal to be detected in the detection interval and the duration of the detection interval.

[0025] Optionally, for each of the detection intervals, a measurement value is obtained according to the starting value and the ending value of the indication data within the detection interval, and the step of obtaining the detection result data according to the offset between the preset expected value corresponding to the detection interval and the measurement value also includes: providing a count value according to the first-bit result value, and adding 1 to the count value when the first-bit result value is in a valid state, and restoring the count value to an initial value when the first-bit result value is in an invalid state; and judging whether the count value is greater than a second threshold value, and if so, setting the second-bit result value of the detection result data to a valid state to characterize that the frequency change of the signal to be detected is in an abnormal state, and if not, setting the second-bit result value to an invalid state to characterize that the frequency change of the signal to be detected is in a normal state.

[0026] Optionally, the signal to be detected changes linearly within the linear interval of each frame period and is reset to an initial level within the waiting interval of each frame period, each detection interval is included in the corresponding linear interval, and the step of obtaining the starting value and the ending value of the indication data within the detection interval includes: sampling the signal to be detected according to a sampling clock signal to obtain the starting value and the ending value of the indication data within the detection interval, and the starting time and the ending time of the detection interval respectively correspond to adjacent and same-direction clock edges in the sampling clock signal.

[0027] Optionally, the step of providing the signal to be detected and the indication data includes: down-converting the signal to be detected according to a set frequency division ratio; and / or shaping the signal to be detected into a square wave, wherein the indication data is generated based on the down-converted signal to be detected, or the shaped signal to be detected, or the down-converted and shaped signal to be detected.

[0028] According to the radar system, signal detection device and signal detection method provided by the embodiments of the present invention, by updating each data bit in the indication data according to the signal edge of the signal to be detected, it is possible to judge whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range according to the starting value and the ending value of the indication data in the detection interval, so as to realize real-time monitoring of the frequency change of the signal to be detected. In the radar system of the embodiment of the present invention, since the frequency of the signal to be detected changes in proportion to the swept frequency signal generated by the signal source, the detection result data provided by the signal detection device can indicate whether the signal source is working abnormally and whether the radar system is working abnormally. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0030] Figure 1 A schematic diagram showing the structure of a radar system according to an embodiment of the present invention is shown;

[0031] Figure 2 Show Figure 1 A schematic structural diagram of an embodiment of a signal source;

[0032] Figure 3 A schematic diagram showing waveforms of a frequency sweep signal and a frequency control voltage in an embodiment of the present invention is shown;

[0033] Figure 4 A schematic block diagram showing a signal detection device according to an embodiment of the present invention;

[0034] Figure 5 A schematic block diagram showing a signal detection device according to another embodiment of the present invention;

[0035] Figure 6 A schematic diagram showing the structure of a ring register link according to an embodiment of the present invention;

[0036] Figure 7 Show Figure 6 Schematic diagram of the circuit structure of each register in;

[0037] Figure 8 Show Figure 4 or a schematic block diagram of an implementation of the processing circuit in 5;

[0038] Fig. 9 Show Figure 4 or a schematic block diagram of another implementation of the processing circuit in 5;

[0039] Fig.10 A schematic flow chart showing a signal detection method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0040] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0041] System Overview

[0042] Figure 1 A schematic structural diagram of a radar system according to an embodiment of the present invention is shown. Figure 2 Show Figure 1 A structural schematic diagram of an embodiment of a signal source in FIG. Figure 3 A schematic diagram showing waveforms of a signal to be detected and a frequency control voltage in an embodiment of the present invention is shown.

[0043] like Figure 1 As shown, the radar system of the embodiment of the present invention includes: a transceiver antenna, a receiving channel, a transmitting channel, a signal source, a signal processing module and a signal detection device. Among them, the transceiver antenna, the receiving channel, the transmitting channel and the signal processing module serve as a radar transceiver, and the radar transceiver provides a transmitting signal and / or processes an echo signal according to a sweep signal provided by the signal source.

[0044] The following will be based on Figures 1 to 3 The various parts of the radar system based on the frequency modulated continuous wave system in this embodiment are described. However, the embodiment of the present invention is not limited thereto, and one / some unmentioned conventional structures or modules may also be included in the radar system in the embodiment of the present invention.

[0045] (1) Transceiver antenna

[0046] The transceiver antenna includes a transmitting antenna 1 and a receiving antenna 2. The transmitting antenna 1 provides a spatially radiated electromagnetic wave based on the transmitting signal, and the electromagnetic wave is reflected on the surface of the target object. The reflected electromagnetic wave is captured by the receiving antenna, so that the receiving antenna 2 obtains an echo signal. Since in the radar system 100 of the embodiment of the present invention, the transmitting signal is a frequency modulated continuous wave with a continuously changing frequency, the radar system 100 of the frequency modulated continuous wave system can obtain information such as the distance and speed of the target object based on the frequency difference between the transmitting signal and the echo signal, wherein the speed of the target object can be obtained, for example, by calculating multiple distance measurements.

[0047] (2) Signal source

[0048] The signal source 6 is used to generate a frequency-changing sweep signal SFM, the frequency of which changes in a trend such as a triangular wave or a sawtooth wave, and has a linear change trend within the detection interval. The sweep signal SFM can be a periodic signal or a non-periodic signal, which is not limited in the present application.

[0049] As an optional embodiment, the signal source 6 is, for example, Figure 2 The phase-locked loop structure (Phase Locked Loop, PLL for short) shown includes a charge pump (Charge Pump, CP for short) 610, a loop filter (Loop Filter, LP for short) 620, a voltage-controlled oscillator (Voltage Controlled Oscillator, VCO for short) 630, a feedback divider 640, and a phase frequency detector (PFD for short) 650 and other modules.

[0050] The phase frequency detector 650, the charge pump 610, the loop filter 620 and the voltage controlled oscillator 630 are sequentially cascaded, and the output end of the voltage controlled oscillator 630 provides an output frequency sweep signal SFM. The feedback frequency divider 640 receives the frequency sweep signal SFM output by the voltage controlled oscillator 630, divides the frequency sweep signal SFM to obtain a down-frequency sweep signal SFM_div, and provides the down-frequency sweep signal SFM_div to the phase frequency detector 650, thereby forming a feedback control loop in the phase locked loop structure.

[0051] The feedback divider 640 is, for example, a multi-modulus divider (MMD), which can divide the frequency of the sweep signal SFM according to the frequency division ratio set by the mode control signal to obtain the down-frequency sweep signal SFM_div, thereby realizing a programmable frequency division function. When the frequency division ratio set by the mode control signal changes continuously, the frequency of the sweep signal SFM can change continuously.

[0052] The frequency and phase detector 650 compares the frequency and phase of the reference signal Fref with the frequency and phase of the frequency reduction scanning signal SFM_div to generate a first state signal Qa and a second state signal Qb representing the comparison result. As an example, the reference signal Fref can be provided by a crystal oscillator or by other circuits or modules, and the present application does not limit this.

[0053] The charge pump 610 generates an analog voltage signal Vo according to the received first state signal Qa and second state signal Qb. The first state signal Qa and the second state signal Qb are used to increase and decrease the voltage value of the analog voltage signal Vo, respectively.

[0054] The analog voltage signal Vo is filtered by the loop filter 620 to obtain the frequency control voltage Vc, so that the voltage controlled oscillator 630 generates a frequency sweep signal SFM under the control of the frequency control voltage Vc, and the frequency of the frequency sweep signal SFM corresponds to the voltage value of the frequency control voltage Vc. Figure 3 As shown, the voltage value of the frequency control voltage Vc has a linear change trend in each linear interval Tchrip_up, for example: the frequency control voltage Vc increases linearly from the preset voltage at the start of each linear interval, and the frequency sweep signal provided by the voltage-controlled oscillator 630 under the action of the preset voltage has a minimum frequency FL; at the end of each linear interval, the frequency control voltage Vc reaches the highest voltage, and the frequency sweep signal provided by the voltage-controlled oscillator 630 under the action of the highest voltage has a maximum frequency FH; in the waiting interval between each two adjacent linear intervals, the frequency control voltage Vc is reset to the preset voltage. Therefore, the frequency of the frequency sweep signal SFM provided by the voltage-controlled oscillator 630 changes linearly with the frequency control voltage Vc in each linear interval.

[0055] In some optional embodiments, the duration of each linear interval Tchrip_up is equal and the duration of each waiting interval is equal, and each linear interval and each waiting interval are alternately distributed in the time domain, so that the frequency control voltage Vc has a frame period and presents a triangular wave or a sawtooth wave within each frame period.

[0056] This embodiment describes the signal source 6 by taking the above phase-locked loop structure as an example. However, the signal source of the embodiment of the present invention is not limited thereto. The signal source 6 may also be implemented by other circuits capable of generating a frequency sweep signal.

[0057] When the radar system is working, it must be ensured that the phase-locked loop structure including the voltage-controlled oscillator is in a normal working state. Therefore, how to detect the working state of the phase-locked loop structure (or the signal source of other structures) is the key to ensure the normal operation of the radar system. The present invention monitors whether the phase-locked loop structure is in a normal working state by detecting the swept frequency signal or the down-converted signal of the swept frequency signal, thereby ensuring the normal operation of the radar system.

[0058] (3) Receiving channel and transmitting channel

[0059] The transmitting channel 3 and the receiving channel 4 are coupled to the transmitting antenna 1 and the receiving antenna 2, respectively. The transmitting channel 3 is connected to the signal source 6 to receive the swept frequency signal SFM, and the transmitting channel 3 provides a transmitting signal to the transmitting antenna 1 according to the swept frequency signal SFM, and processes the swept frequency signal SFM to generate a first signal S1. The receiving channel 4 is connected to the receiving antenna 2 to receive the echo signal, and performs filtering and other processing on the echo signal to generate a second signal S2.

[0060] (4) Mixing unit

[0061] The frequency mixing unit 5 is connected to the transmitting channel 3 and the receiving channel 4 to receive the first signal S1 and the second signal S2, so as to obtain the beat signal SD according to the first signal S1 and the second signal S2. The frequency of the beat signal SD is the difference between the frequency of the first signal S1 and the frequency of the second signal S2, so as to characterize the difference between the time when the echo signal is received and the time when the transmit signal is transmitted, and the difference is related to the distance, speed and other information of the target object. The frequency of the beat signal SD is, for example, proportional to the distance between the target object and the radar.

[0062] (5) Signal processing module

[0063] The signal processing module 8 receives the beat signal SD provided by the frequency mixing unit 5, and obtains the detection result Sdata according to the frequency of the beat signal SD. The detection result Sdata includes information such as the distance and speed of the target object relative to the radar system.

[0064] The signal processing module 8 includes, for example, an analog-to-digital converter for generating a corresponding digital signal according to the beat signal SD and a computing unit for performing calculations on the digital signal.

[0065] (6) Signal detection device

[0066] The radar system of the embodiment of the present invention further comprises a signal detection device 7, which detects the signal to be detected STST provided by the signal source 6. The signal to be detected STST (such as Figure 3 As shown in the figure) can be a swept frequency signal SFM, or a down-converted signal of the swept frequency signal SFM.

[0067] As an example, the signal to be detected STST is, for example, a down-converted scanning signal SFM_div provided by the feedback divider 640 in the signal source 6 .

[0068] As another example, Figure 2As shown, the signal source 6 also includes a frequency divider 660, which is coupled to the output end of the voltage-controlled oscillator 630 to receive the swept frequency signal SFM, and is used to reduce the frequency of the swept frequency signal SFM to obtain the signal to be detected STST, so as to make the frequency of the signal to be detected STST conform to the operating frequency range of the signal detection device 7.

[0069] It should be noted that the divider 660 can be set in a hardware module for implementing the signal source 6, or can be set in a different hardware module from the components included in the signal source 6 such as the voltage-controlled oscillator 630, or can be set in the same hardware module as the signal detection device 7, or exist in other forms, and the embodiments of the present invention do not impose any restrictions on this.

[0070] The signal detection device 7 is used to provide the indication data Dstate, and update the indication data Dstate according to each signal edge of the signal to be detected STST (i.e., the level change edge of the signal to be detected STST, which may include each rising edge and / or each falling edge) within the detection interval, so that it is possible to judge whether the average value of the frequency of the signal to be detected STST within the detection interval meets the expected range according to the starting value and the ending value of the indication data Dstate within the detection interval. For example, the signal detection device 7 may update the corresponding data bits in the indication data Dstate at each rising edge and each falling edge of the signal to be detected STST, or may update the corresponding data bits in the indication data Dstate only at each rising edge or each falling edge of the signal to be detected STST.

[0071] It should be noted that, in the embodiments of the present invention, Figure 3 The linear interval Tchrip_up shown can be directly used as the detection interval. However, the embodiment of the present invention is not limited thereto, and in other embodiments, the detection interval can also be a part of the linear interval Tchrip_up.

[0072] Figure 4 A schematic block diagram of a signal detection device according to an embodiment of the present invention is shown below. Figure 4 The signal detection device 7 of this embodiment is described in detail.

[0073] like Figure 4 As shown, the signal detection device 7 includes a ring register link 7100 and a processing circuit 7200 .

[0074] The ring register link 7100 is used to provide indication data Dstate having multiple data bits, and update each data bit D1-Dn in the indication data Dstate according to the signal edge of the signal to be detected STST, where n is a natural number greater than 1.

[0075] For example, when a rising edge appears in the signal to be detected STST, the logic state of a corresponding data bit Di in the indication data Dstate changes (from 1 to 0 or from 0 to 1, referred to as the i-th update). Subsequently, when a falling edge appears in the signal to be detected STST, the logic state of another data bit Dj in the indication data Dstate after the i-th update changes (referred to as the j-th update). By analogy, it can be seen that: in each frame period, the signal to be detected STST has a rising edge and a falling edge, and the indication data Dstate can be updated twice, that is, the indication data Dstate has two corresponding data bits updated. Among them, i and j are non-zero natural numbers less than or equal to n.

[0076] In some optional embodiments, when i is less than n, j is equal to i+1, and when i is equal to n, j is equal to 1, so that each data bit D1 to Dn in the indication data Dstate can be cyclically updated according to the signal edge of the signal to be detected STST.

[0077] In the above description, the i-th update of the indication data Dstate occurs when the signal to be detected STST has a rising edge. It should be noted that in some other equivalent embodiments, the i-th update of the indication data Dstate may occur when the signal to be detected STST has a falling edge. Accordingly, the j-th update of the indication data Dstate may occur when the signal to be detected STST has a rising edge. In addition, in the description of the various embodiments of the present invention, the update of a data bit in the indication data Dstate refers to the update of the logic value of the data bit from 1 to 0 or from 0 to 1.

[0078] In this document, various data values ​​that may be provided by the indication data Dstate during the continuous updating process are referred to as various state values ​​of the indication data Dstate.

[0079] The processing circuit 7200 is connected to the output end of the ring register link 7100 to receive the indication data Dstate. The processing circuit 7200 is used to obtain the preset expected value of the indication data Dstate corresponding to each detection interval, and determine whether the average value of the frequency of the signal to be detected STST in the detection interval meets the expected range according to the starting value and the end value of the indication data Dstate in each detection interval and the preset expected value corresponding to the detection interval.

[0080] As an optional embodiment, in the linear interval, the processing circuit 7200 can sample the indication data Dstate under the triggering of the clock edge (rising edge or falling edge) of the sampling clock signal to obtain the starting value and the ending value of the indication data Dstate in each detection interval. In this case, each detection interval corresponds to a corresponding sampling period in the sampling clock signal, and the starting time and the ending time of each detection interval correspond to two adjacent and co-directional clock edges of the sampling clock signal. This embodiment will be described in detail below, however, the embodiments of the present invention are not limited thereto, and each detection interval is not limited to corresponding to a sampling period of the sampling clock signal, but may also correspond to multiple continuous sampling periods, and may also be related to other signals used to indicate the starting time and the ending time of the detection interval.

[0081] Specifically, in each detection interval, the processing circuit 7200 can sample and obtain the starting value of the indication data Dstate at the starting moment of the detection interval, and as the signal edge of the signal to be detected STST appears, each data bit D1-Dn in the indication data Dstate is cyclically updated; the processing circuit 7200 obtains the ending value of the indication data Dstate at the end moment of the detection interval. It can be seen that the difference between the ending value and the starting value is related to the number of times the indication data Dstate is updated, that is, related to the total number of signal edges that appear in the signal to be detected STST in the detection interval. Therefore, the difference between the starting value and the ending value of the indication data Dstate in the detection interval is related to the average frequency of the signal to be detected STST in the detection interval. Based on this, the processing circuit 7200 can obtain a measurement value according to the difference between the starting value and the ending value of the indication data Dstate in each detection interval, and provide the detection result data Sout according to the preset expected value corresponding to the measurement value and the sampling period, so that the detection result data Sout can characterize whether the average value of the frequency of the signal to be detected STST in each detection interval meets the expected range.

[0082] It should be noted that the "start value" disclosed herein refers to the data value indicating the data Dstate at the start time of the detection interval; the "end value" refers to the data value indicating the data Dstate at the end time of the detection interval. The start value and the end value are respectively one of the state values ​​indicating the data Dstate.

[0083] In some optional embodiments, the preset expected value can represent the expected number of occurrences of the signal edge of the signal to be detected STST within the detection interval, for example, the expected average value of the frequency of the signal to be detected STST within the detection interval. Based on this, the processing circuit 7200 can calculate the predicted end value of the indication data Dstate within the detection interval according to the starting value of the indication data within the detection interval, the preset expected value corresponding to the detection interval, and the duration of the detection interval; then, the processing circuit 7200 can compare the end value obtained by sampling with the predicted end value obtained by calculation. If the two are consistent within the allowable error range, it means that the average value of the frequency of the signal to be detected STST within the detection interval meets the expected range. If the two are inconsistent within the allowable error range, it means that the average value of the frequency of the signal to be detected STST within the detection interval does not meet the expected range, the signal source 6 (such as Figure 1 as shown) and the radar system is not functioning properly.

[0084] In some other optional embodiments, the preset expected value may be a value calculated based on the total number of state values ​​that may be provided by the specified data Dstate and the expected number of occurrences of the signal edge of the signal to be detected STST in the detection interval. Based on this, for each detection interval, the processing circuit 7200 may determine whether the average value of the frequency of the signal to be detected STST in the detection interval satisfies the expected range based on the difference between the starting value and the ending value of the signal to be detected STST in the detection interval and the preset expected value corresponding to the detection interval. This embodiment will be described in detail later and will not be elaborated here.

[0085] exist Figure 4In the illustrated embodiment, the ring register link 7100 has a clock end, which directly receives the signal to be detected STST, so that the ring register link uses the signal to be detected STST as the clock signal clk. As mentioned above, since the signal to be detected STST is a swept frequency signal SFM or a down-converted signal of the swept frequency signal SFM, it is possible to know whether the average value of the frequency of the swept frequency signal SFM in the detection interval meets the expected frequency range according to the known frequency ratio between the signal to be detected STST and the swept frequency signal SFM and the detection result data Sout provided by the processing circuit 7200, that is, the detection result data Sout provided by the processing circuit 7200 can also characterize whether the average value of the frequency of the swept frequency signal SFM in the detection interval meets the expected range. When the detection result data Sout indicates that the average value of the frequency of the signal to be detected STST in the detection interval meets the expected range, it means that the signal source works normally and the frequency change of the swept frequency signal SFM is correct, and the radar system can work normally at this time; when the detection result data indicates that the average value of the frequency of the signal to be detected STST in the detection interval does not meet the expected range, it means that the signal source works abnormally and the frequency change of the swept frequency signal SFM does not meet the expected range, and the radar system works abnormally at this time.

[0086] Figure 5 A schematic block diagram showing a signal detection device according to another embodiment of the present invention.

[0087] In the above description, the ring register chain 7100 directly uses the signal to be detected STST as the clock signal clk, but the embodiment of the present invention is not limited thereto, and the clock end of the ring register chain 7100 can receive any signal whose frequency is related to the frequency of the sweep frequency signal SFM. For example, in some alternative embodiments, Figure 5 As shown, the signal detection device 7 further includes a driving circuit 7300 for down-converting and / or shaping the signal to be detected STST, and using the down-converted and / or shaped signal to be detected STST as a clock signal clk of the ring register chain 7100 .

[0088] like Figure 5 As shown, the driving circuit 7300 includes, for example, a shaping circuit, which is used to buffer and / or shape the signal to be detected, so that the signal to be detected input to the ring register chain 7100 is a square wave signal, which can improve the detection accuracy of the ring register chain 7100 for the signal to be detected.

[0089] The driving circuit 7300 may further include a frequency reduction circuit (for example, implemented by a frequency division circuit structure). The frequency reduction unit can be cascaded before the shaping circuit or cascaded after the shaping circuit to reduce the frequency of the signal to be detected according to the set frequency division ratio, thereby further improving the detection accuracy of the ring register chain 7100 for the signal to be detected and reducing the performance requirements of the ring register chain 7100.

[0090] It should be noted that the frequency divider 660 (eg Figure 2 ) and the driving circuit 7300 (as shown Figure 5 The functions of the frequency reduction circuits in FIG. 7 and FIG. 8 are the same, that is, the frequency of the signal to be detected input to the ring register chain 7100 is reduced to within the operating frequency range of the ring register chain 7100. Therefore, the frequency divider 660 (as shown in FIG. 7 Figure 2 ) and the driving circuit 7300 (as shown Figure 5 The frequency reduction circuits in the embodiment shown in the figure may exist at the same time or one of them may be selected, and this application does not impose any limitation on this.

[0091] Take the application of millimeter wave radar as an example: the form of the swept frequency signal SFM in the time domain is a frequency modulated continuous wave (FMCW), and its frequency varies in the frequency range of 30 GHz to 300 GHz, and the operating frequency of each register in the ring register link 7100 is at the megahertz level. Therefore, it is necessary to reduce the frequency of the swept frequency signal SFM to obtain the signal to be detected, so that the frequency of the clock signal clk input to the ring register link 7100 falls within the operating frequency range of the ring register link 7100. The frequency reduction process can be performed by Figure 2 The divider 660 and / or Figure 5 Meanwhile, since each register in the ring register chain 7100 usually needs to be triggered by a clock signal clk in the form of a square wave, when the frequency sweep signal SFM is a frequency modulated continuous wave in the form of a sine wave, the signal to be detected input to the ring register chain 7100 can be shaped into a square wave as the clock signal clk, and the shaping process can be performed by Figure 5 The shaping circuit in the driving circuit 7300 is shown as being implemented. As mentioned above, the shaping process proposed here can be performed before the frequency reduction process or after the frequency reduction process, and this application does not limit this.

[0092] exist Figure 5 In the illustrated embodiment, the ring register chain 7100 and the processing circuit 7200 are connected to Figure 4 The embodiments shown are the same or similar, so they will not be described in detail.

[0093] The ring register link 7100 and the processing circuit 7200 of the embodiment of the present invention are described in detail below.

[0094] Ring register link

[0095] Figure 6 A schematic diagram showing the structure of a ring register link according to an embodiment of the present invention is shown. Figure 7 Show Figure 6 The circuit structure diagram of each register in the following table is shown in Figure 1. Figure 6 and Figure 7 The ring register link of the embodiment of the present invention is described in detail.

[0096] like Figure 6 As shown, the ring register chain 7100 includes a plurality of registers 7110 cascaded in sequence, and the last stage of registers is cascaded before the first stage of registers to form a ring chain.

[0097] Each level of register 7110 generates the output signal DOUT of this level and the corresponding data bits in the indication data Dstate according to the clock signal clk, the inverted clock signal clkb and the input signal DIN of this level. Each level of register 7110 corresponds to different data bits in the indication data Dstate.

[0098] The ring register chain 7100 further includes an odd number of inverters INV1 cascaded between the first-stage register and the last-stage register, so that the first-stage register can obtain the input signal of the current stage according to the inverted signal of the output signal provided by the last-stage register. Each stage register other than the first-stage register obtains the input signal of the current stage according to the output signal provided by the register cascaded in the previous stage.

[0099] The ring register chain 7100 further includes an odd number of inverters INV0 for generating an inverted clock signal clkb according to the clock signal clk, so that the inverted clock signal clkb is an inverted signal of the clock signal clk.

[0100] In an optional embodiment, if Figure 6 As shown, the number of data bits n indicating the data Dstate is a non-zero even number, and each level of register 7110 corresponds to two corresponding adjacent data bits in the indication data Dstate. For example, the first level register 7110 is used to output the data bit D1 and the data bit D2 in the indication data Dstate, and the second level register 7110 is used to output the data bit D3 and the data bit D4 in the indication data Dstate, and so on.

[0101] As an example, each level of register 7110 can update the corresponding first data bit Dk in the indication data Dstate (output by the DF1 terminal of the register of this level) according to the rising edge of the clock signal clk, and update the corresponding second data bit Dp in the indication data Dstate (output by the DF2 terminal of the register of this level) according to the falling edge of the clock signal clk. Wherein, k and p are non-zero natural numbers less than or equal to n, and p is preferably equal to k+1.

[0102] In other embodiments, each level of register 7110 can update the corresponding first data bit Dk in the indication data Dstate according to the falling edge of the clock signal clk, and update the corresponding second data bit Dp in the indication data Dstate according to the rising edge of the clock signal clk. The principle is the same as the above embodiment and will not be repeated.

[0103] It should be noted that “updating a certain data bit” mentioned in this article refers to resetting the corresponding data bit according to the current state of each related signal, that is, updating the corresponding data bit in the indication data Dstate may or may not change the logical state of the data bit.

[0104] As an optional embodiment, Figure 7 As shown, each level of register 7110 includes at least two levels of sampling and holding modules. The number of cascaded sampling and holding modules in each level of register 7110 can be the same as the number of bits of the indication data corresponding to each level of register. In this embodiment, each level of register corresponds to 2 data bits, and each level of register includes a first level of sampling and holding module and a second level of sampling and holding module as an example for description, but the embodiment of the present application is not limited thereto.

[0105] like Figure 7 As shown, the first stage sampling and holding module 7111 samples the input signal DIN of the register at this stage in the sampling state to generate the transfer signal DZ, and the second stage sampling and holding module 7112 samples the transfer signal DZ in the sampling state to generate the output signal DOUT of the register at this stage.

[0106] The first stage sampling and holding module 7111 has a sampling state and a holding state, and enters the sampling state and the holding state alternately according to the clock signal clk. In the sampling state, the first stage sampling and holding module 7111 updates the transfer signal DZ according to the input signal DIN of the register of this stage; in the holding state, the first stage sampling and holding module 7111 keeps the transfer signal unchanged.

[0107] As an optional embodiment, the first-stage sampling and holding module 7111 may include a transmission gate controlled by the clock signal clk. The transmission gate includes, for example, field effect transistors M11 and M12, the sources of which are connected and receive the input signal DIN of the register 7110 at this stage, the drains of which are connected and provide the transfer signal DZ; the gates of the field effect transistors M11 and M12 receive the clock signal clk and the inverted clock signal clkb, respectively.

[0108] The first stage sampling and holding module 7111 may further include an even number of inverters (NOT gates) for buffering the input signal DIN input to the transmission gate and / or buffering the transfer signal DZ output by the transmission gate.

[0109] The second-stage sampling and holding module 7112 may have the same circuit structure as the first-stage sampling and holding module 7111. The second-stage sampling and holding module 7112 may include, for example, a transmission gate composed of field effect transistors M21 and M22. The sources of the field effect transistors M21 and M22 are connected and receive the transmission signal DZ provided by the first-stage sampling and holding module 7111. The drains of the field effect transistors M21 and M22 are connected and provide the output signal DOUT of the register at this stage. The gates of the field effect transistors M21 and M22 receive the clock signal clk and the inverted clock signal clkb, respectively. The second-stage sampling and holding module 7112 may also include an even number of inverters for buffering the transmission signal DZ input to the transmission gate and / or buffering the output signal DOUT provided by the register at this stage.

[0110] In an optional embodiment, the transmission gate in the first stage sampling and holding module 7111 is cascaded between two inverters, and the transmission gate in the second stage sampling and holding module 7112 is cascaded between another two inverters, so that a precise sampling and holding function can be achieved with a simple circuit structure.

[0111] In order to make the working states of the second-stage sampling and holding module 7112 and the first-stage sampling and holding module 7111 different at the same time, that is, the first-stage sampling and holding module 7112 and the first-stage sampling and holding module 7111 alternately enter the sampling state and alternately enter the holding state, the transmission gate in the second-stage sampling and holding module 7112 and the transmission gate in the first-stage sampling and holding module 7111 are alternately turned on under the control of the clock signal clk.

[0112] As an optional embodiment, the gates of the field effect transistors M12 and M21 receive the inverted clock signal clkb, the gates of the field effect transistors M11 and M22 receive the clock signal clk, the field effect transistors M11 and M21 are, for example, PMOS transistors, and the field effect transistors M12 and M22 are, for example, NMOS transistors. Thus, when the clock signal clk is at a low level, the transmission gate in the first-stage sampling and holding module 7111 is turned on, so that the transfer signal DZ is the same as the input signal DIN received by the register of this stage, at which time the first-stage sampling and holding module 7111 works in a sampling state, and the second-stage sampling and holding module 7112 works in a holding state; when the clock signal clk is at a high level, the transmission gate in the second-stage sampling and holding module 7112 is turned on, so that the output signal DOUT provided by the register of this stage is the same as the transfer signal DZ provided by the first-stage sampling and holding module 7111, at which time the first-stage sampling and holding module 7111 works in a holding state, and the second-stage sampling and holding module 7112 works in a sampling state.

[0113] like Figure 7 As shown, each level of register 7110 also includes a first-level buffer module 7113 and a second-level buffer module 7114. The first-level buffer module 7113 buffers the transfer signal DZ output by the first-level sampling and holding module 7111 to drive / shape to obtain the first data bit Dk corresponding to the register of this level in the indication data Dstate, and the second-level buffer module 7114 buffers the output signal DOUT provided by the second-level sampling and holding module 7112 to drive / shape to obtain the second data bit Dp corresponding to the register of this level in the indication data Dstate. The first-level buffer module 7113 and the second-level buffer module 7114, for example, respectively include an even number of cascaded inverters (not gates).

[0114] In the above embodiment, each level of sampling and holding module and each level of buffer module receive, for example, the same power supply voltage, such as a high-level power supply voltage VDD and a low-level voltage VSS.

[0115] Processing circuit

[0116] Figure 8 Show Figure 5 or Figure 4 A schematic block diagram of an implementation of a processing circuit in FIG.

[0117] The following is based on Figure 8 The implementation method shown describes and illustrates the processing circuit of the embodiment of the present invention, but the embodiment of the present invention is not limited to this. Other implementation principles of the processing circuit are described above, and those skilled in the art may also use other judgment methods to determine whether the average value of the frequency of the signal to be detected in the detection interval is within the expected range.

[0118] like Figure 8 As shown, the processing circuit 7200 includes a sampling unit 7210 , a storage unit 7220 and a first determination unit 7230 .

[0119] The sampling unit 7210 is used to sample the indication data Dstate provided by the ring register link 7100 at the start time of the detection interval to obtain the starting value Dstate_ini of the indication data in the detection interval, and to sample the indication data Dstate provided by the ring register link 7100 at the end time of the detection interval to obtain the ending value Dstate_end of the indication data in the detection interval. The sampling unit 7210 receives a sampling clock signal clk_cs, the frequency of which is less than the frequency of the clock signal clk of the ring register link 7100, and the sampling period Tsample of the sampling clock signal clk_cs corresponds to one detection interval, so that the sampling unit 7210 can obtain the starting value Dstate_ini and the ending value Dstate_end by sampling under the control of the sampling clock signal clk_cs.

[0120] The storage unit 7220 is used to pre-store various possible state values ​​Dstate_1 to Dstate_2n of the indication data, and store the sequence numbers corresponding to each state value of the indication data in the output logical order of the ring register link, so as to establish a relationship lookup table between different state values ​​and each sequence number, such as the relationship lookup table shown in Table 1 below.

[0121] Table 1 Pre-stored relationship lookup table between different status values ​​and sequence numbers

[0122]

[0123]

[0124] In each detection interval, the first judgment unit 7230 is used to obtain the difference Δa between the sequence number a2 corresponding to the end value Dstate_end of the indication data in the detection interval and the sequence number a1 corresponding to the starting value Dstate_ini of the indication data in the detection interval according to the above-mentioned relationship lookup table, and obtain the measurement value of the detection interval according to the difference Δa. Further, the first judgment unit 7230 can be used to determine whether the offset a_os between the measurement value of the detection interval and the preset expected value a_ref is greater than the first threshold value. If so, the first bit result value Sout[0] of the detection result data Sout is set to a valid state (for example, 1, or 0 in other embodiments). If not, the first bit result value Sout[0] of the detection result data is set to an invalid state (for example, 0, or 1 in other embodiments), so that the first bit result value Sout[0] can represent whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range, for the following reasons:

[0125] As described above, the clock signal clk of the ring register link 7100 is a signal to be detected, a frequency-reduced signal of the signal to be detected, a signal to be detected after square wave shaping, or a signal to be detected after square wave shaping and frequency reduction, etc. Therefore, there is a set ratio Ndiv between the frequency of the swept signal provided by the signal source and the frequency of the clock signal clk, and the set ratio is usually a positive real number greater than or equal to 1.

[0126] Assuming that the frequency of the frequency sweep signal SFM in the detection interval is fixed to f0, and the duration of the detection interval is equal to a sampling period Tsample of the sampling clock signal clk_cs, then in the detection interval, the frequency of the clock signal clk is f0 / Ndiv, and the number of times the indication data Dstate provided by the ring register link 7100 is updated in the detection interval is equal to:

[0127] 2*Tsample / [1 / (f0 / N div )]

[0128] However, since the swept frequency signal SFM actually increases linearly in each detection interval, the expected number of times the indication data Dstate output by the ring register link 7100 is updated between every two adjacent sampling points is equal to:

[0129] {2*Tsample / [1 / (F y-1 / N div )]+2*Tsample / [1 / (F y / N div )]} / 2

[0130] Right now:

[0131] Tsample*(F y-1 +F y ) / N div

[0132] Where y is a natural number greater than or equal to 1, Fy and Fy-1 are the expected frequency of the swept frequency signal SFM corresponding to the current sampling point (the current clock edge of the sampling clock signal clk_cs) and the expected frequency of the swept frequency signal SFM corresponding to the adjacent previous sampling point (the next clock edge of the sampling clock signal clk_cs). Fy-1 and Fy correspond to Figure 3 Frequencies F1 and F2 are shown.

[0133] Table 1 shows 16 (i.e., 2n) state values ​​of the ring register chain 7100, taking 8-bit indication data Dstate (i.e., n=8) as an example. In this example, the ring register chain may include 4 levels of registers, and each level of registers corresponds to 2 data bits in the indication data. The ring register chain 7100 outputs 16 times as a cycle and cyclically outputs 16 state values ​​of the indication data Dstate in an output logic sequence, and these 16 state values ​​correspond to sequence numbers 1 to 16 in sequence according to the output logic sequence of the ring register chain 7100.

[0134] According to the above analysis, two adjacent clock edges in the sampling clock signal can define a detection interval. The remainder obtained by dividing the expected number of times the indication data Dstate is updated within the detection interval by 16 can be used to calculate the preset expected value a_ref corresponding to the detection interval. The preset expected value represents the ideal value of the difference Δa calculated by the first judgment unit 7230.

[0135] Based on this, the first judgment unit 7230 can judge whether the offset a_os between the difference Δa (i.e., the measured value) and the preset expected value a_ref is greater than the first threshold. If so, it means that the deviation between the difference Δa and the preset expected value a_ref is too large and exceeds the allowable range determined by the first threshold. At this time, the first judgment unit 7230 can set the first result value Sout[0] of the detection result data Sout to a valid state to indicate that the average value of the frequency of the signal to be detected STST in the detection interval does not meet the expected range, so that the signal source and the radar system can be known to be in an abnormal working state according to the first result value Sout[0] of the valid state; if not, it means that the deviation between the difference Δa and the preset expected value a_ref is within the allowable range determined by the first threshold. At this time, the first judgment unit 7230 can set the first result value Sout[0] of the detection result data Sout to an invalid state to indicate that the average value of the frequency of the signal to be detected STST in the detection interval meets the expected range, so that the signal source and the radar system can be known to be in a normal working state according to the first result value Sout[0] of the invalid state.

[0136] As an optional embodiment, the first judgment unit 7230 may include: a search module, used to search for corresponding sequence numbers a1 and a2 in the storage unit 7220 according to the start value and end value provided by the sampling unit 7210; a calculation module, used to calculate the difference Δa according to the sequence numbers a1 and a2, and calculate the offset between the difference Δa and the preset expected value a_ref; a comparison module, used to compare the offset with the first threshold to generate a first bit result value Sout[0].

[0137] Fig. 9 Show Figure 6 A schematic block diagram of another implementation of the processing circuit in FIG.

[0138] As a further optimized embodiment, Fig. 9 As shown, in addition to the sampling unit 7210, the storage unit 7220 and the first judgment unit 7230 described in the above embodiment, the processing circuit 7200 may further include a second judgment unit 7240. The second judgment unit 7240 is used to provide a second bit result value Sout[1] in the detection result data Sout, so as to further provide detection result information of the signal to be detected.

[0139] like Fig. 9 As shown, the second judgment unit 7240 is used to generate a second result value Sout[1] according to the first result value Sout[0]. The second judgment unit 7240 includes a counter 7241 and a comparator 7242.

[0140] The counter 7241 is used to provide a count value num according to the first result value Sout[0]. When the first result value Sout[0] is in a valid state, the counter 7241 adds 1 to the count value num; and when the first result value Sout[0] received by the counter 7241 is in an invalid state, the counter 7241 resets the count value num to an initial value. Thus, the count value num can represent the number of sampling cycles in which the first result value Sout[0] continuously represents an abnormal working state, that is, the number of sampling cycles in which the frequency of the sweep signal SFM continuously does not meet the preset frequency.

[0141] The comparator 7242 is used to compare the count value num provided by the counter 7241 with the second threshold value max_ref to obtain the second result value Sout[1]. When the count value num is greater than the second threshold value max_ref, the comparator 7242 will output the second result value Sout[1] in a valid state, indicating that the average value of the frequency of the signal to be detected STST in a plurality of consecutive detection intervals / sampling periods exceeding the expected number does not meet the expected range, which means that the signal source and the radar system are in an abnormal working state for a long time and are not easy to recover to normal by themselves; and when the count value num is less than / equal to the second threshold value max_ref, the comparator 7242 outputs the second result value Sout[1] in an invalid state, indicating that the frequency change of the signal to be detected and the related swept frequency signal is in line with expectations.

[0142] In an optional embodiment, the subsequent circuit connected to the comparator 7242 may be triggered by the valid second result value Sout[1] to initiate an early warning prompt, and the early warning prompt includes but is not limited to a sound prompt, a pop-up prompt, an optical prompt, etc. When the second result value Sout[1] is in an invalid state, the subsequent circuit does not need to initiate an early warning prompt.

[0143] The present invention further provides a signal detection device as described in the above embodiments, which is used to determine whether the average value of the frequency of the signal to be detected in each detection interval meets the expected range.

[0144] According to the radar system and signal detection device provided by the embodiment of the present invention, by updating each data bit of the indication data according to the signal edge of the signal to be detected, it is possible to judge whether the average value of the frequency of the signal to be detected in each detection interval meets the expected range according to the starting value and the ending value of the indication data in the detection interval, so as to realize real-time monitoring of the frequency of the signal to be detected. In the radar system of the embodiment of the present invention, since the frequency of the signal to be detected changes proportionally with the swept frequency signal generated by the signal source, the detection result data provided by the signal detection device can be used to indicate whether the signal source and the radar system are in a normal working state.

[0145] In some optional embodiments, the signal detection device can use a sampling clock signal to sample the indication data to obtain the starting value of the indication data at the starting time of the detection interval and the ending value of the indication data at the ending time of the detection interval, and obtain the corresponding measurement value based on the starting value and the ending value, so that it can be judged whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range based on the offset between the measurement value corresponding to each detection interval and the preset expected value, so as to realize real-time monitoring of the frequency of the signal to be detected.

[0146] For example, for a signal source including a phase-locked loop structure, when the calculated offset is less than / equal to the first threshold, it can be determined that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; and in order to improve the accuracy of the judgment, the signal detection device and radar heartache of the embodiment of the present invention can perform judgment processing for multiple detection intervals respectively, and only in all or a preset proportion of the detection intervals, the offset is less than / equal to the above-mentioned first threshold, and at the same time shows a certain regular change or the change amplitude is small, the phase-locked loop structure is judged to be in a normal working state. Among them, the judgment of the change amplitude can be set based on the actual accuracy requirements.

[0147] In addition, for a phase-locked loop structure in an abnormal working state, the signal detection device and radar system disclosed in the embodiment of the present invention can also determine whether the phase-locked loop structure is in a locked state or an unstable state by further analyzing and judging the change law of the offset obtained in different detection intervals (that is, in the embodiment of the present application, the abnormal working state may include a locked state and an unstable state). For example, when the offset obtained in adjacent sampling periods (for example, corresponding to adjacent detection intervals) changes randomly or changes by a large amplitude, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it can be considered that some components in the phase-locked loop structure may be damaged at this time; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

[0148] Fig.10 The flowchart of the signal detection method according to the embodiment of the present invention is shown, which includes steps S810 to S850. The method is applied to the signal detection device and radar system of the above-mentioned embodiments, for example.

[0149] In step S810, a signal to be detected is provided according to the frequency sweep signal, so that the frequency of the signal to be detected and the frequency of the frequency sweep signal are in a set ratio. The frequency of the frequency sweep signal changes linearly within the detection interval, so that the frequency of the signal to be detected also changes linearly within the detection interval.

[0150] In step S820, indication data having a plurality of data bits is provided, and corresponding data bits in the indication data are updated according to the signal edge of the signal to be detected.

[0151] As an optional embodiment, each rising edge and / or each falling edge of the signal to be detected can be used as a signal edge for updating the indication data. Step S820 can include: cyclically updating the value of each data bit of the indication data in turn under the triggering of each signal edge; and updating the value of a corresponding data bit in the indication data under the triggering of each signal edge.

[0152] In step S830, the indication data is sampled at the start time and the end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval, and the measurement value corresponding to the detection interval is obtained according to the start value and the end value.

[0153] In step S840, for each detection interval, a corresponding preset expected value is calculated, and an offset between the measured value corresponding to the detection interval and the preset expected value is obtained.

[0154] In step S850, detection result data is obtained according to the offset to indicate whether the average values ​​of the frequencies of the signal to be detected and the frequency sweep signal within the detection interval meet the expected range.

[0155] It should be noted that the signal detection method provided in the embodiment of the present invention may include the technical details and features proposed in the above description of the signal detection device and radar system of each embodiment, and the same parts will not be repeated here.

[0156] The signal detection method provided by the embodiment of the present invention updates each data bit in the indication data according to the signal edge of the signal to be detected, so as to judge whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range according to the starting value and the ending value of the indication data in the detection interval, so as to realize real-time monitoring of the frequency of the signal to be detected. Since the frequency of the signal to be detected changes in proportion to the swept frequency signal, the detection result data generated by the signal detection method of the embodiment of the present invention can be used to indicate whether the signal source and the radar system are in a normal working state.

[0157] In some optional embodiments, the signal detection method can utilize a sampling clock signal to sample the indication data to obtain a starting value of the indication data at the starting time of the detection interval and an ending value of the indication data at the ending time of the detection interval, and obtain corresponding measurement values ​​based on the starting value and the ending value, so that it is possible to judge whether the average value of the frequency of the signal to be detected within the detection interval meets the expected range based on the offset between the measurement value corresponding to each detection interval and the preset expected value, so as to realize real-time monitoring of the frequency of the signal to be detected.

[0158] It should be noted that, in this article, the term "comprises", "includes" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0159] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A signal detection device, It is characterized in that include: a ring register link, for updating the value of a corresponding data bit in the indication data according to each signal edge of a signal to be detected, wherein the frequency of the signal to be detected changes linearly within a detection interval, and the signal to be detected is a swept frequency signal provided to a transmission channel of a radar system or a frequency-reduced signal of the swept frequency signal; as well as A processing circuit is used to obtain a measurement value according to the starting value and the ending value of the indication data within the detection interval, and to obtain detection result data according to the offset between the measurement value and the preset expected value corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected within the detection interval meets the expected range.

2. The signal detection device according to claim 1, It is characterized in that Each rising edge and / or each falling edge of the signal to be detected is the signal edge, For each of the detection intervals, the ring register chain is adapted to: cyclically updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and The value of a corresponding data bit in the indication data is updated under the triggering of each signal edge.

3. The signal detection device according to claim 1, It is characterized in that The ring register chain includes a plurality of registers cascaded in sequence, each of the registers being used to provide different data bits in the indication data, each of the registers being suitable for providing an output signal of the register at that stage according to the signal to be detected and an input signal of the register, and providing a corresponding data bit in the indication data according to the signal to be detected and the input signal of the register at that stage and / or according to the output signal of the register, Among them, in the plurality of registers cascaded in sequence: The first-stage register obtains the input signal of the first-stage register according to the inverted signal of the output signal provided by the last-stage register; and Each level of registers other than the first level of registers obtains an input signal of the register of that level according to an output signal provided by a register cascaded in the previous level.

4. The signal detection device according to claim 3, It is characterized in that The register at each level updates the corresponding first data bit in the indication data according to the rising edge of the signal to be detected, and updates the corresponding second data bit in the indication data according to the falling edge of the signal to be detected.

5. The signal detection device according to claim 4, It is characterized in that The registers at each level include: A cascaded sampling and holding module chain comprises at least a first-stage sampling and holding module and a second-stage sampling and holding module, wherein the first-stage sampling and holding module samples an input signal of a register of the stage in a sampling state to generate a transfer signal, and the second-stage sampling and holding module samples the transfer signal in a sampling state to generate an output signal of the register of the stage; and a buffer module, providing the first data bit according to the transfer signal, and providing the second data bit according to the output signal, The first-stage sampling and holding module and the second-stage sampling and holding module enter the sampling state alternately according to the level state of the signal to be detected.

6. The signal detection device according to claim 1, It is characterized in that The detection result data includes a first bit result value, and the processing circuit includes: a sampling unit, configured to sample the indication data at a start time and an end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval; a storage unit, configured to pre-store a relational lookup table to indicate sequence numbers corresponding to a plurality of state values ​​of the indication data in an output logic order of the ring register link, the plurality of state values ​​including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judging unit, configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and to judge whether the offset is greater than a first threshold value, If yes, the first judgment unit sets the first bit result value to a valid state to indicate that the average value of the frequency of the signal to be detected within the detection interval does not meet the expected range. If not, the first judgment unit sets the first bit result value to an invalid state to indicate that the average value of the frequency of the signal to be detected within the detection interval meets the expected range.

7. The signal detection device according to claim 6, It is characterized in that The preset expected value is: a data value obtained by calculating based on the total number of the multiple state values ​​and the expected number of occurrences of the signal edge of the to-be-detected signal within the detection interval.

8. The signal detection device according to claim 7, It is characterized in that For each of the detection intervals: The measured value is equal to the difference, The preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, The set value is equal to the product of the expected average value of the frequency of the signal to be detected within the detection interval and the duration of the detection interval.

9. The signal detection device according to claim 6, It is characterized in that The processing circuit further comprises: a counter for providing a count value according to the first-bit result value, the counter being responsive to the first-bit result value in a valid state to increase the count value by 1, and being responsive to the first-bit result value in an invalid state to reset the count value to an initial value; and a comparator, configured to determine whether the count value is greater than a second threshold, If yes, the comparator sets the second bit result value of the detection result data to a valid state to indicate that the frequency change of the signal to be detected is in an abnormal state. If not, the comparator sets the second bit result value to an invalid state to indicate that the frequency change of the signal to be detected is in a normal state.

10. The signal detection device according to claim 1, It is characterized in that The signal to be detected is a frequency modulated continuous wave signal with a frame period, the signal to be detected changes linearly in a linear interval of each frame period and is reset to an initial level in a waiting interval of each frame period, and each detection interval is included in a corresponding linear interval. For each of the detection intervals, the processing circuit samples the signal to be detected according to the sampling clock signal to obtain the starting value and the ending value of the indication data in the detection interval, and the starting time and the ending time of the detection interval correspond to two adjacent and same-direction clock edges in the sampling clock signal respectively.

11. The signal detection device according to claim 1, It is characterized in that The signal detection device also includes: A frequency reduction circuit, cascaded before the ring register link, for reducing the frequency of the signal to be detected according to a set frequency division ratio; and / or A shaping circuit, cascaded before the ring register link, is used to shape the signal to be detected into a square wave, The ring register link provides the indication data according to the signal to be detected after downconversion, or the signal to be detected after shaping, or the signal to be detected after downconversion and shaping.

12. A signal detection method, It is characterized in that include: Providing a signal to be detected, wherein the frequency of the signal to be detected changes linearly within a detection interval; Providing indication data having a plurality of data bits, and updating corresponding data bits in the indication data according to a signal edge of the signal to be detected; Sampling the indication data at the start time and the end time of the detection interval to obtain a start value and an end value of the indication data within the detection interval; as well as For each of the detection intervals, a measurement value is obtained according to the start value and the end value of the indication data in the detection interval, and a detection result data is obtained according to the offset between the preset expected value corresponding to the detection interval and the measurement value. The detection result data indicates whether the average value of the frequency of the signal to be detected within the detection interval meets the expected range.

13. The signal detection method according to claim 12, It is characterized in that Each rising edge and / or each falling edge of the signal to be detected is the signal edge, and the step of updating the corresponding data bit in the indication data according to the signal edge of the signal to be detected comprises: cyclically updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and The value of a corresponding data bit in the indication data is updated under the triggering of each signal edge.

14. The signal detection method according to claim 12, It is characterized in that For each of the detection intervals, the steps of obtaining a measurement value according to the starting value and the ending value of the indication data in the detection interval, and obtaining the detection result data according to the offset between the preset expected value corresponding to the detection interval and the measurement value include: Obtaining a relational lookup table, the relational lookup table indicating sequence numbers respectively corresponding to a plurality of state values ​​of the indication data in an output logical order, the plurality of state values ​​including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; Obtaining the measurement value according to the difference between the first sequence number and the second sequence number; determining whether the offset is greater than a first threshold, If yes, then the first result value of the detection result data is set to a valid state to indicate that the average value of the frequency of the signal to be detected within the detection interval does not meet the expected range, If not, the first bit result value is set to an invalid state to indicate that the average value of the frequency of the signal to be detected within the detection interval meets the expected range.

15. The signal detection method according to claim 14, It is characterized in that Also includes: The preset expected value is obtained by calculation based on the total number of the multiple state values ​​and the expected number of occurrences of the signal edge of the to-be-detected signal within the detection interval.

16. The signal detection method according to claim 15, It is characterized in that For each of the detection intervals: The measured value is equal to the difference, The preset expected value is equal to the remainder obtained by dividing twice the set value corresponding to the detection interval by the total number of the multiple state values, The set value is equal to the product of a preset frequency average value of the signal to be detected within the detection interval and a duration of the detection interval.

17. The signal detection method according to claim 15, It is characterized in that For each of the detection intervals, the step of obtaining a measurement value according to the starting value and the ending value of the indication data in the detection interval, and obtaining the detection result data according to the offset between the preset expected value corresponding to the detection interval and the measurement value also includes: Providing a count value according to the first result value, and adding 1 to the count value when the first result value is in a valid state, and restoring the count value to an initial value when the first result value is in an invalid state; and determining whether the count value is greater than a second threshold, If yes, then the second bit result value of the detection result data is set to a valid state to indicate that the frequency change of the signal to be detected is in an abnormal state. If not, the second bit result value is set to an invalid state to indicate that the frequency change of the signal to be detected is in a normal state.

18. The signal detection method according to claim 12, It is characterized in that The signal to be detected changes linearly in a linear interval of each frame period and is reset to an initial level in a waiting interval of each frame period, each detection interval is included in the corresponding linear interval, and the step of obtaining the starting value and the ending value of the indication data in the detection interval includes: The signal to be detected is sampled according to a sampling clock signal to obtain the starting value and the ending value of the indication data in the detection interval, and the starting time and the ending time of the detection interval correspond to adjacent and same-direction clock edges in the sampling clock signal respectively.

19. The signal detection method according to claim 12, It is characterized in that The step of providing the signal to be detected and the indication data comprises: Down-converting the signal to be detected according to a set frequency division ratio; and / or The signal to be detected is shaped into a square wave, The indication data is generated according to the signal to be detected after frequency reduction, or the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

20. A radar system, It is characterized in that include: A phase-locked loop structure, comprising a voltage-controlled oscillator, the voltage-controlled oscillator generating a frequency sweep signal according to a frequency control voltage, the frequency of the frequency sweep signal varying with the voltage value of the frequency control voltage; The signal detection device according to any one of claims 1 to 11, used to use the swept frequency signal or the clock signal as the signal to be detected, the frequency of the clock signal being in a set ratio to the frequency of the swept frequency signal; and The radar transceiver provides a transmission signal and / or processes an echo signal according to the frequency sweep signal.

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