Display device

Abstract

The present disclosure relates to a display device, comprising: a lower pattern disposed on a substrate; an active pattern disposed on the lower pattern; a driving voltage line connected to the source region of the active pattern; and a pixel electrode connected to the drain region of the active pattern. The active pattern comprises a source region, a channel region and a drain region, and the channel region of the active pattern overlaps with the lower pattern in a plan view. The driving voltage line overlaps with the lower pattern to form a first capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0120303 filed on October 10, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device; more particularly, to a display device having a capacitor formed by at least a driving voltage line. Background Art

[0004] A display device is a device for displaying an image, and recently, a light emitting diode display has attracted attention as a self-luminous display device.

[0005] Unlike liquid crystal displays, light emitting diode displays have self-luminous properties without a separate light source, so the thickness and weight of the light emitting diode display can be reduced. In addition, the light emitting diode display exhibits high quality characteristics such as low power consumption, high brightness and high response speed.

[0006] Generally, a light emitting diode display includes a substrate, a plurality of thin film transistors disposed on the substrate, a plurality of insulating layers disposed between wirings constituting the thin film transistors, and a light emitting device connected to the thin film transistors. For example, the light emitting device may include an organic light emitting element.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore the above information may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0008] The present disclosure is directed to providing a display device capable of improving image quality.

[0009] According to an exemplary embodiment of the present inventive concept, a display device includes: a lower pattern, the lower pattern is disposed on a substrate; an active pattern, the active pattern is disposed on the lower pattern; a driving voltage line, the driving voltage line is connected to the source region of the active pattern; and a pixel electrode, the pixel electrode is connected to the drain region of the active pattern. The active pattern includes a source region, a channel region, and a drain region, and in a plan view, the channel region of the active pattern overlaps with the lower pattern. The driving voltage line overlaps with the lower pattern to form a first capacitor.

[0010] According to an exemplary embodiment of the inventive concept, a display device includes: a first conductive layer, the first conductive layer including a lower pattern on a substrate; a first insulating layer, the first insulating layer is on the first conductive layer; an active pattern, the active pattern is disposed on the first insulating layer and includes a source region, a channel region and a drain region; a second conductive layer, the second conductive layer is disposed on the active pattern and includes a gate electrode overlapping the channel region; a second insulating layer, the second insulating layer is disposed on the second conductive layer; a third conductive layer, the third conductive layer is disposed on the second insulating layer and includes a driving voltage line and a data line separated from the driving voltage line; a third insulating layer, the third insulating layer is disposed on the third conductive layer; a pixel electrode layer, the pixel electrode layer includes a first pixel electrode disposed on the third insulating layer; a fourth conductive layer, the fourth conductive layer is disposed between the third insulating layer and the pixel electrode layer; and a fourth insulating layer, the fourth insulating layer is disposed between the fourth conductive layer and the pixel electrode layer. The fourth conductive layer includes a first contact member disposed on an end of the data line to contact the end.

[0011] According to an exemplary embodiment of the present invention, a display device includes: a first scan line and a second scan line; a driving gate electrode, the driving gate electrode is arranged between the first scan line and the second scan line; a data line, a driving voltage line, an initialization voltage line and a common voltage line, the data line, the driving voltage line, the initialization voltage line and the common voltage line intersecting the first scan line and the second scan line; a first transistor, the first transistor being electrically connected to the driving voltage line and the driving gate electrode; a second transistor, the second transistor being electrically connected to the first scan line and the data line; a third transistor, the third transistor being electrically connected to the second scan line, the first transistor and the initialization voltage line; a capacitor electrode, the capacitor electrode being electrically connected to a drain region of the first transistor; a light emitting diode (LED), the light emitting diode (LED) being electrically connected to the capacitor electrode; and a lower pattern, in a plan view, the lower pattern overlapping with a channel region of the first transistor. The lower pattern is electrically connected to the capacitor electrode, and in the plan view, the lower pattern overlaps with at least one of the driving voltage line, the initialization voltage line and the common voltage line to form a first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a circuit diagram of one pixel of a display device according to an exemplary embodiment,

[0013] Figure 2 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment,

[0014] Figure 3 It is taken along line IIIa-IIIb Figure 2 A cross-sectional view of a display device shown in FIG.

[0015] Figure 4 It is taken along line IVa-IVb and line IVb-IVc Figure 2 A cross-sectional view of a display device shown in FIG.

[0016] Figure 5 It is taken along the line Va-Vb Figure 2 A cross-sectional view of a display device shown in FIG.

[0017] Figure 6 It is taken along the line Va-Vb Figure 2 Another exemplary cross-sectional view of a display device shown in FIG.

[0018] Figure 7 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment,

[0019] Figure 8 It is taken along line VIIIa-VIIIb Figure 7 A cross-sectional view of a display device shown in FIG.

[0020] Fig. 9 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment,

[0021] Fig.10 and Fig.11 They are taken along line IIIa-IIIb. Figure 2 A cross-sectional view of a display device shown in FIG.

[0022] Fig.12 and Fig.13 1 and 2 are plan layout diagrams of a plurality of pixels of a display device according to exemplary embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0024] The drawings and description are to be regarded as illustrative in nature and not restrictive, and like reference numerals refer to like elements throughout the specification.

[0025] In addition, in the drawings, the size and thickness of each element are arbitrarily shown for the convenience of description, and the present invention is not necessarily limited to the size and thickness of each element shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for the sake of clarity. In the drawings, the thickness of layers and regions are exaggerated for the convenience of description.

[0026] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean being positioned on an object portion or being positioned below an object portion, and do not necessarily mean being positioned on the upper side of an object portion based on the direction of gravity.

[0027] In addition, unless explicitly described to the contrary, the word “comprise” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0028] Throughout this specification and the claims that follow, a plan view indicates a view when observing a surface parallel to two directions (e.g., direction DR1 and direction DR2) that intersect each other, and a cross-sectional view indicates a view when observing a surface taken in a direction (e.g., direction DR3) perpendicular to the surface parallel to directions DR1 and DR2. In addition, unless otherwise specified, overlapping with two constituent elements indicates that the two constituent elements overlap in direction DR3 (e.g., a direction perpendicular to the upper surface of the substrate).

[0029] Figure 1 is a circuit diagram of one pixel of a display device according to an exemplary embodiment.

[0030] Reference Figure 1 According to an exemplary embodiment, the display device includes a plurality of pixels, and one pixel includes a plurality of transistors T1, T2, and T3, a storage capacitor Cst, and at least one light emitting diode (LED) ED. In the present exemplary embodiment, an example in which one pixel includes one light emitting diode (LED) ED is described.

[0031] The plurality of transistors T1, T2 and T3 include first, second and third transistors T1, T2 and T3. The terms source electrode and drain electrode described below are to distinguish two electrodes provided at respective sides of a channel of each of the transistors T1, T2 and T3, and the two terms may be used interchangeably.

[0032] A gate electrode G1 of the first transistor T1 is connected to a first terminal of a storage capacitor Cst, a source electrode S1 of the first transistor T1 is connected to a driving voltage line transmitting a driving voltage ELVDD, and a drain electrode D1 of the first transistor T1 is connected to an anode of a light emitting diode (LED) ED and a second terminal of the storage capacitor Cst. The first transistor T1 may receive a data voltage DAT according to a switching operation of the second transistor T2 to charge the storage capacitor Cst, and may then provide a driving current to the light emitting diode (LED) ED according to a voltage stored in the storage capacitor Cst.

[0033] The gate electrode G2 of the second transistor T2 is connected to the first scan line transmitting the first scan signal SC, the source electrode S2 of the second transistor T2 is connected to the data line transmitting the data voltage DAT or the reference voltage, and the drain electrode D2 of the second transistor T2 is connected to the first terminal of the storage capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 may be turned on according to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and the first terminal of the storage capacitor Cst.

[0034] The gate electrode G3 of the third transistor T3 is connected to the second scan line transmitting the second scan signal SS, the source electrode S3 of the third transistor T3 is connected to the second terminal of the storage capacitor Cst, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode (LED) ED, and the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line transmitting the initialization voltage INIT. The third transistor T3 can be turned on according to the second scan signal SS to transmit the initialization voltage INIT to the anode of the light emitting diode (LED) ED and the second terminal of the storage capacitor Cst, thereby initializing the voltage of the anode of the light emitting diode (LED) ED.

[0035] A first terminal of the storage capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and a second terminal of the storage capacitor Cst is connected to the source electrode S3 of the third transistor T3 and an anode of the light emitting diode (LED) ED. A cathode of the light emitting diode (LED) ED is connected to a common voltage line transmitting a common voltage ELVSS.

[0036] The display device further includes a driving voltage line ( Figure 2172a) between the holding capacitor Ced. For example, a first terminal of the holding capacitor Ced is electrically connected to the anode of the light emitting diode (LED) ED, and a second terminal of the holding capacitor Ced is electrically connected to a driving voltage line, which is electrically connected to the source electrode S1 of the first transistor T1. In an exemplary embodiment, the holding capacitor Ced can be used to minimize any fluctuations in the voltage at the anode of the light emitting diode (LED) ED, thereby keeping the voltage at the anode constant.

[0037] The light emitting diode (LED) ED may emit light according to the driving current of the first transistor T1.

[0038] Will describe Figure 1 , specifically, an example of operation during one frame will be described. In this example, transistors T1, T2, and T3 are N-channel transistors. The inventive concept is not limited thereto. For example, transistors T1, T2, and T3 may be P-channel transistors.

[0039] For ease of description, a frame may start with an initialization period, during which a high-level first scan signal SC and a high-level second scan signal SS are provided to turn on the second transistor T2 and the third transistor T3. A reference voltage from a data line is supplied to the gate electrode G1 of the first transistor T1 and the first terminal of the storage capacitor Cst through the turned-on second transistor T2, and an initialization voltage INIT is supplied to the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode (LED) ED through the turned-on third transistor T3. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode (LED) ED are initialized to the initialization voltage INIT. At this time, the storage capacitor Cst stores the voltage difference between the reference voltage and the initialization voltage INIT.

[0040] Next, in the sensing period of the first scanning signal SC during which the second scanning signal SS becomes low level, remains at low level and remains at high level, the second transistor T2 remains in the on state, and the third transistor T3 is turned off. The gate electrode G1 of the first transistor T1 and the first terminal of the storage capacitor Cst maintain the reference voltage through the turned-on second transistor T2, and the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode (LED) ED are disconnected from the initialization voltage INIT through the turned-off third transistor T3. Therefore, when the current flows from the source electrode S1 to the drain electrode D1, the first transistor T1 is turned off, and then the voltage of the drain electrode D1 becomes the "threshold voltage Vth". Vth represents the threshold voltage of the first transistor T1. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the storage capacitor Cst, and the sensing of the threshold voltage Vth of the first transistor T1 is completed. By generating a data signal compensated by reflecting the sensed characteristic information during the sensing period, the characteristic deviation of the first transistor T1, which may be different for each pixel, can be compensated from the outside.

[0041] Next, in the data input period during which the high-level first scan signal SC is supplied and the low-level second scan signal SS is supplied, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from the data line is supplied to the first terminal of the storage capacitor Cst and the gate electrode G1 of the first transistor T1 via the turned-on second transistor T2. In this case, the anode of the light emitting diode (LED) ED and the drain electrode D1 of the first transistor T1 can substantially maintain the potential in the sensing period through the first transistor T1 in the turned-off state.

[0042] Next, in a light emitting period during which the first transistor T1 turned on by the data voltage DAT transmitted to the gate electrode G1 generates a driving current according to the data voltage DAT, the light emitting diode (LED) ED may emit light by the driving current.

[0043] Figure 2 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment, Figure 3 It is taken along line IIIa-IIIb Figure 2 A cross-sectional view of a display device shown in FIG. Figure 4 It is taken along line IVa-IVb and line IVb-IVc Figure 2 A cross-sectional view of a display device shown in FIG. Figure 5 It is taken along the line Va-Vb Figure 2 A cross-sectional view of a display device shown in FIG. Figure 6 It is taken along the line Va-Vb Figure 2 Another exemplary cross-sectional view of a display device shown in FIG.

[0044] For example, the display device 1000 may include three pixels PX1, PX2, and PX3. In a plan view, each of the three pixels PX1, PX2, and PX3 may be defined in a region in which a pixel is provided for each of the pixels PX1, PX2, and PX3. Figure 1 The plurality of transistors T1, T2 and T3 and the storage capacitor Cst are provided. For each of the pixels PX1, PX2 and PX3, the light emitting area may be defined as the area in which light is emitted. Figure 1 For example, the light emitting area of ​​each pixel in pixels PX1, PX2 and PX3 is the same as that located at Figure 2 On the layout Figure 1 The pixel electrodes of the corresponding light emitting diodes (LEDs) ED overlap. In an exemplary embodiment, the light emitting regions of the three pixels PX1, PX2, and PX3 may emit red light, green light, and blue light, respectively. The area of ​​the pixel electrode 191b, the area of ​​the pixel electrode 191a, and the area of ​​the pixel electrode 191c may be reduced in the order of the area of ​​the pixel electrode 191b, the area of ​​the pixel electrode 191a, and the area of ​​the pixel electrode 191c.

[0045] The display device 1000 according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material such as glass, plastic, etc., and may have flexibility.

[0046] A barrier layer as an insulating layer may be disposed on the substrate 110, and a lower layer including a plurality of lower patterns 111a, 111b, and 111c as a first conductive layer may be disposed on the barrier layer. The lower layer may be conductive. For example, the lower layer may include a semiconductor material including various conductive metals or having equivalent conductive properties.

[0047] The buffer layer 120 is disposed on the lower layer. The buffer layer 120 may include an insulating layer. The lower layer may be disposed between the substrate 110 and the buffer layer 120.

[0048] An active layer including a plurality of active patterns 130a, 130b, and 130c is disposed on the buffer layer 120. A lower layer may be disposed between the substrate 110 and the active layer. The active patterns 130a, 130b, and 130c may be disposed in the pixels PX1, PX2, and PX3, respectively, and may include channel regions 134a, 134b, and 134c, respectively. The channel regions 134a, 134b, and 134c may form channels of the transistors T1, T2, and T3, respectively, as described above. Each of the active patterns 130a, 130b, and 130c may also include a conductive region connected to the corresponding channel of the transistors T1, T2, and T3. For example, the conductive regions of the active patterns 130a, 130b, and 130c include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of each of the transistors T1, T2, and T3. The active pattern 130a of the first transistor T1 and the active pattern 130c of the third transistor T3 may be connected to each other.

[0049] The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0050] The insulating pattern 144 of the first insulating layer is disposed on the active layer. Specifically, the insulating pattern 144 may overlap with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and may be disposed on the channel regions 134a, 134b, and 134c. The insulating pattern 144 need not substantially overlap with the conductive regions of the active patterns 130a, 130b, and 130c.

[0051] The second conductive layer may be disposed on the insulating pattern 144. The second conductive layer may include a first scan line 151 transmitting the first scan signal SC as described above, a second scan line 152 transmitting the second scan signal SS, a horizontal initialization voltage line 153 transmitting the initialization voltage INIT, a horizontal driving voltage line 172b transmitting the driving voltage ELVDD, a driving gate electrode 155, a first gate electrode 154a, a second gate electrode 154b, a third gate electrode 154c connected to the driving gate electrode 155, etc. The gate electrode G1, the gate electrode G2, and the gate electrode G3 in the above circuit diagram correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c, respectively.

[0052] The first scan line 151 and the second scan line 152, the transverse initialization voltage line 153, and the transverse driving voltage line 172b may extend in the first direction DR1. The driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152. The second gate electrode 154b is connected to the first scan line 151 and may have a shape protruding downward from the first scan line 151. The third gate electrode 154c is connected to the second scan line 152 and may have a shape protruding upward from the second scan line 152.

[0053] The driving gate electrode 155 provided in each of the pixels PX1, PX2, and PX3 may include an extension portion 155a protruding upward and extending approximately in the second direction DR2. In the first pixel PX1 and the second pixel PX2, the first gate electrode 154a may protrude downward from the driving gate electrode 155 and extend approximately in the second direction DR2. In the third pixel PX3, the first gate electrode 154a may be folded at least twice at a portion connected to the driving gate electrode 155. For example, unlike in the first pixel PX1 and the second pixel PX2, the first gate electrode 154a of the third pixel PX3 may be tilted downward from the driving gate electrode 155 and then protrude downward in the second direction DR2.

[0054] The first gate electrode 154a intersects the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b intersects the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c intersects the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

[0055] The second insulating layer 160 may be disposed on the second conductive layer. The buffer layer 120 and / or the second insulating layer 160 may include a plurality of contact holes 24 , 26 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 , and 69 .

[0056] The third conductive layer may be disposed on the second insulating layer 160. The third conductive layer may include a plurality of data lines 171a, 171b, and 171c, a driving voltage line 172a, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, a plurality of connection members 174, 176, 177, and 178, and a plurality of driving voltage patterns 172c and 172d.

[0057] The data lines 171 a , 171 b , and 171 c , the driving voltage line 172 a , the common voltage line 170 , the initialization voltage line 173 , and the driving voltage patterns 172 c and 172 d extend substantially in the second direction DR2 to be elongated, thereby crossing the first scan line 151 and / or the second scan line 152 .

[0058] As a group in Figure 2 The plurality of pixels PX1, PX2, and PX3 repeated in the first direction DR1 may be arranged adjacent to each other in the first direction DR1. The common voltage line 170 may be disposed at both the right and left sides of the plurality of pixels PX1, PX2, and PX3 of a group. That is, for each pixel of the plurality of pixels PX1, PX2, and PX3 of a repeating group, a common voltage line 170 may be formed. When the plurality of pixels PX1, PX2, and PX3 of a repeating group includes three pixels PX1, PX2, and PX3, the data lines 171a, 171b, and 171c, at least one driving voltage line 172a, and at least one initialization voltage line 173 may be disposed between two adjacent common voltage lines 170.

[0059] Each of the data lines 171a, 171b, and 171c passes through at least one contact hole 64 ( Figure 2 Two contact holes 64 in each pixel PX1, PX2, and PX3 are shown to be electrically connected to the source region 133b of the active pattern 130b.

[0060] Figure 2 An end portion 179 of one data line 171 a is shown, but each of the data lines 171 a , 171 b , and 171 c may include such an end portion. The end portion 179 may be disposed in a pad region disposed at an edge of the display device 1000 .

[0061] The driving voltage line 172a extends through the first pixel PX1 in the second direction DR2. The driving voltage patterns 172c and 172d may overlap with the second pixel PX2. The driving voltage pattern 172d partially overlaps with the third pixel PX3. For example, the driving voltage line 172a overlaps with the pixel electrode 191a of the first pixel PX1; the driving voltage pattern 172c may overlap with the pixel electrode 191b of the second pixel PX2; and the driving voltage pattern 172d overlaps with both the pixel electrode 191b of the second pixel PX2 and the pixel electrode 191c of the third pixel PX3. The driving voltage pattern 172d overlaps with the pixel electrode 191b of the pixel PX2 without being electrically connected to the first transistor T1 of the second pixel PX2. Instead, the driving voltage pattern 172d may be electrically connected to the first transistor T1 of the third pixel PX3. The driving voltage line 172a may extend through the first pixel PX1 in the second direction DR2. The driving voltage patterns 172c and 172d may partially extend into the second pixel PX2 without crossing the second pixel PX2. Similar to the data line 171a, the driving voltage line 172a may include an end portion 172e disposed in a pad region.

[0062] The driving voltage line 172a and the driving voltage patterns 172c and 172d pass through at least one contact hole 61 ( Figure 2 The two contact holes 61 of the pixels PX1 and PX2 and one contact hole 61 of the pixel PX3 are shown to be electrically connected to the source region 133a of the active pattern 130a. In addition, the driving voltage line 172a and the driving voltage patterns 172c and 172d are formed through at least one contact hole 60( Figure 2 Two contact holes 60 of each pixel PX1, PX2, and PX3 are shown to be electrically connected to the transverse driving voltage line 172b. Therefore, the transverse driving voltage line 172b and the driving voltage patterns 172c and 172d can transmit the driving voltage ELVDD together with the driving voltage line 172a, and the driving voltage ELVDD in the entire display device 1000 can be transmitted in a grid shape in both the first direction DR1 and the second direction DR2.

[0063] The initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 153 through the contact hole 69 of the second insulating layer 160. For example, the horizontal initialization voltage line 153 is used so that the initialization voltage line 173 is shared by the three pixels PX1, PX2 and PX3. The horizontal initialization voltage line 153 can transmit the initialization voltage INIT together with the initialization voltage line 173. For example, for each of the three pixels PX1, PX2 and PX3, the initialization voltage line 173 is formed. The initialization voltage INIT received by the initialization voltage line 173 can be transmitted to all the pixels PX1, PX2 and PX3 through the horizontal initialization voltage line 153.

[0064] The capacitor electrode 175 may be disposed within each pixel PX1, PX2, and PX3. The capacitor electrode 175 may overlap a majority of the corresponding driving gate electrode 155, and the second insulating layer 160 may be disposed between the capacitor electrode 175 and the driving gate electrode 155. For example, the capacitor electrode 175 may have a maximum width greater than a maximum width of the driving gate electrode 155. The maximum width of each of the capacitor electrode 175 and the driving gate electrode 155 may be measured in the first direction DR1. The capacitor electrode 175, the driving gate electrode 155, and the second insulating layer 160 disposed between the capacitor electrode 175 and the driving gate electrode 155 may form a storage capacitor Cst.

[0065] The capacitor electrode 175 may include a portion having a maximum width measured in the first direction DR1 and a connection portion 175a having a width smaller than the maximum width of the capacitor electrode 175. The connection portion 175a may protrude downward from the portion of the capacitor electrode 175 having the maximum width of the capacitor electrode 175. The connection portion 175a passes through at least one contact hole 62 ( Figure 2Three contact holes 62 of each pixel PX1, PX2 and PX3 are shown to be electrically connected to the drain region 135a of the active pattern 130a and the source region 133c of the active pattern 130c connected to the drain region 135a. In addition, the capacitor electrode 175 is electrically connected to the lower pattern 111a via the contact hole 68 of the second insulating layer 160 and the buffer layer 120.

[0066] The connecting member 174 is electrically connected to the second scan line 152 and the lower pattern 111c via the two contact holes 24 of the buffer layer 120 and the second insulating layer 160, or the connecting member 174 is electrically connected to the second scan line 152 and the lower pattern 111c only via the two contact holes 24 of the second insulating layer 160, so that the second scan line 152 can be electrically connected to the lower pattern 111c.

[0067] The connecting member 176 is electrically connected to the first scan line 151 and the lower pattern 111b via the two contact holes 26 of the buffer layer 120 and the second insulating layer 160, or the connecting member 176 is electrically connected to the first scan line 151 and the lower pattern 111b only via the two contact holes 26 of the second insulating layer 160, so that the first scan line 151 can be electrically connected to the lower pattern 111b.

[0068] In each of the pixels PX1, PX2, and PX3, the connection member 177 is connected via at least one contact hole 63 ( Figure 2 It is shown that two contact holes 63 in each pixel PX1, PX2 and PX3 are electrically connected to the drain region 135c of the active pattern 130c, and are electrically connected to the horizontal initialization voltage line 153 via the contact hole 67 of the second insulating layer 160, so that the drain region 135c of the active pattern 130c can be electrically connected to the horizontal initialization voltage line 153.

[0069] The transverse initialization voltage line 153 extends in the first direction DR1 through the three pixels PX1, PX2, and PX3, however, the transverse initialization voltage line 153 may be disposed between two adjacent common voltage lines 170 without crossing the two common voltage lines 170. The transverse initialization voltage line 153 crosses the three adjacent data lines 171a, 171b, and 171c, and may extend only to the initialization voltage line 173.

[0070] In each of the pixels PX1, PX2, and PX3, the connection member 178 is connected via at least one contact hole 65 ( Figure 2It is shown that two contact holes 65) in each pixel PX1, PX2 and PX3 are electrically connected to the drain region 135b of the active pattern 130b, and are electrically connected to the extension 155a of the driving gate electrode 155 via the contact hole 66 of the second insulating layer 160, so that the drain region 135b of the active pattern 130b and the extension 155a of the driving gate electrode 155 can be electrically connected to each other.

[0071] At least one of the first conductive layer, the second conductive layer, and the third conductive layer may include at least one of metals (e.g., copper, aluminum, magnesium, silver, gold, platinum, palladium, nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum, and alloys thereof, etc.). Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a single layer or a plurality of layers.

[0072] For example, the third conductive layer may have a multi-layer structure including a lower layer including titanium and an upper layer including copper.

[0073] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to the driving voltage line 172a and the driving voltage patterns 172c and 172d to receive the driving voltage ELVDD.

[0074] The lower pattern 111a corresponding to the first transistor T1 overlaps the channel region 134a of the first transistor T1 and is disposed between the channel region 134a of the first transistor T1 and the substrate 110. The lower pattern 111a may be used to prevent external light from reaching the channel region 134a, thereby reducing leakage current and characteristic degradation. The lower pattern 111a is electrically connected to the drain region 135a of the first transistor T1 through the capacitor electrode 175.

[0075] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to the data lines 171a, 171b, and 171c to receive the data voltage DAT or the reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

[0076] The lower pattern 111b corresponding to the second transistor T2 overlaps the channel region 134b and is disposed between the channel region 134b of the second transistor T2 and the substrate 110 to prevent external light from reaching the channel region 134b, thereby reducing leakage current and characteristic degradation. Because the lower pattern 111b is electrically connected to the first scan line 151, the lower pattern 111b can be used together with the second gate electrode 154b as a double gate electrode of the second transistor T2. For example, the second gate electrode 154b and the lower pattern 111b can be used as a top gate electrode of the second transistor T2 and a bottom gate electrode of the second transistor T2, respectively.

[0077] The third transistor T3 includes a channel region 134 c , a source region 133 c , a drain region 135 c , and a third gate electrode 154 c . The drain region 135 c of the third transistor T3 may receive an initialization voltage INIT from the lateral initialization voltage line 153 .

[0078] The lower pattern 111c corresponding to the third transistor T3 overlaps the channel region 134c and is disposed between the channel region 134c of the third transistor T3 and the substrate 110 to prevent external light from reaching the channel region 134c, thereby reducing leakage current and characteristic degradation. Because the lower pattern 111c is electrically connected to the second scan line 152, the lower pattern 111c can be used together with the third gate electrode 154c as a double gate electrode of the third transistor T3. For example, the third gate electrode 154c and the lower pattern 111c can be used as a top gate electrode of the third transistor T3 and a bottom gate electrode of the third transistor T3, respectively.

[0079] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer. The third insulating layer 181 may include a contact hole 83a disposed on the capacitor electrode 175, a contact hole 89a disposed on the end portion 179 of the data lines 171a, 171b and 171c, and a contact hole 81 disposed on the common voltage line 170.

[0080] A fourth conductive layer including a plurality of contact members 190 a , 190 b , 190 c , 190 d , and 190 e may be disposed on the third insulating layer 181 .

[0081] Contact members 190a, 190b, and 190c may be respectively disposed in pixels PX1, PX2, and PX3 and contact the capacitor electrode 175 via the contact hole 83a so as to be electrically connected to the capacitor electrode 175. Contact member 190d may contact the common voltage line 170 via the contact hole 81 so as to be electrically connected to the common voltage line 170. Contact member 190e may contact end portions 179 of data lines 171a, 171b, and 171c via the contact hole 89a so as to be electrically connected to the end portions 179 of the data lines 171a, 171b, and 171c.

[0082] The contact members 190a, 190b, 190c, 190d and 190e can increase the adhesion of the capacitor electrode 175 of the third conductive layer, the common voltage line 170 and the end 179 of the data lines 171a, 171b and 171c, which are in contact with the contact members 190a, 190b, 190c, 190d and 190e, to other conductive layers, and can prevent oxidation of the third conductive layer. Specifically, when the upper layer of the third conductive layer includes copper, oxidation of copper can be prevented. To this end, when the upper layer of the third conductive layer includes a conductive material for preventing corrosion of the upper layer of the third conductive layer (e.g., copper), the fourth conductive layer may include a conductive material for preventing corrosion of copper by covering the upper layer of the third conductive layer. For example, the fourth conductive layer may include a conductive material of a metal oxide (e.g., ITO and IZO, etc.).

[0083] The fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer. The fourth insulating layer 182 may include a contact hole 83b disposed on each of the contact members 190a, 190b, and 190c and overlapping with the contact hole 83a, and a contact hole 89b disposed on the contact member 190e and overlapping with the contact hole 89a. The fifth insulating layer 350 on the fourth insulating layer 182 may include an opening 356 connected to the contact hole 89b.

[0084] The contact member 190e can be exposed to the outside by the contact hole 89b, so that it can be electrically contacted with a separate driving circuit chip, a circuit film or a circuit board. For example, the contact member 190e can be exposed to the outside by the contact hole 89b and the opening 356 connected to each other, so that the contact member 190e can be electrically connected to an external device.

[0085] At least one of the buffer layer 120, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiON) and / or an organic insulating material. Specifically, the fourth insulating layer 182 may include an inorganic insulating material and / or an organic insulating material such as polyimide, an acrylic polymer or a siloxane polymer, and may have a substantially flat upper surface.

[0086] On the fourth insulating layer 182, a pixel electrode layer including a plurality of pixel electrodes 191a, 191b, and 191c may be provided as a fifth conductive layer. Figure 2As shown, each pixel electrode 191a, 191b and 191c can be set to correspond to each pixel PX1, PX2 and PX3. The plane size and shape of the pixel electrodes 191a, 191b and 191c arranged in three adjacent pixels PX1, PX2 and PX3 can be different from each other, but this is not restrictive. For example, in three pixels PX1, PX2 and PX3, the plane size of the pixel electrode 191b, the pixel electrode 191a and the pixel electrode 191c can be reduced in the order of the pixel electrode 191b, the pixel electrode 191a and the pixel electrode 191c. In this case, the pixel PX2 can represent green, the pixel PX1 can represent red, and the pixel PX3 can represent blue.

[0087] Each pixel electrode 191a, 191b, and 191c may contact each contact member (contact member) 190a, 190b, and 190c through the contact hole 83b, and be electrically connected to the capacitor electrode 175 through the contact members 190a, 190b, and 190c. Therefore, each pixel electrode 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1, thereby receiving a voltage from the first transistor T1.

[0088] The pixel electrode layer may include a semi-transparent conductive material or a reflective conductive material.

[0089] The fifth insulating layer 350 may be disposed on the fourth insulating layer 182. The fifth insulating layer 350 has an opening 355 disposed on the pixel electrodes 191a, 191b, and 191c. The fifth insulating layer 350 may include an organic insulating material such as a polyacrylic-based resin or a polyimide resin.

[0090] The emission layer 370 is disposed on the fifth insulating layer 350 and the pixel electrode layer. The emission layer 370 may include a portion disposed in the opening 355 of the fifth insulating layer 350. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material. Alternatively, at least a portion of the fifth insulating layer 350 does not need to be covered by the emission layer 370.

[0091] The fifth insulating layer 350 and the emission layer 370 may include a contact hole 82 disposed on a contact member (contact member) 190d.

[0092] The common electrode 270 is disposed on the emission layer 370. The common electrode 270 may be continuously formed across the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may be electrically connected to the common voltage line 170 by contacting the contact member 190d through the contact hole 82, thereby receiving the common voltage ELVSS.

[0093] The common electrode 270 may include a conductive transparent material.

[0094] The pixel electrodes 191a, 191b and 191c of each pixel PX1, PX2 and PX3, the emission layer 370 and the common electrode 270 together form a light emitting diode (LED) ED, and the pixel electrodes 191a, 191b and 191c or the common electrode 270 become a cathode and the other becomes an anode. An example in which the pixel electrodes 191a, 191b and 191c become anodes is described.

[0095] Reference Figure 2 , the lower pattern 111a may further include an extension portion 111aa overlapping the driving voltage line 172a and the driving voltage patterns 172c and 172d in a plan view. Therefore, the plane size of the lower pattern 111a may be larger than the plane size of the lower pattern 111b or the lower pattern 111c. According to the present exemplary embodiment, the lower pattern 111a is electrically connected to the pixel electrodes 191a, 191b and 191c as anodes via the capacitor electrode 175, and the extension portion 111aa of the lower pattern 111a overlaps the driving voltage line 172a transmitting a predetermined voltage and the driving voltage patterns 172c and 172d. The buffer layer 120 and the second insulating layer 160 are disposed between the extension portion 111aa of the lower pattern 111a and the driving voltage line 172a, thereby forming a capacitor Ced for enhancing the function of maintaining the voltage of the anode.

[0096] The extension portion 111 aa may also overlap the source region 133 a of the active pattern 130 a connected to the driving voltage line 172 a .

[0097] On the other hand, the lower pattern 111a is electrically connected to the pixel electrodes 191a, 191b, and 191c through the capacitor electrode 175, and also overlaps with the channel region 134a of the first transistor T1, reducing the current change rate in the saturation region of the voltage-current characteristic diagram of the first transistor T1, so that the range of the region in which the output current of the first transistor T1 is constant can be expanded. Therefore, even if there is a change in the source-drain voltage Vds of the first transistor T1, the output current of the first transistor T1 remains constant, thereby improving the output saturation characteristic. Therefore, the brightness deviation between pixels caused by the output current of the first transistor T1 is reduced, thereby improving the image quality.

[0098] Reference Figure 6 , this exemplary embodiment is similar to Figure 5The structures shown in are substantially the same. For ease of description, only the differences will be described. The fourth insulating layer 182 may further include a contact hole 81a disposed on the contact member 190d, and the pixel electrode layer may further include a contact member 191d contacting the contact member 190d through the contact hole 81a. Therefore, the fifth insulating layer 350 and the emission layer 370 may include a contact hole 82a disposed on the contact member 191d. The common electrode 270 contacts the contact member 191d via the contact hole 82a to be electrically connected to the common voltage line 170, thereby receiving the common voltage ELVSS.

[0099] Next, we will refer to Figures 7 to 9 and the above-mentioned drawings to describe the display device 1000 a according to an exemplary embodiment. Figures 7 to 9 The exemplary embodiment shown in FIG. Figures 2 to 6 The above exemplary embodiments are shown in FIG. 1 , and for convenience, the same reference numerals are used for corresponding constituent elements, although the functions of the corresponding constituent elements may be the same, the planar structures or cross-sectional structures may be slightly different. The same applies to other subsequent drawings.

[0100] Figure 7 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment, and Figure 8 It is taken along line VIIIa-VIIIb Figure 7 A cross-sectional view of a display device shown in FIG.

[0101] Reference Figure 7 and Figure 8 , the display device 1000a according to the exemplary embodiment is substantially the same as most of the display device 1000 according to the above exemplary embodiment, however, the fourth conductive layer may further include extension portions 190a1, 190b1, and 190c1 connected to the contact members 190a, 190b, and 190c. In other words, the contact members 190a, 190b, and 190c may include the extension portions 190a1, 190b1, and 190c1.

[0102] Each of the extension portions 190a1, 190b1, and 190c1 overlaps with the driving voltage line 172a provided in the first pixel PX1 and the driving voltage patterns 172c and 172d provided in the second pixel PX2. The contact members 190a, 190b, and 190c are provided in the pixels PX1, PX2, and PX3, respectively. The extension portion 190c1 extends from the contact member 190c into the third pixel PX3 along the first direction DR1, and then further extends within the second pixel PX2 along the second direction DR2. The third insulating layer 181 is provided between the extension portion 190a1 of the contact member 190a and the driving voltage line 172a to form a holding capacitor Ced that can be used to enhance the function of holding the voltage of the anode of the light emitting diode (LED) ED. Similarly, the extension portion 190b1 and the driving voltage pattern 172c may form a holding capacitor Ced for the light emitting diode (LED) ED of the second pixel PX2; and the extension portion 190c1 and the driving voltage pattern 172d may form a holding capacitor Ced for the light emitting diode (LED) ED of the third pixel PX3.

[0103] Each of the extension portions 190a1, 190b1, 190c1 may extend in the second direction DR2 to overlap the driving voltage line 172a and the driving voltage patterns 172c and 172d, respectively.

[0104] Fig. 9 is a plan layout diagram of a plurality of pixels PX1 , PX2 , and PX3 of a display device according to an exemplary embodiment.

[0105] Reference Fig. 9 , the display device 1000b according to the present exemplary embodiment is substantially the same as most of the display devices 1000 and 1000a according to the various exemplary embodiments described above, but the fourth conductive layer may include extended contact members 190a2, 190b2, and 190c2 that are completely formed in each pixel PX1, PX2, and PX3, instead of including the contact members 190a, 190b, and 190c. That is, each extended contact member 190a2, 190b2, and 190c2 may not only overlap with the driving voltage line 172a and the driving voltage patterns 172c and 172d provided in each pixel PX1, PX2, and PX3 via the third insulating layer 181, but may also overlap with other regions of each pixel PX1, PX2, and PX3. For example, as Fig. 9As shown, each extended contact member 190a2, 190b2 and 190c2 may overlap with most of the pixel electrodes 191a, 191b and 191c of the corresponding pixels PX1, PX2 and PX3, and may have a shape similar to each pixel electrode 191a, 191b and 191c. Each extended contact member 190a2, 190b2 and 190c2 may also overlap with the driving gate electrode 155, the capacitor electrode 175, etc. of the corresponding pixels PX1, PX2 and PX3, or in addition, may overlap with at least a portion of the transistors T1, T2 and T3. The extended contact member 190c2 of the pixel PX3 may overlap with the adjacent common voltage line 170.

[0106] exist Figures 7 to 9 In the exemplary embodiment shown in FIG. 1 , unlike the above exemplary embodiments, the lower pattern 111 a may or may not include the extension portion 111 aa . Figure 7 and Figure 8 An example without the extended portion 111aa is shown, and Fig. 9 An example including an extended portion 111 aa is shown.

[0107] Next, refer to Fig.10 A display device according to an exemplary embodiment is described.

[0108] Fig.10 It is taken along line IIIa-IIIb Figure 2 Another example of a cross-sectional view of a display device is shown in FIG.

[0109] Reference Fig.10 , the display device according to the exemplary embodiment is substantially the same as most of the above exemplary embodiments except for a sixth insulating layer 122 disposed on the second conductive layer and the buffer layer 120 and a sixth conductive layer disposed between the sixth insulating layer 122 and the second insulating layer 160 .

[0110] The sixth insulating layer 122 may contact the top surfaces of the conductive regions of the active patterns 130a, 130b, and 130c. The sixth insulating layer 122 may include a contact hole 61a and contact holes 62a and 68a. The contact hole 61a overlaps the contact hole 61 of the second insulating layer 160.

[0111] In the present exemplary embodiment, a capacitor electrode 157 located in the sixth conductive layer may be included instead of the above-mentioned capacitor electrode 175. The capacitor electrode 157 may be electrically connected to the drain region 135a of the active pattern 130a via the contact hole 62a, and may be electrically connected to the lower pattern 111a via the contact hole 68a. The capacitor electrode 157 may have a planar shape similar to that of the capacitor electrode 175 described above. The capacitor electrode 157 may overlap a large portion of the corresponding driving gate electrode 155. The sixth insulating layer 122 may be disposed between the capacitor electrode 157 and the driving gate electrode 155 to form a storage capacitor Cst.

[0112] The sixth conductive layer may further include a connection pattern that contacts the underlying conductive layer via a contact hole. Fig.10 The sixth conductive layer includes a connection pattern 163 contacting the source region 133a of the active pattern 130a through the contact hole 61a, and the driving voltage line 172a contacts the connection pattern 163 through the contact hole 61 of the second insulating layer 160 and is electrically connected to the connection pattern 163 to be electrically connected to the source region 133a of the active pattern 130a.

[0113] Next, refer to Fig.11 A display device according to an exemplary embodiment is described.

[0114] Fig.11 It is taken along line IIIa-IIIb Figure 2 Another example of a cross-sectional view of a display device is shown in FIG.

[0115] Reference Fig.11 , the display device according to the exemplary embodiment is substantially the same as most of the above exemplary embodiments except for the seventh insulating layer 180 disposed between the third conductive layer and the third insulating layer 181 and the seventh conductive layer disposed between the seventh insulating layer 180 and the third insulating layer 181.

[0116] The seventh conductive layer may include a conductive pattern extending almost parallel to patterns such as data lines 171a, 171b, and 171c, driving voltage lines 172a, common voltage lines 170, initialization voltage lines 173, etc. disposed in the third conductive layer below so as to be electrically connected to patterns such as data lines 171a, 171b, and 171c, driving voltage lines 172a, common voltage lines 170, initialization voltage lines 173, etc. disposed in the third conductive layer below. For example, referring to Fig.11, the seventh conductive layer may further include a conductive pattern 183 electrically connected to the driving voltage line 172a via the contact hole 80 of the seventh insulating layer 180. In a plan view, the conductive pattern 183 may have a planar shape similar to that of the third conductive layer generally connected to the conductive pattern 183. The conductive pattern 183 may be used to reduce resistance by transmitting the same voltage as the third conductive layer connected to the conductive pattern 183.

[0117] Alternatively, portions of the data lines 171a, 171b and 171c, the driving voltage lines 172a, the common voltage lines 170, the initialization voltage lines 173, the capacitor electrodes 175, the connecting members 174, 176, 177 and 178, and the plurality of driving voltage patterns 172c and 172d of the third conductive layer may be disposed in the third conductive layer, and the remainder of the data lines 171a, 171b and 171c, the driving voltage lines 172a, the common voltage lines 170, the initialization voltage lines 173, the capacitor electrodes 175, the connecting members 174, 176, 177 and 178, and the plurality of driving voltage patterns 172c and 172d of the third conductive layer may be disposed in the seventh conductive layer.

[0118] Next, refer to Fig.12 and Fig.13 and the above-mentioned drawings to describe a display device 1000c according to an exemplary embodiment.

[0119] Fig.12 and Fig.13 1 and 2 are plan layout diagrams of a plurality of pixels PX4 , PX5 , and PX6 of a display device 1000 c according to exemplary embodiments, respectively.

[0120] First, refer to Fig.12 , the connection relationship and stacking structure of the constituent elements of the display device 1000c according to the exemplary embodiment are substantially the same as most of the display devices 1000, 1000a and 1000b according to the above exemplary embodiments, however, the detailed shapes and connection methods of the constituent elements may be different. Focus on the differences from the aforementioned exemplary embodiments.

[0121] The plurality of pixels PX4 , PX5 , and PX6 of the repeating group may be arranged adjacent to each other in the second direction DR2 .

[0122] The pixels PX4, PX5, and PX6 of one column may be disposed between two adjacent common voltage lines 170, and the plurality of data lines 171a, 171b, and 171c may be disposed between the pixels PX4, PX5, and PX6 of one column and the common voltage line 170 on one side. In addition, the driving voltage line 172 and the initialization voltage line 173 may be disposed between the pixels PX4, PX5, and PX6 of one column and the common voltage line 170 on the other side. That is, the plurality of data lines 171a, 171b, and 171c may be disposed on one side relative to the pixels PX4, PX5, and PX6 of one column, and the driving voltage line 172 and the initialization voltage line 173 may be disposed on the other side.

[0123] The first scan line 151 and the second scan line 152 may be disposed under and over the plurality of pixels PX4 , PX5 , and PX6 of the repeating group, respectively.

[0124] The first conductive layer described above may include a plurality of lower patterns 111, and each lower pattern 111 may be disposed in each of the pixels PX4, PX5, and PX6. The first conductive layer may further include a transverse common voltage line 170a extending substantially in the first direction DR1.

[0125] The active patterns 130a, 130b, and 130c disposed in the active layer may include channel regions 134a, 134b, and 134c forming each channel of the transistors T1, T2, and T3, and source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c. In the present exemplary embodiment, in each of the pixels PX4, PX5, and PX6, the active patterns 130a, 130b, and 130c may be separated from each other.

[0126] The second conductive layer may include a first scan line 151, a second scan line 152, a driving gate electrode 155, a second gate electrode 154b, a third gate electrode 154c, etc. Each of the first scan line 151 and the second scan line 152 may extend in the first direction DR1. Each driving gate electrode 155 may be provided to correspond to each pixel PX4, PX5, and PX6. A plurality of second gate electrodes 154b corresponding to the plurality of pixels PX4, PX5, and PX6 are connected to each other and are generally formed in a shape extending in the second direction DR2, thereby extending toward the second scan line 152. A plurality of third gate electrodes 154c corresponding to the plurality of pixels PX4, PX5, and PX6 are connected to each other and are generally formed in a shape extending in the second direction DR2, thereby extending toward the first scan line 151.

[0127] The driving gate electrode 155 disposed at each pixel PX1, PX2, and PX3 may include a first gate electrode 154a in a shape protruding upward or downward. The first gate electrode 154a crosses the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b crosses the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c crosses the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

[0128] The third conductive layer may include the plurality of data lines 171 a , 171 b , and 171 c , the driving voltage line 172 , the common voltage line 170 , the initialization voltage line 173 , the capacitor electrode 175 , and the plurality of connection members 178 as described above.

[0129] Each of the data lines 171 a , 171 b , and 171 c , the driving voltage line 172 , the common voltage line 170 , and the initialization voltage line 173 extends substantially in the second direction DR2 to cross the first and second scan lines 151 and 152 .

[0130] Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130b through the contact hole 64. The driving voltage line 172 is electrically connected to the source region 133a of the active pattern 130a through the contact hole 61. The initialization voltage line 173 is electrically connected to the drain region 135c of the active pattern 130c via the contact hole 63a. The contact holes 61, 63a, and 64 may be formed in the second insulating layer 160 described above.

[0131] The capacitor electrode 175 may be disposed one by one on each pixel PX1, PX2, and PX3 and may be disposed between the driving voltage line 172 and the data line 171c. The capacitor electrode 175 overlaps most of the corresponding driving gate electrode 155 so that the second insulating layer 160 is between the capacitor electrode 175 and the driving gate electrode 155 to form a storage capacitor Cst.

[0132] The capacitor electrode 175 is electrically connected to the drain region 135a of the active pattern 130a through the contact hole 62 of the second insulating layer 160, and is electrically connected to the source region 133c of the active pattern 130c through the contact hole 63b of the second insulating layer 160. In addition, the capacitor electrode 175 is electrically connected to the lower pattern 111 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120. The driving gate electrode 155 includes an opening 55a for contact between the capacitor electrode 175 and the drain region 135a of the active pattern 130a overlapping with the contact hole 62, so that the driving gate electrode 155 can have a shape surrounding the vicinity of the contact hole 62.

[0133] In each pixel PX4, PX5 and PX6, the connecting member 178 is electrically connected to the drain region 135b of the active pattern 130b through the contact hole 65 of the second insulating layer 160, and is electrically connected to the extension portion 155a of the driving gate electrode 155 through the contact hole 66 of the second insulating layer 160, so that the drain region 135b of the active pattern 130b and the extension portion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0134] The third insulating layer 181 may include a contact hole 83 a disposed on the capacitor electrode 175 , a contact hole 89 a disposed on the end portions 179 of the data lines 171 a , 171 b , and 171 c , and a contact hole 81 disposed on the common voltage line 170 .

[0135] The display device 1000c according to the present exemplary embodiment may include the fourth conductive layer as described above.

[0136] A plurality of pixel electrodes 191a, 191b, and 191c disposed at the pixel electrode layer of the fifth conductive layer are disposed to correspond to each of the pixels PX4, PX5, and PX6. Each of the pixel electrodes 191a, 191b, and 191c may be electrically connected to the capacitor electrode 175 through the contact hole 83b of the fourth insulating layer 182 as described above. In this case, a contact member disposed in the fourth conductive layer may be disposed between each of the pixel electrodes 191a, 191b, and 191c and the capacitor electrode 175. Each of the pixel electrodes 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175, thereby receiving a voltage from the first transistor T1.

[0137] The pixel electrode layer may further include a contact member 191d overlapping the common electrode 270 as described above. In addition, the fourth conductive layer may further include a contact member contacting the contact member 191d. The common electrode 270 is electrically connected to the contact member 191d through the contact hole 82, and the contact member 191d is electrically connected to the common voltage line 170 through the contact hole 81, thereby receiving the common voltage ELVSS. That is, the common electrode 270 may receive the common voltage ELVSS from the common voltage line 170 through the contact member 191d.

[0138] The common voltage line 170 may be electrically connected to the lateral common voltage line 170 a through the contact hole 70 .

[0139] The second conductive layer may further include a conductive pattern 150a overlapping the common voltage line 170 and conductive patterns 150b and 150c overlapping the driving voltage line 172. In this case, the conductive pattern 150a may be electrically connected to the common voltage line 170 through a plurality of contact holes 60a of the second insulating layer 160 to reduce resistance. The conductive patterns 150b and 150c may be electrically connected to the driving voltage line 172 through a plurality of contact holes 60b and 60c of the second insulating layer 160 to reduce resistance.

[0140] The lower pattern 111 may further include an extension portion 111 s overlapping at least one of the driving voltage line 172 , the initialization voltage line 173 , and the common voltage line 170 . Fig.12 An example is shown in which the lower pattern 111 includes an extension portion 111s that overlaps all of the driving voltage line 172, the initialization voltage line 173, and the common voltage line 170. Alternatively, the extension portion 111s may overlap only the driving voltage line 172 among the driving voltage line 172, the initialization voltage line 173, and the common voltage line 170 or may overlap only the driving voltage line 172 and the initialization voltage line 173.

[0141] According to the present exemplary embodiment, the extending portion 111s of the lower pattern 111 overlaps at least some of the driving voltage line 172, the initialization voltage line 173 and the common voltage line 170 and transmits a constant voltage, thereby forming a capacitor Ced for enhancing the function of maintaining the voltage of the anode of the light emitting diode (LED) ED.

[0142] Next, refer to Fig.13 , the display device 1000d according to the exemplary embodiment further includes a fourth conductive layer. The fourth conductive layer may include a plurality of contact members 190a3, 190b3, and 190c3 positioned corresponding to each pixel PX4, PX5, and PX6. The contact members 190a3, 190b3, and 190c3 may contact and be electrically connected to the capacitor electrode 175 via a contact hole provided in the third insulating layer 181, and each pixel electrode 191a, 191b, and 191c may contact and be electrically connected to each contact member 190a3, 190b3, and 190c3 via a contact hole 83c included in the fourth insulating layer 182.

[0143] The contact members 190a3, 190b3, and 190c3 overlap at least one of the driving voltage line 172, the initialization voltage line 173, and the common voltage line 170 via the third insulating layer 181, thereby forming a capacitor Ced for enhancing the function of maintaining the voltage of the anode of the light emitting diode (LED) ED. Fig.13An example is shown in which the contact members 190a3, 190b3, and 190c3 overlap all of the driving voltage line 172, the initialization voltage line 173, and the common voltage line 170. Alternatively, the contact members 190a3, 190b3, and 190c3 may overlap only the driving voltage line 172 among the driving voltage line 172, the initialization voltage line 173, and the common voltage line 170 or may overlap only the driving voltage line 172 and the initialization voltage line 173.

[0144] While the invention has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the disclosure.

Claims

1. A display device, wherein: The display device comprises: substrate; a lower pattern, the lower pattern being arranged on the substrate; an active pattern disposed on the lower pattern, wherein the active pattern includes a source region, a channel region, and a drain region, and in a plan view, the channel region of the active pattern overlaps with the lower pattern; a driving voltage line directly connected to the source region of the active pattern via a contact hole exposing the active pattern, wherein the driving voltage line overlaps the active pattern and the lower pattern, wherein the driving voltage line and the lower pattern form a first capacitor, and wherein the lower pattern is positioned lower than the active pattern; and A pixel electrode is connected to the drain region of the active pattern and the lower pattern.

2. The display device according to claim 1, wherein: The display device further includes: a first capacitor electrode, the first capacitor electrode being separated from the driving voltage line, Wherein, the first capacitor electrode is electrically connected to the lower pattern and the pixel electrode.

3. The display device according to claim 2, wherein: The display device further includes: a gate electrode, the gate electrode overlapping the channel region; and a driving gate electrode electrically connected to the gate electrode, wherein the first capacitor electrode is also electrically connected to the drain region, and The first capacitor electrode overlaps the driving gate electrode to form a second capacitor.

4. The display device according to claim 3, wherein: The display device further includes: a first scan line and a second scan line, the first scan line and the second scan line extending in a first direction and crossing the driving voltage line, and In the plan view, the gate electrode is disposed between the first scan line and the second scan line.

5. The display device according to claim 3, wherein: The display device further includes: a data line, the data line being separated from the driving voltage line; and A first contact member is disposed on an end portion of the data line and contacts the end portion.

6. The display device according to claim 5, wherein: The display device further includes: A second contact member is disposed between the pixel electrode and the first capacitor electrode and contacts the pixel electrode and the first capacitor electrode.

7. The display device according to claim 6, wherein: In the plan view, the second contact member includes an extending portion overlapping the driving voltage line.

8. The display device according to claim 7, wherein: The extending portion overlaps the gate electrode and the first capacitor electrode.

9. The display device according to claim 6, wherein: The display device further includes: A common voltage line for transmitting a common voltage and an initialization voltage line for transmitting an initialization voltage, wherein: The second contact member overlaps at least one of the driving voltage line, the initialization voltage line, and the common voltage line.

10. The display device according to claim 3, wherein: The display device further includes: a second capacitor electrode electrically connected to the lower pattern, and The second capacitor electrode overlaps the gate electrode to form a third capacitor.

11. The display device according to claim 1, wherein: In the plan view, the lower pattern overlaps the source region.

12. The display device according to claim 1, wherein: The display device further includes: a common voltage line for transmitting a common voltage and an initialization voltage line for transmitting an initialization voltage, The lower pattern includes an extended portion overlapping at least one of the driving voltage line, the initialization voltage line, and the common voltage line.

13. A display device, wherein: The display device comprises: substrate; a first conductive layer, the first conductive layer comprising a lower pattern on the substrate; a first insulating layer, the first insulating layer being on the first conductive layer; an active pattern, the active pattern being disposed on the first insulating layer and comprising a source region, a channel region and a drain region; a second conductive layer disposed on the active pattern and comprising a gate electrode overlapping the channel region; a second insulating layer, the second insulating layer being disposed on the second conductive layer; a third conductive layer, the third conductive layer being disposed on the second insulating layer and comprising a driving voltage line and a data line separated from the driving voltage line; a third insulating layer, the third insulating layer being disposed on the third conductive layer; a pixel electrode layer, the pixel electrode layer comprising a first pixel electrode disposed on the third insulating layer; a fourth conductive layer, the fourth conductive layer being disposed between the third insulating layer and the pixel electrode layer; and a fourth insulating layer, the fourth insulating layer being disposed between the fourth conductive layer and the pixel electrode layer, The fourth conductive layer includes a first contact member disposed on an end portion of the data line to contact the end portion.

14. The display device according to claim 13, wherein: The third conductive layer further includes a first capacitor electrode separated from the driving voltage line, and The fourth conductive layer further includes a second contact member disposed between and in contact with the first pixel electrode and the first capacitor electrode.

15. The display device according to claim 14, wherein: The second contact member includes an extending portion overlapping the driving voltage line in a plan view to form a first capacitor.

16. The display device according to claim 15, wherein: The extending portion also overlaps the gate electrode and the first capacitor electrode.

17. The display device according to claim 13, wherein: The lower pattern is electrically connected to the first pixel electrode, The lower pattern overlaps the channel region, and The lower pattern also overlaps the driving voltage line in a plan view to form a first capacitor.

18. The display device according to claim 13, wherein: The display device further includes: a fifth conductive layer, the fifth conductive layer being disposed on the third conductive layer; and a fifth insulating layer, the fifth insulating layer being disposed between the third conductive layer and the fifth conductive layer, The fifth conductive layer includes a conductive pattern electrically connected to at least a portion of the third conductive layer.

19. A display device, wherein: The display device comprises: a first scan line and a second scan line; a driving gate electrode, wherein the driving gate electrode is disposed between the first scanning line and the second scanning line; a data line, a driving voltage line, an initialization voltage line, and a common voltage line, wherein the data line, the driving voltage line, the initialization voltage line, and the common voltage line intersect the first scan line and the second scan line; a first transistor electrically connected to the driving voltage line and the driving gate electrode; a second transistor electrically connected to the first scan line and the data line; a third transistor, the third transistor being electrically connected to the second scan line, the first transistor and the initialization voltage line; a capacitor electrode electrically connected to a drain region of the first transistor; a light emitting diode electrically connected to the capacitor electrode; and a lower pattern, wherein in a plan view, the lower pattern overlaps with a channel region of the first transistor, wherein the lower pattern is electrically connected to the capacitor electrode, and In the plan view, the lower pattern overlaps at least one of the driving voltage line, the initialization voltage line, and the common voltage line to form a first capacitor.

20. The display device according to claim 19, wherein: In the plan view, the driving gate electrode and the capacitor electrode overlap each other to form a second capacitor.

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