Semiconductor package

Abstract

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units connecting the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width in a direction parallel to an upper surface of the first package substrate that is greater than a width of the first semiconductor chip in the direction parallel to the upper surface of the first package substrate, and an upper fill layer including a central portion between the first semiconductor chip and the interposer and an outer portion surrounding the central portion, the outer portion having a thickness in a direction perpendicular to the upper surface of the first package substrate that is greater than a thickness of the central portion in the direction perpendicular to the upper surface of the first package substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0123270, filed with the Korean Intellectual Property Office on October 16, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to semiconductor packages, and more specifically, to package stacks. Background Technology

[0004] To meet the need for miniaturized and highly integrated semiconductor packages, package stacks have been developed. A package stack has a structure in which one sub-package is stacked on top of another sub-package. Therefore, package stacks can occupy a small area and enable miniaturization and high integration of semiconductor packages. Summary of the Invention

[0005] According to one aspect of the embodiments, a semiconductor package is provided, comprising: a first packaging substrate; a first semiconductor chip located on the first packaging substrate; a plurality of first chip connection units connecting the first packaging substrate to the first semiconductor chip; an interposer located on the first semiconductor chip, the width of the interposer in a direction parallel to an upper surface of the first packaging substrate being greater than the width of the first semiconductor chip in a direction parallel to the upper surface of the first packaging substrate; and an upper filler layer comprising a central portion located between the first semiconductor chip and the interposer layer and an outer portion surrounding the central portion, the thickness of the outer portion in a direction perpendicular to the upper surface of the first packaging substrate being greater than the thickness of the central portion in a direction perpendicular to the upper surface of the first packaging substrate.

[0006] According to another aspect of the embodiments, a semiconductor package is provided, comprising: a first packaging substrate; a first semiconductor chip located on the first packaging substrate; a plurality of first chip connection units connecting the first packaging substrate to the first semiconductor chip; an interposer located on the first semiconductor chip, the width of the interposer in a direction parallel to an upper surface of the first packaging substrate being greater than the width of the first semiconductor chip in a direction parallel to the upper surface of the first packaging substrate; an upper filler layer filling the space between the interposer layer and the first semiconductor chip; and a lower filler layer comprising a central portion filling the space between the first semiconductor chip and the first packaging substrate and an outer portion surrounding the central portion, wherein the thickness of the outer portion of the lower filler layer in a direction perpendicular to the upper surface of the first packaging substrate is greater than the thickness of the central portion of the lower filler layer in a direction perpendicular to the upper surface of the first packaging substrate.

[0007] According to another aspect of the embodiments, a semiconductor package is provided, comprising: a first sub-package and a second sub-package. The first sub-package includes a first packaging substrate, a first semiconductor chip on the first packaging substrate, a plurality of first chip interconnect units between the first packaging substrate and the first semiconductor chip, an interposer on the first semiconductor chip, an upper filler layer filling the space between the interposer layer and the first semiconductor chip, and a lower filler layer filling the space between the first semiconductor chip and the first packaging substrate. The width of the interposer layer in a direction parallel to the upper surface of the first packaging substrate is greater than the width of the first semiconductor chip in a direction parallel to the upper surface of the first packaging substrate. The second sub-package includes a plurality of inter-package interconnect units located on the interposer layer, a second packaging substrate located on the plurality of inter-package interconnect units, at least one second semiconductor chip located on the second packaging substrate, and a second molding unit surrounding the at least one second semiconductor chip and covering the upper surface of the second packaging substrate. At least one of the upper filler layer and the lower filler layer is in contact with the sidewall of the first semiconductor chip. Attached Figure Description

[0008] The features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0009] FIG. 1A A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0010] FIG. 1B A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0011] FIG. 1C A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0012] FIG. 2 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0013] FIG. 3 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0014] FIG. 4 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0015] FIG. 5 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0016] FIG. 6A A plan view of a first packaging substrate included in a semiconductor package according to an embodiment is shown;

[0017] FIG. 6B A plan view of a first packaging substrate included in a semiconductor package according to an embodiment is shown;

[0018] FIG. 6C A plan view of a first packaging substrate included in a semiconductor package according to an embodiment is shown;

[0019] FIG. 7 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0020] FIG. 8 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0021] FIG. 9 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0022] FIG. 10 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0023] FIG. 11 A cross-sectional view of a semiconductor package according to an embodiment is shown;

[0024] FIG. 12A to FIG. 12D A cross-sectional view is shown of a stage in a method for manufacturing a semiconductor package according to an embodiment;

[0025] FIG. 13 A cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment is shown;

[0026] FIG. 14 A cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment is shown;

[0027] FIG. 15 A cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment is shown;

[0028] FIG. 16A and FIG. 16B A cross-sectional view is shown of a stage in a method for manufacturing a semiconductor package according to an embodiment;

[0029] FIG. 17 A cross-sectional view of a method for manufacturing a semiconductor package according to an embodiment is shown;

[0030] FIG. 18A and FIG. 18B Cross-sectional views of stages in a method for manufacturing a semiconductor package according to an embodiment are shown; and

[0031] FIG. 19A to FIG. 19C A cross-sectional view is shown of a stage in a method for manufacturing a semiconductor package according to an embodiment. Detailed Implementation

[0032] FIG. 1A This is a cross-sectional view showing a semiconductor package 1000a according to an embodiment.

[0033] Reference FIG. 1A The semiconductor package 1000a may include a first sub-package SP1 and a second sub-package SP2. The second sub-package SP2 may be stacked on the first sub-package SP1. For example, the semiconductor package 1000a may be a package stack.

[0034] The first sub-package SP1 may include a first packaging substrate 110, a first semiconductor chip 120, a plurality of first chip interconnect units 130, an interposer 140, an upper filler layer 150a, a plurality of wires 170, and a first molding unit 180.

[0035] The first packaging substrate 110 may be a printed circuit board (PCB). The PCB may be a rigid PCB or a flexible PCB. The first packaging substrate 110 may include a substrate base layer, multiple lower connection pads, multiple upper connection pads, multiple conductive traces, multiple vias, and a solder mask layer.

[0036] The substrate base layer in the first packaging substrate 110 may include, for example, phenolic resin, epoxy resin, polyimide resin, or combinations thereof. For example, the substrate base layer may include flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), polyamide short fiber mat (thermount), cyanate ester, polyimide, or liquid crystal polymer. In some embodiments, the first packaging substrate 110 may be a multilayer PCB, wherein the substrate base layer is configured with multiple layers.

[0037] Multiple lower connection pads in the first packaging substrate 110 can be disposed on the lower surface of the substrate base layer, and multiple upper connection pads can be disposed on the upper surface of the substrate base layer. The multiple lower connection pads can be connected to multiple external connection units 190, and the multiple upper connection pads can be connected to multiple first chip connection units 130 and multiple wires 170. The multiple lower connection pads and multiple upper connection pads may each include, for example, copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au), or combinations thereof.

[0038] Multiple conductive wires and multiple vias in the first packaging substrate 110 can be disposed in the substrate base layer and on the surface of the substrate base layer. The multiple conductive wires and multiple vias can connect to multiple lower connection pads and multiple upper connection pads. The multiple conductive wires and multiple vias can each comprise, for example, Cu, Ni, Al, Ag, Au, or combinations thereof.

[0039] The solder mask layer of the first packaging substrate 110 may be disposed on each of the upper and lower surfaces of the substrate base layer. However, the solder mask layer may not cover the multiple upper connection pads and multiple lower connection pads.

[0040] A first semiconductor chip 120 may be disposed on a first packaging substrate 110. The first semiconductor chip 120 may have a first width W1 in a direction parallel to the upper surface of the first packaging substrate 110 (e.g., in the Y direction). The first semiconductor chip 120 may be a logic chip or a memory chip. A logic chip may be, for example, a memory controller chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. A memory chip may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip.

[0041] A plurality of first chip connection units 130 can connect the first semiconductor chip 120 to the first packaging substrate 110. The plurality of first chip connection units 130 can be, for example, a plurality of bumps. In this case, the plurality of first chip connection units 130 can be disposed between the first semiconductor chip 120 and the first packaging substrate 110. Each of the plurality of first chip connection units 130 can each include, for example, Au, Cu, Ni, tin (Sn), lead (Pb), or combinations thereof.

[0042] An interposer 140 may be disposed on the first semiconductor chip 120, for example, the first semiconductor chip 120 may be centered relative to the interposer 140. The interposer 140 may connect the first package substrate 110 to the second package substrate 210. The interposer 140 may have a second width W2 in a direction parallel to the upper surface of the first package substrate 110 (e.g., in the Y direction). The second width W2 of the interposer 140 may be greater than the first width W1 of the first semiconductor chip 120; for example, the interposer 140 may hang over each side of the first semiconductor chip 120.

[0043] Interposer 140 may include an interposer substrate, a plurality of connection pads 140U, and a plurality of conductive wirings. The interposer substrate may include, for example, an organic material, glass, ceramic, or semiconductor. The interposer substrate may include, for example, silicon (Si). The plurality of connection pads 140U may be disposed on the upper surface of the interposer substrate. The plurality of conductive wirings may connect the plurality of connection pads 140U. The plurality of connection pads 140U and the plurality of conductive wirings may each include, for example, Cu, Ni, Al, Ag, Au, or combinations thereof.

[0044] An upper filler layer 150a may be disposed between the first package substrate 110 and the interposer layer 140. The upper filler layer 150a may be spaced apart from the first package substrate 110. The upper filler layer 150a may contact the lower surface of the interposer layer 140 and the upper surface of the first semiconductor chip 120; for example, the upper filler layer 150a may contact the entire lower surface of the interposer layer 140 and the entire upper surface of the first semiconductor chip 120. In some embodiments, the upper filler layer 150a may contact the entire upper surface of the first semiconductor chip 120 and the entire lower surface of the interposer layer 140. The upper filler layer 150a may contact the sidewalls of the first semiconductor chip 120 to cover the sidewalls of the first semiconductor chip 120. The upper filler layer 150a may have a third width W3 in a direction parallel to the upper surface of the first package substrate 110 (e.g., in the Y direction). In some embodiments, the third width W3 of the upper filler layer 150a may be the same as the second width W2 of the interposer layer 140. For example, as... FIG. 1A As shown, the third width W3 of the upper filling layer 150a can be measured along the top surface of the upper filling layer 150a.

[0045] The upper filler layer 150a may include a central portion P1a and an outer portion P2a. The central portion P1a and the outer portion P2a of the upper filler layer 150a may be provided as a single, seamless unit, for example, formed simultaneously from the same material. For example, the central portion P1a of the upper filler layer 150a may be a portion that completely fills the space between the first semiconductor chip 120 and the interposer layer 140. For example, the outer portion P2a of the upper filler layer 150a may be a portion that extends from the central portion P1a and is located around the central portion P1a, for example, extending from the central portion P1a along the remainder of the bottom surface of the interposer layer 140 and along the entire sidewall of the first semiconductor chip 120.

[0046] The central portion P1a of the upper filler layer 150a may be disposed between the first semiconductor chip 120 and the interposer layer 140, and may contact the upper surface of the first semiconductor chip 120 and the lower surface of the interposer layer 140. The outer portion P2a of the upper filler layer 150a may surround, for example, the entire periphery of the central portion P1a, and may contact the lower surface of the interposer layer 140. In some embodiments, the outer portion P2a of the upper filler layer 150a may contact the sidewalls of the first semiconductor chip 120 to cover the sidewalls of the first semiconductor chip 120. In some embodiments, the lower surface of the outer portion P2a of the upper filler layer 150a and the lower surface of the first semiconductor chip 120 may be disposed at the same level, for example, at the same level as each other. For example, in a direction perpendicular to the upper surface of the first packaging substrate 110 (e.g., in the Z direction), the height of the lower surface of the outer portion P2a of the upper filling layer 150a from the first packaging substrate 110 may be the same as the height of the lower surface of the first semiconductor chip 120 from the first packaging substrate 110 in a direction perpendicular to the upper surface of the first packaging substrate 110 (e.g., in the Z direction).

[0047] The central portion P1a of the upper filler layer 150a may have a first thickness T1 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction), and the outer portion P2a of the upper filler layer 150a may have a second thickness T2 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction). The second thickness T2 may be greater than the first thickness T1. The thickness of the outer portion P2a of the upper filler layer 150a that hangs over the first semiconductor chip 120 may be greater than the thickness of the central portion P1a of the upper filler layer 150a, thereby preventing the hanging portion of the interposer layer 140 from deflecting.

[0048] The upper filler layer 150a may include a film on board (FOD) or a film on adhesive film (DAF). For example, the upper filler layer 150a may be formed by curing FOD or DAF. The upper filler layer 150a may include, for example, an epoxy-based organic material.

[0049] Multiple conductive lines 170 can connect the interposer 140 to the first package substrate 110. The multiple conductive lines 170 can, for example, extend from the upper surface of the interposer 140 to the upper surface of the first package substrate 110. Each of the multiple conductive lines 170 may comprise, for example, Au, Cu, Ag, Al, or combinations thereof.

[0050] The first molding unit 180 may surround the first semiconductor chip 120, a plurality of first chip interconnect units 130, a plurality of wires 170, an upper filler layer 150a, and an interposer layer 140, and may cover the upper surface of the first packaging substrate 110. For example, as FIG. 1AAs shown, the first molding unit 180 can surround the entire periphery of the interposer layer 140 having the upper filling layer 150a, and can fill the space between the bottom surface of the upper filling layer 150a and the top surface of the first packaging substrate 110, as well as the space between adjacent first chip interconnect units 130.

[0051] The first molding unit 180 may include multiple openings of a plurality of connection pads 140U exposing the inter-package connection unit 290 to contact the inter-package 140. The first molding unit 180 may include, for example, a thermosetting resin, a thermoplastic resin, an ultraviolet (UV) curable resin, or a combination thereof. The first molding unit 180 may include, for example, an epoxy resin, a silicone resin, or a combination thereof. The first molding unit 180 may include, for example, an epoxy molding compound (EMC).

[0052] The semiconductor package 1000a may further include an external connection unit 190. The external connection unit 190 may be disposed on the lower surface of the first package substrate 110. The external connection unit 190 can connect the semiconductor package 1000a to an external circuit. The external connection unit 190 may include, for example, Au, Cu, Ni, Sn, Pb, or combinations thereof. The external connection unit 190 may include, for example, solder balls.

[0053] The second sub-package SP2 may include a second packaging substrate 210, at least one second semiconductor chip 220, an adhesive layer 230, a plurality of second chip connection units 270, a second molding unit 280, and an inter-package connection unit 290.

[0054] The second packaging substrate 210 can be a PCB. The second packaging substrate 210 can be disposed above the first sub-package SP1, for example, overlapping the top of the first sub-package SP1.

[0055] At least one second semiconductor chip 220 may be disposed on the second packaging substrate 210. For example, the second packaging substrate 210 may be located between the at least one second semiconductor chip 220 and the first sub-package SP1. The second semiconductor chip 220 may be a logic chip or a memory chip. In some embodiments, the second semiconductor chip 220 may be a semiconductor chip of a different type than the first semiconductor chip 120. For example, the second semiconductor chip 220 may be a memory chip, and the first semiconductor chip 120 may be a logic chip. FIG. 1AThe diagram shows four second semiconductor chips 220. However, the number of second semiconductor chips 220 included in the second sub-package SP2 is not limited to four, but can be varied. In some embodiments, two or more second semiconductor chips 220 may be stacked on top of each other in a vertical direction (e.g., in the Z direction). In some embodiments, two or more second semiconductor chips 220 may be disposed on the second package substrate 210 in a horizontal direction (e.g., in the XY plane), and may, for example, be spaced apart from each other in the X and / or Y directions.

[0056] By using the adhesive layer 230, the second semiconductor chip 220 can be attached to the second packaging substrate 210, for example, and / or attached to the bottom of another second semiconductor chip 220. The adhesive layer 230 may include, for example, DAF, non-conductive film (NCF), or non-conductive paste (NCP).

[0057] A plurality of second chip connection units 270 can connect the second semiconductor chip 220 to the second packaging substrate 210. Each of the plurality of second chip connection units 270 can be, for example, a wire. The plurality of second chip connection units 270 may each include, for example, Au, Cu, Ag, Al or combinations thereof.

[0058] The second molding unit 280 may surround the second semiconductor chip 220 and the plurality of second chip interconnect units 270, and may cover the upper surface of the second packaging substrate 210. The second molding unit 280 may include, for example, thermosetting resin, thermoplastic resin, UV-curable resin, or a combination thereof. The second molding unit 280 may include, for example, epoxy resin, silicone resin, or a combination thereof. The second molding unit 280 may include, for example, EMC.

[0059] Multiple inter-package connection units 290 may be disposed between the lower surface of the second package substrate 210 and the interposer layer 140. The multiple inter-package connection units 290 may be respectively disposed in openings included in the first molding unit 180. The multiple inter-package connection units 290 may respectively contact multiple connection pads 140U of the interposer layer 140 exposed by the first molding unit 180. The multiple inter-package connection units 290 may connect the first sub-package SP1 to the second sub-package SP2. Each of the multiple inter-package connection units 290 may include, for example, Au, Cu, Ni, Sn, Pb, or combinations thereof. Each of the multiple inter-package connection units 290 may include, for example, solder balls.

[0060] In the semiconductor package 1000a according to an embodiment, the outer portion P2a of the upper filler layer 150a may be substantially thicker in the direction along the normal of the first package substrate 110 compared to the central portion P1a of the upper filler layer 150a. Because the outer portion P2a of the upper filler layer 150a is relatively thick, it can adequately support the edge portion of the interposer layer 140 that hangs over the first semiconductor chip 120, thereby preventing or substantially reducing the deflection (e.g., bending) of the edge portion of the interposer layer 140 toward the first package substrate 110.

[0061] FIG. 1B This is a cross-sectional view showing a semiconductor package 1000b according to an embodiment. The following will describe... FIG. 1B The semiconductor package 1000b shown is... FIG. 1A The differences between the semiconductor packages 1000a shown.

[0062] Reference FIG. 1B The semiconductor package 1000b may include a first sub-package SP1b and a second sub-package SP2. That is, the semiconductor package 1000b may include the first sub-package SP1b, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0063] Specifically, such as FIG. 1B As shown, the first sub-package SP1b may include an upper filler layer 150b, instead of FIG. 1A The first sub-package SP1 shown includes an upper filler layer 150a. The upper filler layer 150b may include a central portion P1b and an outer portion P2b. The outer portion P2b of the upper filler layer 150b may, for example, only cover a portion of the sidewall of the first semiconductor chip 120. The lower surface of the outer portion P2b of the upper filler layer 150b may be positioned, for example, at a level higher than the lower surface of the first semiconductor chip 120 relative to the top surface of the first package substrate 110. That is, the height of the lower surface of the outer portion P2b of the upper filler layer 150b from the upper surface of the first package substrate 110 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction) may be greater than the height of the lower surface of the first semiconductor chip 120 from the upper surface of the first package substrate 110 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction).

[0064] FIG. 1C This is a cross-sectional view showing a semiconductor package 1000c according to an embodiment. The following will describe... FIG. 1C The semiconductor package 1000c shown is... FIG. 1AThe differences between the semiconductor packages 1000a shown.

[0065] Reference FIG. 1C The semiconductor package 1000c may include a first sub-package SP1c and a second sub-package SP2. That is, the semiconductor package 1000c may include the first sub-package SP1c, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0066] Specifically, such as FIG. 1C As shown, the first sub-package SP1c may include an upper filler layer 150c, instead of FIG. 1A The first sub-package SP1 shown includes an upper filler layer 150a. The upper filler layer 150c may include a central portion P1c and an outer portion P2c. The lower surface of the outer portion P2c of the upper filler layer 150c may be positioned, for example, at a level lower than the lower surface of the first semiconductor chip 120 relative to the top surface of the first package substrate 110. That is, the height of the lower surface of the outer portion P2c of the upper filler layer 150c from the upper surface of the first package substrate 110 in a direction perpendicular to the upper surface (e.g., in the Z direction) may be less than the height of the lower surface of the first semiconductor chip 120 from the upper surface of the first package substrate 110 in the same direction. However, the outer portion P2c of the upper filler layer 150c may be spaced apart from the first package substrate 110.

[0067] FIG. 2 This is a cross-sectional view showing a semiconductor package 2000 according to an embodiment. The following will describe... FIG. 2 The semiconductor package 2000 shown is... FIG. 1A The differences between the semiconductor packages 1000a shown.

[0068] Reference FIG. 2 The semiconductor package 2000 may include a first sub-package SP1 and a second sub-package SP2d. That is, the semiconductor package 2000 may include the second sub-package SP2d, rather than... FIG. 1A The second sub-package SP2 of the semiconductor package 1000a shown.

[0069] Specifically, such as FIG. 2 As shown, in the second sub-package SP2d, multiple semiconductor chips 220 can be connected via the second chip interconnect unit 270d instead of... FIG. 1AThe second chip interconnect unit 270 included in the second sub-package SP2 shown is connected to the second package substrate 210. The second chip interconnect unit 270d may include a plurality of through-silicon vias (TSVs) 271 and a plurality of bumps 273. The plurality of TSVs 271 may be disposed in each of the plurality of semiconductor chips 220. In some embodiments, the plurality of TSVs 271 may not be disposed in the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220. Each of the plurality of TSVs 271 may include silicon (Si). Each of the plurality of bumps 273 may be disposed between two adjacent second semiconductor chips 220. Each bump 273 may be connected to a corresponding TSV 271. In some embodiments, a wiring layer connecting the corresponding bump 273 to the corresponding TSV 271 may be provided between each of the bumps 273 and the corresponding TSV 271. An insulating layer may be further provided between each of the bumps 273 and the corresponding TSV 271.

[0070] The second molding unit 280d may surround the second semiconductor chip 220 and may cover the upper surface of the second packaging substrate 210. The second molding unit 280d may cover the upper surface of the second packaging substrate 210 and the side surface of the second semiconductor chip 220. In some embodiments, such as FIG. 2 As shown, the second molding unit 280d can cover the upper surface of the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220. In other embodiments, with FIG. 2 Unlike other methods, the second molding unit 280d may not cover the upper surface of the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220. The upper surface of the second molding unit 280d and the upper surface of the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220 may be disposed on the same plane.

[0071] In some embodiments, a heat dissipation component may be attached to the upper surface of the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220. A thermal interface material (TIM) layer may be disposed between the upper surface of the topmost second semiconductor chip 220 of the stacked plurality of second semiconductor chips 220 and the heat dissipation component.

[0072] FIG. 3 This is a cross-sectional view showing a semiconductor package 3000 according to an embodiment. The following will describe... FIG. 3 The semiconductor package 3000 shown is FIG. 1A The differences between the semiconductor packages 1000a shown.

[0073] Reference FIG. 3The semiconductor package 3000 may include a first sub-package SP1e and a second sub-package SP2. That is, the semiconductor package 3000 may include the first sub-package SP1e, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0074] Specifically, such as FIG. 3 As shown, the first sub-package SP1e may include an upper filler layer 150e, instead of FIG. 1A The first sub-package SP1 shown includes an upper filler layer 150a. The upper filler layer 150e may include a central portion P1e and an outer portion P2e. The outer portion P2e of the upper filler layer 150e may not cover at least a portion of the sidewall of the first semiconductor chip 120. In some embodiments, the outer portion P2e of the upper filler layer 150e may not cover the sidewall of the first semiconductor chip 120. In other embodiments, the outer portion P2e of the upper filler layer 150e may cover the upper portion of the sidewall of the first semiconductor chip 120, but may not cover the lower portion of the sidewall of the first semiconductor chip 120.

[0075] For example, such as FIG. 3 As shown, the outer portion P2e of the upper filler layer 150e can extend along the bottom of the interposer layer 140, rather than extending along the entire sidewall of the first semiconductor chip 120. For example, the sidewall of the outer portion P2e facing the sidewall of the first semiconductor chip 120 can be inclined away from the first semiconductor chip 120. For example, the outer portion P2e of the upper filler layer 150e can include extending further away from the first semiconductor chip 120 in a direction closer to the first package substrate 110, for example, facing the inner wall of the first semiconductor chip 120. That is, as the distance from the first package substrate 110 decreases, the distance between the inner wall and the first semiconductor chip 120 in the Y direction can increase. The inner wall can be inclined in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction).

[0076] FIG. 4 This is a cross-sectional view showing a semiconductor package 4000 according to an embodiment. The following will describe... FIG. 4 The semiconductor package 4000 shown is FIG. 1A The differences between the semiconductor packages 1000a shown.

[0077] Reference FIG. 4 The semiconductor package 4000 may include a first sub-package SP1f and a second sub-package SP2. That is, the semiconductor package 4000 may include a first sub-package SP1f, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0078] Specifically, such as FIG. 4 As shown, the first sub-package SP1f may include a first chip interconnect unit 130f, instead of FIG. 1A The first sub-package SP1 shown includes a first chip interconnect unit 130. The first chip interconnect unit 130f can connect the first semiconductor chip 120 to the first package substrate 110. The first chip interconnect unit 130f can be, for example, a wire. In this case, the first chip interconnect unit 130f can extend between the upper surface of the first semiconductor chip 120 and the upper surface of the first package substrate 110. In some embodiments, the upper filler layer 150a can be spaced apart from the first package substrate 110 without contacting it, and a portion of the first chip interconnect unit 130f can be disposed in the upper filler layer 150a. For example, the upper portion of the first chip interconnect unit 130f can be disposed in the upper filler layer 150a, and the lower portion of the first chip interconnect unit 130f can be disposed in the first molding unit 180. In some other embodiments, the upper filler layer 150a can contact the first package substrate 110 and can completely surround the first chip interconnect unit 130f.

[0079] FIG. 5 This is a cross-sectional view showing a semiconductor package 5000 according to an embodiment. The following will describe... FIG. 5 The semiconductor package 5000 shown is FIG. 1A The differences between the semiconductor packages 1000a shown.

[0080] Reference FIG. 5 The semiconductor package 5000 may include a first sub-package SP1g and a second sub-package SP2. That is, the semiconductor package 5000 may include the first sub-package SP1g, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0081] Specifically, such as FIG. 5 As shown, the first sub-package SP1g may include the first package substrate 110a, instead of FIG. 1AThe first sub-package SP1 shown includes a first package substrate 110. The first package substrate 110a may include: a base portion 111 including a flat upper surface; and a protrusion 115 protruding in a direction perpendicular to the upper surface of the base portion 111 (e.g., in the Z direction). For example, the protrusion 115 may extend upward from the upper surface of the base portion 111 to contact the bottom of the upper filler layer 150a. The protrusion 115 may be a solder mask dam. At least a portion of the protrusion 115 may include a portion of the solder mask layer of the first package substrate 110a. The protrusion 115 may have a fourth width W4 in a direction parallel to the upper surface of the first package substrate 110a (e.g., in the Y direction). The protrusion 115 may have a height H from the upper surface of the base portion 111 in a direction perpendicular to the upper surface of the first package substrate 110a (e.g., in the Z direction). In some embodiments, the fourth width W4 of the protrusion 115 may be greater than the height H of the protrusion 115. When the fourth width W4 of the protrusion 115 is greater than the height H of the protrusion 115, the area of ​​the upper filling layer 150a supported by the protrusion 115 can be widened, and thus, the deflection of the overhang portion of the intermediate layer 140 supported by the upper filling layer 150a can be effectively prevented.

[0082] The upper filler layer 150a can contact the protrusion 115 of the first package substrate 110a. Specifically, the outer portion P2a of the upper filler layer 150a can contact the protrusion 115 of the first package substrate 110a. That is, the upper filler layer 150a can be supported by the protrusion 115 of the first package substrate 110a. Therefore, the portion of the interposer layer 140 that hangs over the first semiconductor chip 120 can be supported by the outer portion P2a of the upper filler layer 150a and the protrusion 115, thus effectively preventing the deflection of the portion of the interposer layer 140 that hangs over the first semiconductor chip 120.

[0083] FIG. 6A This is a plan view of the first packaging substrate 110a included in the semiconductor package according to an embodiment. (Refer to...) FIG. 6A The first packaging substrate 110a may include a protrusion 115. Viewed from above, the protrusion 115 of the first packaging substrate 110a may be formed in a closed loop shape to have a certain (e.g., constant) width W4. In some embodiments, as seen from above, the protrusion 115 of the first packaging substrate 110a may include a quadrilateral upper surface, and the protrusion 115 may have a quadrilateral ring shape.

[0084] FIG. 6B This is a plan view of the first packaging substrate 110b included in the semiconductor package according to an embodiment. FIG. 5 The semiconductor package 5000 shown may include FIG. 6B The first packaging substrate 110b shown is not... FIG. 6AThe first packaging substrate 110a shown is illustrated.

[0085] Reference FIG. 6B The first packaging substrate 110b may include a plurality of protrusions 115b. The plurality of protrusions 115b may be disposed along a dicing ring and may be spaced apart from each other. Each of the plurality of protrusions 115b may have a generally cuboid shape, but is not limited thereto.

[0086] FIG. 6C This is a plan view of the first packaging substrate 110c included in the semiconductor package according to an embodiment. FIG. 5 The semiconductor package 5000 shown may include FIG. 6C The first packaging substrate 110c shown is not the one shown. FIG. 6A The first packaging substrate 110a shown is illustrated.

[0087] Reference FIG. 6C The first package substrate 110c may include a plurality of protrusions 115c. The plurality of protrusions 115c may be spaced apart from each other. Each of the plurality of protrusions 115c may be adjacent to a corresponding edge of the upper surface of the first package substrate 110c and may extend in a direction parallel to the corresponding edge. For example, the upper surface of the first package substrate 110c may include a first edge E1 and a second edge E2 extending in the Y direction and opposite to each other, and a third edge E3 and a fourth edge E4 extending in the X direction and opposite to each other. One of the plurality of protrusions 115c may extend in the Y direction and may be closer to the first edge E1 than the second edge E2. Another of the plurality of protrusions 115c may extend in the Y direction and may be closer to the second edge E2 than the first edge E1. Another of the plurality of protrusions 115c may extend in the X direction and may be closer to the third edge E3 than the fourth edge E4. Another of the plurality of protrusions 115c may extend in the X direction and may be closer to the fourth edge E4 than the third edge E3. For example, such as FIG. 6C As shown, the plurality of protrusions 115c may be four protrusions spaced apart from each other and arranged in a rectangular shape (in the top view), but the embodiments are not limited thereto.

[0088] FIG. 7 This is a cross-sectional view showing a semiconductor package 7000 according to an embodiment. The following will describe... FIG. 7 The semiconductor package 7000 shown is... FIG. 1A The differences between the semiconductor packages 1000a shown.

[0089] Reference FIG. 7The semiconductor package 7000 may include a first sub-package SP1h and a second sub-package SP2. That is, the semiconductor package 7000 may include the first sub-package SP1h, rather than... FIG. 1A The first sub-package SP1 of the semiconductor package 1000a shown.

[0090] Specifically, such as FIG. 7 As shown, with FIG. 1A Unlike the first sub-package SP1 shown, the first sub-package SP1h may also include an underfill layer 160. The underfill layer 160 may be disposed between the first semiconductor chip 120 and the first package substrate 110 and may surround a plurality of first chip interconnect units 130. The underfill layer 160 may include, for example, DAF, underfill, NCF, or NCP. The underfill layer 160 may include, for example, an epoxy-based organic material.

[0091] FIG. 8 This is a cross-sectional view showing a semiconductor package 8000 according to an embodiment. The following will describe... FIG. 8 The semiconductor package 8000 shown is... FIG. 7 The differences between the semiconductor packages 7000 shown.

[0092] Reference FIG. 8 The semiconductor package 8000 may include a first sub-package SP1i and a second sub-package SP2. That is, the semiconductor package 8000 may include a first sub-package SP1i, rather than... FIG. 7 The first sub-package SP1h of the semiconductor package 7000 shown.

[0093] Specifically, such as FIG. 8 As shown, the first sub-package SP1i may include an upper fill layer 150i, instead of FIG. 7 The first sub-package SP1h shown includes an upper filler layer 150a. The upper filler layer 150i may include an outer portion P2i and a central portion P1i. The central portion P1i of the upper filler layer 150i may be disposed between the first semiconductor chip 120 and the interposer layer 140. The outer portion P2i of the upper filler layer 150i may surround the central portion P1i and may contact the lower surface of the interposer layer 140, the lower filler layer 160, the sidewall of the first semiconductor chip 120, and the first package substrate 110.

[0094] Since the outer portion P2i of the upper filler layer 150i contacts the first package substrate 110, the outer portion P2i of the upper filler layer 150i can be supported by the first package substrate 110. Therefore, the portion of the interposer layer 140 that hangs over the first semiconductor chip 120 can be supported by the first package substrate 110 and the outer portion P2i of the upper filler layer 150i. Thus, deflection of the hanging portion of the interposer layer 140 can be prevented or substantially minimized.

[0095] FIG. 9 This is a cross-sectional view showing a semiconductor package 9000 according to an embodiment. The following will describe... FIG. 9 The semiconductor package 9000 shown is... FIG. 8 The differences between the semiconductor packages 8000 shown.

[0096] Reference FIG. 9 The semiconductor package 9000 may include a first sub-package SP1j and a second sub-package SP2. That is, the semiconductor package 9000 may include the first sub-package SP1j, rather than... FIG. 8 The first sub-package SP1i of the semiconductor package 8000 shown.

[0097] Specifically, such as FIG. 9 As shown, the first sub-package SP1j may include an underfill layer 160j, instead of FIG. 8 The first sub-package SP1i shown includes a lower filler layer 160. The lower filler layer 160j may contact at least a portion of the sidewall of the first semiconductor chip 120. For example, the lower filler layer 160j may contact the lower portion of the sidewall of the first semiconductor chip 120. In some embodiments, the sidewall of the lower filler layer 160j may protrude outward from the space 2 between the first package substrate 110 and the first semiconductor chip 120 to the outside.

[0098] FIG. 10 This is a cross-sectional view showing a semiconductor package 10000 according to an embodiment. The following will describe... FIG. 10 The semiconductor package 10000 shown is... FIG. 8 The differences between the semiconductor packages 8000 shown.

[0099] Reference FIG. 10 The semiconductor package 10000 may include a first sub-package SP1k and a second sub-package SP2. That is, the semiconductor package 10000 may include the first sub-package SP1k, rather than... FIG. 8 The first sub-package SP1i of the semiconductor package 8000 shown.

[0100] Specifically, such as FIG. 10As shown, the first sub-package SP1k may include a lower fill layer 160k and an upper fill layer 150k, instead of FIG. 8 The first sub-package SP1i includes a lower filler layer 160 and an upper filler layer 150i. The lower filler layer 160k may include a central portion P3k and an outer portion P4k. The central portion P3k of the lower filler layer 160k may be disposed between the first semiconductor chip 120 and the first package substrate 110. The outer portion P4k of the lower filler layer 160k may surround the central portion P3k and may contact the upper surface of the first package substrate 110 and the sidewall of the first semiconductor chip 120. The outer portion P4k of the lower filler layer 160k may cover the entire sidewall of the first semiconductor chip 120. The upper surface of the outer portion P4k of the lower filler layer 160k and the upper surface of the first semiconductor chip 120 may be coplanar.

[0101] The lower filler layer 160k may have a fifth width W5 in a direction parallel to the upper surface of the first package substrate 110 (e.g., in the Y direction). In some embodiments, the fifth width W5 of the lower filler layer 160k may be the same as the second width W2 of the interposer layer 140. In some other embodiments, the fifth width W5 of the lower filler layer 160k may be greater than the second width W2 of the interposer layer 140. The width W5 of the lower filler layer 160k may be less than the second width W2 of the interposer layer 140.

[0102] The central portion P3k of the lower filler layer 160k may have a third thickness T3 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction), and the outer portion P4k of the lower filler layer 160k may have a fourth thickness T4 in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction). The third thickness T3 of the central portion P3k of the lower filler layer 160k may be less than the fourth thickness T4 of the outer portion P4k of the lower filler layer 160k.

[0103] The upper filler layer 150k may not cover the sidewalls of the first semiconductor chip 120. The upper filler layer 150k may include a central portion P1k and an outer portion P2k. The central portion P1k of the upper filler layer 150k may be disposed between the first semiconductor chip 120 and the interposer layer 140. The outer portion P2k of the upper filler layer 150k may surround the central portion P1k of the upper filler layer 150k and may contact the lower surface of the interposer layer 140 and the lower filler layer 160k. The upper filler layer 150k may include a flat lower surface. The outer portion P2k and the central portion P1k of the upper filler layer 150k may have the same thickness in a direction perpendicular to the upper surface of the first package substrate 110 (e.g., in the Z direction).

[0104] In the semiconductor package 10000 according to an embodiment, the portion of the interposer 140 that hangs over the first semiconductor chip 120 can be supported by an upper filler layer 150k and a lower filler layer 160k. Therefore, deflection of the hanging portion of the interposer 140 can be prevented.

[0105] FIG. 11 This is a cross-sectional view showing a semiconductor package 11000 according to an embodiment. The following will describe... FIG. 11 The semiconductor package 11000 shown is... FIG. 10 The differences between the semiconductor packages 10000 shown.

[0106] Reference FIG. 11 The semiconductor package 11000 may include a first sub-package SP1m and a second sub-package SP2. That is, the semiconductor package 11000 may include the first sub-package SP1m, rather than... FIG. 10 The first sub-package SP1k of the semiconductor package 10000 shown.

[0107] Specifically, such as FIG. 11 As shown, the first sub-package SP1m may include an upper filler layer 150m and a lower filler layer 160m, respectively replacing... FIG. 10 The first sub-package SP1k shown includes an upper fill layer 150k and a lower fill layer 160k. The upper fill layer 150k may include a central portion P1m and an outer portion P2m. The outer portion P2m of the upper fill layer 150k may contact a portion of the sidewall of the first semiconductor chip 120. The lower fill layer 160k may include a central portion P3m and an outer portion P4m. The outer portion P4m of the lower fill layer 160k may contact another portion of the sidewall of the first semiconductor chip 120. The lower surface of the upper fill layer 150k may contact the upper surface of the lower fill layer 160k. The boundary surface between the lower surface of the upper fill layer 150k and the upper surface of the lower fill layer 160k may be positioned at a level lower than the upper surface of the first semiconductor chip 120 and higher than the lower surface of the first semiconductor chip 120.

[0108] FIG. 12A to FIG. 12D This is a cross-sectional view illustrating stages in a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 1A to FIG. 3 The methods for each of the semiconductor packages are shown in the figure.

[0109] Reference FIG. 12AA first semiconductor chip 120, to which multiple first chip connection units 130 are attached, can be attached to a first packaging substrate 110 such that the multiple first chip connection units 130 face the first packaging substrate 110. The multiple first chip connection units 130 can connect the first semiconductor chip 120 to the first packaging substrate 110.

[0110] exist FIG. 12A The illustration shows the external connection unit 190 being attached to the lower surface of the first package substrate 110 before the first semiconductor chip 120 is attached to it; however, this embodiment is not limited to this. In some embodiments, such as FIG. 12D As shown, the second sub-package SP2 can be attached to the first sub-package SP1, and then the external connection unit 190 can be attached to the lower surface of the first package substrate 110.

[0111] Reference FIG. 12B The upper filler layer 150a can be attached to the lower surface of the interposer layer 140. Subsequently, the interposer layer 140 to which the upper filler layer 150a is attached can be attached to the first semiconductor chip 120 such that the upper filler layer 150a faces the first semiconductor chip 120. That is, the interposer layer 140 having the upper filler layer 150a can be disposed above the first semiconductor chip 120 such that the upper filler layer 150a faces the top of the first semiconductor chip 120. When the interposer layer 140 (on the lower surface of the interposer layer 140) is attached to the lower surface of the interposer layer 140... FIG. 12B While attaching the upper filler layer 150a to the first semiconductor chip 120 (in the downward direction of the arrow in the diagram), pressure can be applied to the interposer layer 140. When pressure is applied to the interposer layer 140, the upper filler layer 150a can deform based on the shape of the first semiconductor chip 120. For example, the portion of the upper filler layer 150a hanging over the semiconductor chip 120 can be pushed along the sidewall of the first semiconductor chip 120 towards the first package substrate 110. In other words, the lower surface of the upper filler layer 150a can move downwards more than the upper surface of the first semiconductor chip 120, for example, beyond the upper surface of the first semiconductor chip 120. Pressure can be applied to the interposer layer 140 until the height from the upper surface of the first package substrate 110 to the lower surface of the upper filler layer 150a becomes equal to the height from the upper surface of the first package substrate 110 to the lower surface of the first semiconductor chip 120.

[0112] Therefore, as FIG. 12C As shown, the thickness T2 of the outer portion P2a of the upper filling layer 150a can be greater than the thickness T1 of the central portion P1a of the upper filling layer 150a. FIG. 12CAs further shown, the interposer 140 can be connected to the first package substrate 110 by using a plurality of wires 170. For example, the plurality of wires 170 can be formed to extend from the upper surface of the interposer 140 to the upper surface of the first package substrate 110.

[0113] Subsequently, the first molding unit 180 can be formed on the first packaging substrate 110. The first molding unit 180 can be formed to surround the first semiconductor chip 120, a plurality of first chip interconnect units 130, a plurality of wires 170, an upper filler layer 150a and an interposer layer 140, and cover the upper surface of the first packaging substrate 110.

[0114] Reference FIG. 12D Multiple openings for exposing the interposer layer 140U can be formed in the first molding unit 180, thereby forming the first sub-package SP1. For example, the multiple openings can be formed by a laser drilling process.

[0115] It can be fabricated independently of the first sub-package SP1 FIG. 1A The second sub-package SP2 is shown in the figure. The process of fabricating the second sub-package SP2 will be described. At least one second semiconductor chip 220 can be attached to a second packaging substrate 210 using an adhesive layer 230. The second packaging substrate 210 can be connected to the second semiconductor chip 220 by a plurality of second chip connection units 270. A second molding unit 280 can be formed around the plurality of second chip connection units 270 and the second semiconductor chip 220 and covering the upper surface of the second packaging substrate 210. A plurality of inter-package connection units 290 can be attached to the lower surface of the second packaging substrate 210, thereby fabricating the second sub-package SP2.

[0116] Subsequently, the second sub-package SP2 can be attached to the first sub-package SP1 so that the multiple inter-package connection units 290 contact the multiple connection pads 140U of the interposer layer 140 through the multiple openings of the first molding unit 180. Thus, the semiconductor package 1000a can be completed.

[0117] In some embodiments, a plurality of lower inter-package connection units, each connected to a plurality of connection pads 140U of the interposer 140, may be disposed in a plurality of openings that expose the plurality of connection pads 140U of the interposer 140. Subsequently, a plurality of upper inter-package connection units may be attached to the lower surface of the second package substrate 210, and the plurality of lower inter-package connection units may then be connected to the plurality of upper inter-package connection units, thereby forming a plurality of inter-package connection units 290.

[0118] In order to manufacture FIG. 1B The semiconductor package 1000b shown is, for example FIG. 12AAs shown, the first semiconductor chip 120 can be attached to the first packaging substrate 110. Subsequently, referring to... FIG. 1B The upper filler layer 150b can be attached to the lower surface of the interposer layer 140. The interposer layer 140, to which the upper filler layer 150b is attached, can be placed on the first semiconductor chip 120. Subsequently, pressure can be applied to the interposer layer 140 until the height from the upper surface of the first packaging substrate 110 to the lower surface of the upper filler layer 150b is greater than the height from the upper surface of the first packaging substrate 110 to the lower surface of the first semiconductor chip 120. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0119] In order to manufacture FIG. 1C The semiconductor package 1000c shown is, for example FIG. 12A As shown, the first semiconductor chip 120 can be attached to the first packaging substrate 110. Subsequently, referring to... FIG. 1C The upper filler layer 150c can be attached to the lower surface of the interposer layer 140. The interposer layer 140, to which the upper filler layer 150c is attached, can be placed on the first semiconductor chip 120. Subsequently, pressure can be applied to the interposer layer 140 until the height from the upper surface of the first package substrate 110 to the lower surface of the upper filler layer 150c becomes less than the height from the upper surface of the first package substrate 110 to the lower surface of the first semiconductor chip 120. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0120] In order to manufacture FIG. 2 The semiconductor package 2000 shown is configured to perform the above-mentioned reference. FIG. 12A to FIG. 12D The described process is used to fabricate the first sub-package SP1. Subsequently, the following can be fabricated: FIG. 2 The second sub-package SP2d is shown. The process of fabricating the second sub-package SP2d may include fabricating a stacked structure in which second semiconductor chips 220 connected to each other via TSV 271 and bumps 273 are stacked, placing the stacked structure on a second packaging substrate 210, and forming a second molding unit 280. Subsequently, by coupling the second sub-package SP2d to the first sub-package SP1, the process can be completed. FIG. 2 The second semiconductor package 2000 is shown.

[0121] In order to manufacture FIG. 3 The semiconductor package 3000 shown is, for example FIG. 12A As shown, the first semiconductor chip 120 can be attached to the first packaging substrate 110. Then, referring to... FIG. 3The upper filler layer 150e can be attached to the lower surface of the interposer layer 140. The interposer layer 140 with the upper filler layer 150e attached thereto can be placed on the first semiconductor chip 120. Subsequently, the lower surface of the upper filler layer 150e can be moved downwards, in which case heat and / or pressure can be applied to the interposer layer 140 to prevent the upper filler layer 150e from covering at least a portion of the sidewalls of the first semiconductor chip 120. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0122] FIG. 13 This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 4 The method of the semiconductor package 4000 shown.

[0123] Reference FIG. 13 The first semiconductor chip 120 can be attached to the first packaging substrate 110. Subsequently, the first semiconductor chip 120 can be connected to the first packaging substrate 110 via a first chip connection unit 130f. For example, the first chip connection unit 130f can be formed to extend from the upper surface of the first semiconductor chip 120 to the upper surface of the first packaging substrate 110.

[0124] Subsequently, the upper filler layer 150a can be attached to the lower surface of the interposer layer 140. The interposer layer 140, to which the upper filler layer 150a is attached, can then be placed on the first semiconductor chip 120, and pressure can be applied to the interposer layer 140. Therefore, the upper filler layer 150a can surround a portion of the first chip interconnect unit 130f. In some embodiments, the upper filler layer 150a and the first package substrate 110 can be spaced apart from each other without contacting each other. In some other embodiments, the upper filler layer 150a can contact the first package substrate 110 and can completely surround the first chip interconnect unit 130f. Subsequent processes and manufacturing FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0125] FIG. 14 This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 5 The method of the semiconductor package 5000 shown.

[0126] Reference FIG. 14A first packaging substrate 110a, including protrusions 115, can be provided. An upper filler layer 150a can be attached to the lower surface of an interposer layer 140. Subsequently, the interposer layer 140, to which the upper filler layer 150a is attached, can be placed on a first semiconductor chip 120, and pressure can be applied to the interposer layer 140 to make the upper filler layer 150a contact the protrusions 115. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0127] FIG. 15 This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 7 The method of the semiconductor package 7000 shown.

[0128] Reference FIG. 15 A first semiconductor chip 120 can be attached to a first packaging substrate 110. A lower filler layer 160 surrounding a plurality of first chip interconnect units 130 can fill the space between the first packaging substrate 110 and the first semiconductor chip 120. In some embodiments, the lower filler layer 160 can be attached to the lower surface of the first semiconductor chip 120, allowing the first semiconductor chip 120 to be placed on the first packaging substrate 110 with the lower filler layer 160 facing the first packaging substrate 110, and pressure can be applied to the first semiconductor chip 120. In some other embodiments, the first semiconductor chip 120 can be attached to the first packaging substrate 110, and then a lower filler layer 160 filling the space between the first packaging substrate 110 and the first semiconductor chip 120 can be formed. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0129] FIG. 16A and 16B This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 8 The method of the semiconductor package 8000 shown.

[0130] Reference FIG. 16A As mentioned above FIG. 15 The first semiconductor chip 120 can be attached to the first packaging substrate 110 so that the lower filler layer 160 fills the space between the first packaging substrate 110 and the first semiconductor chip 120. An upper filler layer 150i can be formed on or attached to the lower surface of the interposer layer 140. Subsequently, the interposer layer 140 with the upper filler layer 150i attached thereto can be placed on the first semiconductor chip 120 so that the upper filler layer 150i faces the first semiconductor chip 120. Pressure and heat can then be applied to the interposer layer 140.

[0131] Therefore, as FIG. 16B As shown, the upper filler layer 150i is deformable, therefore, the upper filler layer 150i can contact the upper surface of the first package substrate 110. In some embodiments, the upper filler layer 150i can contact the side surface of the lower filler layer 160. Subsequent processes and manufacturing FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0132] FIG. 17 This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 9 The method of the semiconductor package 9000 shown.

[0133] Reference FIG. 17 A first semiconductor chip 120 can be attached to a first packaging substrate 110. A lower filler layer 160 surrounding a plurality of first chip interconnect units 130 can fill the space between the first packaging substrate 110 and the first semiconductor chip 120. In this case, the lower filler layer 160j can be formed to cover at least a portion of the sidewalls of the first semiconductor chip 120. In some embodiments, for example, the lower filler layer 160j can be attached to the lower surface of the first semiconductor chip 120, and then the first semiconductor chip 120 can be placed on the first packaging substrate 110 such that the lower filler layer 160j faces the first packaging substrate 110. Subsequently, by applying pressure to the first semiconductor chip 120, the plurality of first chip interconnect units 130 can be connected to the first packaging substrate 110. In such a process, a portion of the lower filler layer 160j can overflow from the space between the first packaging substrate 110 and the first semiconductor chip 120 to the outside and can protrude protrudingly. In some embodiments, the lower filler layer 160j can overflow from the space between the first package substrate 110 and the first semiconductor chip 120 to the outside and can contact at least a portion of the sidewall of the first semiconductor chip 120. In some other embodiments, the first semiconductor chip 120 can be attached to the first package substrate 110, and then the lower filler layer 160j can be formed to fill the space between the first package substrate 110 and the first semiconductor chip 120 and contact the sidewall of the first semiconductor chip 120. Subsequent processes and manufacturing FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0134] FIG. 18A and 18B This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 10 The method of the semiconductor package 10000 shown.

[0135] ReferenceFIG. 18A A lower filler layer 160k can be formed such that the upper surface of the first semiconductor chip 120 and the upper surface of the lower filler layer 160k are coplanar. In some embodiments, the first semiconductor chip 120 can be attached to a first packaging substrate 110, and then the lower filler layer 160k can be formed such that the lower filler layer 160k surrounds the first semiconductor chip 120, and the upper surface of the first semiconductor chip 120 and the upper surface of the lower filler layer 160k are coplanar. In some other embodiments, the first semiconductor chip 120 to which the lower filler layer 160k is attached can be attached to the first packaging substrate 110, with the lower filler layer 160k facing the first packaging substrate 110. Subsequently, a tape can be attached to the upper surface of the first semiconductor chip 120 and the upper surface of the lower filler layer 160k, and pressure can be applied to the tape. Subsequently, when the tape is removed, the upper surface of the first semiconductor chip 120 and the upper surface of the lower filler layer 160k can be coplanar.

[0136] Reference FIG. 18B An interposer 140, to which an upper filler layer 150k is attached, can be attached to a first semiconductor chip 120 such that the upper filler layer 150k faces the first semiconductor chip 120. Subsequent processes and manufacturing... FIG. 1A The method is the same for the semiconductor package 1000a shown, therefore its detailed description is omitted.

[0137] FIG. 19A to FIG. 19C This is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. The manufacturing process will be described below. FIG. 11 The method of the semiconductor package 11000 shown.

[0138] Reference FIG. 19A The lower filler layer 160m can be formed to cover only a portion of the sidewalls of the first semiconductor chip 120. In some embodiments, the first semiconductor chip 120 can be attached to the first packaging substrate 110 and the lower filler layer 160m can be formed on the first packaging substrate 110 such that the lower filler layer 160m covers only a portion of the sidewalls of the first semiconductor chip 120.

[0139] Refer to 19B to FIG. 19C The upper filler layer 150m can be attached to the lower surface of the interposer layer 140. Subsequently, the interposer layer 140 to which the upper filler layer 150m is attached can be placed on the first semiconductor chip 120 such that the upper filler layer 150m faces the first semiconductor chip 120, and by applying pressure to the interposer layer 140, the upper filler layer 150m can cover another portion of the sidewall of the first semiconductor chip 120.

[0140] By summarizing and reviewing, the example embodiment provides a semiconductor package in which the deflection of the interposer in the package is reduced. That is, support is provided between the substrate and the portion of the interposer 140 that hangs over the first semiconductor chip 120 to reduce the deflection of the hanging portion. The support may include a thick portion of an upper filler layer, a protrusion projecting from the substrate, and a lower filler layer extending toward the interposer between the semiconductor chip and the substrate.

[0141] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art upon filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package comprising: a first package substrate; a first semiconductor chip on the first package substrate; a plurality of first chip connection units for connecting the first package substrate to the first semiconductor chip; an interposer on the first semiconductor chip, the interposer having a width in a direction parallel to an upper surface of the first package substrate that is greater than a width of the first semiconductor chip in the direction parallel to the upper surface of the first package substrate; a molding unit surrounding the interposer; and an upper fill layer including a central portion between the first semiconductor chip and the interposer, and an outer portion surrounding the central portion, the outer portion having a thickness in a direction perpendicular to the upper surface of the first package substrate that is greater than a thickness of the central portion in the direction perpendicular to the upper surface of the first package substrate, wherein a width of the upper fill layer in the direction parallel to the upper surface of the first package substrate is the same as a width of the interposer in the direction parallel to the upper surface of the first package substrate. the outer portion of the upper fill layer is in contact with a lower surface of the interposer and with sidewalls of the first semiconductor chip.

2. The semiconductor package of claim 1, wherein, the upper fill layer is spaced apart from the first package substrate.

3. The semiconductor package of claim 1, wherein, the upper fill layer is in contact with the first package substrate.

4. The semiconductor package of claim 1, wherein, 5. The semiconductor package of claim 4, wherein the first package substrate includes a base portion and a protrusion protruding upward from an upper surface of the base portion, and the upper fill layer is in contact with the protrusion of the first package substrate. the protrusion of the first package substrate has a closed loop shape in plan view.

6. The semiconductor package of claim 5, wherein, a width of the protrusion in a direction parallel to the upper surface of the first package substrate is greater than a height of the protrusion in a direction perpendicular to the upper surface of the first package substrate.

7. The semiconductor package of claim 5, wherein, the upper fill layer is in contact with an entire upper surface of the first semiconductor chip and an entire lower surface of the interposer.

8. The semiconductor package of claim 1, wherein, 9. The semiconductor package of claim 1, further comprising a lower fill layer between the first package substrate and the first semiconductor chip, the lower fill layer surrounding the plurality of first chip connection units. the lower fill layer is in contact with the upper fill layer.

10. The semiconductor package of claim 9, wherein, the lower fill layer is in contact with at least a portion of sidewalls of the first semiconductor chip.

11. The semiconductor package of claim 9, wherein, 12. The semiconductor package of claim 1, further comprising: a second package substrate on the interposer; a package-to-package connection unit between the second package substrate and the interposer; and at least one second semiconductor chip on the second package substrate.

13. A semiconductor package comprising: a first package substrate; a first semiconductor chip on the first package substrate; a plurality of first chip connection units for connecting the first package substrate to the first semiconductor chip; ​ ​ an interposer on the first semiconductor chip, a width of the interposer in a direction parallel to the upper surface of the first package substrate being greater than a width of the first semiconductor chip in the direction parallel to the upper surface of the first package substrate; a molding unit surrounding the interposer; an upper filling layer filling a space between the interposer and the first semiconductor chip; and a lower filling layer including a central portion filling a space between the first semiconductor chip and the first package substrate, and an outer portion surrounding the central portion of the lower filling layer, a thickness of the outer portion of the lower filling layer in a direction perpendicular to the upper surface of the first package substrate being greater than a thickness of the central portion of the lower filling layer in the direction perpendicular to the upper surface of the first package substrate, wherein a width of the upper filling layer in the direction parallel to the upper surface of the first package substrate is the same as a width of the interposer in the direction parallel to the upper surface of the first package substrate. the upper filling layer includes a central portion between the first semiconductor chip and the interposer, and an outer portion surrounding the central portion of the upper filling layer, and a thickness of the outer portion of the upper filling layer in a direction perpendicular to the upper surface of the first package substrate is greater than a thickness of the central portion of the upper filling layer in the direction perpendicular to the upper surface of the first package substrate.

14. The semiconductor package of claim 13, wherein, the lower filling layer is in contact with the upper filling layer.

15. The semiconductor package of claim 13, wherein, the upper filling layer is in contact with an upper portion of a sidewall of the first semiconductor chip.

16. The semiconductor package of claim 13, wherein, an upper surface of the first semiconductor chip and an upper surface of the outer portion of the lower filling layer are coplanar.

17. The semiconductor package of claim 13, wherein, the outer portion of the lower filling layer is in contact with a lower portion of the sidewall of the first semiconductor chip.

18. The semiconductor package of claim 13, wherein, the outer portion of the lower filling layer is in contact with an entire sidewall of the first semiconductor chip.

19. The semiconductor package of claim 13, wherein, 20. The semiconductor package of claim 13, further comprising: a second package substrate on the interposer; a package-to-package connection unit between the second package substrate and the interposer; and at least one second semiconductor chip on the second package substrate.

21. The semiconductor package of claim 13, further comprising a plurality of wires connecting an upper surface of the interposer to the first package substrate. the molding unit surrounds the lower filling layer and covers the first package substrate.

23. A semiconductor package, comprising:

22. The semiconductor package of claim 13, wherein, a first sub-package including: a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units between the first package substrate and the first semiconductor chip, an interposer on the first semiconductor chip, a width of the interposer in a direction parallel to an upper surface of the first package substrate being greater than a width of the first semiconductor chip in the direction parallel to the upper surface of the first package substrate, a first molding unit surrounding the interposer; and an upper filling layer filling a space between the interposer and the first semiconductor chip, and a lower filling layer filling a space between the first semiconductor chip and the first package substrate. ​ a lower filling layer filling a space between the first semiconductor chip and the first package substrate; and a second sub-package including: a plurality of inter-package connection units on the interposer, a second package substrate on the plurality of inter-package connection units, at least one second semiconductor chip on the second package substrate, and a second molding unit surrounding the at least one second semiconductor chip and covering an upper surface of the second package substrate, wherein at least one of the upper filling layer and the lower filling layer is in contact with a sidewall of the first semiconductor chip, wherein a width of the upper filling layer in a direction parallel to the upper surface of the first package substrate is the same as a width of the interposer in the direction parallel to the upper surface of the first package substrate.

24. The semiconductor package of claim 23, wherein, the upper filling layer is in contact with the sidewall of the first semiconductor chip, and the lower filling layer is spaced apart from the sidewall of the first semiconductor chip. the upper filling layer is in contact with the sidewall of the first semiconductor chip, and the lower filling layer is spaced apart from the sidewall of the first semiconductor chip.

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