Display device and method of manufacturing the same

Abstract

The present invention relates to a display device and a manufacturing method thereof, wherein the display device comprises a planarization layer covering transistors in a display area on a substrate, an organic light emitting diode on the planarization layer, a pad electrode in a non-display area surrounding the display area on the substrate, and a sacrificial layer residue covering the side surface of the pad electrode.

Description

Technical Field

[0001] Exemplary embodiments of the present inventive concept relate to an organic light emitting display device and a method of manufacturing the same. More particularly, exemplary embodiments of the present inventive concept relate to an organic light emitting display device for improving display quality and a method of manufacturing the same. Background Art

[0002] Recently, the importance of flat panel display devices having excellent characteristics such as thinness, light weight, and low power consumption has been increasing. Among the flat panel display devices, liquid crystal display devices and organic light emitting display devices are widely commercialized because they have excellent resolution and image quality. Specifically, organic light emitting display devices have attracted attention as next-generation flat panel display devices due to their high response speed, low power consumption, and self-luminescence. Summary of the invention

[0003] An embodiment relates to a display device, including a planarization layer covering transistors in a display area on a substrate, an organic light emitting diode on the planarization layer, a pad electrode in a non-display area surrounding the display area on the substrate, and a capping layer covering side surfaces of the pad electrode.

[0004] The capping layer may include a material having an etch selectivity ratio different from that of the planarization layer.

[0005] The pad electrode may include a first layer on the substrate, a second layer on the first layer, and a third layer on the second layer. The capping layer may cap a side surface of the first layer and a side surface of the second layer of the pad electrode.

[0006] The first layer and the third layer may include titanium (Ti). The second layer may include an aluminum alloy.

[0007] The display device may further include: a wire in the non-display area, the wire being connected to the pad electrode. A side surface of the wire may be capped by a capping layer.

[0008] The wire may include a first layer, a second layer, and a third layer sequentially stacked. The capping layer may cap a side surface of the first layer and a side surface of the second layer of the wire.

[0009] The organic light emitting diode may include a first electrode formed on the planarization layer, a pixel defining layer including an opening exposing the first electrode, an organic light emitting layer in the opening of the pixel defining layer, and a second electrode on the organic light emitting layer.

[0010] An embodiment also relates to a method for manufacturing a display device, comprising: forming a pad electrode in a non-display area surrounding a display area on a substrate, forming a planarization layer on the substrate to have a first thickness, the planarization layer covering a transistor formed in the display area, forming a planarization layer in the display area and forming a sacrificial layer covering the pad electrode in the non-display area, polishing the planarization layer and the sacrificial layer by a chemical mechanical polishing (CMP) process so that the planarization layer has a second thickness less than the first thickness and so that a sacrificial layer residue exposing an upper surface of the pad electrode and covering a side surface of the pad electrode is formed, and forming an organic light emitting diode on the planarization layer having the second thickness.

[0011] The sacrificial layer may include a material having an etch selectivity different from that of the planarization layer in a chemical mechanical polishing process.

[0012] The planarization layer and the sacrificial layer may be polished using a slurry having a polishing rate ratio different from that of the planarization layer and the sacrificial layer in a chemical mechanical polishing process.

[0013] The paste may include a corrosion inhibitor to prevent corrosion of the pad electrode.

[0014] The planarization layer may include an organic material, and the sacrificial layer may include an inorganic material. The sacrificial layer may be polished using a first slurry for polishing the inorganic material. A second slurry for polishing the organic material may be used to polish a portion of the thickness of the planarization layer.

[0015] When the thickness of the sacrificial layer formed on the pad electrode of the non-display area is greater than or equal to the first thickness of the planarization layer, the slurry may be selected such that a polishing rate ratio of the sacrificial layer is greater than a polishing rate ratio of the planarization layer.

[0016] When the thickness of the sacrificial layer formed on the pad electrode of the non-display area is less than the first thickness of the planarization layer, the slurry may be selected such that a polishing rate ratio of the sacrificial layer is less than a polishing rate ratio of the planarization layer.

[0017] The slurry may be squeezed by a hard polishing pad to perform the polishing process.

[0018] The pad electrode may include a first layer formed on the substrate, a second layer formed on the first layer, and a third layer formed on the second layer. The sacrificial layer residue may cap side surfaces of the first layer and the second layer of the pad electrode.

[0019] The first layer and the third layer may include titanium (Ti), and the second layer may include an aluminum alloy.

[0020] The method may further include: forming a wire in the non-display area, the wire being connected to the pad electrode. A side surface of the wire may be capped by a sacrificial layer residue.

[0021] The wire may include a first layer, a second layer, and a third layer sequentially stacked. The sacrificial layer residue may cap a side surface of the first layer and a side surface of the second layer of the wire.

[0022] Forming an organic light emitting diode may include: forming a first electrode on a planarization layer having a second thickness, forming a pixel defining layer having an opening exposing the first electrode, forming an organic light emitting layer in the opening of the pixel defining layer, and forming a second electrode on the organic light emitting layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 illustrates a plan view of a display device according to an exemplary embodiment;

[0025] Figure 2 Picture shows Figure 1 An enlarged view of a portion A of a display device;

[0026] Figure 3 The diagram shows the Figure 2 A cross-sectional view taken along lines II-I' and II-II'; and

[0027] Figures 4 to 9 Cross-sectional views illustrating stages of a method of manufacturing a display device according to an exemplary embodiment are illustrated. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.

[0029] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It should also be understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be an intervening layer. Further, it should be understood that when a layer is referred to as being "below" another layer, the layer may be directly below, or there may be one or more intervening layers. In addition, it should also be understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or there may be one or more intervening layers. The same reference numerals throughout the text refer to the same elements.

[0030] Figure 1A plan view of a display device according to an exemplary embodiment is illustrated.

[0031] Reference Figure 1 , a display device according to an exemplary embodiment may include a display area DA and a non-display area NDA. A plurality of pixels PX may be arranged in the display area DA. In the display area DA, an image may be displayed based on light emitted by the plurality of pixels PX.

[0032] The non-display area NDA may be located on at least one side of the display area DA. For example, the non-display area NDA may surround the display area DA. The non-display area NDA may include a pad area PDA in which a plurality of pads 170 are arranged.

[0033] Figure 2 Picture shows Figure 1 An enlarged view of portion A of the display device. Figure 3 The diagram shows the Figure 2 Cross-sectional views taken along lines II' and II-II'.

[0034] Reference Figure 2 and Figure 3 According to an exemplary embodiment, the display device may include a substrate 110, a thin film transistor TFT, a wire 160, a pad electrode 170, and an organic light emitting diode OLED. The organic light emitting diode OLED may include a first electrode 195, a pixel defining layer 197, an organic light emitting layer 210, and a second electrode 220.

[0035] The substrate 110 may be a transparent or opaque insulating substrate. For example, the substrate 110 may include glass or plastic such as polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyacrylate, or the like.

[0036] The buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be located in the display area DA and the non-display area NDA. The buffer layer 115 may help block impurities such as oxygen, water, etc. from penetrating the substrate 110. In addition, the buffer layer 115 may provide a flat surface on the top surface of the substrate 110. The buffer layer 115 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. In some embodiments, the buffer layer 115 may be omitted.

[0037] The thin film transistor TFT and the storage capacitor CST may be disposed on the buffer layer 115 in the display area DA. The thin film transistor TFT may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 150. In some embodiments, the thin film transistor TFT may have a top gate structure in which the gate electrode 130 is located on top of the semiconductor layer 120. In some embodiments, the thin film transistor TFT may have a bottom gate structure in which the gate electrode is located below the semiconductor layer 120.

[0038] The semiconductor layer 120 may be disposed on the buffer layer 115. The semiconductor layer 120 may be formed of amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like. The semiconductor layer 120 may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0039] The gate insulating layer 125 may be disposed on the buffer layer 115 and may cover the semiconductor layer 120. The gate insulating layer 125 may be located in the display area DA and the non-display area NDA. The gate insulating layer 125 may insulate the gate electrode 130 from the semiconductor layer 120. The gate insulating layer 125 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0040] The gate electrode 130 may be disposed on the gate insulating layer 125. The gate electrode 130 may overlap the channel region of the semiconductor layer 120. The gate electrode 130 may be formed of a first metal layer. The first metal layer may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), or the like, or an alloy of the metal.

[0041] An interlayer insulating layer 135 covering the gate electrode 130 may be disposed on the gate insulating layer 125. The interlayer insulating layer 135 may be located in the display area DA and the non-display area NDA. The interlayer insulating layer 135 may insulate the source electrode 140 and the drain electrode 150 from the gate electrode 130. The interlayer insulating layer 135 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0042] The source electrode 140 and the drain electrode 150 may be located on the interlayer insulating layer 135. The source electrode 140 and the drain electrode 150 may be connected to the source region and the drain region of the semiconductor layer 120 through contact holes formed in the interlayer insulating layer 135 and the gate insulating layer 125, respectively. The source electrode 140 and the drain electrode 150 may be formed by a second metal layer. The second metal layer may include an aluminum alloy. The aluminum alloy may include any one of copper (Cu), vanadium (V) and silicon (Si). The second metal layer may include a first layer 171, a second layer 172, and a third layer 173 stacked sequentially.

[0043] For example, the first layer 171 may be disposed on a lower surface of the second layer 172, and the third layer 173 may be disposed on an upper surface of the second layer 172. The first layer 171, the second layer 172, and the third layer 173 may include titanium (Ti), aluminum alloy, and titanium (Ti), respectively.

[0044] The storage capacitor CST includes a first storage electrode 133 formed of the same first metal layer as the gate electrode 130, and a second storage electrode 153 formed of the same second metal layer as the source electrode 140 and the drain electrode 150. The second storage electrode 153 may overlap the first storage electrode 133. The storage capacitor CST may be defined in an overlapping region of the first storage electrode 133 and the second storage electrode 153.

[0045] The wire 160 and the pad electrode 170 connected to the end of the wire 160 may be disposed on the interlayer insulating layer 135 of the non-display area NDA.

[0046] The wire 160 may be formed of the same second metal layer as the source electrode 140 and the drain electrode 150. The wire 160 may include a first layer 171, a second layer 172, and a third layer 173 sequentially stacked. The second layer 172 of the wire 160 may be used as a main wire layer. The first layer 171 and the third layer 173 of the wire 160 may be used as auxiliary wire layers for protecting the bottom surface and the top surface of the second layer 172, respectively.

[0047] The pad electrode 170 may be formed of the same second metal layer as the source electrode 140 and the drain electrode 150. The pad electrode 170 may be integrally formed with the line 160. The pad electrode 170 may include a first layer 171, a second layer 172, and a third layer 173 sequentially stacked. The second layer 172 of the pad electrode 170 may be used as a main electrode layer. The first layer 171 and the third layer 173 of the pad electrode 170 may be used as auxiliary electrode layers for protecting the bottom surface and the top surface of the second layer 172, respectively.

[0048] According to exemplary embodiments, the sacrificial layer residue 183 d (eg, the capping layer 183 d ) may cap the side surface of the pad electrode 170 disposed in the non-display area NDA.

[0049] The sacrificial layer residue 183d may prevent the side surface of the pad electrode 170 from being exposed. The side surface of the first layer 171 and the side surface of the second layer 172 of the first layer 171, the second layer 172, and the third layer 173 of the pad electrode 170 may be prevented from being exposed.

[0050] The sacrificial layer residue 183 d may cap the side surface of the second layer 172 of the pad electrode 170 to protect the main electrode layer of the pad electrode 170 from damage such as corrosion.

[0051] In addition, the sacrificial layer residue 183 d may cap the side surface of the wire 160 arranged in the non-display area NDA.

[0052] The sacrificial layer residue 183 d may cap the side surface of the second layer 172 of the wire 160 to protect the main line layer of the wire 160 from damage such as corrosion.

[0053] A planarization layer 181 having a thick thickness may be disposed on the interlayer insulating layer 135 in the display area DA to cover the source electrode 140 and the drain electrode 150. The planarization layer 181 may insulate the first electrode 195 from the source electrode 140 and the drain electrode 150. The planarization layer 181 may include an organic material such as acrylic resin, epoxy resin, polyimide resin, and polyester resin.

[0054] According to an exemplary embodiment, the thickness of the planarization layer 181 may be reduced by a predetermined amount through a CMP (chemical mechanical polishing) process, thereby eliminating a thickness difference that may be caused by the presence of a stacked layer disposed under the planarization layer 181 .

[0055] The first electrode 195 may be disposed on the planarization layer 181 in the display area DA. The first electrode 195 may be connected to the drain electrode 150 of the thin film transistor TFT through a contact hole formed in the planarization layer 181.

[0056] In an exemplary embodiment, the first electrode 195 may include a first layer 191, a second layer 192, and a third layer 193 sequentially stacked. For example, the first layer 191 may be disposed on a lower surface of the second layer 192, and the third layer 193 may be disposed on an upper surface of the second layer 192.

[0057] The first layer 191, the second layer 192, and the third layer 193 of the first electrode 195 may include indium tin oxide (ITO), silver, and indium tin oxide, respectively. The second layer 192 of the first electrode 195 may be used as a main electrode layer. The first layer 191 and the third layer 193 of the first electrode 195 may be used as auxiliary electrode layers for protecting the bottom surface and the top surface of the second layer 192, respectively.

[0058] A pixel defining layer 197 covering the first electrode 195 may be disposed on the planarization layer 181 in the display area DA. The pixel defining layer 197 may insulate the second electrode 220 from the first electrode 195. The pixel defining layer 197 may include an opening exposing the top surface of the first electrode 195, and may define a light emitting region. The pixel defining layer 197 may include an organic material such as an acrylic resin, an epoxy resin, a polyimide resin, and a polyester resin.

[0059] The organic light emitting layer 210 may be disposed in the opening exposing the top surface of the first electrode 195. The organic light emitting layer 210 may include a low-molecular organic compound or a high-molecular organic compound.

[0060] In one exemplary embodiment, the organic light emitting layer 210 may emit red light, green light, or blue light. In some embodiments, when the organic light emitting layer 210 emits white light, the organic light emitting layer 210 may have a multilayer structure including a red light emitting layer, a green light emitting layer, and a blue light emitting layer, or may have a single layer structure including a red light emitting material, a green light emitting material, and a blue light emitting material.

[0061] The second electrode 220 may be disposed on the organic light emitting layer 210 in the display area DA. The second electrode 220 may be disposed on the organic light emitting layer 210 and the pixel defining layer 197. The second electrode 220 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0062] Figures 4 to 9 are cross-sectional views of stages of a method of manufacturing a display device according to an exemplary embodiment.

[0063] Reference Figure 4 , a thin film transistor TFT, a line 160 and a pad electrode 170 may be formed on the substrate 110 .

[0064] The buffer layer 115 may be formed on the display area DA and the non-display area NDA on the substrate 110. For example, the buffer layer 115 may be formed by a suitable method such as chemical vapor deposition, sputtering, etc. using silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0065] The semiconductor layer 120 may be formed in the display area DA of the substrate 110 on which the buffer layer 115 is formed. For example, the semiconductor layer 120 may be formed by forming a layer including a silicon-containing material, an oxide semiconductor, or the like on the entire surface of the buffer layer 115 and patterning the formed layer. When the semiconductor layer 120 is formed using a silicon-containing material, an amorphous silicon layer may be formed on the entire surface of the buffer layer 115 and crystallized to form a polycrystalline silicon layer. Hereinafter, after the semiconductor layer 120 is patterned, impurities may be doped on both sides of the patterned polycrystalline silicon layer to form the semiconductor layer 120 including a source region, a drain region, and a channel region between the source region and the drain region.

[0066] The gate insulating layer 125 may be formed on the display area DA and the non-display area NDA of the substrate 110 on which the semiconductor layer 120 is formed. For example, the gate insulating layer 125 may be formed using silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0067] A first metal layer may be formed on the gate insulating layer 125. The first metal layer may be patterned to form a gate electrode 130 and a first storage electrode 133 in the display area DA. The gate electrode 130 may overlap the semiconductor layer 120. The first metal layer may be formed using a metal, a metal alloy, or the like.

[0068] The interlayer insulating layer 135 may be formed in the display area DA and the non-display area NDA in which the gate electrode 130 and the first storage electrode 133 are formed. For example, the interlayer insulating layer 135 may be formed using silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0069] A plurality of contact holes exposing the semiconductor layer 120 may be formed in the interlayer insulating layer 135 and the gate insulating layer 125. For example, the contact holes may expose a source region and a drain region of the semiconductor layer 120, respectively.

[0070] The second metal layer may be formed on the substrate 110 on which the interlayer insulating layer 135 is formed, and the second metal layer may be patterned. The second metal layer may be used to form the source electrode 140, the drain electrode 150, and the second storage electrode 153 in the display area DA and the line 160 and the pad electrode 170 in the non-display area NDA.

[0071] The second metal layer may include an aluminum alloy. The aluminum alloy may include any one of copper (Cu), vanadium (V), and silicon (Si).

[0072] According to an exemplary embodiment, the second metal layer may have a multilayer structure including a first layer 171, a second layer 172, and a third layer 173 sequentially stacked. For example, the second metal layer may include a layer including titanium (Ti), a layer including an aluminum alloy, and a layer including titanium sequentially stacked on the interlayer insulating layer 135. Therefore, each of the source electrode 140, the drain electrode 150, the second storage electrode 153, the wire 160, and the pad electrode 170 may have a stack structure of Ti / aluminum alloy / Ti.

[0073] Reference Figure 5 , a planarization layer 181 covering the source electrode 140 and the drain electrode 150 may be formed with a first thickness t1 in the display area DA in which the interlayer insulating layer 135 is formed.

[0074] The planarization layer 181 may include a contact hole exposing the drain electrode 150 in the display area DA. The planarization layer 181 may be removed in the non-display area NDA to expose the line 160 and the pad electrode 170. The planarization layer 181 may be formed of, for example, polyimide resin, photoresist, acrylic resin, polyamide resin, siloxane resin, or the like.

[0075] The planarization layer 181 in the display area DA may have a thickness difference Δt of about 0.3 μm according to a thickness difference of a stacked structure below the planarization layer 181 .

[0076] The CMP process may be performed to remove the thickness difference Δt present in the planarization layer 181 in the display area DA.

[0077] Reference Figure 6 , for the CMP process, the sacrificial layer 183 may be formed on the substrate 110 on which the planarization layer 181 is formed. The sacrificial layer 183 may be formed with a second thickness t2 in the display area DA. The sacrificial layer 183 may be formed with a third thickness t3 in the non-display area NDA. The third thickness t3 may be defined from the top surface of the pad electrode 170 to the top surface of the sacrificial layer 183 in the non-display area NDA.

[0078] The sacrificial layer 183 may include a material having an etch selectivity ratio different from that of the planarization layer 181 .

[0079] According to one exemplary embodiment, the sacrificial layer 183 may be formed of an organic material such as a photoresist.

[0080] According to one exemplary embodiment, the sacrificial layer 183 may be formed of an inorganic material such as silicon oxide, silicon nitride, indium zinc oxide (IZO), or the like.

[0081] Reference Figure 7 , the substrate 110 having the sacrificial layer 183 formed thereon may be subjected to a CMP process using a CMP apparatus.

[0082] The CMP apparatus 500 may include a slurry 530 and a polishing pad 550 .

[0083] The slurry 530 may include a plurality of polishing particles 510 .

[0084] The slurry 530 may have a polishing rate ratio different from the polishing rate ratio of the planarization layer 181 and the polishing rate ratio of the sacrificial layer 183 .

[0085] According to an exemplary embodiment, a polishing rate ratio of the planarization layer 181 to the sacrificial layer 183 may be as high as 10:1.

[0086] According to one exemplary embodiment, the polishing rate ratio of the planarization layer 181 and the sacrificial layer 183 may be adjusted differently according to the material properties and coating conditions of the sacrificial layer 183. For example, when the third thickness t3 of the sacrificial layer 183 formed in the non-display area NDA is greater than the first thickness t1 of the planarization layer 181 formed in the display area DA, the polishing rate ratio of the sacrificial layer 183 may be adjusted to be greater than the polishing rate ratio of the planarization layer 181. However, when the third thickness t3 of the sacrificial layer 183 formed in the non-display area NDA is less than the first thickness t1 of the planarization layer 181 formed in the display area DA, the polishing rate ratio of the sacrificial layer 183 may be adjusted to be less than the polishing rate ratio of the planarization layer 181.

[0087] In the CMP process, considering that the upper surface of the pad electrode 170 formed in the non-display area NDA is exposed, the paste 530 may include a corrosion inhibitor of the material of the third layer 173 corresponding to the upper surface of the pad electrode 170. For example, the paste 530 may include a corrosion inhibitor of titanium (Ti).

[0088] The hard polishing pad 550 may press the slurry 530 to perform a CMP process of the substrate to be processed. The distance between the sacrificial layer 183 and the polishing pad 550 in the display area DA may be relatively small, and the distance between the sacrificial layer 183 and the polishing pad 550 may be relatively large in the non-display area NDA. The pressure of the plurality of polishing particles of the slurry 530 in the display area DA may be greater than the pressure of the plurality of polishing particles of the slurry 530 in the non-display area NDA. Therefore, the pad electrode 170 of the non-display area NDA may be prevented from being damaged by the polishing process, and the planarization process efficiency of the planarization layer 181 in the display area DA may be improved.

[0089] According to an exemplary embodiment, when the sacrificial layer 183 is formed of an organic material similar to that of the planarization layer 181 , the sacrificial layer 183 and the planarization layer 181 may be simultaneously subjected to a CMP process using a slurry 530 having a polishing rate ratio different from that of the sacrificial layer 183 and the planarization layer 181 .

[0090] Reference Figure 8 , the sacrificial layer 183 in the display area DA may be completely removed by the CMP process, and the planarization layer 181 may be partially removed. The thickness difference Δt of about 0.3 μm present in the planarization layer 181 in the display area DA may be removed. The planarization layer 181 in the display area DA may have a fourth thickness t4 thinner than the first thickness t1 before the CMP process, and may have a flat surface.

[0091] The sacrificial layer 183 in the non-display area NDA may be partially removed to expose the upper surface of the pad electrode 170. The side surface of the pad electrode 170 may be capped by a residual portion 183d of the sacrificial layer having a thickness d of the first layer and the second layer of the pad electrode 170. By capping the side surface of the pad electrode 170, the residual portion 183d of the sacrificial layer (hereinafter referred to as "sacrificial layer residual 183d") may protect the second layer 172 as the main electrode layer of the pad electrode 170 from damage such as corrosion.

[0092] According to an exemplary embodiment, if the sacrificial layer 183 is to be formed of an inorganic material different from that of the planarization layer 181, it may be difficult to control the polishing rate ratio of the sacrificial layer 183 and the planarization layer 181. The sacrificial layer 183 and the planarization layer 181 may undergo CMP processes using different slurries 530, respectively.

[0093] First, a first polishing process may be performed using a first slurry 530 for removing an inorganic material, thereby removing the sacrificial layer 183 formed of the inorganic material in the display area DA and in the non-display area NDA.

[0094] Next, a second polishing process is performed using the second slurry 530 for removing organic materials, thereby removing some thickness of the planarization layer 181 formed of the organic material in the display area DA. A thickness difference Δt of about 0.3 μm present in the planarization layer 181 in the display area DA may be removed.

[0095] Reference Figure 8 , the planarization layer 181 in the display area DA may have a fourth thickness t4 thinner than the first thickness t1 before the CMP process, and may have a flat surface.

[0096] When the sacrificial layer 183 in the non-display area DA is removed, the top surface of the pad electrode 170 may be exposed, and the side surface of the pad electrode 170 may still be covered by the sacrificial layer residue 183d formed with the thickness d of the first layer and the second layer of the pad electrode 170. The sacrificial layer residue 183d remaining on the side surface of the pad electrode 170 may cap the side surface of the pad electrode 170. The sacrificial layer residue 183d may protect the second layer 172, which is the main electrode layer of the pad electrode 170, from damage such as corrosion.

[0097] Therefore, the planarization layer 181 in the display area DA may have a flat surface through the CMP process. In addition, a side surface of the pad electrode 170 of the non-display area NDA may be capped by the sacrificial layer residue 183d.

[0098] Figure 2The side surfaces of the wires 160 of the non-display area NDA shown in FIG. 1 may also be capped by the sacrificial layer residue 183 d. Therefore, the second layer 172 as a main line layer of the wires 160 of the non-display area NDA may be protected from damage such as corrosion.

[0099] Reference Fig. 9 , the first electrode 195 may be formed on the planarization layer 181 planarized by the CMP process. The first electrode 195 may include a first layer 191, a second layer 192, and a third layer 193 that are sequentially stacked. For example, the first electrode 195 may have a stack structure of ITO / Ag / ITO by sequentially depositing a layer including indium tin oxide (ITO), a layer including silver (Ag), and a layer including indium tin oxide (ITO).

[0100] A pixel defining layer 197 having an opening exposing the first electrode 195 may be formed in the display area DA on the substrate 110 on which the first electrode 195 is formed.

[0101] For example, the pixel defining layer 197 may be formed of polyimide resin, photoresist, acrylic resin, polyamide resin, siloxane resin, or the like.

[0102] Reference Figure 3 , the organic light emitting layer 210 may be formed in the opening of the pixel defining layer 197. For example, the organic light emitting layer 210 may be formed of a low molecular weight organic compound or a high molecular weight organic compound using screen printing, inkjet printing, vapor deposition, or the like.

[0103] The second electrode 220 may be formed on the substrate 110 in which the pixel defining layer 197 and the organic light emitting layer 210 are formed. For example, the second electrode 220 may be formed of lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or the like.

[0104] Embodiments may be applicable to display devices and electronic devices having display devices. For example, embodiments may be applicable to computer monitors, laptop computers, digital cameras, cellular phones, smart phones, smart tablets, televisions, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, navigation systems, game consoles, video phones, etc.

[0105] By way of summary and review, a flat panel display device can be formed with a circuit layer including an optical element in a display area and a transistor and a capacitor for driving the optical element. The circuit layer is stacked with a plurality of metal layers and a plurality of insulating layers. Therefore, the optical element arranged on the pixel circuit is arranged. In order to improve the optical properties and optical efficiency of the optical element, a planarization layer is formed with a thick thickness to planarize the thickness difference caused by the pixel circuit before forming the element. However, due to the complexity of the stacked structure under the planarization layer, it may be difficult to remove the thickness difference.

[0106] The embodiment provides a display device for improving optical characteristics due to planarization of a display area and a method of manufacturing the display device.

[0107] The planarization layer of the display area can be planarized by a CMP process using a sacrificial layer to remove the thickness difference of the planarization layer. Therefore, the optical characteristics and light efficiency of the display area can be improved. The sacrificial layer residue remaining in the non-display area of ​​the display device can protect the pad electrode and the line from damage such as corrosion by capping the side surface of the pad electrode and the line.

[0108] Example embodiments have been disclosed herein, and although specific terms are employed, such specific terms are used and are to be interpreted only in a general and descriptive sense and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: a planarization layer covering the transistors in the display area on the substrate; an organic light emitting diode, on the planarization layer; A pad electrode in a non-display area surrounding the display area on the substrate; as well as a capping layer, covering the side surface of the pad electrode, The capping layer only partially overlaps the side surface of the pad electrode, and the capping layer and the planarization layer are residues of different layers formed by a same chemical mechanical polishing process.

2. The display device according to claim 1, wherein: The capping layer includes a material having an etch selectivity different from that of the planarization layer.

3. The display device according to claim 1, wherein: The pad electrode includes a first layer on the substrate, a second layer on the first layer, and a third layer on the second layer, and the capping layer caps a side surface of the first layer and a side surface of the second layer of the pad electrode, and The first layer and the third layer include titanium, and the second layer includes an aluminum alloy.

4. The display device according to claim 3, further comprising: a line in the non-display area, the line being connected to the pad electrode, wherein a side surface of the line is capped by the capping layer, and The wire includes the first layer, the second layer, and the third layer which are sequentially stacked, and the capping layer caps a side surface of the first layer and a side surface of the second layer of the wire.

5. A method for manufacturing a display device, the method comprising: forming a pad electrode in a non-display area surrounding the display area on the substrate; forming a planarization layer on the substrate to have a first thickness, the planarization layer covering the transistor formed in the display area; forming a sacrificial layer covering the planarization layer in the display area and the pad electrode in the non-display area; polishing the planarization layer and the sacrificial layer by a chemical mechanical polishing process so that the planarization layer has a second thickness less than the first thickness and so that a sacrificial layer residue exposing an upper surface of the pad electrode and capping a side surface of the pad electrode is formed; and An organic light emitting diode is formed on the planarization layer having the second thickness.

6. The method according to claim 5, wherein: The sacrificial layer includes a material having an etch selectivity different from an etch selectivity of the planarization layer in the chemical mechanical polishing process.

7. The method according to claim 5, wherein: In the chemical mechanical polishing process, the planarization layer and the sacrificial layer are polished using a slurry having a polishing rate ratio different from a polishing rate ratio of the planarization layer and the sacrificial layer.

8. The method according to claim 7, wherein: The paste includes a corrosion inhibitor that prevents corrosion of the pad electrode.

9. The method according to claim 8, wherein: The pad electrode includes a first layer formed on the substrate, a second layer formed on the first layer, and a third layer formed on the second layer, and The sacrificial layer residue covers the side surface of the first layer and the side surface of the second layer of the pad electrode, and Wherein the first layer and the third layer include titanium, and the second layer includes an aluminum alloy.

10. The method according to claim 9, further comprising: forming a line in the non-display area, the line being connected to the pad electrode, wherein the side surfaces of the wires are capped by the sacrificial layer residues, and The wire includes the first layer, the second layer, and the third layer which are sequentially stacked, and the sacrificial layer residue caps a side surface of the first layer and a side surface of the second layer of the wire.

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