Method for operating a controller for controlling a nonvolatile memory device and a memory device

Abstract

A method for operating a controller for controlling a non-volatile memory device and a storage device are disclosed. The method includes: enabling a command latch enable signal, an address latch enable signal, and a write enable signal; and sending a plurality of data signals including a command and an address to the non-volatile memory device in synchronization with the enabled write enable signal. The number of DQ lines through which the plurality of data signals are sent is greater than the number of bits of each of the plurality of data signals. The method also includes: after sending a command, disabling the command latch enable signal; and after sending an address, disabling the address latch enable signal and the write enable signal.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2018-0137034 filed on November 9, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a memory device such as a nonvolatile memory device. More particularly, the present disclosure relates to an operation method of a memory device having a wide input / output. Background Art

[0003] Semiconductor memories are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices that lose data stored therein when power is turned off, and examples include static random access memory (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain data stored therein even when power is turned off, and examples include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0004] In a communication system, an integrated circuit (IC) and an external memory device such as a random access memory (RAM) can be configured to transmit data bits (referred to as DQ data signals) in short bursts via data lines (referred to as DQ lines). The transmitting device also sends a DQS strobe signal with a corresponding clock edge burst along a separate bidirectional DQS line for the receiving device to correctly capture the data in the DQ data signal. The receiving device uses the clock edge of the DQS strobe signal to sample and latch the data bits in the DQ data signal.

[0005] Flash memory devices are widely used as high-capacity storage media. There are various specifications that define the operating requirements of flash memory devices. Generally, a DQ data signal includes a command, an address, and data, and is sent serially. For the purpose of this disclosure, in the operating requirements of the specifications for a storage device, a wide input / output of a storage device may be considered as a storage device having a number of DQ lines greater than the number of bits of each DQ data signal. When a storage device with a wide input / output is used under a specific specification without modification, various problems such as a reduction in performance may occur. Summary of the invention

[0006] Embodiments of the present disclosure provide a solution to a problem that occurs when a storage device has a wide input / output under specifications for the storage device.

[0007] In particular, an embodiment of the present disclosure provides a method of improving an operation speed of a storage device by controlling a control signal for a controller to recognize a command and data.

[0008] According to an exemplary embodiment, a method for operating a controller for controlling a nonvolatile memory device includes: enabling a command latch enable signal, an address latch enable signal, and a write enable signal. The method also includes: sending a plurality of data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. The number of DQ lines through which the plurality of data signals are sent is greater than the number of bits of each of the plurality of data signals. The method also includes disabling the command latch enable signal after sending the command. Disabling the address latch enable signal and the write enable signal after sending the address.

[0009] According to another exemplary embodiment, a method of operating a controller that controls a nonvolatile memory device includes: enabling a write enable signal. The method also includes: sending a first control signal indicating a command or an address directed to the nonvolatile memory device; sending a second control signal indicating the command to the nonvolatile memory device; and sending a plurality of data signals including the command and the address to the nonvolatile memory device in synchronization with the enabled write enable signal. The number of DQ lines through which the plurality of data signals are sent is greater than the number of bits of each of the plurality of data signals. The method also includes: after sending the command, disabling the second control signal; and after sending the command and the address, disabling the first control signal.

[0010] According to yet another exemplary embodiment, a storage device includes: a nonvolatile memory device and a controller. The controller enables a command latch enable signal, an address latch enable signal, and a write enable signal to be sent to the nonvolatile memory device, and sends a plurality of data signals including a command and an address to the nonvolatile memory device. The number of DQ lines through which the plurality of data signals are sent is greater than the number of bits of each of the plurality of data signals. The controller disables the command latch enable signal after sending the command, and disables the address latch enable signal and the write enable signal after sending the address. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1A storage device according to an exemplary embodiment of the present disclosure is shown.

[0013] Figure 2 Shown in detail Figure 1 An exemplary configuration of a storage device.

[0014] Figure 3 Show Figure 2 An exemplary configuration of one of a plurality of nonvolatile memory devices of a storage device.

[0015] Figure 4 is a timing diagram showing the timing of signals input to the nonvolatile memory device.

[0016] Figure 5 is another timing diagram showing the timing of signals input to a nonvolatile memory device.

[0017] Figure 6 An operating method of a controller controlling a nonvolatile memory device according to an exemplary embodiment of the present disclosure is illustrated.

[0018] Figure 7 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0019] Figure 8 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0020] Fig. 9 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0021] Fig. 10A and Fig. 10B is a timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0022] Fig.11 An operating method of a controller for controlling a nonvolatile memory device according to an embodiment of the present disclosure is illustrated.

[0023] Fig.12 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an embodiment of the present disclosure.

[0024] Fig.13 Shown in detail Figure 1 An exemplary configuration of a storage device.

[0025] Fig.14 An operating method of a controller controlling a nonvolatile memory device according to an exemplary embodiment of the present disclosure is illustrated.

[0026] Fig.15 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0027] Fig.16 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0028] Fig.17 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure.

[0029] Fig.18 A solid-state drive (SSD) system to which the secure erasing and secure writing of the present disclosure is applied is shown. DETAILED DESCRIPTION

[0030] Below, the embodiments of the present disclosure may be described in detail and clearly so that a person having ordinary skill in the art can easily realize the inventive concepts described herein.

[0031] Figure 1 A memory device according to an exemplary embodiment of the present disclosure is shown. The memory device 100 may include a controller 110 and a nonvolatile memory device (NVM) 120. The nonvolatile memory device 120 may be connected to the controller 110 through a plurality of channels, and two or more nonvolatile memory devices may be connected to each channel.

[0032] The controller 110 may control a read operation and a write operation of the nonvolatile memory device 120. For example, the controller 110 may provide a command CMD, an address ADDR, and data DATA to the nonvolatile memory device 120 by using a plurality of data signals DQ. The controller 110 may transmit the command CMD and the address ADDR to the nonvolatile memory device 120 by using the data signal DQ, and may receive the data DATA from the nonvolatile memory device 120. The controller 110 may also transmit a control signal CTRL and a data strobe signal DQS to the nonvolatile memory device 120.

[0033] In one embodiment, the control signal CTRL, the data strobe signal DQS, and the data signal DQ may be transmitted to the nonvolatile memory device 120 through different signal lines from each other. The control signal CTRL and the data strobe signal DQS may be used to identify the data signal DQ transmitted from the controller 110 to the nonvolatile memory device 120 or exchanged between the controller 110 and the nonvolatile memory device 120.

[0034] In response to the received signal, nonvolatile memory device 120 may receive data DATA from controller 110 or may transmit data DATA to controller 110. For example, nonvolatile memory device 120 may determine that data signal DQ corresponds to command CMD, address ADDR, or data DATA of data signal DQ based on control signal CTRL.

[0035] In one embodiment, the nonvolatile memory device 120 may include a NAND flash memory. However, the present disclosure is not limited thereto. For example, the nonvolatile memory device 120 may include, for example, at least one of a volatile memory and a nonvolatile memory, such as a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM).

[0036] In one embodiment, the data signal DQ may be sent from the controller 110 to the non-volatile memory device 120 via a DQ line of a wide I / O. Typically, the number of bits constituting each data signal DQ and the number of DQ lines through which the data signal DQ is sent may be the same. For example, each data signal consisting of 8 bits is sent to the non-volatile memory device 120 via 8 DQ lines. That is, the data signal DQ is sent serially. However, according to an embodiment of the present disclosure, the number of DQ lines may be greater than the number of bits of each data signal, and this may be referred to as a wide input / output herein. For example, the number of DQ lines may be 16, 32, or 64, but the present disclosure is not limited thereto.

[0037] According to the present disclosure, since the data signal DQ is transmitted to the nonvolatile memory device 120 through the DQ line of the wide I / O, the time for the data signal DQ to be completely transmitted can be shortened. In addition, according to the present disclosure, the time point of the subsequent operation (for example, the transmission of the data DATA) can be advanced by controlling the control signal CTRL required to identify the data signal DQ, and thus, the performance of the memory device 100 can be improved. This will be described in detail later.

[0038] Figure 2 Shown in detail Figure 11. An exemplary configuration of a memory device 100. The memory device 100 may include a controller 110 and a nonvolatile memory device 120. In one embodiment, for simplicity of explanation, only one channel (hereinafter, referred to as a "first channel") CH1 of a plurality of channels is shown, and only two nonvolatile memory devices (hereinafter, referred to as a "first nonvolatile memory device NVM1" and a "second nonvolatile memory device NVM2") are shown as being connected to the first channel CH1.

[0039] The controller 110 and other controllers described herein may be a circuit having a memory storing instructions and a processor (e.g., a microprocessor) executing the instructions. The controller 110 may communicate with the nonvolatile memory devices NVM1 and NVM2 via the first channel CH1. For example, the controller 110 may exchange a plurality of data signals DQ1 to DQ4 with the first nonvolatile memory device NVM1 via the first channel CH1 by using the control signal CTRL. The controller 110 may also exchange data signals DQ1 to DQ4 with the second nonvolatile memory device NVM2 via the first channel CH1 by using the control signal CTRL. That is, the nonvolatile memory devices NVM1 and NVM2 may share a portion of the control signal CTRL and the data signals DQ1 to DQ4. The data signals DQ1 to DQ4 include a command CMD, an address ADDR, and data DATA.

[0040] In an embodiment, the control signal CTRL may include, for example, one or more of the enable signals / CE1 and / CE2, the ready and busy signals R / B1 and R / B2, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, and the read enable signal / RE. The command latch enable signal CLE and other command latch enable signals described herein are used to latch signals sent through the DQ lines as described herein. The address latch enable signal ALE and other address latch enable signals described herein are also used to latch signals sent through the DQ lines as described herein. The command latch enable signal CLE and the address latch enable signal ALE are used to latch different signals (i.e., for command "C" or for addresses (such as, A1 to A5)).

[0041] The "enable" signal used as a term herein may be used to indicate that a corresponding function is enabled when the "enable" signal is in a specific state (such as high). Enable may therefore be used to indicate placing the "enable" signal in a specific state (such as high) such that, as a result, the corresponding function for the "enable" signal is enabled.

[0042] In the time interval when the command latch enable signal CLE is at a logic high, the command CMD may be input synchronously with the write enable signal / WE. That is, the command CMD may be latched at the rising edge of the write enable signal / WE. In the time interval when the address latch enable signal ALE is at a logic high, the address ADDR may be input synchronously with the write enable signal / WE. That is, the address ADDR may be latched at the rising edge of the write enable signal / WE.

[0043] Figure 3 Show Figure 2 One of the nonvolatile memory devices NVM1 and NVM2 of the storage device. In one embodiment, the configuration of the first nonvolatile memory device NVM1 is shown. The first nonvolatile memory device NVM1 may include a memory cell array 121, an address decoder 122, a page buffer 123, an input / output circuit 124, and a control logic circuit 125. The control logic circuit 125 may store the control logic in a memory and execute the control logic using a processor such as a microprocessor, or may implement the control logic using a circuit element such as an application specific integrated circuit (ASIC). References to "logic" herein refer to implementations with specific circuits and circuitry.

[0044] Before continuing, it should be clear that this includes Figure 3 The accompanying drawings of the present invention show and refer to circuit systems with labels such as "circuit", "controller" and "decoder". Such circuit systems may include processors, including microprocessors or application-specific integrated circuits (ASICs) and other elements with other labels. As is conventional in the field of the inventive concept described herein, examples may be described and illustrated in terms of blocks such as circuits and other elements that perform the functions described. These blocks (which may be referred to herein as circuits, controllers, decoders, etc.) are physically implemented by analog circuits and / or digital circuits (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc.) and may be selectively driven by firmware and / or software. For example, the circuit may be implemented in one or more semiconductor chips, or on a substrate support (such as a printed circuit board, etc.). The circuits constituting the blocks may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuit systems), or by a combination of dedicated hardware for performing some functions of the blocks and a processor for performing other functions of the blocks. Without departing from the scope of the present disclosure, each block of the example may be physically divided into two or more interactive and discrete blocks. Likewise, the illustrated blocks may be physically combined into more complex blocks without departing from the scope of the present disclosure.

[0045] The memory cell array 121 may include memory blocks BLK1 to BLKm. Each of the memory blocks BLK1 to BLKm may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each memory cell may include a single-level cell (SLC) storing one bit or a multi-level cell (MLC) storing at least two bits.

[0046] The address decoder 122 is connected to the memory cell array 121 through the word line WL, the string selection line SSL and the ground selection line GSL. The address decoder 122 can receive the address ADDR from the outside, and can decode the received address ADDR to drive the word line WL. For example, the address ADDR can be a physical address obtained by converting the logical address. The address conversion operation can be performed by the controller 110 (refer to Figure 1 ) driven by the Flash Translation Layer (FTL).

[0047] The page buffer 123 is connected to the memory cell array 121 through a plurality of bit lines BL. Under the control of the control logic circuit 125, the page buffer 123 may control the bit lines BL so that the data DATA received from the input / output circuit 124 is stored in the memory cell array 121. Under the control of the control logic circuit 125, the page buffer 123 may read the data stored in the memory cell array 121 and may transmit the read data to the input / output circuit 124. In one embodiment, the page buffer 123 may receive data from the input / output circuit 124 in units of pages or may read data from the memory cell array 121 in units of pages.

[0048] The input / output circuit 124 may receive data DATA from an external device and may provide the received data DATA to the page buffer 123 .

[0049] The control logic circuit 125 may receive a command CMD and a control signal CTRL from the outside, and control the address decoder 122, the page buffer 123, and the input / output circuit 124 in response to the received signals CMD and CTRL. For example, the control logic circuit 125 may control any other component in response to the signals CMD and CTRL so that the data DATA is stored in the memory cell array 121. The control logic circuit 125 may control any other component in response to the signals CMD and CTRL so that the data DATA stored in the memory cell array 121 is transmitted to an external device. The control signal CTRL may be a signal provided by the controller 110 to control the nonvolatile memory device NVM1.

[0050] The control logic circuit 125 may generate various voltages required for the operation of the nonvolatile memory device NVM1. For example, the control logic circuit 125 may generate a plurality of program voltages, a plurality of pass voltages, a plurality of selection read voltages, a plurality of non-selection read voltages, a plurality of erase voltages, and / or a plurality of verification voltages. The control logic circuit 125 may provide the generated voltages to the address decoder 122 or the substrate of the memory cell array 121.

[0051] Figure 4 is a timing diagram showing the timing of signals input to the nonvolatile memory device. Figure 4 The timing diagram is associated with the case where the number of bits constituting each data signal DQ and the number of DQ lines are the same. In one embodiment, it is assumed that each data signal DQ is an 8-bit data signal, and a plurality of data signals are serially transmitted to the nonvolatile memory device through 8 DQ lines. Figure 4 In the example, "C" indicates a command, and A1 to A5 indicate addresses. In one embodiment, A1 and A2 may indicate a memory cell array ( Figure 3 121), and A3 to A5 may indicate the row address of the memory cell array.

[0052] The nonvolatile memory device to which the data signal DQ is to be input is selected by the chip enable signal / CE. Thereafter, the command latch enable signal CLE may be turned to logic high, and the command "C" may be latched at the rising edge of the write enable signal / WE when the command latch enable signal CLE is at logic high. After the command "C" is latched, the command latch enable signal CLE may be turned to logic low. Generally, the command latch enable signal CLE and other command latch enable signals described herein are used to latch commands sent through the DQ line.

[0053] After command "C" is latched, address latch enable signal ALE turns to logic high. During the time interval when address latch enable signal ALE is at logic high, addresses A1 to A5 may be latched at the rising edge of write enable signal / WE. After addresses A1 to A5 are latched, address latch enable signal ALE may turn to logic low. Generally, address latch enable signal ALE and other address latch enable signals described herein are used to latch addresses sent through DQ lines.

[0054] according to Figure 4 In the timing diagram shown in , since the command "C" and addresses A1 to A5 are latched through 6 cycles, the rising edges of at least six pulses of the write enable signal / WE are required. However, this count may be the minimum count required to identify the data signal DQ, and more rising edges of the write enable signal / WE may be required depending on the type of command.

[0055] Figure 5is another timing diagram showing the timing of signals input to a nonvolatile memory device. Figure 5 The timing diagram of is associated with a case where the number of DQ lines is greater than the number of bits constituting each data signal DQ (ie, a case of wide I / O). Figure 5 FIG. 4 shows an embodiment when the number of DQ lines is 32. Figure 5 Describe in Figure 4 A problem occurs when the timing rules are applied to a memory device including DQ lines of wide I / Os.

[0056] In the case where command "C" is a write command, command "C" and addresses A1 to A5 are sequentially input to the nonvolatile memory device through the DQ lines of the wide I / O. In detail, command "C" and addresses A1 to A3 are input to the nonvolatile memory device at the first rising edge (i.e., the first cycle) of the write enable signal / WE. The 8 bits (e.g., DQ[7:0]) constituting command "C" are input to the nonvolatile memory device through 8 DQ lines. The bits (e.g., DQ[15:8]) constituting address A1 are input to the nonvolatile memory device through 8 DQ lines. The remaining addresses A2 and A3 are input similarly to the above description.

[0057] Thereafter, addresses A4 and A5 are input to the nonvolatile memory device at the second rising edge of the write enable signal / WE (i.e., the second cycle). The 8 bits constituting address A4 are DQ[7:0] and are input to the nonvolatile memory device through 8 DQ lines. Address A5 is input similarly to the description above for address A1, but now address A5 is input at the second rising edge of the write enable signal / WE in the second cycle.

[0058] However, if the reference Figure 4 The existing specification of the timing rules described Figure 5 For a write operation in a configuration of 100 (i.e., with 32 DQ lines), the rising edges of the six pulses of the write enable signal / WE for identifying the command "C" and addresses A1 to A5 will be maintained without modification. In order to comply with relevant specifications (e.g., ToggleDDR, ONFI, etc.), when the rising edges of the write enable signal / WE in six cycles of the command "C" and addresses A1 to A5 are processed, dummy data (e.g., dummy addresses) may be sent to the nonvolatile memory device during the remaining cycles of the write enable signal / WE. Figure 5 As shown in , the use of unnecessary pulses of the write enable signal / WE input to the non-volatile memory device may result in performance degradation when less than six cycles are required.

[0059] For example, refer to Figure 5, only two rising edges of the write enable signal / WE in two cycles are required to identify the command "C" and the addresses A1 to A5, and the remaining four rising edges are unnecessary. In this way, in the case where the controller sends the write enable signal / WE including the pulse associated with the unnecessary rising edge to the nonvolatile memory device without modification, the timing of the subsequent operation (for example, the input / output of the data DATA) is unnecessarily delayed. When performing any other operation (such as a read operation and a write operation), the above-mentioned performance degradation also occurs.

[0060] In order to solve the performance degradation that occurs when the data signal DQ is transmitted through the wide I / O, the controller as described in the present disclosure controls the command latch enable signal CLE, the address latch enable signal ALE and the write enable signal / WE. This will be described in detail later.

[0061] Figure 6 The operation method of the controller for controlling the nonvolatile memory device according to the exemplary embodiment of the present disclosure is shown. In order to show how to solve the existing problem or provide an improvement to the existing configuration, the following will be described with reference to FIG. Figure 5 A comparison of embodiments is given in the description.

[0062] In operation S110, the controller may enable the command latch enable signal CLE and the address latch enable signal ALE (e.g., to logic high). Typically, in the case where the controller sends the data signal DQ serially, the nonvolatile memory device latches the command (e.g., using the command latch enable signal CLE) and then latches the address (e.g., using the address latch enable signal ALE). For this reason, when the command is latched via the command latch enable signal CLE, the address latch enable signal ALE is not enabled. However, according to an embodiment of the present disclosure, the controller sends the command and all or part of the address to the nonvolatile memory device simultaneously or together through different DQ lines from each other. Therefore, the controller simultaneously enables the command latch enable signal CLE and the address latch enable signal ALE.

[0063] In one embodiment, the time interval at which the command latch enable signal CLE is enabled may include the time interval at which the command "C" is input. However, in order to ensure a margin, the time interval at which the command latch enable signal CLE is enabled may be wider than the time interval at which the command "C" is input, but may be limited to a range for preventing the address from being latched in the next cycle. The time point at which the command latch enable signal CLE is enabled and the time point at which the address latch enable signal ALE is enabled do not need to be exactly the same, and it is sufficient that the nonvolatile memory device can latch the command and / or address at the first rising edge of the write enable signal / WE.

[0064] In addition, in operation S110, the controller may enable the write enable signal / WE. The write enable signal / WE being enabled may indicate that the write enable signal / WE includes a rising edge for latching a command and / or an address (i.e., a pulse including an edge rising from a low level before the pulse stabilizes or starts to fall back from a high level to a low level).

[0065] In operation S120, the controller transmits the data signal DQ to the nonvolatile memory device through the DQ line of the wide I / O. For example, the data signal DQ may be transmitted to the nonvolatile memory device aligned with the rising edge of the pulse of the write enable signal / WE. For example, the center of each data signal may be aligned with the rising edge of the write enable signal / WE.

[0066] In operation S130, the controller may disable the command latch enable signal CLE (eg, to logic low) after sending the command. The time interval during which the command latch enable signal CLE is enabled may include the time interval during which the command is sent, but may be limited to a range for preventing the address from being latched in the next cycle.

[0067] In operation S140, the controller may disable the address latch enable signal ALE (eg, to logic low) after sending all addresses. For example, the time interval during which the address latch enable signal ALE is enabled may include: Figure 5 The time interval between sending addresses in two cycles.

[0068] In addition, in operation S140, the controller may disable the write enable signal / WE (e.g., to logic high) after sending all addresses. In this way, the pulses of the write enable signal / WE are not sent as many as the count defined in the existing relevant specifications, and the pulses of the write enable signal / WE are sent so that the minimum number of rising edges required to latch the command and address is ensured. In other words, even if the specification may define additional pulses of the write enable signal / WE, the controller may disable the write enable signal / WE at all addresses due to, for example, Figure 6 The wide input / output in the embodiment is given the opportunity to disable the write enable signal / WE after being sent.

[0069] However, in Figure 6 In the embodiment of the present invention, the controller simultaneously sends the command "C" and the addresses A1 to A3 to the nonvolatile memory device through the DQ lines different from each other in the first cycle. In addition, since both the command latch enable signal CLE and the address latch enable signal ALE are enabled in the first cycle of the write enable signal / WE, the nonvolatile memory device will recognize the command "C" and the addresses A1 to A3 to distinguish the command "C" from the addresses A1 to A3. Next, how to recognize the command and the address will be described in detail.

[0070] Figure 7is another timing diagram showing the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Assume that command “C” is a write command (eg, 80h). For better understanding, reference will be made to Figure 2 Give a description.

[0071] The controller 110 may simultaneously send a plurality of data signals DQ[7:0], DQ[15:8], DQ[23:16], and DQ[31:24] to a nonvolatile memory device (e.g., NVM1) in a first cycle. The controller 110 may simultaneously send control signals so that the data signals DQ[7:0], DQ[15:8], DQ[23:16], and DQ[31:24] are recognized by the nonvolatile memory device. For example, Figure 2 The data signals DQ1 to DQ4 may correspond to each of DQ[7:0], DQ[15:8], DQ[23:16], and DQ[31:24].

[0072] In one embodiment, a pair of commands (also referred to as a "command set") can be used to identify commands and addresses latched by a non-volatile memory device in the same cycle. A command end signal CE indicating the end of sending command "C" can be sent to the non-volatile memory device together with the sending of command "C". In other words, the command end signal CE indicates the end of sending command "C". For example, command "C" can be sent to the non-volatile memory device as DQ[7:0] via the relevant DQ lines. The command end signal CE can be sent to the non-volatile memory device as DQ[15:8] via the relevant DQ lines. Figure 6 Compared with the embodiment of the present invention, the command end signal CE is Figure 7 In the embodiment of is added and provided for distinguishing the command "C" from the address without unnecessarily increasing the number of cycles required for the overall transmission. Figure 7 In the example, even if the command end signal CE is added, the command "C" and the address are still sent within two cycles.

[0073] The command end signal CE may include various codes recognized by the nonvolatile memory device and notify the end of the transmission of the command "C". When the command end signal CE is input to the nonvolatile memory device, other data signals (e.g., DQ[23:16] and DQ[31:24]) input to the nonvolatile memory device in the first cycle and data signals input to the nonvolatile memory device in the next cycle may be recognized as addresses. Here, the first cycle refers to the first time interval in which the command and / or address are latched at the first rising edge of the write enable signal / WE.

[0074] In one embodiment, the input / output circuits (e.g., Figure 3124) can sequentially buffer DQ[7:0], DQ[15:8], DQ[23:16], and DQ[31:24] through the relevant DQ lines. In this way, the controller can analyze the command end signal CE received as DQ[15:8] and can recognize that the data received as DQ[7:0] corresponds to the command.

[0075] Continue to refer to Figure 7 , a command "C", a command end signal "CE", and addresses A1 and A2 may be sent to the nonvolatile memory device in the first cycle, and addresses A3 to A5 may be sent to the nonvolatile memory device in the second cycle. Here, the second cycle refers to a second time interval in which a command or address is latched at the second rising edge of the write enable signal / WE.

[0076] As described above, when the address is completely sent, dummy data (e.g., dummy address) may be sent to the non-volatile memory device as DQ[31:24] in the second cycle. For example, the dummy address may indicate a physical address that does not actually exist in / at the storage area. When the address is completely sent, the address latch enable signal ALE may be disabled to a logic low, and the write enable signal / WE may maintain a stable level at a logic high without cycling to a logic low under other circumstances. Through the above operations, the timing of subsequent operations may be advanced. In one embodiment, as Figure 7 As shown in , when the loading time tADL from address to data in a write operation is advanced, the speed of the write operation can be improved.

[0077] Figure 8 1 is another timing diagram showing the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. In one embodiment, it is assumed that the first command C1 and the second command C2 correspond to a set of read commands (e.g., 00h and 30h). For better understanding, reference will be made to Figure 2 Give a description.

[0078] In an embodiment in which a first command C1, a command end signal CE, and addresses A1 and A2 are sent to a nonvolatile memory device in a first cycle and addresses A3 to A5 are sent to the nonvolatile memory device in a second cycle, Figure 7 Therefore, further description will be omitted to avoid redundancy. Figure 8 In the embodiment of the present invention, the second command C2 associated with the read operation is sent together with the first command C1.

[0079] In the cycle after the second cycle, the controller 110 may send the second command C2 as DQ[7:0] to the nonvolatile memory device (e.g., NVM1). However, in the second cycle, the command latch enable signal CLE may be disabled so that the address of the second cycle is not latched by the command latch enable signal CLE. However, in order to latch the second command C2 in the third cycle, the controller 110 may enable the command latch enable signal CLE again. For example, the time interval in which the command latch enable signal CLE is enabled again may include the time interval in which the second command C2 is sent.

[0080] Simultaneously with the third cycle, the controller 110 may send dummy commands (eg, DQ[15:8], DQ[23:16], and DQ[31:24]) to the nonvolatile memory device through the remaining DQ lines in addition to the DQ lines through which the second command C2 is sent.

[0081] After the second command C2 is completely transmitted in the cycle after the second cycle, the controller 110 may disable the command latch enable signal CLE and may disable the write enable signal / WE to be logic high. Figure 8 In the third cycle, the latch is at the rising edge of the write enable signal / WE, so the write enable signal / WE can be disabled by simply keeping the write enable signal / WE at a high level. Figure 8 As shown in , the time interval between the third rising edge and the sixth rising edge of the write enable signal / WE can be additionally ensured. Therefore, the timing of the time required to output the read data D0 to D8 in the read operation (for example, tR (data transfer from the flash memory array to the register), tRR (preparation to / RE low), tPRE (read preamble), and tRC (read cycle time)) can be advanced. As a result, the read speed of the nonvolatile memory device is improved. The timing of the advanced time can be considered to mean moving the time earlier, performing the operation faster or earlier than otherwise, and / or skipping one or more first operations that would otherwise be performed in order to perform the second operation with an advanced timing.

[0082] also, Figure 8 The embodiment corresponds to an embodiment in which a plurality of data signals including an address and two commands are transmitted in two cycles by using 32 DQ lines. However, in the case of using more DQ lines, the address and the plurality of commands can be completely transmitted in two cycles. For example, in the case where the storage device includes 64 DQ lines, all of the first command C1, the command end signal CE, and the addresses A1 to A5 can be transmitted to the nonvolatile memory device in the first cycle, and the second command C2 can be transmitted in the second cycle, and therefore, both the command and the address can be transmitted in two cycles.

[0083] Fig. 91 is another timing diagram showing the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Figure 2 Give a description.

[0084] In one embodiment, in order to identify a command and an address to be transmitted to a nonvolatile memory device (e.g., NVM1), a portion of the first channel CH1 may be allocated as a channel through which a command is transmitted, and the remaining portion of the first channel CH1 may be allocated as a channel through which an address is transmitted. In one embodiment, a DQ line through which a command is transmitted may be allocated as a first command channel CH1c, and a DQ line through which an address is transmitted may be allocated as a first address channel CH1a. Fig. 9 DQC[7:0] and DQC[15:8] shown in indicate data signals associated with commands, and DQA[23:16] and DQA[31:24] indicate data signals associated with addresses.

[0085] In one embodiment, the controller 110 may send the command "C" as DQC[7:0] to the nonvolatile memory device (e.g., NVM1) through the first command channel CH1c in the first cycle. At the same time, the controller 110 may also send the dummy command as DQC[15:8] to the nonvolatile memory device through the first command channel CH1c in the first cycle. The controller 110 may also send the addresses A1 and A2 as DQA[23:16] and DQA[31:24] to the nonvolatile memory device through the first address channel CH1a in the first cycle.

[0086] In one embodiment, the controller 110 may send the addresses A3 to A5 to the nonvolatile memory device through the first address channel CH1 a in a cycle after the first cycle.

[0087] In addition, Fig. 9 In the embodiment shown in , 16 DQ lines corresponding to DQC[7:0] and DQC[15:8] are allocated to the command channel, and 16 DQ lines corresponding to DQA[23:16] and DQA[31:24] are allocated to the address channel. However, the present disclosure is not limited thereto.

[0088] and Figure 7 Compared with the embodiment of the present invention, the case where the command channel and the address channel are separated as described above may require an additional rising edge of the write enable signal / WE. Fig. 9 In the embodiment of the present invention, the timing of subsequent operations can be advanced. Therefore, the performance of the storage device 100 can be improved.

[0089] Fig. 10A and Fig. 10B1 is a timing diagram showing the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Figure 2 Give a description.

[0090] Reference Fig. 10A , the controller 110 may generate a control signal for identifying data signals that are different from each other. In one embodiment, the controller 110 may generate a first command latch enable signal CLE1 and a first address latch enable signal ALE1 for identifying DQ[7:0] and command "C". That is, the first command latch enable signal CLE1 and the first address latch enable signal ALE1 are only used to identify DQ[7:0] and are not used to identify any other data signal. Therefore, it does not matter whether addresses A1 to A3 are latched simultaneously by the non-volatile memory device (e.g., NVM1) in the first cycle. As described above, the controller 110 generates a second command latch enable signal CLE2 and a second address latch enable signal ALE2 for identifying DQ[15:8]. The controller 110 generates a third command latch enable signal CLE3 and a third address latch enable signal ALE3 for identifying DQ[23:16]. The controller 110 generates a fourth command latch enable signal CLE4 and a fourth address latch enable signal ALE4 for identifying DQ[31:24]. Fig. 10A In the embodiment of , since only the first command latch enable signal CLE1 is used to identify command “C” or any command in this embodiment, the second command latch enable signal CLE2, the third command latch enable signal CLE3 and the fourth command latch enable signal CLE4 are always all set to low values. Similarly, in Fig. 10A In an embodiment, various address latch enable signals ALE1 to ALE4 are only set to high values ​​when the corresponding addresses A1 to A5 are latched in the first cycle or the second cycle. In an embodiment, in addition to a pair of existing control signals (e.g., CLE1 and ALE1), the controller 110 may further include three pairs of pins for sending three pairs of additional control signals (CLE2 and ALE2, CLE3 and ALE3, CLE4 and ALE4) to the nonvolatile memory device. Fig. 10A As shown in the figure, performance gain still occurs after the second cycle.

[0091] Fig. 10B Most of the embodiments are similar to Fig. 10A However, the values ​​of DQ[23:16] and DQ[31:24] in the second cycle are irrelevant. Fig. 10A The embodiments are different. Fig. 10BIn the case of the embodiment of FIG. 1 , a dummy command may be sent as DQ[23:16] and DQ[31:24] in the second cycle. However, in this case, in order to latch the dummy command, the command latch enable signal may be enabled. That is, Fig. 10B As shown in , the third command latch enable signal CLE3 and the fourth command latch enable signal CLE4 may be enabled in the second cycle to latch the dummy command. Fig. 10B As shown in the figure, performance gain still occurs after the second cycle.

[0092] Fig.11 An operating method of a controller for controlling a nonvolatile memory device according to an embodiment of the present disclosure is illustrated. Fig.12 1 is another timing diagram showing the timing of signals input to a nonvolatile memory device according to an embodiment of the present disclosure. In this embodiment, a method of identifying a command and an address by sending the command and the address in different cycles via a DQ line of a wide I / O will be described. For better understanding, reference will be made to Figure 2 , Fig.11 and Fig.12 Give a description.

[0093] In operation S210, the controller 110 may enable the command latch enable signal CLE and the write enable signal / WE. When the write enable signal / WE is enabled, the write enable signal / WE may include a pulse including a rising edge for latching the command "C" and the addresses A1 to A5. The controller 110 may send the command latch enable signal CLE and the write enable signal / WE to the nonvolatile memory device (e.g., NVM1).

[0094] In one embodiment, the time interval at which the command latch enable signal CLE is enabled may include the time interval at which the command "C" is input. However, in order to ensure a margin, the time interval at which the command latch enable signal CLE is enabled may be wider than the time interval at which the command "C" is input, but may be limited to a range for preventing the address from being latched by the command latch enable signal CLE in the next cycle.

[0095] In operation S220, the controller 110 may send a command "C" and a dummy command to the nonvolatile memory device in the first cycle. The command "C" may be sent to the nonvolatile memory device as DQ[7:0], and the dummy command may be sent to the nonvolatile memory device as DQ[15:8], DQ[23:16], and DQ[31:24]. The nonvolatile memory device may recognize the command by latching the command "C" at the first rising edge of the received write enable signal / WE.

[0096] In operation S230, after the command "C" is completely transmitted, the controller 110 may disable the command latch enable signal CLE. Before the address is transmitted to the nonvolatile memory device, the controller 110 may enable the address latch enable signal ALE.

[0097] In operation S240, the controller 110 may transmit addresses A1 to A5 to the nonvolatile memory device. The nonvolatile memory device may recognize the addresses by latching the addresses A1 to A5 in a cycle after the first cycle of the received write enable signal / WE.

[0098] In operation S250, after addresses A1 to A5 are completely transmitted, the controller 110 may disable the address latch enable signal ALE and the write enable signal / WE. For example, the address latch enable signal ALE may turn to logic low and the write enable signal / WE may remain at logic high.

[0099] In this embodiment, since the command and the address are sent to the nonvolatile memory device in different cycles, a separate scheme for identifying the command and the address may not be required, unlike the above-described embodiment. Figure 7 Compared with the embodiment of the present invention, the rising edge of the write enable signal / WE is required again, and the timing of subsequent operations can also be advanced. Therefore, the performance of the storage device 100 can be improved.

[0100] Fig.13 Shown in detail Figure 1 Another exemplary configuration of a memory device. The memory device 200 may include a controller 210 and a nonvolatile memory device 220. The memory device 200 includes a DQ line of a wide I / O and is mostly similar to Figure 2 Hereinafter, the difference between the storage device 100 and the storage device 200 will be mainly described.

[0101] The controller 210 may communicate with the nonvolatile memory devices NVM1 and NVM2 through the first channel CH1. The controller 210 may exchange data signals DQ1 to DQ4 with the nonvolatile memory devices NVM1 and NVM2 through the first channel CH1 by using a control signal CTRL. The data signals DQ1 to DQ4 may correspond to DQ[7:0], DQ[15:8], DQ[23:16], and DQ[31:24], respectively. Each data signal may include a command CMD, an address ADDR, and / or data DATA.

[0102] In one embodiment, the control signal CTRL includes, for example, chip enable signals / CE1 and / CE2, ready and busy signals R / B1 and R / B2, command and address latch enable signal CALE, command address indication signal CA (CA1 to CA4), write enable signal / WE, and read enable signal / RE.

[0103] In one embodiment, the command and address latch enable signal CALE and the command address indication signals CA1 to CA4 may be used to identify commands and addresses. The command and address latch enable signal CALE may be enabled within a time interval (or cycle) for sending a command or address. The command address indication signal CA may indicate a command or address according to a logic state. For example, a command address indication signal CA at a logic high may indicate a command pointing to a non-volatile memory device, and a command address indication signal CA at a logic low may indicate an address pointing to a non-volatile memory device. However, the present disclosure is not limited thereto. For example, a command address indication signal CA at a logic low may indicate a command pointing to a non-volatile memory device, and a command address indication signal CA at a logic high may indicate an address pointing to a non-volatile memory device.

[0104] Fig.14 An operating method of a controller controlling a nonvolatile memory device according to an exemplary embodiment of the present disclosure is illustrated. Fig.15 1 is another timing diagram showing the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Fig.13 , Fig.14 and Fig.15 Give a description.

[0105] In operation S310, the controller 210 may enable the write enable signal / WE. The write enable signal / WE being enabled may mean that the write enable signal / WE includes a pulse including a rising edge for latching a command or address (ie, a pulse including an edge rising from a low level to a high level).

[0106] In operation S320, the controller 210 may send a first control signal to the nonvolatile memory device NVM1. The first control signal may indicate that a command and an address are sent. In one embodiment, a command or an address may be sent to the nonvolatile memory device during a first time interval in which the first control signal is a logic high state. Conversely, a command and an address may not be sent during a second time interval in which the first control signal is a logic low state. In one embodiment, the first control signal may be a command and address latch enable signal CALE.

[0107] In operation S330, the controller 210 may send a second control signal to the nonvolatile memory device. A command is sent based on the logic states of the first control signal and the second control signal. In one embodiment, a command is sent in a first time interval when the first control signal is at a logic high and the second control signal is at a logic high. Conversely, an address is sent in a second time interval when the first control signal is at a logic high and the second control signal is at a logic low. In one embodiment, the second control signal may be any one of the command address indication signals CA1 to CA4.

[0108] In operation S340, the controller 210 may send a command "C" and addresses A1 to A5 to the nonvolatile memory device. The command "C" and addresses A1 to A3 are sent to the nonvolatile memory device in the first cycle, and addresses A4 and A5 are sent to the nonvolatile memory device in the second cycle.

[0109] The command "C" and addresses A1 to A3 sent in the first cycle may be latched by the nonvolatile memory device at the first rising edge of the write enable signal / WE. Addresses A4 and A5 sent in the second cycle may be latched by the nonvolatile memory device at the second rising edge of the write enable signal / WE. The controller 210 may send dummy data as DQ[23:16] and DQ[31:24] to the nonvolatile memory device in the second cycle.

[0110] In operation S350, after transmitting the command, the controller 210 may disable the second control signal. Since the activation of the second control signal corresponds to the command and the deactivation of the second control signal corresponds to the address, information on the address to be transmitted may be sufficiently transmitted even if the second control signal is disabled.

[0111] In operation S360, after transmitting the command and address, the controller 210 may disable the first control signal and the write enable signal / WE. Since the first control signal indicates a command or address directed to the nonvolatile memory device, the disablement of the first control signal indicates that the command and address are completely transmitted.

[0112] The embodiment is described as the second control signal indicating a command directed to the non-volatile memory device, but the second control signal may also be used to indicate an address. In one embodiment, the address is sent during a first time interval when the first control signal is at a logic high and the second control signal is at a logic high. Conversely, the command is sent during a second time interval when the first control signal is at a logic high and the second control signal is at a logic low.

[0113] In addition, instead of Figure 2In the case of using the command latch enable signal CLE and the address latch enable signal ALE described in the embodiment, in this embodiment, the command and address latch enable signal CALE and the newly defined command address indication signals CA1 to CA4 are used. Therefore, in this embodiment, three pins for transmitting control signals to the nonvolatile memory device can be used.

[0114] According to this embodiment, it is possible to prevent a pulse having a rising edge of the write enable signal / WE from being unnecessarily transmitted after the data signal DQ is completely transmitted. As a result, since the timing of subsequent operations (eg, transmission of data) is advanced, the performance of the memory device 200 can be improved.

[0115] Fig.16 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Fig.16 Most of the embodiments are similar to Fig.15 Therefore, further description will be omitted to avoid redundancy. For better understanding, reference will be made to Fig.13 Give a description.

[0116] In one embodiment, each of the data signals DQ1 to DQ4 may consist of 7 bits. That is, the data signals DQ1 to DQ4 may correspond to each of DQ[6:0], DQ[13:7], DQ[20:14], and DQ[27:21]. Therefore, each data signal may be transmitted to the nonvolatile memory device through 7 DQ lines.

[0117] exist Fig.15 In the embodiment of Figure 2 Compared with the embodiment of FIG. 1 , three pins for sending control signals are used. However, in Fig.16 In the embodiment, since each data signal consists of 7 bits, Fig.15 Compared with the embodiment of FIG. 1 , three DQ lines can be ensured. Therefore, no additional pin for transmitting a control signal is required.

[0118] Fig.17 is another timing diagram illustrating the timing of signals input to a nonvolatile memory device according to an exemplary embodiment of the present disclosure. Fig.17 Most of the embodiments are similar to Fig.15 and 16 Therefore, further description will be omitted to avoid redundancy. For better understanding, reference will be made to Fig.13 Give a description.

[0119] In one embodiment, in order to identify a command and an address to be transmitted to the nonvolatile memory device, a portion of the first channel CH1 may be allocated as a channel through which the command is transmitted, and the remaining portion of the first channel CH1 may be allocated as a channel through which the address is transmitted. In one embodiment, a DQ line through which the command is transmitted may be allocated as a first command channel CH1c, and a DQ line through which the address is transmitted may be allocated as a first address channel CH1a. Fig.17 , DQC[7:0] as shown in the figure indicates data signals associated with commands, and DQA[15:8], DQA[23:16], and DQA[31:24] as shown in the figure indicate data signals associated with addresses.

[0120] In one embodiment, the controller 210 may send a command "C" as DQC[7:0] to the nonvolatile memory device (e.g., NVM1) through the first command channel CH1c in the first cycle. The controller 210 may send addresses A1, A2, and A3 as DQA[15:8], DQA[23:16], and DQA[31:24] to the nonvolatile memory device through the first address channel CH1a in the first cycle. However, since the sending of the command "C" ends in the first cycle, addresses A4 and A5 may be sent to the nonvolatile memory device through the first address channel CH1a in a cycle after the first cycle.

[0121] In one embodiment, the controller 210 may send the addresses A4 and A5 as DQA[15:8] and DQA[23:16] to the nonvolatile memory device through the first address channel CH1a in a cycle after the first cycle.

[0122] exist Fig.17 In the embodiment shown in , 8 DQ lines corresponding to DQC[7:0] are allocated as command channels, and 24 DQ lines corresponding to DQA[15:8], DQA[23:16], and DQA[31:24] are allocated as address channels. However, the present disclosure is not limited thereto.

[0123] According to the above embodiments, the problems that occur when the existing relevant specifications are applied to the memory device with the DQ line of the wide I / O can be solved in various ways. Since the address latch enable signal ALE and / or the write enable signal / WE are prevented from being unnecessarily enabled, the timing of performing subsequent operations (e.g., data exchange) can be advanced. Therefore, the performance of the memory device 200 can be improved, which can include faster operation speed, more efficient operation with reduced cycle amount, and consideration of auxiliary effects such as delineation between commands and addresses.

[0124] Fig.18FIG. 1 shows an SSD system 1000 (solid state drive system) to which the wide I / O of the present disclosure is applied. Fig.18 , the SSD system 1000 may include a host 1100 and an SSD 1200 .

[0125] The SSD 1200 may exchange a signal SIG with the host 1100 through a signal connector 1201 and may be supplied with power PWR through a power connector 1202. The SSD 1200 may include an SSD controller 1210, a plurality of flash memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240.

[0126] The SSD controller 1210 may control the flash memories 1221 to 122n in response to a signal SIG received from the host 1100. For example, the SSD controller 1210 may control the flash memories 1221 to 122n based on a reference signal SIG. Figures 1 to 17 The described embodiment controls control signals (e.g., address latch enable signal ALE and write enable signal / WE) to be input to flash memories 1221 to 122n. SSD controller 1210 can improve the performance of SSD 1200 by preventing address latch enable signal ALE and write enable signal / WE from being unnecessarily enabled.

[0127] The flash memories 1221 to 122n may operate under the control of the SSD controller 1210. The auxiliary power supply 1230 may be connected to the host 1100 through the power connector 1202. The auxiliary power supply 1230 may be charged by the power PWR from the host 1100. In the case where the power PWR is not smoothly supplied from the host 1100, the auxiliary power supply 1230 may provide power to the SSD 1200.

[0128] According to the present disclosure, the operation speed of a storage device can be increased by controlling a control signal for identifying a command and data.

[0129] While the inventive concept of the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method of operating a controller for controlling a non-volatile memory device, the method comprising: Enable the command latch enable signal, address latch enable signal and write enable signal at the same time; transmitting a plurality of data signals including commands and addresses to a nonvolatile memory device in synchronization with a first rising edge of an enabled write enable signal, wherein the plurality of data signals are transmitted through data lines having a number greater than a number of bits of each of the plurality of data signals; After sending the command, disabling the command latch enable signal; and After sending the address, the address latch enable signal and the write enable signal are disabled.

2. The method according to claim 1, wherein: The controller sends a command to the nonvolatile memory device in a first cycle including a first rising edge of a write enable signal.

3. The method according to claim 2, wherein: The controller also sends a command end signal indicating the end of sending the command in the first cycle.

4. The method according to claim 3, wherein: The controller sends a command to the nonvolatile memory device via a first data line of the data lines, and The controller sends a command end signal to the nonvolatile memory device through a second data line of the data line.

5. The method according to claim 1, wherein: The data line is divided into a command channel and an address channel, a command is sent through the command channel and an address is sent through the address channel.

6. The method according to claim 5, wherein: The controller sends a command to the nonvolatile memory device through the command channel in a first cycle including a first rising edge of the write enable signal, and The controller sends an address to the nonvolatile memory device through an address channel in a first cycle.

7. The method according to claim 1, wherein: The command latch enable signal includes a first command latch enable signal and a second command latch enable signal. The address latch enable signal includes a first address latch enable signal and a second address latch enable signal. Wherein, the first command latch enable signal and the first address latch enable signal are used to latch a signal sent through a first data line of the data line, and The second command latch enable signal and the second address latch enable signal are used to latch a signal sent through a second data line of the data line.

8. A method of operating a controller for controlling a non-volatile memory device, the method comprising: Enable the write enable signal; sending a first control signal indicating a command and an address to a nonvolatile memory device; sending a second control signal indicative of a command to the nonvolatile memory device; transmitting a plurality of data signals including commands and addresses to a nonvolatile memory device in synchronization with a first rising edge of an enabled write enable signal, wherein the plurality of data signals are transmitted through data lines having a number greater than a number of bits of each of the plurality of data signals; After sending the command, disabling the second control signal; and After sending the command and address, the first control signal is disabled.

9. The method according to claim 8, wherein: sending a command during a first time interval when the first control signal is at a logic high and the second control signal is at a logic high, and The address is sent in a second time interval when the first control signal is at a logic high and the second control signal is at a logic low.

10. The method according to claim 9, wherein: The number of bits of each of the plurality of data signals is eight, and the number of data lines is a multiple of eight.

11. The method according to claim 9, wherein: The number of bits of each of the plurality of data signals is seven, and the number of data lines is a multiple of seven.

12. The method according to claim 8, wherein: The data line is divided into a command channel and an address channel, a command is sent through the command channel and an address is sent through the address channel.

13. The method according to claim 12, wherein: The controller sends a command to the nonvolatile memory device through the command channel in a first cycle including a first rising edge of the write enable signal, and The controller sends an address to the nonvolatile memory device through an address channel in a first cycle.

14. A storage device, comprising: a non-volatile memory device; as well as a controller configured to simultaneously enable a command latch enable signal, an address latch enable signal, and a write enable signal so as to be transmitted to a nonvolatile memory device, and transmit a plurality of data signals including a command and an address to the nonvolatile memory device in synchronization with a first rising edge of the enabled write enable signal, wherein the plurality of data signals are transmitted through data lines, the number of which is greater than the number of bits of each of the plurality of data signals, The controller disables a command latch enable signal after sending a command, and disables an address latch enable signal and a write enable signal after sending an address.

15. The storage device according to claim 14, wherein: The controller sends a command to the nonvolatile memory device in a first cycle including a first rising edge of a write enable signal.

16. The storage device according to claim 15, wherein: The controller also sends a command end signal indicating the end of sending the command in the first cycle.

17. The storage device according to claim 16, wherein: The controller sends a command to the nonvolatile memory device via a first data line of the data lines, and The controller sends a command end signal to the nonvolatile memory device through a second data line of the data line.

18. The storage device according to claim 14, wherein: The data line is divided into a command channel and an address channel. Commands are sent through the command channel and addresses are sent through the address channel. wherein the controller sends a command to the nonvolatile memory device through a command channel in a first cycle including a first rising edge of a write enable signal, and The controller sends an address to the nonvolatile memory device through an address channel in a first cycle.

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