Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a peripheral area; a transistor located in the display area; a pixel electrode connected to the transistor; a common electrode overlapping the pixel electrode; and an organic insulating layer located between the common electrode and the substrate and overlapping at least a portion of the peripheral area, wherein a thickness of a portion of the organic insulating layer overlapping the display area and a thickness of a portion of the organic insulating layer overlapping the peripheral area are different from each other, and the organic insulating layer includes a valley penetrating the organic insulating layer and overlapping the peripheral area.

Description

[0001] The Korean Patent Application No. 10-2018-0140837 filed on November 15, 2018 in the Korean Intellectual Property Office and entitled “DISPLAY DEVICE” is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to a display device. Background Art

[0003] The display device includes a display panel, and the display panel includes a light emitting element and a circuit element for driving the light emitting element on a substrate. The display panel may include an encapsulation substrate to help prevent penetration of external moisture or oxygen, thereby preventing the light emitting element from being damaged by moisture or oxygen.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. Summary of the invention

[0005] An embodiment relates to a display device, comprising: a substrate including a display area and a peripheral area; a transistor located in the display area; a pixel electrode connected to the transistor; a common electrode overlapping the pixel electrode; and an organic insulating layer located between the common electrode and the substrate and overlapping at least a portion of the peripheral area, wherein a thickness of a portion of the organic insulating layer overlapping the display area and a thickness of a portion of the organic insulating layer overlapping the peripheral area are different from each other, and the organic insulating layer includes a valley penetrating the organic insulating layer and overlapping the peripheral area.

[0006] The organic insulating layer overlapping the display area may have a first height, the organic insulating layer overlapping the peripheral area may have a second height, and the first height may be higher than the second height.

[0007] The first height may be approximately twice the second height.

[0008] The display device may further include an encapsulation layer on the common electrode and overlapping the display region and the peripheral region, and the encapsulation layer may include first and second inorganic layers and an organic layer between the first and second inorganic layers.

[0009] The touch line may be located on the encapsulation layer overlapping the peripheral area, and the touch electrode may be located on the encapsulation layer overlapping the display area.

[0010] One side of the encapsulation layer on which the touch line is disposed and one side of the encapsulation layer on which the touch electrode is disposed may have a step difference.

[0011] The organic layer may be disposed in the valley.

[0012] The display device may further include a dam disposed in the peripheral region, wherein a distance from the dam to an edge of the display region may be greater than a distance from an edge of the organic layer to the edge of the display region.

[0013] The transistor may further include: a semiconductor layer located on the substrate; a gate electrode overlapping the semiconductor layer; and a source electrode and a drain electrode connected to the semiconductor layer. The display device may further include a first connecting member located on the drain electrode and connecting the pixel electrode and the drain electrode.

[0014] The organic insulating layer may include: a first organic insulating layer between the source electrode and the first connecting member and between the drain electrode and the first connecting member; and a second organic insulating layer between the first connecting member and the pixel electrode.

[0015] One region of at least one of the first organic insulating layer and the second organic insulating layer overlapping the display region and another region overlapping the peripheral region may have a thickness difference.

[0016] An embodiment also relates to a display device, comprising: a substrate including a display area and a peripheral area; a transistor located in the display area; an organic insulating layer located on the transistor; a light emitting diode connected to the transistor; an encapsulation layer located on the light emitting diode and including an organic layer; and a touch line and a touch electrode located on the encapsulation layer, wherein the organic insulating layer includes a valley overlapping with the peripheral area, the organic layer is arranged in the valley, and the organic insulating layer overlapping with the display area and the organic insulating layer overlapping with the peripheral area have a step difference.

[0017] The transistor may further include: a semiconductor layer located on the substrate; a gate electrode stacked with the semiconductor layer; and a source electrode and a drain electrode connected to the semiconductor layer, wherein the display device may further include a first connecting member located on the drain electrode and connecting the pixel electrode and the drain electrode.

[0018] The organic insulating layer may include: a first organic insulating layer between the source electrode and the first connecting member and between the drain electrode and the first connecting member; and a second organic insulating layer between the first connecting member and the pixel electrode.

[0019] One region of at least one of the first organic insulating layer and the second organic insulating layer overlapping the peripheral region may be thinner than another region overlapping the display region.

[0020] The encapsulation layer may further include a first inorganic layer and a second inorganic layer, wherein the organic layer may be located between the first inorganic layer and the second inorganic layer.

[0021] An embodiment also relates to a display device, comprising: a substrate including a display area and a peripheral area; a semiconductor layer located on the substrate overlapping the display area; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode connected to the semiconductor layer; a first connecting member located on the drain electrode and connected to the drain electrode; a pixel electrode located on the first connecting member and connected to the first connecting member; an emission layer and a common electrode overlapping the pixel electrode; an organic insulating layer located between the common electrode and the substrate and overlapping at least a portion of the peripheral area, wherein the organic insulating layer includes a valley overlapping the peripheral area; and a power wiring arranged in the peripheral area and overlapping the valley.

[0022] The display device may further include a second connection member located on the same layer as the first connection member and disposed in the peripheral region, and the second connection member may overlap the valley.

[0023] The organic insulating layer may include a first organic insulating layer between the drain electrode and the first connecting member and a second organic insulating layer between the first connecting member and the pixel electrode, the first organic insulating layer may include a first valley, and the second organic insulating layer may include a second valley.

[0024] The display device may further include an encapsulation layer on the common electrode, wherein the encapsulation layer may include a first inorganic layer and a second inorganic layer and an organic layer between the first inorganic layer and the second inorganic layer, and the organic layer is disposed in the second valley. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a schematic top view of a display device according to an example embodiment;

[0027] Figure 2 Shows Figure 1 A schematic cross-sectional view taken along line AA';

[0028] Figure 3 Shows Figure 1 A schematic cross-sectional view taken along line AA';

[0029] Figure 4 Shows Figure 1 A schematic cross-sectional view taken along line AA';

[0030] Figure 5 Shows Figure 1 A schematic cross-sectional view taken along line AA';

[0031] Figure 6An equivalent circuit diagram showing a pixel of a display device according to example embodiments; and

[0032] Figure 7 A schematic cross-sectional view of a pixel of a display device according to example embodiments is shown. DETAILED DESCRIPTION

[0033] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey example implementations to those skilled in the art. In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. The same reference numerals represent the same elements throughout.

[0034] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "above" mean positioned on or below an object portion, and do not necessarily mean positioned on the upper side of an object portion based on the direction of gravity.

[0035] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” and “comprises” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0036] In addition, in this specification, the phrase "on a plane" means viewing the target portion from the top, and the phrase "on a cross section" means viewing the cross section formed by vertically cutting the target portion from the side.

[0037] In the following, reference will be made to Figure 1 and Figure 2 A display device according to example embodiments is described. Figure 1 is a schematic top view of a display device according to example embodiments. Figure 2 yes Figure 1 A schematic cross-sectional view taken along line AA'.

[0038] Reference Figure 1 The display device according to the present example embodiment may include a driving unit including a display panel 10 , a flexible printed circuit film 20 coupled to the display panel 10 , and an IC chip 30 .

[0039] The display panel 10 includes a display area DA corresponding to a screen displaying an image (for example, within a plane defined by an x-axis direction and a y-axis direction intersecting the x-axis direction) and a peripheral area PA provided at the periphery of the display area DA. Figure 1 In the middle, the quadrilateral single-point dash line The inner side of the dashed line corresponds to the display area DA, and the outer side of the dashed line corresponds to the peripheral area PA.

[0040] In the display area DA, the pixels PX may be arranged in the form of a matrix, for example. Signal lines such as scan lines (gate lines), light emitting control lines, data lines, driving voltage lines, etc. may be provided in the display area DA. Each pixel PX may be connected to the scan lines, the light emitting control lines, the data lines, and the driving voltage lines. Each pixel PX may receive a scan signal (gate signal), a light emitting control signal, a data signal, and a driving voltage from the signal lines. Each pixel PX may include a light emitting element, which may be an organic light emitting diode.

[0041] The display area DA may include a touch portion for sensing a contact touch or a non-contact touch of a user.

[0042] exist Figure 1 , the display area DA is shown as a rounded quadrangle as an example. The display area DA may have various shapes such as a polygon, a circle, an ellipse, and the like.

[0043] Circuits and / or signal lines may be provided in the peripheral area PA to generate and / or transmit various signals applied to the display area DA. In the present exemplary embodiment, a pad portion PP is provided in the peripheral area PA of the display panel 10, and a pad is formed in the pad portion PP to receive an external signal of the display panel 10. The pad portion PP may extend in a first direction (x-axis direction) along the periphery of one edge of the display panel 10. The flexible printed circuit film 20 may be bonded to the pad portion PP, and the pad of the flexible printed circuit film 20 may be electrically connected to the pad of the pad portion PP.

[0044] A driving unit that generates and / or processes various signals for driving the display panel 10 may be provided in the peripheral area PA. The driving unit may include: a data driver that applies a data signal to a data line; an emission driver (light-emitting driver) that applies an emission control signal (light-emitting control signal) to an emission control line (light-emitting control line); and a signal controller that controls the data driver, the scan driver, and the emission driver. The scan driver and the emission driver may be integrated with the display panel 10, or may be provided at the left and right sides of the display area DA or at one side of the display area DA. The data driver and the signal controller may be provided as an IC chip (driving IC chip) 30, and the IC chip 30 may be installed in the peripheral area PA of the display panel 10. The IC chip 30 may be installed in the flexible printed circuit film 20, and the IC chip 30 may be bonded to the display panel 10 and thus electrically connected to the display panel 10.

[0045] The display panel 10 may include an encapsulation layer EN that completely covers the display area DA. The encapsulation layer EN may prevent moisture or oxygen from penetrating into the display panel 10, for example, preventing moisture or oxygen from penetrating into the light emitting element, by sealing the display area DA. An edge of the encapsulation layer EN may be located between an edge of the display panel 10 and the display area DA.

[0046] A valley VA surrounding the display area DA may be provided in the peripheral area PA. The valley VA represents an area where an organic insulating layer (e.g., a first organic insulating layer 181 described in detail below in conjunction with the first valley V1) is removed. The organic insulating layer may be susceptible to moisture penetration. Therefore, in the valley VA where the organic insulating layer is removed, moisture that penetrates along a portion of the organic insulating layer may be prevented from entering the display area DA.

[0047] The valley VA may be disposed along an edge of the display panel 10, for example, may be disposed along four edges of the display panel 10. The edge of the valley VA may be substantially parallel to the edge of the display panel 10.

[0048] The display panel 10 may include a bending region BR. The bending region BR may be disposed in the peripheral region PA between the display region DA and the pad portion PP. The bending region BR may be disposed to cross the display panel 10 in a first direction (x-axis direction). The display panel 10 may be bent with a predetermined radius of curvature relative to a bending axis parallel to the first direction (x-axis direction) in the bending region BR. When the display panel 10 is a top emission type, the pad portion PP and the flexible printed circuit film 20 disposed farther from the display region DA than the bending region BR may be bent to be disposed behind the display panel 10. In an electronic device to which a display device is applied, the display panel 10 may be in such a bent state. The bending region BR may be bent relative to one bending axis, or may be bent relative to two or more bending axes. In the accompanying drawings, the bending region BR is disposed in the peripheral region PA, but the bending region BR may be disposed through the display region DA and the peripheral region PA, or may be disposed in the display region DA.

[0049] In the following, reference will be made to Figure 2 A cross-sectional structure of the display panel 10 according to example embodiments is described in detail. Figure 2 An example embodiment is schematically illustrated in cross section at the periphery of the left edge of the display panel 10. The periphery of the right edge of the display panel 10 and the periphery of the left edge of the display panel 10 may be substantially symmetrical to each other.

[0050] Reference Figure 2 , the display area DA will be described, and then the peripheral area PA will be described.

[0051] The substrate 110 includes a display area DA and a peripheral area PA, and a plurality of layers, wirings, and elements are located in the display area DA. Although a plurality of pixels PX may be provided in the display area DA of the display panel 10, only one pixel PX will be shown in the drawings to avoid complexity. In addition, each pixel PX may include, for example, a capacitor, a light-emitting element, and a plurality of transistors, but for the sake of clarity of explanation, the stacked structure of the display panel 10 will be described with specific reference to one transistor and one light-emitting element (light-emitting diode) LED connected to the transistor.

[0052] The substrate 110 may be a flexible substrate or a rigid substrate. The substrate 110 may include a polymer (eg, polyimide, polyamide, polycarbonate, polyethylene terephthalate, etc.) or glass, quartz, ceramic, etc.

[0053] The barrier layer 115 may be located on the substrate 110 and may help prevent penetration of external moisture or impurities. The barrier layer 115 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x )wait.

[0054] The buffer layer 120 may be located on the barrier layer 115. The buffer layer 120 may help block impurities that may diffuse from the substrate 110 into the semiconductor layer 130 during a process for forming the semiconductor layer 130, and may reduce stress applied to the substrate 110. The buffer layer 120 may include an inorganic insulating material such as silicon oxide, silicon nitride, and the like.

[0055] The semiconductor layer 130 may be located on the buffer layer 120. The semiconductor layer 130 may include a source region 131, a drain region 132, and a channel region 133 overlapping the gate electrode 124a. The source region 131 and the drain region 132 disposed at opposite sides of the channel region 133 may both be doped with impurities. The semiconductor layer 130 may include polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0056] A first insulating layer 141 including an inorganic insulating material such as silicon oxide, silicon nitride, etc. or an organic insulating material may be positioned on the semiconductor layer 130. The first insulating layer 141 may include a portion serving as a first gate insulating layer.

[0057] A first gate conductor, which may include a scan line and a gate electrode 124a of a transistor, may be located on the first insulating layer 141. The first gate conductor may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc., or a metal alloy thereof.

[0058] The second insulating layer 142 may be located on the first insulating layer 141 and the first gate conductor. The second insulating layer 142 may include an inorganic insulating material such as silicon oxide, silicon nitride, etc. or an organic insulating material. The second insulating layer 142 includes a portion serving as a second gate insulating layer.

[0059] A second gate conductor such as a storage line including the storage electrode 124b may be located on the second insulating layer 142. The second gate conductor may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc., or a metal alloy thereof.

[0060] The third insulating layer 160 may be located on the second gate conductor. The third insulating layer 160 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material.

[0061] A first data conductor, which may include a data line, a driving voltage line, a power wiring 178 , a source electrode 173 of a transistor, and a drain electrode 175 of a transistor, may be located on the third insulating layer 160 .

[0062] The source electrode 173 and the drain electrode 175 may be connected to the source region 131 and the drain region 132 of the semiconductor layer 130 , respectively, through contact holes formed in the third insulating layer 160 , the second insulating layer 142 , and the first insulating layer 141 .

[0063] The first data conductor may include a metal (such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), etc.) or a metal alloy thereof. The first data conductor may be a multi-layer, such as titanium / aluminum / titanium (Ti / Al / Ti), titanium / copper / titanium (Ti / Cu / Ti), or molybdenum / aluminum / molybdenum (Mo / Al / Mo).

[0064] The gate electrode 124a, the source electrode 173, and the drain electrode 175 form a transistor together with the semiconductor layer 130. In the transistor shown in the drawings, the gate electrode 124a is disposed over the semiconductor layer 130, but the structure of the transistor may be variously modified.

[0065] The first organic insulating layer 181 may be located on the third insulating layer 160 and the first data conductor (i.e., on the power wiring 178, the source electrode 173, and the drain electrode 175). The first organic insulating layer 181 may include an organic insulating material (e.g., polyimide, acrylic polymer, siloxane polymer, etc.), and may also include an inorganic insulating material.

[0066] As described in detail below, a portion of the first organic insulating layer 181 located in the peripheral area PA may include a first valley V1 in which some of the first organic insulating layer 181 is removed.

[0067] The second data conductor, which may include a first connection member 177 , a driving control signal line 179 , and a second connection member 188 , may be positioned on the first organic insulating layer 181 .

[0068] The first connection member 177 may connect the drain electrode 175 and the pixel electrode 191, which will be described below. The first connection member 177 reduces resistance between the drain electrode 175 and the pixel electrode 191, so that a light emitting element that can be driven at a high frequency while having high brightness can be provided.

[0069] The second organic insulating layer 182 may be located on the second data conductor and the first organic insulating layer 181. The second organic insulating layer 182 may include an organic insulating material, and may include, for example, polyimide, acrylic polymer, or the like.

[0070] The pixel electrode 191 of the light emitting diode LED may be located on the second organic insulating layer 182. The pixel electrode 191 may be connected to the first connection member 177 through a contact hole formed in the second organic insulating layer 182, and may be connected to the drain electrode 175 through the first connection member 177.

[0071] The pixel electrode 191 may include a metal (such as silver (Ag), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), copper (Cu), aluminum-neodymium (AlNd), aluminum-nickel-lanthanum (AlNiLa), etc.) or a metal alloy thereof. Alternatively, the pixel electrode 191 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The pixel electrode 191 may be a multilayer such as ITO / Ag / ITO, ITO / Al, etc.

[0072] The barrier rib 360 having an opening overlapping the pixel electrode 191 may be located on the second organic insulating layer 182. The opening of the barrier rib 360 may define each pixel region. The barrier rib 360 may serve as a pixel defining layer. The barrier rib 360 may include an organic insulating material or an inorganic insulating material.

[0073] The emission layer 370 may be disposed on the pixel electrode 191 to overlap the opening defined by the barrier rib 360 .

[0074] The common electrode 270 may be located on the emission layer 370. The common electrode 270 may be formed of a thin metal having a low work function, such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), etc., so that the common electrode 270 has a light-transmitting property. The common electrode 270 may include a transparent conductive material, such as ITO, IZO, etc.

[0075] The pixel electrode 191 , the emission layer 370 , and the common electrode 270 of each pixel PX form a light emitting diode LED such as an organic light emitting diode.

[0076] The encapsulation layer EN may be located on the common electrode 270 and may encapsulate the light emitting diode LED to help prevent penetration of external moisture or oxygen. The encapsulation layer EN may cover the entire area of ​​the display area DA, and an edge of the encapsulation layer EN may be disposed in the peripheral area PA.

[0077] The encapsulation layer EN may include a structure in which one or more inorganic layers and one or more organic layers are stacked. In some example embodiments, the encapsulation layer EN may include a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the encapsulation layer EN, the first inorganic layer 391 and the second inorganic layer 393 may help prevent penetration of moisture or the like, and the organic layer 392 may flatten the surface of the encapsulation layer EN (e.g., the top surface of the encapsulation layer EN).

[0078] The first and second inorganic layers 391 and 393 may include inorganic insulating materials such as silicon oxide, silicon nitride, etc. The organic layer 392 may include organic materials such as acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0079] Although not shown in this specification, a polarization layer may be located on the encapsulation layer EN to reduce reflection of external light.

[0080] The touch electrode TP for sensing touch may be located on the second inorganic layer 393 of the encapsulation layer EN. The touch electrode TP may be located between the encapsulation layer EN and the polarization layer. The touch electrode TP may be formed in the shape of a plurality of blocks and may include a transparent conductive material such as ITO, etc., or may include a metal mesh.

[0081] The touch electrode TP according to the exemplary embodiment may be directly located on the encapsulation layer EN instead of being attached to an additionally provided touch panel. Compared with the case where the touch panel is additionally manufactured and the touch electrode is attached to the touch panel, the process for forming the touch electrode TP may be simplified, and a lightweight and thin display device may be provided.

[0082] Hereinafter, constituent elements disposed in the peripheral area PA will be described. The constituent elements disposed in the peripheral area PA may be explained in conjunction with components disposed in the display area DA, and duplicate explanations may be partially omitted.

[0083] The substrate 110 , the barrier layer 115 , the buffer layer 120 , the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 , which respectively extend from the display area DA, may be sequentially stacked in the peripheral area PA.

[0084] Edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may overlap each other. For example, edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may be substantially aligned.

[0085] Edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may be disposed inside the edge of the substrate 110. Therefore, the edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may be disposed closer to the display area DA than the edge of the substrate 110.

[0086] In the peripheral area PA, crack dams CD may be provided at edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The crack dams CD may help prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115, the buffer layer 120, etc. when the display panel 10 is cut corresponding to the edge of the substrate 110. The crack dams CD may be formed of an organic material, for example, may be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier ribs 360 in the same process.

[0087] The crack dam CD may cover at least one edge of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. In another embodiment, the crack dam CD may not overlap the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160.

[0088] The power wiring 178 may be located on a portion of the third insulating layer 160 disposed in the peripheral area PA. The power wiring 178 may be located on the same layer as the source electrode 173 and the drain electrode 175 disposed in the display area DA. The power wiring 178 may be formed of the same material in the same process as the first data conductor including the source electrode 173 and the drain electrode 175.

[0089] The power wiring 178 may transmit a power voltage having a predetermined level that may be applied to the light emitting diode LED, and may transmit, for example, a common voltage ELVSS (see Figure 6 ). The power wiring 178 may be electrically connected to the pad portion PP through the first end portion and the second end portion thereof, and may surround the display area DA.

[0090] The first organic insulating layer 181 may be located on the power wiring 178 and the third insulating layer 160 .

[0091] The first organic insulating layer 181 overlapping the peripheral area PA may include the above-mentioned first valley V1. The first valley V1 indicates an area from which the first organic insulating layer 181 is removed. The first valley V1 may block a movement path of moisture or the like introduced from outside the substrate 110 through the first organic insulating layer 181 to help prevent moisture from penetrating into the display area DA.

[0092] The first valley V1 may penetrate (eg, completely penetrate) the first organic insulating layer 181. The first valley V1 may have a height substantially the same as a thickness of the first organic insulating layer 181.

[0093] The driving control signal line 179 and the second connection member 188 may be located on a portion of the first organic insulating layer 181 overlapping the peripheral area PA. The driving control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 disposed in the display area DA. The driving control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0094] The driving control signal line 179 can transmit signals such as a vertical start signal, a clock signal, etc. and provide a signal of a low voltage of a specific level to a scanning driver and / or a light-emitting driver, and the scanning driver and / or the light-emitting driver can be set in a driving circuit area in the peripheral area PA.

[0095] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power wiring 178. A portion of the first organic insulating layer 181 overlapping the power wiring 178 may be removed for connection between the second connection member 188 and the power wiring 178.

[0096] The second organic insulating layer 182 may be positioned on the first organic insulating layer 181 , the driving control signal line 179 , and the second connection member 188 .

[0097] The thickness of the second organic insulating layer 182 disposed in the peripheral area PA may be different from the thickness of the second organic insulating layer 182 disposed in the display area DA. The second organic insulating layer 182 overlapping the display area DA may have a first height h1, and the second organic insulating layer 182 disposed in the peripheral area PA may have a second height h2. In the present example embodiment, the first height h1 may be higher than the second height h2, for example, the first height h1 may be approximately twice the second height h2. One side (e.g., top surface) of the second organic insulating layer 182 disposed in the peripheral area PA and one side (e.g., top surface) of the second organic insulating layer 182 disposed in the display area DA may have a step difference.

[0098] The second organic insulating layer 182 having a plurality of regions each having a different height may be formed through a single process, for example, by using a half-tone mask.

[0099] The second organic insulating layer 182 may include a second valley V2. The second valley V2 indicates a region from which the second organic insulating layer 182 is removed. The second valley V2 may block a movement path of moisture or foreign particles moving from the outside through the second organic insulating layer 182 or the first organic insulating layer 181, thereby preventing external moisture or foreign particles from penetrating into the display area DA.

[0100] The second valley V2 may penetrate (eg, completely penetrate) the second organic insulating layer 182 disposed in the peripheral area PA. The height of the second valley V2 may be substantially the same as the thickness of the second organic insulating layer 182 disposed in the peripheral area PA. The height of the second valley V2 may be the same as the second height h2.

[0101] In some example embodiments, the first valley V1 and the second valley V2 may overlap each other. The edge of the first valley V1 and the edge of the second valley V2 may be aligned while overlapping each other. When the first valley V1 and the second valley V2 substantially overlap each other, they may be regarded as a single valley.

[0102] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 may be formed of the same material as the pixel electrode 191 through the same process.

[0103] The third connection member 198 may be connected to the power wiring 178 through the second connection member 188. The third connection member 198 may be connected to the common electrode 270 overlapping the display area DA. The power wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power wiring 178 transmits the common voltage ELVSS as the power voltage, the common electrode 270 may receive the common voltage ELVSS.

[0104] The third connecting member 198 on the second organic insulating layer 182 may have a patterned shape. In the present exemplary embodiment, the third connecting member 198 and the drive control signal line 179 may not substantially overlap each other in the z-axis direction. The drive control signal line 179 may also have a patterned shape and may be disposed in an area that does not overlap the third connecting member 198. The third connecting member 198 and the drive control signal line 179 may be disposed to be misaligned or offset from each other. In a plan view, the third connecting member 198 and the drive control signal line 179 may be disposed in a misaligned area and thus completely form a planar shape. Since the third connecting member 198 and the drive control signal line 179 are not aligned, unnecessary signals generated from the lower portion of the touch line TL may be shielded.

[0105] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than an organic material such as the third connection member 198, moisture or foreign particles moving along the organic insulating layer may be prevented from penetrating into the display area DA.

[0106] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 may be located on the third insulating layer 160.

[0107] The dams D1 and D2 may prevent an organic material having fluidity (such as a monomer used in a process for forming the organic layer 392 of the encapsulation layer EN) from overflowing. Therefore, an edge of the organic layer 392 of the encapsulation layer EN may be substantially closer to the inside than the dams D1 and D2, for example, may be disposed inside the first dam D1. An edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA. An edge of the organic layer 392 may be disposed closer to the display area DA than an edge of the dams D1 and D2.

[0108] The dams D1 and D2 may include at least one layer. The dams D1 and D2 may be formed by using an organic insulating layer, an inorganic insulating layer, or a barrier rib disposed in the display area DA.

[0109] The first dam D1 according to example embodiments may include one layer. In this example embodiment, the first dam D1 may be formed of the same material through the same process as the second organic insulating layer 182. The first dam D1 may be formed of the same material through the same process as the barrier rib 360.

[0110] The second dam D2 according to example embodiments may include a plurality of layers. The second dam D2 may include at least one of a layer formed of the same material as the first organic insulating layer 181 through the same process, a layer formed of the same material as the second organic insulating layer 182 through the same process, and a layer formed of the same material as the barrier rib 360 through the same process.

[0111] The encapsulation layer EN extending from the display area DA may be disposed in the peripheral area PA. The first inorganic layer 391 and the second inorganic layer 393 included in the encapsulation layer EN may extend to the vicinity of the edge of the peripheral area PA where the third insulating layer 160 is disposed. The first inorganic layer 391 and the second inorganic layer 393 of the encapsulation layer EN may extend over the dams D1 and D2 to cover the dams D1 and D2. In the present example embodiment, the contact area of ​​the first inorganic layer 391 and the second inorganic layer 393 is increased, and thus, the bonding force between the first inorganic layer 391 and the second inorganic layer 393 may be increased.

[0112] The edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed at a position not exceeding the first dam D1 while filling the valleys V1 and V2. The organic layer 392 may be disposed in the valleys V1 and V2.

[0113] The organic layer 392 may be formed of an organic material such as a monomer or a reaction product thereof. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the second valley V2 may be determined by the thickness of the second organic insulating layer 182, and according to an example embodiment, the thickness of the second organic insulating layer 182 disposed in the peripheral area PA may be thinner than the thickness of the second organic insulating layer 182 disposed in the display area DA, so the height of the second valley V2 may be reduced. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2 while fully filling the first valley V1 and the second valley V2. According to the present example embodiment, the organic layer 392 may have a flat top surface.

[0114] Compared to the above-described example embodiments, if the height of the second valley V2 in the peripheral area PA is substantially the same as the thickness of the second organic insulating layer 182 in the display area DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the height of the second valley V2 is equal to the first height h1, the organic material does not flow to the periphery of the first dam D1 after filling the first valley V1 and the second valley V2, or does not completely fill the first valley V1 and the second valley V2. Therefore, the top surface of the organic layer 392 is recessed, so that the organic layer 392 does not have a flat top surface. The touch line TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not flattened, the touch line TL is not easily formed, and a short circuit failure may occur.

[0115] A plurality of touch lines TL connected to the touch electrodes TP disposed in the display area DA may be located on the top surface of the encapsulation layer EN. The touch lines TL are connected to the touch electrodes TP and transmit touch sensing signals. The touch lines TL may be formed of the same material as the touch electrodes TP through the same process, or may be formed of different materials through different processes than the touch electrodes TP.

[0116] According to the present exemplary embodiment, the touch line TL disposed in the peripheral area PA and the touch electrode TP disposed in the display area DA may have a step difference. Therefore, one side of the encapsulation layer EN in which the touch line TL is disposed and one side of the encapsulation layer EN in which the touch electrode TP is disposed may have a step difference.

[0117] A protective film (not shown) disposed under the substrate 110 may also be included. The protective film may be attached to the rear side of the display panel 10 by using an adhesive, or may be formed by a coating process without using an adhesive. The protective film may include plastics such as polyethylene terephthalate, polyethylene naphthalate, polyimide, polyethylene sulfide, etc.

[0118] In the following, we will refer to Figures 3 to 5 Display devices according to various example embodiments are described. Figure 3 yes Figure 1 A cross-sectional view of an exemplary embodiment taken along line AA', Figure 4 yes Figure 1 A cross-sectional view of an exemplary embodiment taken along line AA', Figure 5 yes Figure 1 A cross-sectional view of an example embodiment taken along line AA'. Figures 3 to 5 The components provided in the display area DA shown in FIG. Figure 2 The constituent elements described are the same, so the description will be omitted.

[0119] First, refer to Figure 3 , the substrate 110 , the barrier layer 115 , the buffer layer 120 , the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 extending from the display area DA may be sequentially stacked in the peripheral area PA.

[0120] The first insulating layer 141, the second insulating layer 142, and the third insulating layer 160 may be aligned at their edges. For example, an edge of the first insulating layer 141, an edge of the second insulating layer 142, and an edge of the third insulating layer 160 may overlap each other.

[0121] In the peripheral area PA, crack dams CD may be provided at edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The crack dams CD may prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115, the buffer layer 120, etc. when the display panel 10 is cut corresponding to the edge of the substrate 110. The crack dams CD may be formed of an organic material or an inorganic material, for example, may be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier ribs 360 in the same process.

[0122] The power wiring 178 may be located on a portion of the third insulating layer 160 disposed in the peripheral area PA. The power wiring 178 may be located on the same layer as the source electrode 173 and the drain electrode 175 disposed in the display area DA. The power wiring 178 may be formed of the same material in the same process as the first data conductor including the source electrode 173 and the drain electrode 175.

[0123] The power wiring 178 may transmit a power voltage having a predetermined level that may be applied to the light emitting diode LED, and may transmit, for example, a common voltage ELVSS.

[0124] The first organic insulating layer 181 is located on the power wiring 178 and the third insulating layer 160. The thickness of the first organic insulating layer 181 overlapping the peripheral area PA and the thickness of the first organic insulating layer 181 overlapping the display area DA may be different from each other. For example, the first organic insulating layer 181 overlapping the display area DA may have a third height h3, and the first organic insulating layer 181 overlapping the peripheral area PA may have a fourth height h4, and the third height h3 may be higher than the fourth height h4. For example, the third height h3 may be about twice the fourth height h4.

[0125] The first organic insulating layer 181 having a plurality of regions each having a different height may be formed through a single process, for example, by using a half-tone mask.

[0126] The first organic insulating layer 181 overlapping the peripheral area PA may include a first valley V1 in which the first organic insulating layer 181 is removed. The first valley V1 may block a movement path of moisture or the like introduced from outside the substrate 110 through the first organic insulating layer 181 to help prevent moisture from penetrating into the display area DA.

[0127] The height of the first valley V1 may be substantially the same as the thickness of the first organic insulating layer 181 disposed in the peripheral area PA. The height of the first valley V1 may be substantially the same as the fourth height h4.

[0128] The driving control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The driving control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 disposed in the display area DA. The driving control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0129] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power wiring 178. A portion of the first organic insulating layer 181 overlapping the power wiring 178 may be removed for connection between the second connection member 188 and the power wiring 178.

[0130] The second organic insulating layer 182 may be located on the driving control signal line 179 and the second connecting member 188. In various example embodiments, the thickness of the second organic insulating layer 182 overlapping the display area DA and the thickness of the second organic insulating layer 182 overlapping the peripheral area PA may be substantially equal to each other. When the thickness of the second organic insulating layer 182 overlapping the display area DA is a first height h1 and the thickness of the second organic insulating layer 182 overlapping the peripheral area PA is a second height h2, the first height h1 and the second height h2 may be substantially equal to each other. Substantially equal not only indicates completely equal, but also indicates that there may be a slight difference depending on, for example, a process error.

[0131] The second organic insulating layer 182 may include a second valley V2 in which the second organic insulating layer 182 is removed. The second valley V2 may block a movement path of moisture or the like introduced from outside the substrate 110 through the second organic insulating layer 182 to help prevent external moisture from penetrating into the display area DA.

[0132] In various example embodiments, the first valley V1 and the second valley V2 may overlap each other. An edge of the first valley V1 and an edge of the second valley V2 may be aligned while overlapping each other.

[0133] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 may be connected to the power wiring 178 through the second connection member 188, and the third connection member 198 may be connected to the common electrode 270 overlapping the display area DA. The power wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power wiring 178 transmits the common voltage ELVSS as the power voltage, the common electrode 270 may receive the common voltage ELVSS.

[0134] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than an organic material (such as the third connection member 198), moisture or foreign particles may be prevented from penetrating into the display area DA.

[0135] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 may be located on the third insulating layer 160.

[0136] The dams D1 and D2 may prevent an organic material having fluidity (such as a monomer used in a process for forming the organic layer 392 of the encapsulation layer EN) from overflowing. The edge of the organic layer 392 of the encapsulation layer EN may be substantially closer to the inside than the dams D1 and D2, for example, may be disposed inside the first dam D1. The edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA.

[0137] The encapsulation layer EN extending from the display area DA may be disposed in the peripheral area PA. The first and second inorganic layers 391 and 393 included in the encapsulation layer EN may extend to near an edge of the peripheral area PA where the third insulating layer 160 is disposed.

[0138] An edge of the organic layer 392 included in the encapsulation layer EN may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed at a position close to the first dam D1 while filling the valleys V1 and V2.

[0139] The organic layer 392 may be formed using an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the first valley V1 is determined by the thickness of the first organic insulating layer 181, and according to an example embodiment, the thickness of the first organic insulating layer 181 disposed in the peripheral area PA is thinner than the thickness of the first organic insulating layer 181 disposed in the display area DA, so the height of the first valley V1 may be reduced. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2 while fully filling the first valley V1 and the second valley V2. According to the present example embodiment, the organic layer 392 and the encapsulation layer EN including the organic layer 392 may have a flat top surface.

[0140] A plurality of touch wires TL connected to the touch electrodes TP may be located on the top surface of the encapsulation layer EN. Since the touch wires TL are formed on a very flat top surface, they may be stably formed.

[0141] If the height of the first valley V1 is substantially the same as the thickness of the first organic insulating layer 181 disposed in the display area DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the height of the first valley V1 is equal to the third height h3, the organic material may not be sufficient to flow to the periphery of the first dam D1, or the first valley V1 and the second valley V2 may not be completely filled. Therefore, the top surface of the organic layer 392 may be recessed, so that the organic layer 392 may not have a flat top surface. The touch line TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not flattened, the touch line TL may not be easily formed, and a short circuit failure may occur.

[0142] Next, refer to Figure 4 , the substrate 110 , the barrier layer 115 , the buffer layer 120 , the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 , which respectively extend from the display area DA, may be sequentially stacked in the peripheral area PA.

[0143] In the peripheral area PA, crack dams CD may be provided at edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The crack dams CD may prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115, the buffer layer 120, etc. when the display panel 10 is cut corresponding to an edge of the substrate 110.

[0144] The power wiring 178 may be located on a portion of the third insulating layer 160 disposed in the peripheral area PA. The power wiring 178 may be located on the same layer as the source electrode 173 and the drain electrode 175 disposed in the display area DA. The power wiring 178 may be formed of the same material in the same process as the first data conductor including the source electrode 173 and the drain electrode 175.

[0145] The power wiring 178 may transmit a power voltage having a predetermined level that may be applied to the light emitting diode LED, and may transmit, for example, a common voltage ELVSS.

[0146] The first organic insulating layer 181 may be located on the power wiring 178 and the third insulating layer 160. The thickness of the first organic insulating layer 181 disposed in the peripheral area PA may be different from the thickness of the first organic insulating layer 181 disposed in the display area DA. For example, the first organic insulating layer 181 overlapping the display area DA may have a third height h3, and the first organic insulating layer 181 overlapping the peripheral area PA may have a fourth height h4. In the present example embodiment, the third height h3 may be higher than the fourth height h4, for example, the third height h3 may be approximately twice the fourth height h4.

[0147] The first organic insulating layer 181 having a plurality of regions each having a different height may be formed through a single process, for example, by using a half-tone mask.

[0148] The first organic insulating layer 181 overlapping the peripheral area PA may include a first valley V1 in which the first organic insulating layer 181 is removed.

[0149] The height of the first valley V1 may be substantially the same as the thickness of the first organic insulating layer 181 disposed in the peripheral area PA. The height of the first valley V1 may be substantially the same as the fourth height h4.

[0150] The driving control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The driving control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 disposed in the display area DA. The driving control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0151] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power wiring 178. A portion of the first organic insulating layer 181 overlapping the power wiring 178 may be removed for connection between the second connection member 188 and the power wiring 178.

[0152] The second organic insulating layer 182 may be located on the driving control signal line 179 and the second connection member 188 .

[0153] The thickness of the second organic insulating layer 182 overlapping the display area DA and the thickness of the second organic insulating layer 182 overlapping the peripheral area PA may be different from each other. The thickness of the second organic insulating layer 182 disposed in the peripheral area PA may be less than the thickness of the second organic insulating layer 182 disposed in the display area DA. The second organic insulating layer 182 overlapping the display area DA may have a first height h1, and the second organic insulating layer 182 disposed in the peripheral area PA may have a second height h2. In the present example embodiment, the first height h1 may be higher than the second height h2, for example, the first height h1 may be approximately twice the second height h2.

[0154] The second organic insulating layer 182 having a plurality of regions each having a different height may be formed through a single process, for example, by using a half-tone mask.

[0155] The second organic insulating layer 182 may include a second valley V2. The height of the second valley V2 may be substantially the same as the thickness of the second organic insulating layer 182 disposed in the peripheral area PA, for example, the second valley V2 may have a second height h2. The second valley V2 indicates a region from which the second organic insulating layer 182 is removed.

[0156] In various example embodiments, the first valley V1 and the second valley V2 may overlap each other. An edge of the first valley V1 and an edge of the second valley V2 may be aligned while overlapping each other.

[0157] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 may be formed of the same material as the pixel electrode 191 through the same process.

[0158] The third connection member 198 may be connected to the power wiring 178 through the second connection member 188, and the third connection member 198 may be connected to the common electrode 270 overlapping the display area DA. The power wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power wiring 178 transmits the common voltage ELVSS as the power voltage, the common electrode 270 may receive the common voltage ELVSS.

[0159] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. When the first valley V1 and the second valley V2 are filled with a material other than an organic material (such as the third connection member 198), moisture or foreign particles may be prevented from penetrating into the display area DA.

[0160] The encapsulation layer EN may include a first inorganic layer 391, an organic layer 392, and a second inorganic layer 393. In the present example embodiment, an edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may be formed adjacent to the first dam D1 while filling the valleys V1 and V2.

[0161] The organic layer 392 may be formed using an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. The height of the first valley V1 may be determined by the thickness of the first organic insulating layer 181, and the height of the second valley V2 may be determined by the thickness of the second organic insulating layer 182. According to the present example embodiment, the thickness of the first organic insulating layer 181 disposed in the peripheral area PA is thinner than the thickness of the first organic insulating layer 181 disposed in the display area DA, and thus the height of the first valley V1 may be reduced. Similarly, the thickness of the second organic insulating layer 182 disposed in the peripheral area PA is thinner than the thickness of the second organic insulating layer 182 disposed in the display area DA, and thus the height of the second valley V2 may be reduced. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2, while fully filling the first valley V1 and the second valley V2. According to the present example embodiment, the organic layer 392 may have a flat top surface.

[0162] A plurality of touch lines TL connected to the touch electrodes TP may be located on a top surface of the encapsulation layer EN.

[0163] When the heights of the first valley V1 and the second valley V2 are substantially the same as the thicknesses of the first organic insulating layer 181 and the second organic insulating layer 182 disposed in the display area DA, a large amount of organic material may be required to fill the first valley V1 and the second valley V2. In the case where the heights of the first valley V1 and the second valley V2 are equal to the third height h3 and the first height h1, the organic material may not be sufficient to flow to the periphery of the first dam D1, or the first valley V1 and the second valley V2 may not be completely filled. Therefore, the top surface of the organic layer 392 may be recessed, so that the organic layer 392 may not have a flat top surface. The touch line TL connected to the touch electrode TP may be located on the top surface of the organic layer 392. If the top surface of the organic layer 392 is not flattened, the touch line TL may not be easily formed, and a short circuit failure may occur.

[0164] Next, refer to Figure 5 , the substrate 110 , the barrier layer 115 , the buffer layer 120 , the first insulating layer 141 , the second insulating layer 142 , and the third insulating layer 160 , which respectively extend from the display area DA, may be sequentially stacked in the peripheral area PA.

[0165] In the peripheral area PA, crack dams CD may be provided at edges of the first insulating layer 141, the second insulating layer 142, and the third insulating layer 160. The crack dams CD may prevent the spread of cracks that may occur in inorganic insulating layers such as the barrier layer 115, the buffer layer 120, etc. when the display panel 10 is cut corresponding to the edge of the substrate 110. The crack dams CD may be formed of an organic material, for example, may be formed of the same material as at least one of the first organic insulating layer 181, the second organic insulating layer 182, and the barrier ribs 360 through the same process.

[0166] The power wiring 178 may be located on a portion of the third insulating layer 160 disposed in the peripheral area PA. The power wiring 178 may be located on the same layer as the source electrode 173 and the drain electrode 175 disposed in the display area DA. The power wiring 178 may be formed of the same material in the same process as the first data conductor including the source electrode 173 and the drain electrode 175.

[0167] The power wiring 178 may transmit a power voltage having a predetermined level that may be applied to the light emitting diode LED, and may transmit, for example, a common voltage ELVSS.

[0168] The first organic insulating layer 181 may be located on the power wiring 178 and the third insulating layer 160 .

[0169] The first organic insulating layer 181 overlapping the peripheral area PA may include a first valley V1 in which the first organic insulating layer 181 is removed. The first valley V1 may block movement of moisture introduced through the first organic insulating layer 181 to help prevent moisture from penetrating into the display area DA.

[0170] The power wiring 178 according to the present example embodiment may extend toward the display area DA, for example, the power wiring 178 may partially overlap the first valley V1 . The first valley V1 may partially expose the power wiring 178 .

[0171] The driving control signal line 179 and the second connection member 188 may be located on the first organic insulating layer 181. The driving control signal line 179 and the second connection member 188 may be located on the same layer as the first connection member 177 disposed in the display area DA. The driving control signal line 179 and the second connection member 188 may be formed by the same process as the first connection member 177 and may include the same material as the first connection member 177.

[0172] The second connection member 188 may be located on the first organic insulating layer 181 and may be connected to the power wiring 178. A portion of the first organic insulating layer 181 overlapping the power wiring 178 may be removed for connection between the second connection member 188 and the power wiring 178. In an implementation, the second connection member 188 may be connected to the power wiring 178 through the first valley V1, and in example embodiments, this portion of the first organic insulating layer 181 may not be removed.

[0173] The second connection member 188 may be disposed in the first valley V1. The second connection member 188 may extend toward the display area DA while filling the first valley V1. The second connection member 188 may be connected to the power wiring 178 through the first valley V1.

[0174] The second organic insulating layer 182 may be located on the driving control signal line 179 and the second connection member 188. The second organic insulating layer 182 may include a second valley V2 in which the second organic insulating layer 182 is removed.

[0175] In various example embodiments, the first valley V1 and the second valley V2 may overlap each other.The first valley V1 and the second valley V2 may be aligned at their edges while overlapping each other.

[0176] The third connection member 198 located on the same layer as the pixel electrode 191 may be located on the second organic insulating layer 182. The third connection member 198 may be formed of the same material as the pixel electrode 191 through the same process.

[0177] The third connection member 198 may be connected to the power wiring 178 through the second connection member 188, and the third connection member 198 may be connected to the common electrode 270 overlapping the display area DA. The power wiring 178 may be connected to the common electrode 270 through the third connection member 198 and the second connection member 188. When the power wiring 178 transmits the common voltage ELVSS as the power voltage, the common electrode 270 may receive the common voltage ELVSS.

[0178] The third connection member 198 may be disposed in the first valley V1 and the second valley V2. The third connection member 198 may have a shape that penetrates the first organic insulating layer 181 and the second organic insulating layer 182. The third connection member 198 may contact the second connection member 188 in the first valley V1 and the second valley V2. The third connection member 198 is connected to the second connection member 188 through the second valley V2, and the second connection member 188 is connected to the power wiring 178 through the first valley V1, so that the common voltage ELVSS may be transmitted.

[0179] The first valley V1 and the second valley V2 may be mainly filled with materials other than organic materials, such as the second connection member 188 and the third connection member 198. Therefore, moisture or foreign particles may be prevented from penetrating into the display area DA through the first valley V1 and the second valley V2.

[0180] At least one of the dams D1 and D2 may be disposed in the peripheral area PA. The dams D1 and D2 may prevent an organic material having fluidity (such as a monomer used in a process for forming the organic layer 392 of the encapsulation layer EN) from overflowing. Therefore, an edge of the organic layer 392 of the encapsulation layer EN may be substantially closer to the inside than the dams D1 and D2, for example, may be disposed inside the first dam D1.

[0181] The edge of the organic layer 392 may be located between the dams D1 and D2 and the display area DA. The edge of the organic layer 392 may be located between the first dam D1 and the valleys V1 and V2. The organic layer 392 may extend to a position adjacent to the first dam D1 while filling the valleys V1 and V2.

[0182] The organic layer 392 may be formed using an organic material such as a monomer. The organic material may flow into the first valley V1 and the second valley V2 during the process for forming the organic layer 392. In the present exemplary embodiment, the first valley V1 is in a state filled with the second connection member 188, and the second valley V2 is in a state filled with the third connection member 198. Therefore, the organic material provided during the process for forming the organic layer 392 may have an edge located between the first dam D1 and the valleys V1 and V2, while the first valley V1 and the second valley V2 are sufficiently filled even with a small amount of organic material. The organic layer 392 formed on such a structure may have a planarized top surface.

[0183] A plurality of touch lines TL connected to the touch electrodes TP may be located on a top surface of the encapsulation layer EN.

[0184] In the following, reference will be made to Figure 6 and Figure 7 A display area of ​​the display device according to the present exemplary embodiment is described. Figure 6 is a circuit diagram of one pixel of a display device according to this exemplary embodiment, Figure 7 is a schematic cross-sectional view of a pixel of a display device according to example embodiments.

[0185] First, refer to Figure 6 , the pixel PX may be a region divided by the plurality of signal lines 121, 171, and 172. The pixel PX may be a minimum unit for displaying an image. The display device displays an image by using a plurality of pixels PX.

[0186] The signal lines 121, 171, and 172 may include a plurality of gate lines 121 transmitting gate signals (or scan signals), a plurality of data lines 171 transmitting data signals, and a plurality of driving voltage lines (first driving voltage lines) 172 transmitting a driving voltage ELVDD. In the present exemplary embodiment, the data lines 171 and the driving voltage lines 172 are included in the data conductor, and the gate lines 121 will be referred to as gate conductors.

[0187] The gate lines 121 may extend substantially in a row direction and substantially parallel to each other, and vertical direction portions of the data lines 171 and the driving voltage lines 172 may extend substantially in a column direction and substantially parallel to each other.

[0188] Each pixel PX may include a switching thin film transistor Qs, a driving thin film transistor Qd, a storage capacitor Cst, and a light emitting diode LED. Each pixel PX may also include a transistor and a capacitor for compensating a current supplied to the light emitting diode LED.

[0189] In the present exemplary embodiment, the switching thin film transistor Qs transmits the data signal applied to the data line 171 to the driving thin film transistor Qd in response to the scan signal applied to the gate line 121. The driving thin film transistor Qd flows an output current I LD , the output current I LD The size of varies according to the voltage applied between the control terminal and the output terminal. The storage capacitor Cst is charged with an amount of charge corresponding to the data signal applied to the control terminal of the driving thin film transistor Qd, and maintains the amount of charge even after the switching thin film transistor Qs is turned off.

[0190] In the present exemplary embodiment, the light emitting diode LED includes an anode connected to the output terminal of the driving thin film transistor Qd and a power wiring 178 connected to the transmission common voltage ELVSS (see FIG. 1 ). Figures 2 to 5 ) is connected to the cathode of the light emitting diode LED. The light emitting diode LED is connected to the cathode of the light emitting diode LED by driving the output current I of the thin film transistor Qd. LD Change the intensity to display the image.

[0191] Next, refer to Figure 7 , the interlayer structure of the region where the storage capacitor, the driving thin film transistor (hereinafter referred to as "transistor"), etc. are provided will be described. Reference may be omitted in the following description. Figure 2 Repeated description of similar features provided.

[0192] The barrier layer 115 may be located on the substrate 110 to help prevent penetration of moisture or foreign particles introduced from the outside. The buffer layer 120 may be located on the barrier layer 115. The buffer layer 120 may block impurities that may diffuse from the substrate 110 to the semiconductor layer 130 during a process for forming the semiconductor layer 130, and may reduce stress applied to the substrate 110. Each of the barrier layer 115 and the buffer layer 120 may include an inorganic insulating material such as silicon oxide, silicon nitride, etc.

[0193] The semiconductor layer 130 may be located on the buffer layer 120. The semiconductor layer 130 may include a source region 131, a drain region 132, and a channel region 133 overlapping the gate electrode 124a. In the present example embodiment, the source region 131 and the drain region 132 are respectively disposed at opposite sides of the channel region 133 and are doped with impurities. The semiconductor layer 130 may include polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0194] A first insulating layer 141 including an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material may be located on the semiconductor layer 130. The first insulating layer 141 may also be referred to as a first gate insulating layer.

[0195] A first gate conductor including a scan line and a gate electrode 124 a of a transistor may be positioned on the first insulating layer 141 .

[0196] The second insulating layer 142 may be located on the first insulating layer 141 and the first gate conductor. The second insulating layer 142 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material. The second insulating layer 142 may also be referred to as a second gate insulating layer.

[0197] A second gate conductor such as a storage line including the storage electrode 124b may be located on the second insulating layer 142. The gate electrode 124a and the storage electrode 124b may form a reference Figure 6 The storage capacitor Cst is described.

[0198] The third insulating layer 160 may be located on the second gate conductor. The third insulating layer 160 may include an inorganic insulating material (such as silicon oxide, silicon nitride, etc.) or an organic insulating material.

[0199] A first data conductor including a data line 171 , a first driving voltage line 172 , and a source electrode 173 and a drain electrode 175 of a transistor may be located on the third insulating layer 160 .

[0200] Each of the source electrode 173 and the drain electrode 175 may be connected to the source region 131 and the drain region 132 of the semiconductor layer 130 through contact holes formed in the third insulating layer 160 , the second insulating layer 142 , and the first insulating layer 141 , respectively.

[0201] In the present example embodiment, the gate electrode 124a, the source electrode 173, and the drain electrode 175 form a transistor together with the semiconductor layer 130. In the transistor shown in the drawings, the gate electrode 124a is disposed over the semiconductor layer 130, but the structure of the transistor may be variously modified.

[0202] The first organic insulating layer 181 may be located on the third insulating layer 160 and the first data conductor. The first organic insulating layer 181 may include an organic insulating material, for example, polyimide, acrylic polymer, siloxane polymer, etc.

[0203] A second data conductor including a first connection member 177 and a second driving voltage line 177 b may be positioned on the first organic insulating layer 181 .

[0204] The first connection member 177 may connect the drain electrode 175 and the pixel electrode 191. The second driving voltage line 177b may be connected to the first driving voltage line 172 and may transmit a driving voltage. The second driving voltage line 177b may reduce resistance by being connected to the first driving voltage line 172, and may provide a display panel with high brightness and high frequency.

[0205] In the present example embodiment, the second organic insulating layer 182 is positioned on the second data conductor and the first organic insulating layer 181. The second organic insulating layer 182 may include an organic insulating material, and may include, for example, polyimide, acrylic polymer, or the like.

[0206] The pixel electrode 191 of the light emitting diode LED may be located on the second organic insulating layer 182. The pixel electrode 191 may be connected to the first connection member 177 through a contact hole formed in the second organic insulating layer 182, and may be connected to the drain electrode 175 through the first connection member 177.

[0207] The barrier rib 360 having an opening overlapping the pixel electrode 191 may be located on the second organic insulating layer 182. The opening of the barrier rib 360 may define each pixel region. The barrier rib 360 may be referred to as a pixel defining layer. The barrier rib 360 may include an organic insulating material or an inorganic insulating material.

[0208] In the present example embodiment, the emission layer 370 is located on the pixel electrode 191 overlapping the opening of the barrier rib 360 , and the common electrode 270 is located on the emission layer 370 .

[0209] In this exemplary embodiment, the pixel electrode 191, the emission layer 370 and the common electrode 270 of each pixel PX form a light emitting diode LED such as an organic light emitting diode. According to the light emitting direction of the light emitting diode LED, the display device can have any one of a front display type, a rear display type and a one panel dual display type.

[0210] Above the common electrode 270, as previously described with reference to Figure 2 As described above, the encapsulation layer EN and the touch electrodes TP may be sequentially disposed.

[0211] By summarizing and reviewing, instead of sealing the light-emitting element by using the encapsulation substrate, an encapsulation layer may be formed on the light-emitting element, which may reduce the weight of the display panel and reduce the possibility of damaging the display panel. Most of the display panel may be a display area where an image is displayed, but a specific area of ​​the display panel (e.g., an edge area of ​​the display panel) may be a peripheral area where a driving circuit, a signal line, etc. are disposed.

[0212] Embodiments may provide a display panel in which an organic layer of an encapsulation layer disposed in a peripheral region may have a flat top surface. Therefore, a touch line formed on the encapsulation layer may be stably formed. Therefore, a display device with improved reliability may be provided. Embodiments may provide a display device in which a top surface of an encapsulation layer (e.g., an organic layer included in the encapsulation layer) disposed in a peripheral region may be made flat, which may help to be able to form a touch line on the encapsulation layer.

[0213] <Description of the symbol>

[0214] DA: Display Area

[0215] PA: Peripheral Area

[0216] 110: Base

[0217] 191: Pixel electrode

[0218] 270: Common electrode

[0219] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be construed in a general and descriptive sense only, and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as of the time of filing this application that, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, comprising: a substrate, including a display area and a peripheral area; A transistor located in the display area; a pixel electrode connected to the transistor; a common electrode, overlapping the pixel electrode; as well as an organic insulating layer, located between the common electrode and the substrate and overlapping at least a portion of the peripheral region, wherein a first thickness of a portion of the organic insulating layer overlapping the display area and a second thickness of a portion of the organic insulating layer overlapping the peripheral area are different from each other, The organic insulating layer includes a valley penetrating the organic insulating layer and overlapping the peripheral region, and The second thickness of the organic insulating layer adjacent to the valley and formed integrally with the organic insulating layer overlapping the display area is smaller than the first thickness of the organic insulating layer.

2. The display device according to claim 1, wherein: The organic insulating layer overlapping the display area has a first height, the organic insulating layer overlapping the peripheral area has a second height, and the first height is higher than the second height.

3. The display device according to claim 2, wherein: The first height is twice the second height.

4. The display device according to claim 1, wherein: The display device further includes an encapsulation layer located on the common electrode and overlapping the display area and the peripheral area, and The encapsulation layer comprises: a first inorganic layer and a second inorganic layer; and The organic layer is located between the first inorganic layer and the second inorganic layer.

5. The display device according to claim 4, wherein: The touch line is located on the encapsulation layer overlapping the peripheral area, and The touch electrode is located on the encapsulation layer overlapping the display area.

6. The display device according to claim 5, wherein: A first side of the encapsulation layer on which the touch line is disposed and a second side of the encapsulation layer on which the touch electrode is disposed have a step difference.

7. The display device according to claim 4, wherein: The organic layer is disposed in the valley.

8. The display device according to claim 4, further comprising a dam provided in the peripheral area, in, A distance from the dam to an edge of the display area is greater than a distance from an edge of the organic layer to the edge of the display area.

9. The display device according to claim 1, wherein: The transistor further comprises: A semiconductor layer, located on the substrate; a gate electrode stacked with the semiconductor layer; and A source electrode and a drain electrode connected to the semiconductor layer, Wherein, the display device further includes a first connecting member, which is located on the drain electrode and connects the pixel electrode and the drain electrode.

10. The display device according to claim 9, wherein: The organic insulating layer comprises: a first organic insulating layer located between the source electrode and the first connecting member and between the drain electrode and the first connecting member; and a second organic insulating layer, located between the first connecting member and the pixel electrode, Wherein, a first region overlapping the display region and a second region overlapping the peripheral region of at least one of the first organic insulating layer and the second organic insulating layer have a thickness difference.

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