Method for forming a light-emitting element pattern and display device

Abstract

A method for forming a light-emitting element pattern and a display device are provided. The method for forming a light-emitting element pattern according to an embodiment of the inventive concept includes: forming a pattern layer having an opening on a target material; forming a light-emitting element pattern on the target material corresponding to the opening; and removing the pattern layer. Here, the pattern layer includes a first pattern layer disposed on the target material, a second pattern layer disposed on the first pattern layer, and a third pattern layer disposed on the second pattern layer. The second pattern layer has an undercut portion recessed from an edge of the third pattern layer.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2018-0142743, filed on Nov. 19, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a method for forming a light-emitting element pattern and a display device using the light-emitting element pattern. More particularly, the present disclosure relates to a method for forming a light-emitting element pattern with improved process reliability and a display device using the light-emitting element pattern. Background Art

[0003] When manufacturing a display device, at least a part of a layer or a pattern of the display device may be formed by using a photolithography process. The photolithography process may include an exposure process, a development process, and an etching process. Specifically, the photolithography process may be used to form a light-emitting layer.

[0004] A photoresist pattern for forming a light-emitting layer is formed, and then a light-emitting layer is formed on a corresponding pixel region by using the photoresist pattern, and then the photoresist pattern is removed by a lift-off process. However, since the lift-off process is performed while being exposed to the atmosphere, a protective layer for protecting the light-emitting layer from oxygen and moisture in the atmosphere is necessary. Summary of the Invention

[0005] The present disclosure provides a method for forming a light-emitting element pattern and a display device using the light-emitting element pattern, the method improving process reliability.

[0006] Embodiments of the inventive concept provide a method for forming a light-emitting element pattern, the method including the steps of: forming a pattern layer having an opening on a target material; forming a light-emitting element pattern on the target material corresponding to the opening; and removing the pattern layer. The pattern layer includes: a first pattern layer disposed on the target material; a second pattern layer disposed on the first pattern layer; and a third pattern layer disposed on the second pattern layer. The second pattern layer has an undercut portion recessed from an edge of the third pattern layer to define an internal opening between the first pattern layer and the third pattern layer.

[0007] In an embodiment, the step of forming the pattern layer may include: forming a first layer on the target material;

[0008] forming a second layer on the first layer; forming a third layer on the second layer; forming the third pattern layer by patterning the third layer; forming the second pattern layer by patterning the second layer; and forming the first pattern layer by patterning the first layer.

[0009] In an embodiment, the step of forming the third pattern layer may include: exposing the third layer; and forming the third pattern layer having a first opening corresponding to the opening by developing the exposed portion of the third layer.

[0010] In an embodiment, the step of forming the second pattern layer may include forming the second pattern layer having an internal opening by etching the second layer using the third pattern layer as a mask.

[0011] In an embodiment, the second layer may be etched using an isotropic etching method.

[0012] In an embodiment, the step of forming the first pattern layer may include etching the first layer using the third pattern layer as a mask.

[0013] In an embodiment, the first layer may be etched using an anisotropic etching method.

[0014] In an embodiment, the step of forming the pattern layer may include: forming a first layer on a target material; forming a second layer on the first layer; forming a third layer on the second layer; forming the third pattern layer by patterning the third layer; forming a preliminary pattern layer by patterning the second layer; forming the first pattern layer by patterning the first layer; and forming the second pattern layer by etching the preliminary pattern layer.

[0015] In an embodiment, the step of forming the third pattern layer may include: exposing the third layer; and forming the third pattern layer having a first opening corresponding to the opening by developing the exposed portion of the third layer.

[0016] In an embodiment, the step of forming the preliminary pattern layer may include forming the preliminary pattern layer by etching the second layer using the third pattern layer as a mask.

[0017] In an embodiment, the second layer may be etched using an anisotropic etching method.

[0018] In an embodiment, the step of forming the first pattern layer may include etching the first layer using the third pattern layer and the preliminary pattern layer as masks.

[0019] In an embodiment, the first layer may be etched using an anisotropic etching method.

[0020] In an embodiment, the second pattern layer having an internal opening may be formed by etching the preliminary pattern layer using an isotropic etching method.

[0021] In an embodiment, the second pattern layer may include a metal material or an inorganic material.

[0022] In an embodiment, the second pattern layer may have a thickness of several hundred to several thousand angstroms.

[0023] In an embodiment, the target material may include: a substrate layer; and a pixel defining pattern configured to define a pixel region on the substrate layer.

[0024] In an embodiment, the light emitting element pattern may include: a light emitting layer; an electrode layer disposed on the light emitting layer; and a protective layer configured to cover the electrode layer.

[0025] In an embodiment, the protective layer may include an inorganic material.

[0026] In an embodiment, a method for forming a light emitting element pattern includes: forming a first pattern layer having an opening on a target material; forming a light emitting element pattern layer on the target material and in a region corresponding to the opening, and forming a dummy pattern layer on the target material configured to cover a top surface of the first pattern layer; forming a preliminary protective layer configured to cover the dummy pattern layer, sidewalls of the first pattern layer, and the light emitting element pattern layer; forming a second pattern layer on the preliminary protective layer in the region corresponding to the opening; forming a protective layer by removing the dummy pattern layer and the preliminary protective layer on the dummy pattern layer using the second pattern layer as a mask; and removing the first pattern layer and the second pattern layer.

[0027] In an embodiment, the step of forming the first pattern layer may include: forming a first layer on the target material; forming a second layer on the first layer; forming a second sub-pattern layer by patterning the second layer; and forming a first sub-pattern layer by patterning the first layer.

[0028] In an embodiment, the step of removing the first pattern layer and the second pattern layer may include: removing the second pattern layer and the second sub-pattern layer by a lift-off process; and removing the first sub-pattern layer by a developing process or an etching process.

[0029] In an embodiment, the step of forming the light emitting element pattern layer and the dummy pattern layer may include: forming a light emitting layer on the target material; and forming an electrode layer on the light emitting layer.

[0030] In an embodiment, the protective layer may include: a covering portion configured to cover the electrode layer; a protruding portion extending from the covering portion and protruding in a thickness direction of the covering portion; and an extending portion extending parallel to the covering portion from the protruding portion.

[0031] In an embodiment, the target material may include: a substrate layer; and a pixel defining pattern configured to define a pixel region on the substrate layer.

[0032] In an embodiment, a display device includes: a substrate layer; a pixel defining pattern configured to define pixel regions and disposed on the substrate layer; and a light-emitting element pattern disposed on each of the pixel regions. The light-emitting element pattern includes: a light-emitting layer; an electrode layer disposed on the light-emitting layer; and a protective layer configured to cover the electrode layer. The protective layer includes: a covering portion disposed to overlap with the electrode layer; and a protruding portion extending from the covering portion and protruding in a thickness direction of the covering portion.

[0033] The protective layer may further include an extending portion connected to an end of the protruding portion and extending substantially parallel to the substrate layer.

[0034] The extending portion may extend toward the electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0036] Figure 1 is a perspective view showing a display device according to an embodiment of the inventive concept;

[0037] Figure 2 is a cross-sectional view showing a display device according to an embodiment of the inventive concept;

[0038] Figure 3 shows Figure 2 a plan view of a display panel in

[0039] Figure 4 shows Figure 3 an equivalent circuit diagram of a pixel in

[0040] Figure 5 shows Figure 3 a cross-sectional view of a partial structure of a display panel in

[0041] Figure 6 is a flowchart showing a process of forming a light-emitting element pattern according to an embodiment of the inventive concept;

[0042] Figure 7A , Figure 7B and Figure 7C show Figure 6 process diagrams of a process of forming a light-emitting element pattern in

[0043] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8Fis a process diagram showing a process of forming a Figure 7A pattern layer in accordance with an embodiment;

[0044] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E and Figure 9F is a process diagram showing a process of forming a pattern layer in accordance with another embodiment;

[0045] Figure 10 is a cross-sectional view showing a partial structure of a display panel in accordance with another embodiment of the inventive concept; and

[0046] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H and Figure 11I is a process diagram showing a process of forming a Figure 10 light-emitting element pattern in accordance with an embodiment. DETAILED DESCRIPTION

[0047] In this specification, it will be understood that when a component (or region, layer, part) is referred to as being "on" another component, "connected to" or "coupled to" another component, it may be directly disposed on the other component, directly connected / coupled to the other component, or there may also be an intervening third component.

[0048] Like reference numerals denote like elements throughout. Further, in the drawings, for clarity of illustration, the thickness, ratios, and dimensions of components are exaggerated.

[0049] The term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0050] It will also be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. The terms are only used to distinguish one component from other components. For example, in one embodiment, a first element referred to as the first element may be referred to as the second element in another embodiment without departing from the scope of the claims. Unless otherwise stated, terms in the singular form may include the plural form.

[0051] In addition, terms such as "under", "below", "above", and "on" are used to explain the relational association of components shown in the drawings. The terms may be relative concepts and are described based on the directions shown in the drawings.

[0052] The meaning of "comprising" or "including" indicates a property, a fixed quantity, steps, operations, elements, components, or a combination thereof, but does not exclude other properties, fixed quantities, steps, operations, elements, components, or a combination thereof.

[0053] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view showing a display device according to an embodiment of the inventive concept.

[0055] Referring to Figure 1 , a display area DA and a non-display area NDA may be defined on the display device DD. The display area DA on which an image IM is displayed is parallel to a plane defined by a first direction axis DR1 and a second direction axis DR2. The normal direction of the display area DA (i.e., the thickness direction of the display device DD) is indicated by a third direction axis DR3. The front surface (or top surface) and the rear surface (or bottom surface) of each component are distinguished by the third direction axis DR3. However, the directions indicated by the first to third direction axes DR1, DR2, and DR3 may be relative concepts, and thus may be changed with respect to each other. Hereinafter, the first to third directions may be the directions indicated by the first to third direction axes DR1, DR2, and DR3, and may be represented by the same reference numerals, respectively.

[0056] The display device DD may be used for large electronic devices such as televisions, monitors, or outdoor billboards, and medium and small electronic devices such as personal computers, laptop computers, personal digital terminals, vehicle navigation units, game consoles, portable electronic devices, and cameras. The above devices are merely exemplified as exemplary embodiments, and thus, unless departing from the spirit and scope of the invention, the display device DD may be used for other electronic devices.

[0057] The non-display area NDA is an area adjacent to the display area DA and on which the image IM is not displayed. The non-display area NDA may define a border area of the display device DD.

[0058] The non-display area NDA may surround the display area DA. However, the embodiments of the inventive concept are not limited thereto. For example, the non-display area NDA may be adjacent to only a part of the edge of the display area DA.

[0059] Figure 2 is a cross-sectional view showing the display device DD according to an embodiment of the inventive concept.

[0060] Referring to Figure 2 , the display device DD may include a display panel DP and a sensor SU.

[0061] The display panel DP may include a substrate layer BL, a circuit layer ML, a light-emitting element layer EL, and a thin-film encapsulation layer TFE. Although the organic light-emitting display panel is described as an example of the display panel DP in this specification, embodiments of the inventive concept are not limited thereto.

[0062] The substrate layer BL may be a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0063] The circuit layer ML may be disposed on the substrate layer BL. The circuit layer ML may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer.

[0064] The light-emitting element layer EL may be disposed on the circuit layer ML. The light-emitting element layer EL may include, for example, an organic light-emitting diode. However, embodiments of the inventive concept are not limited thereto. For example, depending on the type of the display panel DP, the light-emitting element layer EL may include an inorganic light-emitting diode or an organic-inorganic hybrid light-emitting diode.

[0065] The thin-film encapsulation layer TFE seals the light-emitting element layer EL. The thin-film encapsulation layer TFE may include a plurality of inorganic layers and at least one organic layer disposed between the plurality of inorganic layers. In addition, the thin-film encapsulation layer TFE may further include a buffer layer. The buffer layer may be the layer disposed closest to the sensor SU. The buffer layer may be an inorganic layer or an organic layer.

[0066] The sensor SU may include a circuit for detecting a touch. Touch detection methods of the sensor SU include a resistive layer method, an optical method, a capacitive method, and an ultrasonic method. However, embodiments of the inventive concept are not limited thereto. Among the above methods, when the sensor SU employs the capacitive method, the sensor SU may detect whether a touch is generated by using the capacitance that changes when a touch generation unit touches the screen of the display device DD. The capacitive method may be classified into a mutual capacitance method and a self-capacitance method.

[0067] The sensor SU may be directly disposed on the display panel DP. The expression "directly disposed" means that the sensor SU is directly formed on the display panel DP without using a separate bonding member. However, embodiments of the inventive concept are not limited thereto. For example, the display panel DP and the sensor SU may be bonded to each other by using a bonding member (not shown). In addition, in another embodiment of the inventive concept, the sensor SU may be omitted.

[0068] Figure 3 is a plan view of the display panel in Figure 2 and Figure 4 is an equivalent circuit diagram of the pixel in Figure 3 .

[0069] Referring to Figure 3The display panel DP includes a base layer BL, a plurality of signal lines SGL and a plurality of pixels PX. In the embodiment, for ease of description, a signal circuit diagram of one pixel PX is simply shown.

[0070] The base layer BL includes a display area DA and a non-display area NDA in a plan view. In an embodiment, a rear surface of the base layer BL may be provided as a rear surface of the display panel DP.

[0071] The display area DA may be a region on which an image IM (see Figure 1 ) area. The display panel DP activates the display area DA according to the electrical signal. The image IM is displayed on the activated display area DA.

[0072] Electronic components or various signal lines SGL that supply electrical signals to the display area DA may be disposed on the non-display area NDA. The non-display area NDA cannot be seen from the outside.

[0073] A plurality of signal lines SGL and pixels PX are disposed on the base layer BL. The signal lines SGL may include gate lines GL, data lines DL, and power lines PL. The gate lines GL, data lines DL, and power lines PL may transmit different electrical signals from each other.

[0074] The gate line GL extends in the second direction DR2. The gate line GL may be provided in plurality and spaced apart from each other in the first direction DR1.

[0075] The display panel DP may further include a drive circuit GDC disposed on the base layer BL to provide an electrical signal to the gate line GL. The drive circuit GDC may include a plurality of thin film transistors manufactured by the same process as that of the drive circuit of the pixel PX (e.g., a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process). The signal line SGL may further include a control signal line CSL for providing a control signal to the drive circuit GDC.

[0076] The data line DL extends in the first direction DR1. The data line DL may be electrically insulated from the gate line GL. The data line DL may be disposed in plurality and spaced apart from each other in the second direction DR2.

[0077] The power line PL extends in the first direction DR1. The power line PL may be electrically insulated from the gate line GL and the data line DL. Although the power line PL may be provided in a plurality of lines spaced apart from each other in the second direction DR2, a single power line PL is exemplarily shown for ease of description. Each of the power lines PL may provide a power signal to the pixel PX.

[0078] Pixels PX are set on a display area DA. Although a plurality of pixels PX may be set to be respectively connected to signal lines SGL, for ease of description, a single pixel PX is exemplarily shown. The pixel PX displays an image IM by controlling the amount of light according to an electrical signal.

[0079] Referring Figure 4 , each of the pixels PX may include a first thin-film transistor T1, a second thin-film transistor T2, a capacitor Ccp, and a light-emitting element EC. The first thin-film transistor T1, the second thin-film transistor T2, the capacitor Ccp, and the light-emitting element EC are electrically connected to each other.

[0080] The first thin-film transistor T1 may be a switching element for controlling the conduction and cutoff of the pixel PX. The first thin-film transistor T1 is connected to a gate line GL and a data line DL. The first thin-film transistor T1 is turned on by a gate signal provided via the gate line GL, and provides a data signal provided through the data line DL to the capacitor Ccp.

[0081] The capacitor Ccp is charged with a voltage corresponding to the potential difference between a first power signal ELVDD provided from a power supply line PL and the signal provided from the first thin-film transistor T1. The second thin-film transistor T2 provides the first power signal ELVDD to the light-emitting element EC. The first power signal ELVDD is provided from the power supply line PL and corresponds to the voltage charged in the capacitor Ccp.

[0082] The light-emitting element EC may emit light or control the amount of light according to an electrical signal. For example, the light-emitting element EC may include an organic light-emitting element, a quantum dot light-emitting element, an electrophoretic element, or an electro-wetting element.

[0083] The light-emitting element EC is connected to a power terminal to receive a second power signal ELVSS different from the first power signal ELVDD provided from the power supply line PL. When a driving current corresponding to the difference between the second power signal ELVSS and the electrical signal provided from the second thin-film transistor T2 flows in the light-emitting element EC, the light-emitting element EC may generate light corresponding to the driving current.

[0084] However, embodiments of the inventive concept are not limited thereto. For example, the pixel PX may include electronic elements having various structures and arrays.

[0085] Referring Figure 3 , a circuit board FCB is connected to one side of a display panel DP. The circuit board FCB provides an electrical signal to the display panel DP. The circuit board FCB may generate a signal for controlling the image IM or a power signal, and provide the generated signal to the display panel DP. The circuit board FCB may be a flexible circuit board. A driving element (not shown) may be mounted on the circuit board FCB.

[0086] The printed circuit board FCB is electrically and physically bonded to the display panel DP through a bonding member (e.g., an anisotropic conductive film). The printed circuit board FCB may include signal lines (not shown). The printed circuit board FCB may be bonded to the display panel DP and then bent toward the rear surface of the base layer BL.

[0087] Figure 5 is a cross-sectional view showing Figure 3 a partial structure of the display panel in

[0088] Referring to Figure 3 and Figure 5 , the display panel DP may include a base layer BL, a circuit layer ML, a light-emitting element layer EL, and a thin-film encapsulation layer TFE.

[0089] The circuit layer ML may include transistors TR, a buffer layer BFL, and a plurality of insulating layers L1, L2, L3, and L4.

[0090] The buffer layer BFL may be disposed on the base layer BL, and the transistor TR may be disposed on the buffer layer BFL. Figure 5 The transistor TR in Figure 4 may be the second thin-film transistor T2 in . The transistor TR may include a semiconductor layer ACL, a control electrode GED, a first electrode ED1, and a second electrode ED2.

[0091] The semiconductor layer ACL may be disposed on the buffer layer BFL that provides a reformed surface to the semiconductor layer ACL. In this case, the adhesion force of the semiconductor layer ACL to the buffer layer BFL may be greater than the adhesion force of the semiconductor layer ACL to the base layer BL. In addition, the buffer layer BFL may be a barrier layer for protecting the bottom surface of the semiconductor layer ACL. In this case, the buffer layer BFL may block contaminants or moisture generated from or introduced through the base layer BL from being introduced into the semiconductor layer ACL. In addition, the buffer layer BFL may be a light-blocking layer for blocking external light incident through the base layer BL from being incident on the semiconductor layer ACL. In this case, the buffer layer BFL may further include a light-blocking material.

[0092] The semiconductor layer ACL may include amorphous silicon or polycrystalline silicon. In addition, the semiconductor layer ACL may include a metal oxide semiconductor. The semiconductor layer ACL may include a channel region, a first ion-doped region, and a second ion-doped region. The channel region serves as a channel through which electrons or holes can move, and the first ion-doped region and the second ion-doped region are arranged such that the channel region is disposed between the first ion-doped region and the second ion-doped region.

[0093] The first insulating layer L1 may be disposed on the buffer layer BFL and cover the semiconductor layer ACL. The first insulating layer L1 may include an inorganic material. The inorganic material may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0094] The control electrode GED may be disposed on the first insulating layer L1. The second insulating layer L2 may be disposed on the first insulating layer L1 and cover the control electrode GED. The second insulating layer L2 may include an inorganic material.

[0095] The third insulating layer L3 may be disposed on the second insulating layer L2. The third insulating layer L3 may be a planarization layer providing a planarized surface and may include an inorganic layer. The first electrode ED1 and the second electrode ED2 may be disposed on the third insulating layer L3. Each of the first electrode ED1 and the second electrode ED2 may be connected to the semiconductor layer ACL through a via hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3.

[0096] The fourth insulating layer L4 may be disposed on the third insulating layer L3 and cover the first electrode ED1 and the second electrode ED2. The fourth insulating layer L4 may include a single layer or multiple layers. For example, the single layer may include an organic layer. The multiple layers may be provided by laminating an organic layer and an inorganic layer. The fourth insulating layer L4 may be a planarization layer providing a planarized surface.

[0097] The light-emitting element layer EL may be disposed on the fourth insulating layer L4. The light-emitting element layer EL includes a pixel defining pattern PDL, a plurality of first electrode layers E1, and a plurality of light-emitting element patterns EDP. The pixel defining pattern PDL defines a plurality of pixel regions PXA on the substrate layer BL, and the first electrode layers E1 are disposed corresponding to the plurality of pixel regions PXA respectively. The light-emitting element patterns EDP are disposed on the plurality of first electrode layers E1 respectively.

[0098] The first electrode layer E1 may be disposed on the fourth insulating layer L4 and be electrically connected to the corresponding second electrode ED2 through a via hole passing through the fourth insulating layer L4.

[0099] The pixel defining pattern PDL may be disposed on the circuit layer ML to define the pixel regions PXA. The pixel defining pattern PDL may be disposed on the fourth insulating layer L4 while covering at least a part of the first electrode layer E1. A part of the first electrode layer E1 may not be covered by the pixel defining pattern PDL, and the part may correspond to the pixel regions PXA. Therefore, the pixel defining pattern PDL may also be referred to as a pixel defining layer.

[0100] The light-emitting element pattern EDP may include a light-emitting layer EM, a second electrode layer E2, and a protective layer PVL. The light-emitting layer EM may be disposed between the first electrode layer E1 and the second electrode layer E2. The light-emitting layer EM may have a single-layer structure made of a single material, a single-layer structure made of different materials from each other, or a multi-layer structure including a plurality of layers made of different materials from each other.

[0101] The light-emitting layer EM may include an organic material. The organic material may include commonly used light-emitting materials. However, embodiments of the inventive concept are not limited thereto. For example, the light-emitting layer EM may be made of at least one of materials that emit red, green, or blue light respectively, and include a fluorescent material or a phosphorescent material.

[0102] The second electrode layer E2 may be disposed on the light-emitting layer EM. The second electrode layer E2 may receive a second power supply signal ELVSS (refer to Figure 4 ).

[0103] The protective layer PVL may be disposed on the second electrode layer E2. The protective layer PVL may have a portion that contacts the top surface of the pixel definition pattern PDL. In a plan view, the protective layer PVL may at least overlap with an edge portion of the pixel definition pattern PDL. The protective layer PVL may protect the light-emitting layer EM from moisture and oxygen. The protective layer PVL may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The protective layer PVL may completely cover the top surface and side surface of the second electrode layer E2.

[0104] In an embodiment of the inventive concept, the protective layer PVL may include a covering portion CP and a protruding portion PP. The covering portion CP may cover the second electrode layer E2, and the protruding portion PP may extend from an end of the covering portion CP.

[0105] The covering portion CP overlaps with the second electrode layer E2. The covering portion CP may also cover a part of the pixel definition pattern PDL.

[0106] The protruding portion PP protrudes in the thickness direction of the covering portion CP (i.e., the third direction DR3). The protruding portion PP may have a structure perpendicular to the top surface of the pixel definition pattern PDL or inclined at a predetermined angle with respect to the top surface of the pixel definition pattern PDL.

[0107] The thin film encapsulation layer TFE is disposed on the protective layer PVL and the pixel definition pattern PDL. The thin film encapsulation layer TFE may directly cover the pixel definition pattern PDL and the light-emitting element pattern EDP. In another embodiment of the inventive concept, a covering layer covering the light-emitting element layer EL may be further disposed between the thin film encapsulation layer TFE and the light-emitting element layer EL. In this case, the thin film encapsulation layer TFE may directly cover the covering layer.

[0108] The thin film encapsulation layer TFE may include an organic layer ECL1 and an inorganic layer ECL2 which are sequentially stacked. The organic layer ECL1 may be formed by depositing, printing, or coating an organic material. The inorganic layer ECL2 may be formed by depositing an inorganic material.

[0109] The organic layer ECL1 protects the light-emitting element pattern EDP from foreign substances such as dust particles. The organic layer ECL1 may include a polymer, for example, an acrylic organic layer. However, embodiments of the inventive concept are not limited thereto. Specifically, the organic layer ECL1 may provide a planarized surface by covering the entire covering portion CP and the protruding portion PP of the protective layer PVL.

[0110] The inorganic layer ECL2 may block the introduction of moisture and oxygen therethrough, and includes at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The inorganic layer ECL2 may be made of the same material as the material of the protective layer PVL.

[0111] Although in Figure 5 the thin film encapsulation layer TFE includes one inorganic layer and one organic layer, embodiments of the inventive concept are not limited thereto. For example, the thin film encapsulation layer TFE may include two or more inorganic layers and two or more organic layers. In this case, the thin film encapsulation layer TFE may have a structure in which the inorganic layer and the organic layer are alternately stacked.

[0112] Figure 6 is a flowchart showing a process of forming a light-emitting element pattern according to an embodiment of the inventive concept, Figures 7A to 7C is a process diagram showing Figure 6 the process of forming the light-emitting element pattern in

[0113] Referring to Figure 6 and Figure 7A , in the process of forming a light-emitting element pattern according to an embodiment of the inventive concept, in step S110, a pattern layer PTL having an opening OP is formed on a target material TM.

[0114] Here, the target material TM may include a substrate layer BL and a pixel definition pattern PDL that defines pixel regions PXA1, PXA2, and PXA3 on the substrate layer BL. The target material TM may further include a circuit layer ML disposed between the substrate layer BL and the pixel definition pattern PDL. The target material TM may further include first electrode layers E1-1, E1-2, and E1-3. Figure 5 The first electrode layer E1 in

[0115] In an embodiment of the inventive concept, a pixel region PXA may include a first pixel region to a third pixel region PXA1, PXA2, and PXA3. The first pixel region to the third pixel region PXA1, PXA2, and PXA3 are defined by a pixel defining pattern PDL. Here, first electrode layers E1-1, E1-2, and E1-3 may include a first pixel electrode E1-1 disposed on the first pixel region PXA1, a second pixel electrode E1-2 disposed on the second pixel region PXA2, and a third pixel electrode E1-3 disposed on the third pixel region PXA3.

[0116] Referring to Figure 6 and Figure 7B , a light-emitting element pattern EDP may include a first light-emitting element pattern to a third light-emitting element pattern respectively disposed on the first pixel region PXA1 to the third pixel region PXA3. The first light-emitting element pattern is disposed on the first pixel electrode E1-1 in the first pixel region PXA1, the second light-emitting element pattern is disposed on the second pixel electrode E1-2 in the second pixel region PXA2, and the third light-emitting element pattern is disposed on the third pixel electrode E1-3 in the third pixel region PXA3.

[0117] Although not shown in the drawings, a light-emitting layer EM (referring to Figure 5 ) of the first light-emitting element pattern may be a red light-emitting layer, a light-emitting layer EM of the second light-emitting element pattern may be a green light-emitting layer, and a light-emitting layer EM of the third light-emitting element pattern may be a blue light-emitting layer. Except for the color of the light-emitting layer EM, the first light-emitting element pattern to the third light-emitting element pattern have the same structure. Accordingly, hereinafter, a process of forming the second light-emitting element pattern on the second pixel region PXA2 will be representatively described, and processes of forming the remaining light-emitting element patterns will be omitted.

[0118] For convenience of description, light-emitting element patterns disposed on the first pixel region to the third pixel region PXA1, PXA2, and PXA3 are respectively referred to as a first light-emitting element pattern to a third light-emitting element pattern. However, hereinafter, when a process of forming the second light-emitting element pattern is representatively described, the first light-emitting element pattern to the third light-emitting element pattern are not distinguished, and the first light-emitting element pattern to the third light-emitting element pattern are described as a light-emitting element pattern EDP.

[0119] Referring again to Figure 6 and Figure 7A, the pattern layer PTL may include a first pattern layer PTL1, a second pattern layer PTL2, and a third pattern layer PTL3. The first pattern layer PTL1 is disposed on the target material TM, the second pattern layer PTL2 is disposed on the first pattern layer PTL1, and the third pattern layer PTL3 is disposed on the second pattern layer PTL2. An opening OP for exposing the second pixel electrode E1-2 in the second pixel region PXA2 is defined in the pattern layer PTL.

[0120] The second pattern layer PTL2 may have an undercut portion where the sidewall of the second pattern layer PTL2 is recessed from the sidewall of the third pattern layer PTL3. In addition, the first pattern layer PTL1 may have an undercut portion where the sidewall of the first pattern layer PTL1 is recessed from the sidewall of the third pattern layer PTL3. The sidewall of the first pattern layer PTL1 defining the opening OP may be disposed inside the sidewall of the third pattern layer PTL3 defining the opening OP.

[0121] An internal opening IOP, which is part of the opening OP and further recessed from the sidewalls of the first pattern layer PTL1 and the third pattern layer PTL3, may be disposed in the second pattern layer PTL2 between the first pattern layer PTL1 and the third pattern layer PTL3. That is, the sidewall of the second pattern layer PTL2 may be further recessed than the sidewalls of the first pattern layer PTL1 and the third pattern layer PTL3. Thus, the internal opening IOP may be defined as the region where the second pattern layer PTL2 is removed between the first pattern layer PTL1 and the third pattern layer PTL3.

[0122] In step S120, a light-emitting element pattern EDP is disposed on the target material TM corresponding to the opening OP. As Figure 7B shown, the light-emitting element pattern EDP is formed on the second pixel electrode E1-2 exposed by the opening OP, and a dummy element layer D_EDP is formed on the pattern layer PTL.

[0123] The light-emitting element pattern EDP may include a light-emitting layer EM, a second electrode layer E2, and a protective layer PVL. The light-emitting layer EM may be disposed on the second pixel electrode E1-2. That is, the light-emitting layer EM in each pixel region is disposed on the corresponding pixel electrode exposed through the opening OP of the first electrode layer E1.

[0124] The second electrode layer E2 is disposed on the light-emitting layer EM. That is, the light-emitting layer EM may be disposed between the second pixel electrode E1-2 and the second electrode layer E2.

[0125] The protective layer PVL covers the second electrode layer E2. The protective layer PVL can protect the light-emitting layer EM from moisture and oxygen. The protective layer PVL can include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The protective layer PVL can be made of a material with high step coverage for protecting the light-emitting layer EM.

[0126] The covering portion CP of the protective layer PVL covers the second electrode layer E2. The covering portion CP can overlap with a part of the pixel defining pattern PDL to further cover the said part of the pixel defining pattern PDL. The protruding portion PP of the protective layer PVL can cover the sidewalls of the first pattern layer PTL1. The sidewalls of the first pattern layer PTL1 can be disposed adjacent to the opening OP. The protruding portion PP can at least partially cover the sidewalls of the first pattern layer PTL1.

[0127] The dummy element layer D_EDP disposed on the pattern layer PTL can include a dummy light-emitting layer D_EM, a dummy electrode layer D_E2, and a dummy protective layer D_PVL. The dummy light-emitting layer D_EM, the dummy electrode layer D_E2, and the dummy protective layer D_PVL are sequentially stacked in the third direction DR3.

[0128] The dummy light-emitting layer D_EM is separated from the light-emitting layer EM, and the dummy electrode layer D_E2 is separated from the second electrode layer E2. Due to the undercut provided between the first pattern layer PTL1 and the third pattern layer PTL3, the dummy light-emitting layer D_EM and the dummy electrode layer D_E2 can be separated from the light-emitting layer EM and the second electrode layer E2, respectively.

[0129] The dummy protective layer D_PVL is provided to cover the dummy electrode layer D_E2. The dummy protective layer D_PVL can be made of a material with high step coverage to cover a part of the dummy light-emitting layer D_EM and a part of the dummy electrode layer D_E2, and cover a part of the bottom surface of the third pattern layer PTL3 adjacent to the sidewalls of the third pattern layer PTL3, wherein the said part of the dummy light-emitting layer D_EM and the said part of the dummy electrode layer D_E2 are formed to cover the sidewalls of the third pattern layer PTL3.

[0130] The dummy protective layer D_PVL and the protective layer PVL are formed by one process. However, due to the internal opening IOP defined between the first pattern layer PTL1 and the third pattern layer PTL3, the dummy protective layer D_PVL and the protective layer PVL are separated from each other.

[0131] Refer to Figure 6 and Figure 7C, The process of forming a light-emitting element pattern according to an embodiment of the inventive concept may include a step S130 of removing a pattern layer PTL. The removing process may be a lift-off process. When forming a light-emitting element pattern EDP on a second pixel region PXA2, a pattern layer PTL is provided for a first pixel region PXA1 and a third pixel region PXA3. In step S130, when removing the pattern layer PTL provided on the first pixel region PXA1 and the third pixel region PXA3, a light-emitting element pattern EDP may be formed on the second pixel region PXA2. When removing the pattern layer PTL, a dummy element layer D_EDP formed on the pattern layer PTL is removed together. Therefore, through the above process, a light-emitting element pattern EDP may be formed on the second pixel region PXA2.

[0132] According to the above process, since a material having high step coverage is used for the protective layer PVL, the protection performance for the light-emitting layer EM can be improved. In addition, although a material having high step coverage is used for the protective layer PVL, due to an internal opening IOP, a dummy protective layer D_PVL on the pattern layer PTL and the protective layer PVL in the opening OP can be separated. Therefore, the lift-off process of the pattern layer PTL can be easily performed, and thus the reliability can be improved.

[0133] A light-emitting element pattern may be formed on other pixel regions PXA1 and PXA3 through the above process of forming a light-emitting element pattern.

[0134] Figures 8A to 8F is a process diagram showing the process of forming Figure 7A the pattern layer in

[0135] Referring to Figure 8A , a circuit layer ML is formed on a substrate layer BL. Although not shown in the drawings, the circuit layer ML may have Figure 5 the configuration in

[0136] Referring to Figure 8B , first to third pixel electrodes E1-1, E1-2, and E1-3 are formed on the circuit layer ML. Figure 5 The first electrode layer E1 in

[0137] A pixel-defining pattern PDL is formed on the circuit layer ML. The pixel-defining pattern PDL may cover at least a part of the first pixel electrode to the third pixel electrodes E1-1, E1-2, and E1-3. For example, the pixel-defining pattern PDL may cover the edges of the first pixel electrode to the third pixel electrodes E1-1, E1-2, and E1-3. The regions of the first pixel electrode to the third pixel electrodes E1-1, E1-2, and E1-3 that are exposed due to not being covered by the pixel-defining pattern PDL may be defined as the first pixel region to the third pixel regions PXA1, PXA2, and PXA3, respectively.

[0138] Therefore, the target material TM in Figure 6 and Figure 7A can be prepared. Thereafter, the process of forming the light-emitting element pattern EDP on the target material TM will be described in detail.

[0139] Referring to Figure 8C , a first layer PL1 is formed to cover the pixel-defining pattern PDL and the first pixel electrode to the third pixel electrodes E1-1, E1-2, and E1-3. The first layer PL1 may include an organic fluororesin. However, embodiments of the inventive concept are not limited to the material of the first layer PL1.

[0140] A second layer PL2 is formed on the first layer PL1. The second layer PL2 may include an inorganic material or a metal material such as a metal oxide. In embodiments of the inventive concept, the second layer PL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The second layer PL2 may have a thickness of several hundred to several thousand .

[0141] A third layer PL3 is formed on the second layer PL2. The third layer PL3 may include a photosensitive chemical material.

[0142] Referring to Figure 8D , a mask MK is disposed above the third layer PL3. The mask MK may be a binary mask including a transmission part TP and a light-blocking part BP.

[0143] The third layer PL3 may be a positive photoresist layer or a negative photoresist layer. Hereinafter, the case where the third layer PL3 is a positive photoresist layer will be described exemplarily.

[0144] The light-blocking portion BP can be superimposed on the first pixel region PXA1 and the third pixel region PXA3. The transmissive portion TP can be superimposed on the second pixel region PXA2. After arranging the mask MK above the third layer PL3, light is irradiated to perform an exposure process. Then, the portion of the third layer PL3 corresponding to the light-blocking portion BP is not exposed, and only the portion of the third layer PL3 corresponding to the transmissive portion TP is exposed.

[0145] Thereafter, as Figure 8E shown, by developing the exposed portion of the third layer PL3, a third pattern layer PTL3 having a first opening OP1 is formed in the second pixel region PXA2.

[0146] By patterning the second layer PL2 using the third pattern layer PTL3 as a mask, the Figure 8F second pattern layer PTL2 in

[0147] The second pattern layer PTL2 can have an undercut portion recessed from the edge of the third pattern layer PTL3. Therefore, due to the undercut, a preliminary internal opening P_IOP can be provided between the third pattern layer PTL3 and the first layer PL1. That is, the preliminary internal opening P_IOP can be defined as the region where the second layer PL2 between the third pattern layer PTL3 and the first layer PL1 is removed.

[0148] Thereafter, the first layer PL1 can be etched using the third pattern layer PTL3 as a mask to form the Figure 7A first pattern layer PTL1 in

[0149] Referring to Figure 7A and Figure 8F when the first layer PL1 is removed from the second pixel region PXA2, a pattern layer PTL having an opening OP can be formed in the second pixel region PXA2. An internal opening IOP formed by the preliminary internal opening P_IOP can be provided on the pattern layer PTL. The internal opening IOP can be defined as the region where the second pattern layer PTL2 between the third pattern layer PTL3 and the first pattern layer PTL1 is removed.

[0150] Figures 9A to 9F is a process diagram showing a process of forming a pattern layer according to another embodiment.

[0151] Refer to Figure 9A , on the target material TM including the pixel defining pattern PDL and the first to third pixel electrodes E1-1, E1-2, and E1-3, the first to third layers PL1, PL2, and PL3 are sequentially formed. The target material TM may have the same structure as the target material TM in Figure 8A and Figure 8B .

[0152] The first to third layers PL1 to PL3 may have the same materials and structures as the materials and structures of the first to third layers PL1, PL2, and PL3 in Figure 8C .

[0153] Refer to Figure 9B and Figure 9C , a mask MK is disposed above the third layer PL3. The third layer PL3 can be patterned by using the mask MK. The patterning process of the third layer PL3 can be a photolithography process. Since the patterning process of the third layer PL3 is similar to the patterning processes in Figure 8D and Figure 8E , the detailed description will be omitted.

[0154] After the patterning process of the third layer PL3, a third pattern layer PTL3 including a first opening OP1 is formed. When the second layer PL2 is patterned by using the third pattern layer PTL3 as a mask, a preliminary pattern layer P_PTL2 as in Figure 9D is formed. The patterning process of the second layer PL2 can be an etching process. That is, when the second layer PL2 is etched by using the third pattern layer PTL3 as a mask, the preliminary pattern layer P_PTL2 is formed. Here, the etching process of the second layer PL2 can be an anisotropic etching process.

[0155] Different from the embodiment in Figure 8F , the preliminary pattern layer P_PTL2 in Figure 9D can be formed by etching the second layer PL2 by an anisotropic etching method. Therefore, since the second layer PL2 is etched by using an anisotropic etching process, the preliminary pattern layer P_PTL2 may not have an undercut portion recessed from the edge of the third pattern layer PTL3.

[0156] Thereafter, the first pattern layer PTL1 in Figure 9E can be formed by using the preliminary pattern layer P_PTL2 and the third pattern layer PTL3 as masks. Here, the patterning process of the first layer PL1 can be an etching process. The etching process of the first layer PL1 can be an anisotropic etching process.

[0157] As described above, when removing the first layer PL1 from the second pixel region PXA2, a second opening OP2 may be formed in the second pixel region PXA2.

[0158] Thereafter, by laterally etching the preliminary pattern layer P_PTL2 using an isotropic etching process, the preliminary pattern layer P_PTL2 is etched to have an undercut between the first pattern layer PTL1 and the third pattern layer PTL3. As Figure 9F shown, a second pattern layer PTL2 including an internal opening IOP may be formed. The internal opening IOP may be defined as a region where the preliminary pattern layer P_PTL2 between the third pattern layer PTL3 and the first pattern layer PTL1 is removed.

[0159] As a result, a pattern layer PTL' according to another embodiment of the inventive concept may be completed. Since the process of forming a light-emitting element pattern using the pattern layer PTL' is similar to Figure 6 and Figures 7A to 7C the process of forming a light-emitting element pattern in

[0160] Figure 10 FIG. is a cross-sectional view showing a partial structure of a display panel according to another embodiment of the inventive concept. Figures 11A to 11I FIG. is a process diagram showing the process of forming the light-emitting element pattern in Figure 10 . Among the components in Figure 10 the components identical to those in Figure 5 will be given the same reference numerals, and detailed descriptions thereof will be omitted.

[0161] Since, except for the light-emitting element pattern EDP2 including the light-emitting element pattern EDP of the display panel DP that is structurally different from Figure 5 the display panel DP2 in Figure 10 has the same structure as the structure of the display panel DP in Figure 5 , the light-emitting element pattern EDP2 will be specifically described in Figure 10 .

[0162] Referring to Figure 10 , the light-emitting element pattern EDP2 may include a light-emitting layer EM, a second electrode layer E2, and a protective layer PVL2. The light-emitting layer EM is disposed between the first electrode layer E1 and the second electrode layer E2. The light-emitting layer EM may have a single-layer structure made of a single material, a single-layer structure made of different materials from each other, or a multi-layer structure including multiple layers made of different materials from each other.

[0163] The light-emitting layer EM may include an organic material. The organic material may include commonly used light-emitting materials. However, embodiments of the inventive concept are not limited thereto. For example, the light-emitting layer EM may be made of at least one of materials that emit red, green, or blue light respectively, and include a fluorescent material or a phosphorescent material.

[0164] The second electrode layer E2 may be disposed on the light-emitting layer EM, and the protective layer PVL2 may be disposed on the second electrode layer E2. The protective layer PVL2 may have a portion in contact with the pixel definition pattern PDL. In a plan view, the protective layer PVL2 may at least overlap with an edge portion of the pixel definition pattern PDL.

[0165] The protective layer PVL2 may include a covering portion CP, a protruding portion PP, and an extending portion EP. The covering portion CP may cover the second electrode layer E2, and the protruding portion PP may protrude from the covering portion CP in a third direction DR3. The extending portion EP extends from an end of the protruding portion PP in a second direction DR2 toward the second electrode layer E2.

[0166] The covering portion CP overlaps with the second electrode layer E2. The covering portion CP may also cover a part of the pixel definition pattern PDL.

[0167] The protruding portion PP protrudes in a thickness direction (i.e., the third direction DR3) of the covering portion CP. The protruding portion PP may have a structure perpendicular to a top surface of the pixel definition pattern PDL or inclined at a predetermined angle with respect to the top surface of the pixel definition pattern PDL.

[0168] The extending portion EP may extend from the protruding portion PP to overlap with the covering portion CP. A space between the extending portion EP and the covering portion CP may be filled with a packaging layer TFE. Specifically, an organic layer ECL1 of the packaging layer TFE may provide a planarized surface by completely covering the covering portion CP, the protruding portion PP, and the extending portion EP.

[0169] Refer to Figure 11A , a first layer SL1 covering the pixel definition pattern PDL and the first pixel electrode to the third pixel electrodes E1-1, E1-2, and E1-3 is formed on a target material TM. The first layer SL1 may include an organic fluororesin. However, embodiments of the inventive concept are not limited to the material of the first layer SL1.

[0170] A second layer SL2 is formed on the first layer SL1. The second layer SL2 may include a photosensitive chemical material.

[0171] Refer to Figure 11B, the second sub-pattern layer SPL2 having the first opening OP1 is formed by patterning the second layer SL2. The patterning process of the second layer SL2 can be a photoresist process. The patterning process of the second layer SL2 can include an exposure process and a development process. The second layer SL2 can be a positive photoresist layer or a negative photoresist layer.

[0172] After the patterning process of the second layer SL2, the second sub-pattern layer SPL2 including the first opening OP1 is formed. As Figure 11C shown, the first sub-pattern layer SPL1 is formed by patterning the first layer SL1 using the second sub-pattern layer SPL2 as a mask.

[0173] In another embodiment, the patterning process of the first layer SL1 can be a development process. That is to say, the first layer SL1 can be developed by adjusting the development time in the process of developing the second layer SL2. When the first layer SL1 is additionally developed by increasing the development time, the first layer SL1 corresponding to the first opening OP1 can be removed, and the first sub-pattern layer SPL1 is formed. In the development processes of the first layer SL1 and the second layer SL2, the same developing solution can be used. The developing solution for the development processes of the first layer SL1 and the second layer SL2 can be tetramethylammonium hydroxide (TMAH).

[0174] For another example, the patterning process of the first layer SL1 can be an etching process. That is to say, when the first layer SL1 is etched using the second sub-pattern layer SPL2 as a mask, the first sub-pattern layer SPL1 is formed. Therefore, the first pattern layer SPTL1 including the opening OP is formed on the target material TM.

[0175] As Figure 11C shown, the first sub-pattern layer SPL1 can have an undercut portion recessed from the edge of the second sub-pattern layer SPL2.

[0176] Referring to Figure 11D , the light-emitting layer EM and the second electrode layer E2 are sequentially provided on the target material TM corresponding to the opening OP of the first pattern layer SPTL1. The dummy light-emitting layer D_EM and the dummy electrode layer D_E2 are sequentially provided on the first pattern layer SPTL1. Although the light-emitting layer EM and the dummy light-emitting layer D_EM are provided on the target material TM through the same process, the light-emitting layer EM and the dummy light-emitting layer D_EM are separated by the undercut structure of the first sub-pattern layer SPL1. In addition, although the second electrode layer E2 and the dummy electrode layer D_E2 are provided on the target material through the same process, the second electrode layer E2 and the dummy electrode layer D_E2 are separated by the undercut structure of the first sub-pattern layer SPL1.

[0177] A preliminary protective layer P_PVL is provided on a target material TM to cover the second electrode layer E2 and the dummy electrode layer D_E2. The preliminary protective layer P_PVL may cover a portion of the first pattern layer SPTL1 exposed by the second electrode layer E2 and the dummy electrode layer D_E2. In an embodiment of the inventive concept, the preliminary protective layer P_PVL may partially cover sidewalls of the first sub-pattern layer SPL1 adjacent to the opening OP and a bottom surface of the second sub-pattern layer SPL2 exposed by the opening OP. The preliminary protective layer P_PVL may have an integrated structure without a disconnected portion under the second sub-pattern layer SPL2.

[0178] Referring to Figure 11E , a third layer SL3 is formed on the preliminary protective layer P_PVL. The third layer SL3 may include a photosensitive chemical material.

[0179] The second pattern layer SPTL2 in Figure 11F is formed by patterning the third layer SL3. The patterning process of the third layer SL3 may be a photoresist process. The patterning process of the third layer SL3 may include an exposure process and a development process. The third layer SL3 may be a positive photoresist layer or a negative photoresist layer.

[0180] The third layer SL3 may be a photoresist layer of a different type from the second layer SL2 in Figure 11A . For example, when the second layer SL2 is a positive photoresist layer, the third layer SL3 may be a negative photoresist layer. When the second layer SL2 and the third layer SL3 are photoresist layers of different types from each other, the second layer SL2 and the third layer SL3 may be patterned by using the same mask.

[0181] The second pattern layer SPTL2 may be formed on the preliminary protective layer P_PVL corresponding to the opening OP. In an embodiment of the inventive concept, the second pattern layer SPTL2 may partially overlap with the bottom surface of the second sub-pattern layer SPL2. Accordingly, the second pattern layer SPTL2 may be formed to cover a portion of the preliminary protective layer P_PVL disposed under the bottom surface of the second sub-pattern layer SPL2.

[0182] In another embodiment of the inventive concept, the patterning process of the third layer SL3 may include only a patterning process. A thickness t1 of the third layer SL3 disposed in the opening OP may be greater than a thickness t2 of the third layer SL3 disposed on the first pattern layer SPTL1. In this case, the process of forming the third layer SL3 may be performed. Due to the above thickness difference, even after removing the third layer SL3 on the first pattern layer SPTL1, the third layer SL3 disposed in the opening OP may be retained. The third layer SL3 retained in the opening OP may be formed as the second pattern layer SPTL2.

[0183] The second pattern layer SPTL2 may cover a part of the preliminary protective layer P_PVL intended to be retained in the opening OP, the light-emitting layer EM, and the second electrode layer E2.

[0184] Referring Figure 11F , a part of the preliminary protective layer P_PVL, the light-emitting layer EM, and the second electrode layer E2 covered by the second pattern layer SPTL2 are retained in the opening OP, and the remaining part of the preliminary protective layer P_PVL, the dummy light-emitting layer D_EM, and the dummy electrode layer D_E2 not covered by the second pattern layer SPTL2 are removed. The remaining part of the preliminary protective layer P_PVL, the dummy light-emitting layer D_EM, and the dummy electrode layer D_E2 may be removed by an etching process. Here, the etching process may be a dry etching process.

[0185] After the etching process, the dummy light-emitting layer D_EM, the dummy electrode layer D_E2, and the remaining part of the preliminary protective layer P_PVL covering the second sub-pattern layer SPL2 are removed. Then, as Figure 11G shown, the top surface of the second sub-pattern layer SPL2 can be exposed.

[0186] In addition, the light-emitting layer EM, the second electrode layer E2, and the protective layer PVL2 may be retained in the opening OP. Here, the protective layer PVL2 may include a covering portion CP, a protruding portion PP, and an extending portion EP. The covering portion CP may cover the second electrode layer E2, the protruding portion PP may protrude from the end of the covering portion CP in the third direction DR3. The extending portion EP extends from the end of the protruding portion PP in the second direction DR2. The extending portion EP may cover the top surface of the second pattern layer SPTL2, and the protruding portion PP may cover the sidewall of the second pattern layer SPTL2. The covering portion CP may be covered by the bottom surface of the second pattern layer SPTL2.

[0187] As described above, since the covering portion CP, the protruding portion PP, and the extending portion EP of the protective layer PVL2 are covered by the second pattern layer SPTL2, the covering portion CP, the protruding portion PP, and the extending portion EP of the protective layer PVL2 can be retained without being etched even after the etching process.

[0188] Thereafter, the second sub-pattern layer SPL2 and the second pattern layer SPTL2 are removed by a stripping process. Then, as Figure 11H shown, the first sub-pattern layer SPL1 is exposed on the target material TM. The first sub-pattern layer SPL1 may be removed by a developing process or an etching process. When the first sub-pattern layer SPL1 and the second sub-pattern layer SPL2 on the target material TM are removed, as Figure 11I shown, only the light-emitting element pattern EDP2 is retained.

[0189] Embodiments of the inventive concept may provide a process of forming a pattern of light-emitting elements, in which, when forming a protective layer for protecting a light-emitting layer and an electrode layer, the process can easily perform a stripping process of a photoresist pattern and improve the properties of the protective layer.

[0190] It will be apparent to those skilled in the art that various modifications and variations can be made to the inventive concept. Accordingly, the present disclosure is intended to cover modifications and variations of the present invention as long as they fall within the scope of the claims and their equivalents. Thus, to the maximum extent permitted by law, the scope of the present invention will be determined by the broadest permissible interpretation of the claims and their equivalents and should not be limited or restricted by the foregoing detailed description.

Claims

1. A method for forming a pattern of light-emitting elements, the method comprising the steps of: Forming a pattern layer having an opening on a target material; Forming a pattern of light-emitting elements on the target material corresponding to the opening; And Removing the pattern layer, wherein the pattern layer includes: a first pattern layer disposed on the target material; a second pattern layer disposed on the first pattern layer; and a third pattern layer disposed on the second pattern layer, the second pattern layer has an undercut portion recessed from an edge of the third pattern layer to define an internal opening between the first pattern layer and the third pattern layer, The step of forming the pattern of light-emitting elements on the target material includes: forming a light-emitting layer covering the target material exposed through the opening and a dummy light-emitting layer covering an upper surface of the pattern layer; forming an electrode layer covering the light-emitting layer and a dummy electrode layer covering the dummy light-emitting layer; and forming a protective layer covering the electrode layer and sidewalls of the first pattern layer adjacent to the opening and a dummy protective layer covering the dummy electrode layer, and the protective layer and the dummy protective layer are separated from each other due to the internal opening.

2. The method according to claim 1, wherein, The step of forming the pattern layer includes: Forming a first layer on the target material; Forming a second layer on the first layer; Forming a third layer on the second layer; Forming the third pattern layer by patterning the third layer; Forming the second pattern layer by patterning the second layer; and Forming the first pattern layer by patterning the first layer.

3. The method according to claim 2, wherein, The step of forming the third pattern layer includes: Exposing the third layer; and Forming the third pattern layer having a first opening corresponding to the opening by developing an exposed portion of the third layer.

4. The method according to claim 2, wherein The step of forming the second pattern layer includes forming the second pattern layer having the internal opening by etching the second layer using the third pattern layer as a mask.

5. The method according to claim 4, wherein, Etching the second layer using an isotropic etching method.

6. The method according to claim 2, wherein The step of forming the first pattern layer includes etching the first layer using the third pattern layer as a mask.

7. The method according to claim 6, wherein, Etching the first layer using an anisotropic etching method.

8. The method according to claim 1, wherein The step of forming the pattern layer includes: Forming a first layer on the target material; Forming a second layer on the first layer; Forming a third layer on the second layer; Forming the third pattern layer by patterning the third layer; Forming a preliminary pattern layer by patterning the second layer; Forming the first pattern layer by patterning the first layer; and Forming the second pattern layer by etching the preliminary pattern layer.

9. The method according to claim 8, wherein The step of forming the third pattern layer includes: Exposing the third layer; and Forming the third pattern layer having a first opening corresponding to the opening by developing an exposed portion of the third layer.

10. The method according to claim 8, wherein, The step of forming the preliminary pattern layer includes forming the preliminary pattern layer by etching the second layer using the third pattern layer as a mask.

11. The method according to claim 10, wherein, Etching the second layer using an anisotropic etching method.

12. The method according to claim 8, wherein, The forming step of the first pattern layer includes etching the first layer using the third pattern layer and the preliminary pattern layer as masks.

13. The method according to claim 12, wherein, Etch the first layer using an anisotropic etching method.

14. The method according to claim 8, wherein Form the second pattern layer in which the internal opening is provided by etching the preliminary pattern layer using an isotropic etching method.

15. A display device, the display device comprising: A substrate layer; A pixel defining pattern configured to define pixel regions and disposed on the substrate layer; And A plurality of light emitting element patterns disposed on each of the pixel regions and spaced apart from each other, wherein each of the plurality of light emitting element patterns includes: a light emitting layer; an electrode layer disposed on the light emitting layer; and a protective layer configured to cover the electrode layer, The protective layer includes: a covering portion disposed to overlap the electrode layer; and a protruding portion extending from the covering portion, protruding in the thickness direction of the covering portion and not overlapping the electrode layer in the thickness direction, The display device further includes a packaging layer disposed on the protective layer and the pixel defining pattern, the packaging layer directly contacting the pixel defining pattern and directly contacting the covering portion and the protruding portion of the protective layer.

16. The display device according to claim 15, wherein, The light emitting layer includes an organic light emitting material.

17. The display device according to claim 15, wherein, The protective layer includes an inorganic material.

18. The display device according to claim 15, wherein, The protective layer further includes an extending portion connected to an end of the protruding portion and extending parallel to the substrate layer.

19. The display device according to claim 18, wherein, The extending portion extends toward the electrode layer.

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