Integrated imaging device with improved charge storage capacity

Abstract

Embodiments of the present disclosure relate to an integrated imaging device with improved charge storage capacity. An integrated imaging device includes a pixel having a trench extending into a substrate. The trench is coated with an insulator and filled with a stack including a first polysilicon region and a second polysilicon region. The first and second polysilicon regions are separated from each other by a layer of insulating material. The first polysilicon region can form a gate electrode of a vertical transistor, and the second polysilicon region can form an electrode of a capacitor.

Description

[0001] Priority claim

[0002] This application claims priority from French patent application No. 1871689, filed on November 22, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to integrated circuits, particularly imaging integrated circuits, and more particularly to improvements in the dynamic range of imaging devices. Background Art

[0004] An imaging device typically includes a matrix array of pixels operable to convert an incident light signal into an electrical charge. In each pixel, the charge generated in a photosensitive region (typically a photodiode) is transferred to a read node that is coupled to a transfer circuit and a processing circuit, for example, the processing circuit includes an analog-to-digital converter operable to convert the charge representing the illumination of the pixel into a digital value.

[0005] The value of the illumination of a pixel can take on multiple values, depending on the dynamic range of the imaging device, ie the ability of the imaging device to distinguish between a greater or lesser number of light intensities.

[0006] The dynamic range of an imaging device can be increased by combining multiple captured images. However, image sensors that allow this approach to be implemented include specific and often complex circuits, which are detrimental to the footprint of the integrated circuit.

[0007] There is a need to obtain a high dynamic range imaging device with a small footprint. Summary of the invention

[0008] According to one embodiment, an imaging device is presented that allows for the production of high dynamic range images, wherein the pixels have a small footprint.

[0009] According to one aspect, an integrated imaging device is provided, comprising at least one pixel, the at least one pixel comprising at least one trench extending into a substrate, the at least one trench being coated with an insulator and comprising a stack of a lower first polysilicon region and at least one upper second polysilicon region, the regions being separated by a layer of the insulator.

[0010] Therefore, in the case of a pixel, producing two polysilicon areas inside the same trench is particularly advantageous, since it allows, for example, the production of two separate elements with two independent functions (e.g. a buried transmission gate and a capacitor, or indeed a peripheral isolation area and a capacitor) within the same trench with a small footprint.

[0011] Thus, more generally, such a trench may be advantageously included in any integrated circuit or device.

[0012] In particular, in this case, producing two polysilicon regions inside the same trench is particularly advantageous, since it allows, for example, producing two separate capacitive components with a small footprint.

[0013] Thus, according to another more general aspect, there is provided an integrated circuit or device comprising at least one trench extending into a substrate, the at least one trench being coated with an insulator and comprising a stack of a lower first polysilicon region and at least one upper second polysilicon region, the regions being separated by a layer of the insulator.

[0014] Whatever the intended application, the first polysilicon region produced deeper in the substrate is advantageously insulated from components produced on the front side of the substrate.

[0015] For example, in this case, as described below, when the first polysilicon region forms a transfer gate for a pixel, the transfer gate is insulated from a read node of the pixel, which is implanted at a small depth in the substrate.

[0016] In the case of an integrated imaging device, a pixel may include a capacitor having a first electrode including a second polysilicon region, a dielectric of the capacitor being formed by an insulator, and a second electrode of the capacitor being coupled to a storage region (e.g., a read node) configured to store a charge representing an illumination of the pixel, the pixel further comprising a bias circuit operable to bias the first polysilicon region and the second polysilicon region, respectively.

[0017] Coupling a capacitor to the charge storage region advantageously allows the storage capacity of the region to be increased by biasing the second polysilicon region to an appropriate value.

[0018] As a variant, the pixel may comprise a metallization connecting the second polysilicon region and the storage region.

[0019] This allows the capacity of the storage area (read node) to be increased without the need to use the aforementioned bias circuit.

[0020] The stack may be surmounted by a region of insulator.

[0021] Adjusting the ratio of polysilicon to insulator in the stack can adjust the size of the two polysilicon regions and, therefore, the capacitive effect of the capacitor.

[0022] In a first variant embodiment, the transfer gate and the capacitor of the pixel are located in the trench.

[0023] More precisely, the pixel may include: a photosensitive region; a read node, which includes the storage region; at least one transfer gate, which is operable to transfer the charge accumulated in the photosensitive region to the read node, the at least one groove defines the periphery of the read node, the first polysilicon region forms the transfer gate, the second polysilicon region forms a first electrode of a capacitor, and the read node forms a second electrode of the capacitor.

[0024] The creation of the capacitor and the transmission gate in the same trench advantageously allows the storage capacity of the read node to be increased while maintaining a small footprint.

[0025] According to another variant embodiment, the at least one trench may form a capacitive isolation trench delimiting the periphery of the pixel, the second polysilicon region forming a first electrode of the capacitor, and the second electrode of the capacitor being connected to a read node by means of a metal track.

[0026] According to another aspect, a smart mobile phone is provided comprising an imaging device as described above.

[0027] According to one aspect, a digital camera is proposed comprising an imaging device as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other advantages and features will become apparent by examining the detailed description of entirely non-limiting embodiments and the accompanying drawings, in which:

[0029] Figure 1 is a schematic representation of a pixel of one embodiment of an imaging device from an electrical perspective;

[0030] Figure 2 yes Figure 1 A top view of pixels;

[0031] Figure 3 is along Figure 2 A cross-sectional view taken along line III-III;

[0032] Figure 4 is along Figure 2 A cross-sectional view taken along section line IV-IV;

[0033] Figure 5 A variant embodiment is illustrated;

[0034] Figure 6 A variant embodiment is illustrated;

[0035] Figure 7 A variant embodiment is illustrated;

[0036] Figure 8 The diagram illustrates another aspect;

[0037] Fig. 9 illustrates another aspect; and

[0038] Fig.10 Another variation is illustrated. DETAILED DESCRIPTION

[0039] Figure 1 is a schematic representation of a pixel PX of the imaging device DIS seen from an electrical point of view.

[0040] Although the imaging device DIS comprises a matrix array of pixels, each of the pixels has the same architecture and the same mode of operation. Therefore, for simplicity, a single pixel will be described.

[0041] The pixel PX typically comprises a photosensitive region DL (here a photodiode) operable to generate charge in response to illumination of the pixel PX, a read node SN, and a transfer gate GT configured to transfer charge from the photodiode DL to the read node SN when the transfer gate GT is turned on.

[0042] The read node SN is generally operable to receive the charge generated by the photodiode DL in order to read the charge and convert the charge into a digital value representative of the illumination of the pixel PX.

[0043] The readout is performed by a source follower transistor TS (whose gate is coupled to a read node SN) and a read transistor TL, wherein transistors TS and TL are coupled in series between a supply node B1 and a processing circuit CT, the supply node B1 being operable to deliver a first voltage (e.g., a voltage of 3 volts), and the processing circuit CT being operable to perform operations on the electrical signal from the pixel PX, in particular analog-to-digital conversion.

[0044] The pixel PX also includes an initialization transistor TR (also referred to as a reset transistor) operable to initialize the potential of the read node SN to an initialization value Vi.

[0045] The pixel PX further includes a capacitor C having a first electrode coupled to the bias circuit MP and a second electrode including the read node SN.

[0046] This capacitor CS advantageously allows increasing the charge storage capacity of the read node.

[0047] In operation, during illumination of the pixel PX, charge carriers (electrons and holes) accumulate in the photosensitive area DL and the bias circuit MP biases the transfer gate GT to a first value (here, for example, −0.5 volts) and the first electrode of the capacitor C to a second value (here, for example, 3 volts). This configuration of the bias circuit MP makes it possible to prevent charge from accumulating on the read node during illumination of the pixel.

[0048] Then, the bias circuit MP biases the transfer gate GT and the first electrode of the capacitor C to a second value (here, 3 volts) so as to transfer the electrons accumulated in the light sensing area DL to the read node SN.

[0049] In order to read and process the charge accumulated on the read node, the bias circuit MP biases the gate of the read transistor TL so as to turn on the transistor TL.

[0050] Figure 2 is a top view of a pixel PX, Figure 3 is along Figure 2 The cross-sectional view along the section line III-III in FIG. Figure 4 is along Figure 2 Cross-sectional view along section line IV-IV in FIG.

[0051] The imaging device DIS is here a backside illuminated (BSI) device, i.e. the device is operable to be illuminated from the back side FR of the substrate SB. The front side FV is for its part covered by back end of line (BEOL) interconnects which are not shown in the figures for simplicity.

[0052] For simplicity, in Figures 2 to 4 Only the transmission node SN, the transmission gate GT and the light-sensing area DL are shown.

[0053] The device DIS is manufactured in a semiconductor substrate SB, here for example a silicon substrate having p-type conductivity, and the pixels PX are delimited by capacitive isolation trenches TIC extending around the entire periphery of the pixels.

[0054] A capacitive isolation trench TIC is typically a trench produced in the substrate and extending from its front side FV to a depth of about 3.5 micrometers, coated with an insulator 1 (here silicon oxide, for example) and filled with a conductor 2 (here polysilicon).

[0055] Here, the light-sensitive region DL is created by implanting n-type dopants extending from the front side to a depth of, for example, 3 micrometers.

[0056] The pixel PX also comprises an insulated vertical electrode EVI which delimits the periphery of the reading node SN, the vertical electrode EVI itself being a region doped n-type, the reading node SN being doped more strongly than the photosensitive region and extending into the substrate SB to a depth of about 0.3 micrometers.

[0057] The insulated vertical electrode EVI is a trench produced in the substrate SB and extending from its front side FV to a depth of approximately 0.8 micrometers, the trench being coated with an insulator 1 .

[0058] The vertical electrode EVI is filled with a stack of a first polysilicon region P1 and a second polysilicon region P2 , which are separated by a layer of insulator 1 .

[0059] The second polysilicon region P2 extends from the front side FV of the substrate SB to a depth of about 0.3 micrometers in the substrate SB, ie, to the same depth as the read node SN.

[0060] The first polysilicon region P1 extends below the second polysilicon region P2 to the bottom of the vertical electrode EVI, ie, here to a depth of about 0.8 micrometers.

[0061] The transfer gate GT includes a first polysilicon region P1. A first electrode of the capacitor C includes a second polysilicon region P2, and a second electrode of the capacitor includes a read node SN.

[0062] The insulated vertical electrode further includes an extension EX extending away from the read node and allowing contact with the first polysilicon region.

[0063] Therefore, the transfer gate GT is far enough away from the read node SN to avoid parasitic capacitive coupling between the transfer gate GT and the read node SN during charge transfer from the photosensitive area DL to the read node SN, and biasing the capacitor C allows the storage capacity of the read node SN to be increased via the capacitive effect.

[0064] according to Figure 5 In a variant embodiment illustrated in FIG. 1 , the capacitor C is produced in the capacitive isolation trench TIC.

[0065] Thus, the capacitive isolation trench TIC is filled with a stack of a first polysilicon region P1 and a second polysilicon region P2 , which are separated by the layer of insulator 1 .

[0066] Here too, one electrode of the capacitor C is formed by the second polysilicon region P2 , and the other electrode is formed by the substrate region SBR adjacent to the trench.

[0067] Here, an electrical connection CE is produced between the read node SN and the substrate region SBR. Figure 5 The electrical connections CE schematically shown in are produced by vias and metal tracks of BEOL structures from the interconnection region of the device DIS.

[0068] Therefore, in this embodiment, the storage node is also coupled to capacitor C.

[0069] Here, the insulated vertical electrode EVI includes a stack of a lower polysilicon region forming a transmission gate GT and an upper region of an insulator 1 extending from the front side of the substrate to a depth of approximately 0.3 microns (i.e., to a depth approximately equal to the depth of the read node SN), which can advantageously allow the distance between the transmission gate GT and the read node SN to be increased and thereby electrically isolate the gate from the node.

[0070] The vertical electrodes may also have the same Figures 1 to 4 The structures described are identical and the two embodiments are compatible.

[0071] according to Figure 6 In a variant embodiment illustrated in FIG. 1 , the stack of the first polysilicon region P1 and the second polysilicon region P2 may be covered by a layer of insulator 1, which replaces a portion of the second polysilicon region P2, so here, the second polysilicon region P2 is smaller than the second polysilicon region in other embodiments. Adjusting the size of the second electrode of the capacitor C is an advantageous means of adjusting the storage capacity of the read node SN.

[0072] like Figure 7 As shown in , the capacitive isolation trench TIC may also include more than two polysilicon regions, for example here three regions P1, P2 and P3. This advantageously allows adjusting the capacitance of the read node during operation of the device DIS by, for example, biasing only the second region P2 or indeed biasing both the second region P2 and the third region P3.

[0073] The architecture of the pixel described here corresponds to the architecture of a so-called rolling shutter imaging device. However, it is entirely possible to integrate the embodiments into any other pixel architecture, in particular into a so-called global shutter pixel architecture. For each pixel, in addition to the read node SN, an image sensor of this type also comprises a storage node which allows temporary storage of a charge representing the illumination of the pixel. In this case, the storage node will also be coupled to a capacitor similar to the capacitor C described above.

[0074] Described above and in Figures 1 to 7 The imaging device DIS illustrated in FIG. 1 can be integrated into any type of imaging system, such as Figure 8 The smart phone TPI shown in the figure, or such as Fig. 9 The APN for the digital camera shown in the figure.

[0075] The invention is not limited to the embodiment that has just been described, but covers any variants thereof.

[0076] Therefore, in order to increase the capacity of the read node SN, the biasing device MP (which can bias the first polysilicon region P1 and the second polysilicon region P2, respectively) can be removed, and a metallization (metal track) connecting the read node SN and the second polysilicon region P2 can be provided, such as Fig.10 Very schematically illustrated in FIG.

Claims

1. An integrated imaging device, comprising: At least one pixel, wherein each pixel comprises: a trench extending into the substrate; an insulator coating the groove; a stack within the trench, the stack comprising a first polysilicon region and a second polysilicon region, wherein the first polysilicon region and the second polysilicon region within the stack are insulated from each other by a layer of insulating material; and A capacitor having a first electrode formed by the second polysilicon region, a dielectric formed by the insulating material layer, and a second electrode coupled to a storage region configured to store charge representing an illumination of the pixel. 2 . The apparatus of claim 1 , further comprising a bias circuit configured to bias the first polysilicon region and the second polysilicon region, respectively. 3 . The device of claim 1 , further comprising a metallization electrically connecting the second polysilicon region and the storage region.

4. The device of claim 1 , wherein the at least one pixel further comprises: Photosensitive area; a reading node, the reading node including the storage area; and at least one transfer gate configured to transfer the charges accumulated in the photosensitive region to the read node, wherein the trench defines a periphery of the read node, and wherein the first polysilicon region forms the transfer gate.

5. The device of claim 4 , wherein the trench forms a capacitive isolation trench that delimits the periphery of the pixel, the second polysilicon region forms a first electrode of the capacitor, and the second electrode of the capacitor is connected to the read node by way of a metal track. The device of claim 1 , wherein the stack is covered by a region of insulator.

7. The device of claim 1, wherein the device is a component of a smart mobile phone.

8. The device of claim 1, wherein the device is a component of a digital camera.

9. The apparatus of claim 1, wherein the stack within the trench further comprises a third polysilicon region, wherein the third polysilicon region and the second polysilicon region within the stack are insulated from each other by an additional layer of insulating material.

10. An integrated circuit comprising: substrate; a trench extending into the substrate; an insulator coating the groove; a stack within the trench, the stack comprising a first polysilicon region and a second polysilicon region, wherein the first polysilicon region and the second polysilicon region within the stack are insulated from each other by a layer of insulating material; as well as A capacitor having a first electrode formed by the second polysilicon region, a dielectric formed by the insulating material layer, and a second electrode within the substrate. 11 . The circuit of claim 10 , further comprising a bias circuit configured to bias the first polysilicon region and the second polysilicon region, respectively.

12. The circuit of claim 10, comprising a vertical transistor, the first polysilicon region forming a gate electrode of the vertical transistor.

13. The circuit of claim 10, wherein the trench peripherally surrounds a region of the substrate.

14. The circuit of claim 10, wherein the stack is covered by a region of insulator.

15. The circuit of claim 10, wherein the circuit is a component of a smart mobile phone.

16. The circuit of claim 10, wherein the circuit is a component of a digital camera. 17 . The circuit of claim 10 , wherein the stack within the trench further comprises a third polysilicon region, wherein the third polysilicon region and the second polysilicon region within the stack are insulated from each other by an additional layer of insulating material.

18. The circuit of claim 17, comprising a capacitor having a first electrode formed by one or more of the second and third polysilicon regions, a dielectric formed by the insulating material layer, and a second electrode within the substrate.

19. The circuit of claim 10, wherein the circuit is a component of an imaging pixel.

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