Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, wherein a fin is formed in a semiconductor substrate, the fin has a horizontal fin part extending along a second direction and vertical fin parts vertically arranged on both ends of the horizontal fin part, a first groove extending along a first direction is defined between the two vertical fin parts of the fin, a second source-drain doped region is formed in the horizontal fin part, and a first source-drain doped region is formed in a top end part of the vertical fin part; and a gate is surrounded on a sidewall of the vertical fin part, so that two ring-gate transistors can be formed based on one fin, the control of the gate on the channel and the effective channel length are increased, the short channel effect is overcome, and smaller feature size and higher integration are facilitated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the semiconductor field, especially in memory, methods to increase device integration density include reducing device feature size and improving cell structure. However, as feature size decreases, small-size transistors exhibit severe short-channel effects; therefore, improving the memory cell structure to reduce the area occupied by the memory cell while maintaining the same feature size is an effective way to increase device integration density. Vertical-fin field-effect transistors with buried bit lines are gradually becoming the next 4F due to their simplified mid-row process (MOL). 2 The mainstream of the generation (F represents the minimum linewidth of lithography technology). However, at the same time, its front-end process (FEOL) is becoming increasingly complex.

[0003] Therefore, a new semiconductor device and its fabrication method are needed to reduce the area occupied by the memory cell under the same feature size conditions, simplify the process, enhance the gate's control over the channel, improve the short-channel effect, and improve the device's electrical performance and integration density. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which reduces the area occupied by the memory cell under the same feature size conditions, simplifies the process, enhances the gate's control over the channel, improves the short-channel effect, and improves the electrical performance and integration density of the device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device, comprising:

[0006] A semiconductor substrate having at least one fin, the fin having a horizontal fin portion extending along a second direction and vertical fin portions vertically disposed at two opposite ends of the horizontal fin portion, the two vertical fin portions defining a first trench extending along a first direction between them, a first source / drain doped region formed in the top portion of each vertical fin portion, and a second source / drain doped region provided in the horizontal fin portion, the second source / drain doped region extending along the second direction from a portion of the horizontal fin portion covered by one of the vertical fin portions to a portion covered by the other vertical fin portion; and...

[0007] A gate surrounds the sidewall of the vertical fin portion.

[0008] Optionally, the semiconductor substrate further has a second trench and an isolation trench for defining the region where the fin is located. The second trench extends along the second direction and exposes the sidewalls of the fin extending along the second direction. The isolation trench extends along the first direction and exposes the outer sidewalls of the fin extending along the first direction. The ends of the first trench and the isolation trench extend to the second trench along the first direction to communicate with the second trench on the sidewalls of the second trench. The bottom surface of the first trench is higher than the bottom surface of the second trench, and the bottom surface of the isolation trench is flush with the bottom surface of the second trench, so that the sidewalls of the horizontal fin portion including the second source / drain doped region are exposed in the second trench. An embedded conductor extending along the second direction is embedded in the second trench, and the embedded conductor is electrically connected to the second source / drain doped region.

[0009] Optionally, the semiconductor device further includes a conductive contact structure formed in the second trench and disposed between the buried conductor and the second source / drain doped region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain doped region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the buried conductor. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench, and the length of the conductive contact structure extending along the second direction is less than or equal to the length of the second source / drain doped region extending along the second direction.

[0010] Optionally, the semiconductor device further includes a first dielectric layer, which fills the bottom of the second trench and the bottom of the isolation trench, and the embedded wire is formed on the first dielectric layer.

[0011] Optionally, the semiconductor device further includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer being located between the gate and the fin, and the gate isolation layer filling the first trench, the second trench, and the isolation trench to bury the gate therein.

[0012] Optionally, the semiconductor substrate has fins distributed on both sides of the second trench, and the fins on both sides of the second trench are aligned or staggered.

[0013] Optionally, the semiconductor device is a memory, including a plurality of fins arranged in an array along the first direction and the second direction. Among all the fins, the gates surrounding the sidewalls of a plurality of vertical fin portions aligned in the first direction are electrically connected to each other to form word lines of the memory. A plurality of second source / drain doped regions aligned in the second direction are connected to the same buried wire, which forms bit lines of the memory.

[0014] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0015] A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form an isolation trench extending along the first direction, a second trench extending along the second direction, and at least one fin. The fin has a horizontal fin portion extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between two of the vertical fin portions of the fin. The first trench, the isolation trench, and the second trench communicate on the sidewalls of the second trench.

[0016] A first source / drain doped region, a second source / drain doped region, a buried conductor, and a gate are formed. The first source / drain doped region is formed in the top portion of the vertical fin portion. The second source / drain doped region is formed in the horizontal fin portion and extends along the second direction from a portion of the horizontal fin portion covered by one of the vertical fin portions to a portion covered by another vertical fin portion. The buried conductor is formed in the second trench and electrically connected to the second source / drain doped region. The gate surrounds the sidewall of the vertical fin portion.

[0017] Optionally, the second source / drain doped region is formed in the horizontal fin portion before or after the formation of the embedded wire, and the first source / drain doped region is simultaneously formed in the top portion of the vertical fin portion; or,

[0018] After forming the gate, a second source / drain doped region is formed in the horizontal fin portion, and a first source / drain doped region is formed in the top portion of the vertical fin portion; or,

[0019] Before or after the formation of the embedded conductor, the second source / drain doped region is formed in the horizontal fin portion, and after the formation of the gate, the first source / drain doped region is formed in the top portion of the vertical fin portion.

[0020] Optionally, the step of forming the embedded conductor includes:

[0021] A first dielectric layer is filled in the second trench, the isolation trench, and the first trench;

[0022] A portion of the first dielectric layer in the region corresponding to the second source / drain doped region is etched into the second trench to form a contact hole. The sidewall of one side of the contact hole is the exposed sidewall of the second source / drain doped region, and the sidewall of the opposite side is the sidewall of the remaining first dielectric layer in the second trench.

[0023] A conductive contact structure is filled into the contact hole;

[0024] The first dielectric layer in the second trench is etched to form a wire trench, wherein one sidewall of the wire trench is the sidewall that exposes the conductive contact structure away from the second source / drain doped region, and the other sidewall is the sidewall of the remaining first dielectric layer in the second trench.

[0025] The embedded conductors are filled in the conductor trench, and the embedded conductors are insulated and isolated from the semiconductor substrate outside the second source / drain doped region by the first dielectric layer.

[0026] Optionally, when filling the first dielectric layer into the second trench, the isolation trench, and the first trench, the first dielectric layer completely fills the second trench, the isolation trench, and the first trench; after filling the embedded wire into the wire trench, the top surface of the first dielectric layer, the conductive contact structure, and the embedded wire up to the portion of the horizontal fin located between the two vertical fin portions is etched back.

[0027] Optionally, the step of forming the gate includes:

[0028] A gate dielectric layer is formed on the surfaces of the first trench, the isolation trench, and the second trench to cover the vertical fin portion, the second source / drain doped region, the embedded wire, and the conductive contact structure;

[0029] The gate material is filled in the first trench, the isolation trench, and the second trench having the gate dielectric layer;

[0030] The gate material in the first trench and the isolation trench is etched along the first direction to form a gate surrounding the sidewall of the vertical fin portion, wherein the top surface of the formed gate is lower than the top surface of the vertical fin portion; and,

[0031] A gate isolation layer is filled in the first trench, the isolation trench, and the second trench to bury the gate and isolate the gate from the second source / drain doped region, the buried wire, and the conductive contact structure, respectively.

[0032] Optionally, at least one fin is distributed on both sides of the second groove, and the fins on both sides of the second groove are aligned or staggered.

[0033] Optionally, the semiconductor device is a memory, including a plurality of fins arranged in an array along the first direction and the second direction, wherein the gates surrounding the sidewalls of the plurality of vertical fin portions aligned and arranged in a straight line along the first direction are electrically connected to each other to form the word lines of the memory; and the second source / drain doped regions of the plurality of fins aligned and arranged in a straight line along the second direction are connected to the same buried wire, the buried wire forming the bit lines of the memory.

[0034] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0035] 1. A semiconductor device of the present invention has at least one fin, the fin having a horizontal fin portion extending along a second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion, a first trench extending along a first direction being defined between the two vertical fin portions of the fin, a second source / drain doped region being formed in the portion of the horizontal fin portion covered by the two vertical fin portions and in the portion located between the two vertical fin portions (which may be the entire length of the horizontal fin portion extending along the second direction), a first source / drain doped region being formed in the top end portion of each vertical fin portion; a gate is surrounded on the sidewall of the vertical fin portion below each first source / drain doped region, thereby forming two gate-ring transistors based on one fin. Compared to planar transistors, the surrounding gate enhances channel control, suppresses short-channel effects, and reduces operating voltage. Furthermore, with the same substrate area, the effective channel length can be increased by increasing the height of the semiconductor pillars between the first and second source / drain doped regions (i.e., increasing the height of the vertical fin portion), overcoming short-channel effects and facilitating smaller feature sizes. Additionally, since the second source / drain doped region is located at the bottom of the formed transistor, buried conductors can be concealed within the second trench, eliminating the need for direct leads from the transistor surface. This makes it easier to form isolation around the transistor, reducing device area within the same dimensions and thus providing higher device integration density in a given space. Moreover, because the second source / drain doped region extends to the bottom of the vertical fin portion, it facilitates the fabrication and performance improvement of the conductive contact structure between the buried conductors and the second source / drain doped region.

[0036] 2. The semiconductor device fabrication method of the present invention firstly etches a semiconductor substrate along a first direction and a second direction to form an isolation trench extending along the first direction, a second trench extending along the second direction, and a fin defined by the intersection of the isolation trench and the second trench. The fin has a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of the fin. Next, a buried conductor is formed in the second trench, a first source / drain doped region is formed in the vertical fin portion, a second source / drain doped region is formed in the horizontal fin portion, and a gate is formed surrounding the vertical fin portion. The buried conductor is electrically connected to the second source / drain doped region. Thus, two gate-ring transistors are formed based on one fin. The process is simple, and the device area can be reduced under the same size. In this way, a higher device integration can be provided in a given space, which is beneficial for further miniaturization of product size and improvement of device performance.

[0037] 3. The semiconductor device and its fabrication method of the present invention are applicable to semiconductor memories. Since the second source / drain doped region is located at the bottom of the transistor, it does not need to be directly led out from the transistor surface, making it easier to form isolation between transistors in the array. This reduces the memory cell area within the same size, achieving a cell area of ​​4F. 2 The hexagonal close-packed memory array improves device integration and simplifies the process, significantly reducing the difficulties and process defects in shallow trench isolation manufacturing. Attached Figure Description

[0038] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0039] Figure 2A It is along Figure 1 A schematic diagram of the cross-sectional structure of line AA' in the diagram.

[0040] Figure 2B It is along Figure 1 A schematic diagram of the cross-sectional structure of the BB' line in the diagram.

[0041] Figure 2C It is along Figure 1 A schematic diagram of the cross-sectional structure of the CC' line in the diagram.

[0042] Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to a specific embodiment of the present invention.

[0043] Figure 4 yes Figure 3 The diagram shows a top view of the semiconductor device during step S1 of the fabrication method.

[0044] Figures 5A to 5C These are corresponding to one embodiment of the present invention. Figure 4 A schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0045] Figure 6 yes Figure 3 The diagram shows a top view of the semiconductor device during step S2 of the fabrication method.

[0046] Figures 7A to 7C These are corresponding to one embodiment of the present invention. Figure 6 A schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0047] Figure 8 yes Figure 3 The diagram shows a top view of the semiconductor device during step S3 of the fabrication method.

[0048] Figures 9A to 9C These are corresponding to one embodiment of the present invention. Figure 8 A schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0049] Figure 10 yes Figure 3 The diagram shows a top view of the semiconductor device during step S4 of the fabrication method.

[0050] Figures 11A to 11C These are corresponding to one embodiment of the present invention. Figure 10 A schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0051] Figure 12 yes Figure 3 The diagram shows a top view of the semiconductor device during step S5 of the fabrication method.

[0052] Figures 13A to 13C These are corresponding to one embodiment of the present invention. Figure 12 A schematic diagram of the cross-sectional structure at lines AA', BB', and CC'.

[0053] Figure 14 This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0054] Figure 15 This is a top view of a semiconductor device according to an embodiment of the present invention.

[0055] Figure 16 This is a top view of a semiconductor device according to another embodiment of the present invention.

[0056] Figure 17This is a top view of a semiconductor device according to another embodiment of the present invention.

[0057] The accompanying figure is labeled as follows:

[0058] 100 - Semiconductor substrate; 101 - Fin; 1011 - Vertical fin portion of the fin (i.e., the fin on the sidewall of the first trench 100a); 1012 - Horizontal fin portion of the fin (i.e., the fin at the bottom of the first trench 100a); 100a - First trench; 100b - Second trench; 100c - Isolation trench; 101d - Second source / drain doped region; 101s - First source / drain doped region; 101c - Channel region; 102 - First dielectric layer; 103 - Conductive contact structure; 104 - Buried type Wire; 105 - Gate dielectric layer; 106 - Gate; 107 - Gate isolation layer; H - Initial thickness of semiconductor substrate 100; H1 - Depth of the first trench 100a in fin 101; H2 - Depth of the second trench 100b (including the depth where the second trench 100b communicates with the first trench 100a); H3 - Height of the horizontal fin portion 1012 of the fin 101 (i.e., the depth difference between the depth of the first trench 100a and the depth of the second trench 100b in fin 101). Detailed Implementation

[0059] To make the objectives and features of the present invention more apparent and understandable, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the embodiments described. It should be noted that the meanings of "on" and "on" in this document should be interpreted in the broadest sense, such that "on" and "on" mean not only "directly on" something without intermediate features or layers, but also "on" something with intermediate features or layers.

[0060] Figure 1 This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2A It is along Figure 1 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 2B It is along Figure 1 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 2C It is along Figure 1 A schematic diagram of the cross-sectional structure of the CC' line. Figure 1 To clearly show the buried structures in the semiconductor device, such as the gate, second source / drain doped regions, buried wires, and conductive contact structures, the first dielectric layer on the bottom wall of the first trench, the gate isolation layer, and the semiconductor substrate below the bottom of the fins are omitted. This allows the gate, second source / drain doped regions, buried wires, and conductive contact structures to be displayed on the outside. Figures 2A to 2C The cross-sectional structure shows the omitted first dielectric layer, gate isolation layer, and semiconductor substrate below the bottom of the fins, among other film structures.

[0061] Please refer to Figure 1 as well as Figures 2A to 2C An embodiment of the present invention provides a semiconductor device including a semiconductor substrate 100 having at least one fin 101, a first source / drain doped region 101s, a second source / drain doped region 101d, a buried wire 104, a conductive contact structure 103, and a gate 106.

[0062] The semiconductor substrate 100 can be made of any suitable material well known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The semiconductor substrate 100 has at least one fin 101 (e.g., a U-shaped fin with rounded or right-angled corners). The fin 101 has a horizontal fin portion 1012 extending along a second direction and vertical fin portions 1011 vertically disposed at both ends of the horizontal fin portion 1012. A first trench 100a extending along a first direction is defined between the two vertical fin portions 1011. A second source / drain doped region 101d is formed in the horizontal fin portion 1012 and extends from a portion of the horizontal fin portion 1012 covered by one of the vertical fin portions 1011 to a portion covered by another vertical fin portion 1011. A first source / drain doped region 101s is formed at the top of each vertical fin portion 1011.

[0063] The semiconductor substrate 100 further has at least one second trench 100b extending in a second direction and at least one isolation trench 100c extending in a first direction. Each second trench 100b exposes the sidewall of the corresponding fin 101 extending in the second direction. Each isolation trench 100c is located outside the outer sidewall of the corresponding vertical fin portion 1011 extending in the first direction and facing away from the first trench 100a, and exposes the outer sidewall of the fin 101 extending in the first direction (including the outer sidewall of the vertical fin portion 1011 and the bottom horizontal fin portion 1012). That is, the region where each fin 101 is located is connected by two adjacent second trenches 100b and Two adjacent isolation trenches 100c define the boundary. Each of the first trenches 100a and each of the isolation trenches 100c extends along the first direction to the corresponding second trench 100b, such that the first trench 100a and the isolation trench 100c communicate with the second trench 100b on the sidewall of the second trench 100b. The bottom surface of the first trench 100a is higher than the bottom surface of the second trench 100b, so that the sidewall of the horizontal fin portion 1012 of the corresponding fin 101 is exposed in the second trench 100b. The bottom surface of the isolation trench 100c is flush with the bottom surface of the second trench 100b. That is, the first trench 100a and the isolation trench 100c communicate with the second trench 100b at their intersections, and the second trench 100b has the same depth in all areas, including the intersection. Figure 5B In H2, the depth of the region of the first trench 100a, excluding the intersection with the second trench 100b, is less than the depth of the second trench 100b, for example... Figure 5A H1 in the diagram. The depth of the isolation trench 100c is H2 (e.g., H1). Figure 5A As shown), it is equal to the depth of the second trench 100b.

[0064] The fin 101 is used to form two ring gate transistors sharing a second source / drain doped region 101d. The first source / drain doped region 101s and the second source / drain doped region 101d can be formed by source / drain ion implantation. The first source / drain doped region 101s is formed in the top part of the vertical fin portion 1011, and its top surface is the top surface of the vertical fin portion 1011. The second source / drain doped region 101d is formed in the horizontal fin portion 1012, and its top surface is the top surface of the horizontal fin portion 1012 of the fin 101 (i.e., the bottom surface of the first trench 100a). Furthermore, depending on the transistor structure with different conductivity types, the first source / drain doped region 101s and the second source / drain doped region 101d are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doped ions in the first source / drain doped region 101s and the second source / drain doped region 101d are N-type doped ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. When the transistor structure is a P-type transistor, the doped ions in the first source / drain doped region 101s and the second source / drain doped region 101d are P-type doped ions, such as boron (B) ions and boron fluoride (BF2). + Gallium (Ga) ions, indium (In) ions. In this embodiment, the first source / drain doped region 101s can be the source region, and the second source / drain doped region 101d can be the drain region.

[0065] The embedded conductor 104 is embedded in the second trench 100b and extends along the second direction. The embedded conductor 104 is straight, filling the bottom of the second trench 100b and extending along the second direction to the entire length of the second trench 100b. The embedded conductor 104 is insulated from the semiconductor substrate 100 by a first dielectric layer 102 and electrically connected to the second source / drain doped region 101d by a conductive contact structure 103. The first dielectric layer 102 fills the bottom of the second trench 100b and the isolation trench 100c and has a certain thickness, such that the bottom surface of the embedded conductor 104 is not lower than the bottom surface of the second source / drain doped region 101d, thus isolating it from the horizontal fin portion 1012 below the second source / drain doped region 101d. The top surface of the embedded conductor 104 can be flush with or lower than the top surface of the second source / drain doped region 101d. The length of the conductive contact structure 103 extending along the second direction can be equal to the length of the second source / drain doped region 101d extending along the second direction, thereby increasing the fabrication process window. In other embodiments of the present invention, the length of the conductive contact structure 103 extending along the second direction can also be less than the length of the second source / drain doped region 101d extending along the second direction.

[0066] Furthermore, the embedded conductor 104 can be formed using processes such as vapor deposition, electroplating, chemical vapor deposition, and atomic layer deposition. It can be a single-layer structure or a stacked structure. The stacked structure includes, for example, a variety of materials selected from tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold, but is not limited to these. The material of the first dielectric layer 102 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive contact structure 103 can include at least one of tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold.

[0067] A gate 106 is surrounded on the sidewall of each of the two vertical fin portions 1011 of the fin 101. The top surface of the gate 106 is lower than the top surface of the vertical fin portion 1011 of the fin 101, and the gate 106 is slightly lower than the bottom surface of the first source / drain doped region 101s in height, or it can coincide with the bottom surface. Thus, the two first source / drain doped regions 101s, the two surrounding gates 106, the one second source / drain doped region 101d, and the two channel regions 101c (i.e., the vertical fin portion 1011 between each first source / drain doped region 101s and the second source / drain doped region 101d) on the fin 101 form two ring gate transistors that share the second source / drain doped region 101d. The structure formed by these two ring gate transistors can be called a U-shaped ring gate transistor.

[0068] A gate dielectric layer 105 is also formed between the gate 106 and the fin 101. The gate dielectric layer 105 covers the sidewalls and bottom walls of the first trench 100a above the second source / drain doped region 101d, the second trench 100b above the buried conductor 104, and the isolation trench 100c above the first dielectric layer 102. This layer serves to isolate the vertical fin portions 1011 of the gate 106 and the fin 101, the gate 106 and the second source / drain doped region 101d, and the gate 106 and the buried conductor 104 and conductive contact structure 103, respectively. It also buries the buried conductor 104 and the second source / drain doped region 101d within it. The top surface of the portion of the gate dielectric layer filling the bottom wall of the first trench 100a, the second trench 100b, and the isolation trench 100c is flush with the surface to provide a flat process surface for the formation of the gate 106. The thickness of the gate dielectric layer 105 filled in the first trench 100a, the second trench 100b and the isolation trench 100c can determine the height of the bottom surface of the gate 106. Therefore, the deposition thickness of the gate dielectric layer 105 can be set according to the bottom surface height requirement of the gate 106.

[0069] To prevent leakage between two adjacent gates 106, the semiconductor device further includes a gate isolation layer 107. The gate isolation layer 107 fills the first trench 100a, the isolation trench 100c, and the second trench 100b, and exposes the top surface of the first source / drain doped region 101s, thereby covering and burying the gates 106 and the embedded conductors 104. Preferably, the top surface of the gate isolation layer 107 is flush with the top surface of the vertical fin portion 1011 of the fin 101, providing a flat operating platform for subsequent processes.

[0070] Furthermore, the gate dielectric layer 105 can be formed using processes such as thermal oxidation (dry or wet oxidation), chemical vapor deposition, and atomic layer deposition. The gate film layer corresponding to the gate 106 can be formed using physical vapor deposition or chemical vapor deposition. The gate material can be polycrystalline silicon or a metal gate material. When the gate 106 is made of polycrystalline silicon, the gate dielectric layer 105 can be made of silicon dioxide. When the gate 106 is made of a metal gate material, the gate dielectric layer 105 can be made of a high-k dielectric with a dielectric constant K greater than 7. The gate 106 has a stacked structure, which includes a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 105. The gate isolation layer 107 can be formed using processes such as chemical vapor deposition and atomic layer deposition. The material of the gate isolation layer 107 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride.

[0071] In the semiconductor device of the present invention, the first trench 100a in the fin 101 can be a rounded U-shaped trench or a right-angled U-shaped trench, thereby forming a vertical conductive channel along the current conduction direction (i.e., the current flow direction from a first source / drain doped region 101s to a second source / drain doped region 101d on each side of the first trench 100a). Compared with planar transistors, the vertical channel, while occupying the same substrate area, can increase the effective channel length by increasing the height of the semiconductor pillar (i.e., the vertical fin portion 1011) between the first source / drain doped region 101s and the second source / drain doped region 101d, overcoming the short-channel effect and facilitating the realization of smaller feature sizes. Moreover, since the gate 106 surrounds the vertical fin portion 1011, the channel between the first source / drain doped region 101s and the second source / drain doped region 101d can be controlled on all four sides, improving the channel control capability and thus effectively improving the short-channel effect of the transistor. Furthermore, since one fin can form two transistors sharing a second source-drain doped region, the device density can be increased in the same area.

[0072] Furthermore, in the semiconductor device of the present invention, please refer to... Figure 14 The embedded wires 104 in each second trench 100b can be electrically connected to the second source / drain doped regions 101d of all the fins 101 on one side of the second trench 100b, thereby increasing the fabrication window of the embedded wires 104. At the same time, the U-shaped gate ring transistor formed on one side of the second trench 100b can be simultaneously controlled by the embedded wires 104, simplifying the control operation of the semiconductor device and reducing the control cost.

[0073] In one embodiment of the present invention, the semiconductor device may be a semiconductor memory, please refer to [reference needed]. Figure 14 and 15 The semiconductor device has a plurality of fins 101 arranged in an array along a first direction and a second direction. Here, the first direction X is the word line direction / row direction of the semiconductor memory, and the second direction Y is the bit line direction / column direction of the semiconductor memory. The plurality of fins 101 arranged in the first direction X are arranged into corresponding cell rows, and the plurality of fins 101 arranged in the second direction Y are arranged into corresponding cell columns. The fins 101 on both sides of each second trench 100b are aligned one by one, thereby making the first trench 100a of all the fins 101 in each cell row integrally formed, and the gates 106 on both sides of each first trench 100a are respectively connected to form two word lines of the memory. The embedded wires 104 in each second trench 100b are electrically connected to the second source / drain doped regions 101d of all the fins 101 on one side of the second trench 100b, forming one bit line of the memory. In other words, in the memory, multiple vertical fin portions 1011 are aligned and arranged in a straight line along the first direction X, and the gates 106 surrounding the sidewalls of these vertical fin portions 1011 are also aligned and electrically connected to each other, thereby forming the word lines (extending along the first direction) of the memory; multiple fins 101 are aligned and arranged in a straight line along the second direction Y, and the second source / drain doped regions 101d of these fins 101 are connected to the same buried conductor 104, which forms the bit lines of the memory. In this embodiment, the first direction X and the second direction Y are perpendicular, and the projection of the fins 101 onto the surface of the semiconductor substrate 100 is rectangular. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the first direction X and the second direction Y can also form an angle of 5 degrees to 85 degrees, such as... Figure 16 As shown, the projection of the fin 101 onto the surface of the semiconductor substrate 100 is a regular parallelogram with no right angles in the interior.

[0074] Furthermore, in other embodiments of the semiconductor device of the present invention, when fins 101 are evenly distributed on both sides of each second trench 100b, these fins on both sides of the second trench 100b can also be arranged in a staggered manner. For example, when the semiconductor device is a memory, such as Figure 17 As shown, the memory includes a plurality of fins 101 arranged in an array along the first direction X and the second direction Y, wherein the gates 106 surrounding the sidewalls of the plurality of vertical fin portions 1011 aligned and arranged in a straight line along the first direction X are electrically connected to each other to form the word lines of the memory; and the second source / drain doped regions 101d of the plurality of fins 101 aligned and arranged in a straight line along the second direction are connected to the same buried conductor 104, the buried conductor 104 forming the bit lines of the memory.

[0075] It should be recognized that when the semiconductor device is a device other than a memory, and multiple vertical fin portions 1011 are aligned and arranged in a straight line along the first direction, the gates 106 surrounding the sidewalls of these vertical fin portions 1011 are also independent of each other (not shown), so that these corresponding U-shaped gate-ring transistors can perform different operations because their gates can receive different signals; similarly, the buried wires 104 connected to the multiple second source-drain doped regions 101d aligned and arranged in a straight line along the second direction are also independent of each other (not shown), so that these corresponding U-shaped gate-ring transistors can perform different operations because their second source-drain doped regions 101d can receive different signals. In summary, the semiconductor device of the present invention has at least one fin, the fin having a horizontal fin portion extending along a second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion, a first trench extending along a first direction being defined between the two vertical fin portions of the fin, a second source / drain doped region being formed in the horizontal fin portion, and a first source / drain doped region being formed in the top portion of each vertical fin portion; a gate is surrounded on the sidewall of the vertical fin portion below each first source / drain doped region, thereby forming two gate-around transistors (which can be called a U-shaped gate-around transistor) based on one fin. Compared with planar transistors, the gate surrounding the channel on all four sides can improve the control of the channel. On the one hand, it can suppress short-channel effects and reduce operating voltage. On the other hand, under the premise of occupying the same substrate area, the effective channel length can be increased by increasing the height of the semiconductor pillar between the first and second source / drain doped regions, thus overcoming the short-channel effect and facilitating the achievement of smaller feature sizes. In addition, the second source / drain doped region is located at the bottom of the U-shaped gate-ring transistor, and the buried conductor is buried in the second trench and electrically connected to the second source / drain doped region, without needing to be directly led out from the transistor surface. This makes it easier to form isolation around the transistor, reducing the device area within the same size, and thus providing higher device integration in a given space. This is particularly suitable for semiconductor memories such as high-density dynamic random access memories. Furthermore, since the second source / drain doped region can extend to the entire bottom of the formed U-shaped gate-ring transistor, it is beneficial to increase the fabrication window of the conductive contact structure and ensure the electrical connection performance between the buried conductor and the second source / drain doped region.

[0076] Because the semiconductor device of this invention differs structurally from existing semiconductor devices, its fabrication method also requires corresponding improvements. The following will use the fabrication of dynamic random access memory as an example, combined with... Figures 3 to 17 The following will describe in detail the method for preparing the semiconductor device of the present invention.

[0077] Please refer to Figure 3 An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0078] S1, a semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form an isolation trench extending along the first direction, a second trench extending along the second direction, and a fin having a first trench extending along the first direction. The second trench exposes the sidewall of the fin extending along the second direction, and the isolation trench exposes the sidewall of the fin extending along the first direction. The fin has a horizontal fin portion extending along the second direction and a vertical fin portion vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of the fin. The first trench, the isolation trench, and the second trench are respectively connected on the sidewall of the second trench.

[0079] S2, forming a first source / drain doped region in the top part of the vertical fin portion, and forming a second source / drain doped region in the horizontal fin portion;

[0080] S3, a conductive contact structure and an embedded wire are formed in the second trench, the embedded wire and the conductive contact structure both extend along the second direction, and the embedded wire is electrically connected to the second source / drain doped region through the conductive contact structure;

[0081] S4, forming a gate surrounding the sidewall of the vertical fin portion; and

[0082] S5, fill the gate isolation layer in the first trench, the second trench and the isolation trench.

[0083] Figure 4 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S1. Figure 5A In order to perform step S1 along Figure 4 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 5B In order to perform step S1 along Figure 4 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 5C In order to perform step S1 along Figure 4 A schematic diagram of the cross-sectional structure of the CC' line in the diagram.

[0084] Please refer to Figure 4 , Figures 5A to 5CIn step S1, firstly, a flat semiconductor substrate 100 is provided. The semiconductor substrate 100 provides an operating platform for subsequent processes and can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Its initial thickness is H, which is the height difference between the upper and lower surfaces of the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. Then, the semiconductor substrate 100 is etched along a first direction and a second direction, respectively, to form at least one isolation trench 100c extending along the first direction, at least one second trench 100b extending along the second direction, and at least one fin 101 having a first trench 100a extending along the first direction. The specific process is as follows:

[0085] Step 1: Form a first hard mask pattern (not shown) on the semiconductor substrate 100 to define multiple parallel second trenches 100b, such that the first hard mask pattern can cover and protect the semiconductor substrate 100 area corresponding to the fin 101 while exposing the semiconductor substrate 100 area corresponding to the second trenches 100b. The first hard mask pattern can be a stacked structure having an oxide layer (not shown) and a nitride layer (not shown). More specifically, the oxide layer and the nitride layer can be sequentially formed on the semiconductor substrate 100 using a deposition process or the like. Further, a photoresist (not shown) can be coated onto the surface of the nitride layer, and an exposure and development process can be performed to form a photoresist pattern (not shown). The photoresist pattern can expose the area on the semiconductor substrate 100 where the second trench 100b is to be formed, and the exposed portions can have a side-by-side linear arrangement, for example, the exposed portions can be parallel to each other. Then, the nitride layer and the oxide layer can be sequentially etched using an etching process that utilizes the photoresist pattern as an etching mask to form a first hard mask pattern. Afterwards, the photoresist pattern is removed.

[0086] Step 2: The semiconductor substrate 100 is etched by using the first hard mask pattern as an etching mask to form multiple second trenches 100b with a depth of H2. The semiconductor substrate 100 between two adjacent second trenches 100b forms a complete fin, that is, the second trench 100b exposes the sidewalls of the complete fin extending along the second direction.

[0087] Step 3: A sacrificial layer can be formed on the entire structure to fill the second trench 100b. The material of the sacrificial layer is different from that of the semiconductor substrate 100 to facilitate subsequent removal, such as silicon oxide, silicon nitride, or silicon oxynitride. Subsequently, a chemical mechanical planarization process can be used to remove the first hard mask pattern and the sacrificial layer above it to provide a flat process surface for subsequent processes.

[0088] Step 4: A second hard mask pattern (not shown) can be formed on the remaining sacrificial layer and semiconductor substrate 100. The second hard mask pattern is used to define multiple linear isolation trenches 100c extending side by side along the first direction, so that the second hard mask pattern can expose the semiconductor substrate 100 and sacrificial layer regions corresponding to the isolation trenches 100c while covering and protecting other regions. For example, the exposed portions can be parallel to each other. The formation process of the second hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be described again here.

[0089] Step 5: Etch the semiconductor substrate 100 and the exposed sacrificial layer using an etching process that utilizes the second hard mask pattern as an etching mask. The etching depth is H2 to form multiple isolation trenches 100c with a depth of H2. The isolation trenches 100c extend from the end along the first direction to the second trench 100b, so that the isolation trenches 100c and the second trench 100b are connected on the sidewall of the second trench 100b, and the bottom surface of the isolation trenches 100c is flush with the bottom surface of the second trench 100b. In other words, this step essentially cuts the complete fins between two adjacent second trenches 100b to define the semiconductor substrate 100 region corresponding to each fin 101. In other words, the area enclosed by the intersection of two adjacent second grooves 100b and two adjacent isolation grooves 100c is the area of ​​a fin 101. The end of the isolation groove 100c outside the outer sidewall of each fin 101 extends into the second groove 100b and communicates with the second groove 100b on the sidewall of the second groove 100b.

[0090] Step Six: The second hard mask pattern can be removed to expose the surface of the semiconductor substrate 100, and a third hard mask pattern (not shown) can be formed on the remaining sacrificial layer and semiconductor substrate 100. The third hard mask pattern is used to define multiple linear first trenches 100a that extend along the first direction and are arranged side by side, so that the third hard mask pattern can expose the semiconductor substrate 100 and sacrificial layer regions corresponding to the first trenches 100a while covering and protecting other regions. For example, the exposed portions can be parallel to each other. The formation process of the third hard mask pattern can refer to the formation process of the first hard mask pattern, and will not be described again here.

[0091] Step 7: Etch the semiconductor substrate 100 and the exposed sacrificial layer using an etching process that utilizes the third hard mask pattern as an etching mask. The etching depth is H1, where H1 is less than H2, to form multiple fins 101 with a first trench 100a of depth H1. The first trench 100a extends from its end along a first direction into the second trench 100b, such that the first trench 100a and the second trench 100b are connected on the sidewall of the second trench 100b, and the bottom surface of the first trench 100a is higher than the bottom surface of the second trench 100b. Thus, the fin 101 has a horizontal fin portion 1012 extending along the second direction (i.e., the portion located between adjacent isolation trenches 100c) and a vertical fin portion 1011 vertically disposed at both ends of the horizontal fin portion 1012. The trench defined between the two vertical fin portions 1011 is the first trench 100a extending along the first direction. The horizontal fin portion 1012 is used to form the second source / drain doped region 101d, and the vertical fin portion 1011 is used to subsequently form the first source / drain doped region 101s and the gate 106.

[0092] Step 8: The third hard mask pattern and the remaining sacrificial layer can be removed to expose the surface of the semiconductor substrate 100. The process for removing the sacrificial layer can be a dry etching process or a wet etching process, and the process for removing the third hard mask pattern can be a chemical mechanical planarization process, a dry etching process, or a wet etching process.

[0093] It should be noted that in the above embodiment, the second trench 100b is formed first, then the isolation trench 100c with the same depth as the second trench 100b is formed, and then the first trench 100a with a depth less than the second trench 100b is formed. However, the technical solution of the present invention is not limited to this. The formation order of the first trench 100a, the second trench 100b and the isolation trench 100c can also be adaptively adjusted. For example, the first trench 100a can be formed first, and then the second trench 100b and the isolation trench 100c can be formed in sequence. The specific method is similar to that described above and will not be repeated here.

[0094] It should be understood that in this embodiment, the depth of the isolation trench 100c is different from the depth of the first trench 100a, but the same as the depth of the second trench 100b. Therefore, the patterns of the isolation trench 100c and the second trench 100b can be fabricated on the same mask. While etching the semiconductor substrate 100 along the first direction to form the isolation trench 100c, the semiconductor substrate 100 is also etched to the same depth along the second direction to simultaneously form the isolation trench 100c and the second trench 100b, which can save one mask and simplify the process. The specific method is similar to that described above and will not be repeated here.

[0095] Figure 6This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S2. Figure 7A In order to perform step S2 along Figure 6 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 7B In order to perform step S2 along Figure 6 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 7C In order to perform step S2 along Figure 6 A schematic diagram of the cross-sectional structure of the CC' line. Please refer to... Figure 6 , Figures 7A to 7C In step S2, various source / drain ion implantation processes (including tilt implantation, multi-step implantation, and diffusion) can be used to dope the vertical fin portion 1011 on both sides of the first trench 100a and the horizontal fin portion 1012 at the bottom of the first trench 100a with source / drain ions to form a first source / drain doped region 101s in the top part of the vertical fin portion 1011 of the fin 101 and a second source / drain doped region 101d in the horizontal fin portion 1012 of the fin 101. The second source / drain doped region 101d extends along a second direction from the portion of the horizontal fin portion 1012 covered by one of the vertical fin portions 1011 to the portion covered by the other vertical fin portion 1011. Preferably, the length of the second source / drain doped region 101d extending along the second direction in the horizontal fin portion 1012 is as large as possible, for example, equal to the length of the horizontal fin portion 1012 extending along the second direction (i.e., the length of the fin 101 extending along the second direction), so as to maximize the window for fabricating the conductive contact structure and avoid defects in the conductive contact structure. Furthermore, depending on the transistor structure of different conductivity types, the first source / drain doped region 101s and the second source / drain doped region 101d are doped with ions of the corresponding conductivity type. For example, when the transistor structure is an N-type transistor, the doped ions in the first source / drain doped region 101s and the second source / drain doped region 101d are N-type doped ions, such as phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the first source / drain doped region 101s and the second source / drain doped region 101d are P-type doped ions, such as boron (B) ions and boron fluoride (BF2). + Gallium (Ga) ions, indium (In) ions.

[0096] Figure 8 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S3. Figure 9A In order to perform step S3 along Figure 8 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 9BIn order to perform step S3 along Figure 8 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 9C In order to perform step S3 along Figure 8 A schematic diagram of the cross-sectional structure of the CC' line. Please refer to... Figure 8 , Figures 9A to 9C In step S3, embedded wires 104 (i.e., bit lines of the memory) and conductive contact structures 103 are formed in the second trench 100b. The specific process is as follows:

[0097] Step 1: A first dielectric layer 102 can be formed on the entire semiconductor substrate 100 structure, including the fins 101, the first trench 100a, the isolation trench 100c, and the second trench 100b, using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The first dielectric layer 102 can fill the first trench 100a, the isolation trench 100c, and the second trench 100b, and cover the top surface of the first source / drain doped region 101s. The first dielectric layer 102 can be further planarized at the top to reduce its thickness on the top surface of the first source / drain doped region 101s, providing a flat process platform for subsequent processes. The material of the first dielectric layer 102 only needs to have a high etch selectivity relative to the semiconductor substrate 100, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0098] Step 2: Open the contact hole (not shown) in the second trench 103 for manufacturing the conductive contact structure 103 through a series of processes such as masking, photolithography, and etching. That is, remove the first dielectric layer 102 in the contact hole area. The contact hole exposes the sidewall of the second source / drain doped region 101d facing the second trench 100b, extending in the second direction for all or part of its length. The bottom surface of the contact hole is between the top surface of the horizontal fin portion 1012 and the bottom surface of the second source / drain doped region 101d. That is, the sidewall on one side of the contact hole is the exposed sidewall of the second source / drain doped region 101d, and the sidewall on the opposite side is the sidewall of the remaining first dielectric layer 102 in the second trench 100b.

[0099] Step 3: Fill the contact hole with conductive metal or other materials through processes such as electroplating, sputtering, or chemical vapor deposition. The conductive metal or other materials may include multiple materials such as tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold. Further remove the conductive metal or other materials above the first source / drain doped region 101s through a chemical mechanical polishing process to form a conductive contact structure 103 filled in the contact hole.

[0100] Step 4: A series of processes, including masking, photolithography, and etching, are used to open the wire trench (not shown) in the second trench 100b for manufacturing the embedded wire 104. The depth of the wire trench can be the same as the depth of the conductive contact structure 103 (i.e., the depth of the contact hole), slightly deeper than the depth of the bottom surface of the conductive contact structure 103 (i.e., the depth of the contact hole), or slightly shallower than the depth of the bottom surface of the conductive contact structure 103 (i.e., the depth of the contact hole). The length of the wire trench extends to the entire second trench 100b to facilitate signal access for the transistor. One side of the wire trench exposes the sidewall of the conductive contact structure 103 facing away from the second source / drain doped region 101d, while the other side of the wire trench does not expose the sidewall of the vertical fin portion 1011 facing the second trench 100b. That is, one sidewall of the wire trench exposes the sidewall of the conductive contact structure 103 away from the second source / drain doped region 101d, and the opposite sidewall is the sidewall of the remaining first dielectric layer 102 in the second trench 100b. The wire trench and the contact hole where the conductive contact structure 103 is located are connected.

[0101] Step 5: Fill the conductive metal trench with conductive metal or other materials through processes such as electroplating, sputtering, or chemical vapor deposition. The conductive metal or other materials may include multiple materials selected from tungsten, nickel, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, copper, aluminum, silver, and gold. Further planarize the conductive metal or other materials to the top surface of the first source / drain doped region 101s (which may have a protective layer such as silicon oxide) using a chemical mechanical polishing process to form an embedded conductive wire 104 filling the conductive trench. The embedded conductive wire 104 is insulated and isolated from the semiconductor substrate 100 other than the second source / drain doped region 101d by the first dielectric layer 102.

[0102] Step 6: Etch back the buried wire 104, the conductive contact structure 103, and the top surface of the second source / drain doped region 101d between the first dielectric layer 102 and the vertical fin portion 1011 to re-expose the first trench 100a, the second trench 100b, and the isolation trench 100c that are higher than the second source / drain doped region 101d, so as to provide a process window for gate molding.

[0103] The method described above, which first forms the conductive contact structure 103 and then the embedded wire 104, can increase the operational window for fabricating the conductive contact structure 103, ensuring its performance and avoiding poor electrical connection between the embedded wire 104 and the second source / drain doped region 101d. Furthermore, because the second source / drain doped region 101d extends a relatively long distance along the second direction, not only between the two vertical fin portions 1011 but also extending to the bottom of the two vertical fin portions 1011, the maximum length of the conductive contact structure 103 extending along the second direction can be equal to the maximum length of the second source / drain doped region 101d extending along the second direction. This results in a larger operational window for fabricating the conductive contact structure 103, leading to higher electrical connection performance between the embedded wire 104 and the second source / drain doped region 101d.

[0104] Figure 10 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S4. Figure 11A In order to perform step S4 along Figure 10 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 11B In order to perform step S4 along Figure 10 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 11C In order to perform step S4 along Figure 10 A schematic diagram of the cross-sectional structure of the CC' line. Please refer to... Figure 10 , Figures 11A to 11C In step S4, a gate 106 is formed surrounding the vertical fin portion 1011, and the specific process is as follows:

[0105] Step 1: Based on the required gate type, select a suitable molding process, such as thermal oxidation, chemical vapor deposition, or atomic layer deposition, to form a gate dielectric layer 105 on the entire structure having buried conductors 104 and conductive contact structures 103. The gate dielectric layer 105 not only covers the sidewalls of the exposed vertical fin portion 1011, but also covers the top surface of the second source / drain doped region 101d, the first dielectric layer 102, the buried conductors 104, and the conductive contact structures 103, thus burying the second source / drain doped region 101d, the buried conductors 104, and the conductive contact structures 103 for insulation and isolation from the subsequently formed gate 106. The thickness of the gate dielectric layer 105 is, for example, 3 nm to 30 nm. When the subsequently formed gate 106 is a polysilicon gate, the material of the gate dielectric layer 105 is preferably silicon dioxide; when the subsequently formed gate 106 is a metal gate, the material of the gate dielectric layer 105 is preferably a high-K dielectric (K greater than 7).

[0106] Step 2: A gate material layer for fabricating the gate 106 is deposited on the surface of the gate dielectric layer 105 using processes such as evaporation, electroplating, chemical vapor deposition, and atomic layer deposition. The deposition thickness must be at least the thickness required to form the gate 106. The gate material layer for fabricating the gate 106 can be a single-layer structure or a stacked structure. The material of the gate material layer for fabricating the gate 106 can be a material used to fabricate polysilicon gates, such as undoped polysilicon or doped polysilicon. It can also be a material used to fabricate metal gates, such as a metal barrier layer (TiN, etc.), a work function layer (TiAl, TiN, etc.), and a metal electrode layer (e.g., tungsten W, etc.) sequentially stacked on the surface (including the bottom surface and sidewalls) of the gate dielectric layer 105.

[0107] Step 3: Remove excess material layers used for fabricating gate 106 in the first trench 100a and the isolation trench 100c by etching back through a back etching process. The back etching process can be a dry etching process, thereby forming gate 106 on the two vertical fin portions 1011 of the fin 101, respectively. The gate 106 on the two vertical fin portions 1011 of the fin 101 are spaced apart at the first trench 100a. The top surface of the gate 106 is lower than the top surface of the first source / drain doped region 101s, and may even be lower than or flush with the bottom surface of the first source / drain doped region 101s. At this time, the gate dielectric layer 105 can expose the sidewalls and top surface of the first source / drain doped region 101s and maintain coverage of the top surface of the second source / drain doped region 101d, or it can continue to cover the sidewalls and top surface of the first source / drain doped region 101s and maintain coverage of the top surface of the second source / drain doped region 101d.

[0108] Furthermore, since the manufactured semiconductor device is a memory, the semiconductor substrate 100 has multiple second trenches 100b and multiple isolation trenches 100c as well as multiple fins 101. The gate 106 surrounding the vertical fin portion 1011 arranged in the same straight line along the first direction is uninterrupted at the second trench 100b, thereby forming the word line of the memory.

[0109] It should be recognized that when the semiconductor device being manufactured is not a memory or the like, the gates aligned on both sides of the second trench 100b do not need to be electrically connected together. In step three above, when the gate material layer is etched back, the gate material layer in the second trench 100b is also disconnected at the same time, so that the gates 106 surrounding the vertical fin portions 1011 aligned on both sides of the second trench 100b are independent of each other.

[0110] Figure 12 This is a top view schematic diagram of the semiconductor device fabrication method in one embodiment of the present invention during step S5. Figure 13A In order to perform step S5 along Figure 12 A schematic diagram of the cross-sectional structure of line AA' in the diagram; Figure 13B In order to perform step S5 along Figure 12 A schematic diagram of the cross-sectional structure of the BB' line in the diagram; Figure 13C In order to perform step S5 along Figure 12 A schematic diagram of the cross-sectional structure of the CC' line. Please refer to... Figure 12 , Figures 13A to 13C In step S5, chemical vapor deposition, atomic layer deposition, or other processes can be used to deposit a gate isolation layer 107 in the first trench 100a, isolation trench 100c, and second trench 100b until the deposited gate isolation layer 107 fills the first trench 100a, isolation trench 100c, and second trench 100b. The material of the gate isolation layer 107 includes, but is not limited to, silicon oxide, silicon nitride, and silicon oxynitride. Further, a chemical mechanical planarization process is used to remove excess gate isolation layer 107 and gate dielectric layer 105 above the first source / drain doped region 101s, so that the gate 106 (i.e., the word line of the memory) is buried in the first trench 100a, second trench 100b, and isolation trench 100c, exposing the top surface of the first source / drain doped region 101s for outward lead-out.

[0111] It should be noted that in the above embodiments, the gate 106 is formed by processes such as deposition and etching. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, after forming the gate dielectric layer 105, a sacrificial layer can be filled again into the first trench 100a, the second trench 100b, and the isolation trench 100c, and the sacrificial layer can be etched to form a gate trench surrounding the vertical fin portion 1011. Then, gate material is filled into the gate trench, and the sacrificial layer is removed to form the gate 106. When the gate 106 is a metal gate, a polysilicon gate and a gate isolation layer 107 can be formed first, and then the polysilicon gate can be replaced with a metal gate through a gate replacement process.

[0112] The above embodiments all use memory manufacturing as an example. A fin 101 forms two memory transistors. A gate 106 can extend uninterruptedly along a first direction to the entire length of the semiconductor substrate 100 used to fabricate the memory array, serving as a word line controlling the memory array. Thus, one gate 106 can control all transistors aligned and arranged in a straight line along the first direction. An embedded wire 104 can extend uninterruptedly along a second direction to the entire length of the semiconductor substrate 100 used to fabricate the memory array, such as... Figure 14 and Figure 15As shown, a plurality of vertical fin portions 1011 of a plurality of fins 101 aligned along the first direction X are aligned and arranged on the same straight line so that the corresponding plurality of gates 106 are aligned and electrically connected to each other to form a word line extending along the first direction X; and, in a plurality of fins 101 aligned along the second direction Y and arranged on the same straight line, a plurality of second source / drain doped regions 101d are connected to the same buried conductor 104, the buried conductor 104 constituting the bit line of the memory.

[0113] Furthermore, it should be understood that in the above embodiments, the first source / drain doped region 101s and the second source / drain doped region 101d are formed before the embedded bit line 104 is formed, but the technical solution of the present invention is not limited to this. In one embodiment of the present invention, the second source / drain doped region 101d can be formed in the horizontal fin portion 1012 before the embedded wire 104 is formed, and the first source / drain doped region 101s can be formed in the top portion of the vertical fin portion 1011 after the gate 106 is formed or after the gate isolation layer 107 is formed. In another embodiment of the present invention, after the gate 106 is formed, the first source / drain doped region 101s can be formed in the top portion of the vertical fin portion 1011 using the gate 106 as a mask, and the second source / drain doped region 101s can be formed in the horizontal fin portion 1012. The formed second source / drain doped region 101d is electrically connected to the previously formed embedded wire 104. The specific formation processes of the buried bit line 104, the first source / drain doped region 101s, and the second source / drain doped region 101d in these embodiments are similar to those in the above embodiments, and will not be repeated here.

[0114] It should be further understood that in the semiconductor device fabrication methods of the above embodiments, the first direction X and the second direction Y are perpendicular, and the projection of the fin 101 onto the surface of the semiconductor substrate 100 is rectangular. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, the first direction X and the second direction Y may also form an angle of 5 degrees to 85 degrees, such as... Figure 16 As shown, the projection of the fin 101 onto the surface of the semiconductor substrate 100 is a common parallelogram with no right angles in the interior. The fabrication method of this semiconductor device is basically the same as steps S1 to S5 above. The main difference is that the mask pattern required in each step also needs to be adapted to the pattern structure based on the parallelogram fin 101. The specific fabrication method will not be described in detail here.

[0115] Furthermore, in the semiconductor device fabrication methods of the above embodiments, the fins 101 arranged on both sides of each second trench 100b are aligned. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, these fins 191 on both sides of each second trench 100b can also be staggered. For example, when the semiconductor device is a memory, such as... Figure 17 As shown, the memory includes a plurality of fins 101 arranged in an array along the first direction X and the second direction Y. The gates 106 surrounding the sidewalls of the plurality of vertical fin portions 1011 aligned along the first direction X are electrically connected to each other, forming the word lines of the memory. The second source / drain doped regions 101d of the plurality of fins 101 aligned along the second direction are connected to the same buried conductor 104, which forms the bit lines of the memory. The fabrication method of this semiconductor device is basically the same as steps S1 to S5 described above. The main difference is that the mask pattern required in steps S1 and S2 also needs to be adaptively adjusted to a pattern structure based on the staggered arrangement of the fins 101. The specific fabrication method will not be described in detail here.

[0116] In summary, the semiconductor device fabrication method of the present invention firstly etches an isolation trench extending along the first direction, a second trench extending along the second direction, and a fin along the second direction, respectively, on a semiconductor substrate. The fin has a horizontal fin portion extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between the two vertical fin portions of the fin. Next, a first source / drain doped region is formed in the vertical fin portion, a second source / drain doped region is formed in the horizontal fin portion, a buried conductive line is formed in the second trench, and a gate is formed surrounding the vertical fin portion. The buried conductive line is electrically connected to the second source / drain doped region. Thus, two gate-ring transistors are formed based on a single fin. The process is simple, and the device area can be reduced within the same size. This allows for higher device integration within a given space, which is beneficial for further miniaturization of product size and improvement of device performance.

[0117] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. Therefore, if these modifications and variations fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having at least one fin, the fin having a horizontal fin portion extending along a second direction and vertical fin portions vertically disposed at two opposite ends of the horizontal fin portion, a first trench extending along a first direction defining the two vertical fin portions, a first source / drain doped region formed in the top portion of each vertical fin portion, and a second source / drain doped region provided in the horizontal fin portion, the second source / drain doped region extending along the second direction from a portion of the horizontal fin portion covered by one of the vertical fin portions to a portion covered by the other vertical fin portion; and... A gate surrounds the sidewall of the vertical fin portion; The semiconductor substrate further has a second trench extending along the second direction and exposing the sidewalls of the fins extending along the second direction; the semiconductor substrate has fins distributed on both sides of the second trench, and the fins on both sides of the second trench are aligned. The semiconductor device is a memory, including a plurality of fins arranged in an array along the first direction and the second direction. The first direction is the word line direction of the semiconductor memory, and the second direction is the bit line direction of the semiconductor memory. Among all the fins, the gates surrounding the sidewalls of the plurality of vertical fin portions aligned and arranged in the same straight line along the first direction are electrically connected to each other to form the word line of the memory extending along the first direction. Furthermore, a plurality of second source / drain doped regions aligned and arranged on the same straight line along the second direction are connected to the same embedded wire, the embedded wire constituting the bit line of the memory.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor substrate also has an isolation trench, the isolation trench and the second trench are used to define the area where the fin is located, the isolation trench extends along the first direction and exposes the outer wall of the fin extending along the first direction; The first trench and the isolation trench both extend to the second trench at their ends along the first direction, communicating with the second trench on the sidewall of the second trench. The bottom surface of the first trench is higher than the bottom surface of the second trench, and the bottom surface of the isolation trench is flush with the bottom surface of the second trench, so that the sidewall of the horizontal fin portion including the second source / drain doped region is exposed in the second trench. An embedded wire extending along the second direction is embedded in the second trench, and the embedded wire is electrically connected to the second source / drain doped region.

3. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes a conductive contact structure formed in the second trench and disposed between the buried conductor and the second source / drain doped region. One sidewall of the conductive contact structure contacts the sidewall surface of the second source / drain doped region, and the other sidewall of the conductive contact structure contacts the sidewall surface of the buried conductor. The bottom surface of the conductive contact structure is insulated from the semiconductor substrate surface at the bottom of the second trench, and the length of the conductive contact structure extending along the second direction is less than or equal to the length of the second source / drain doped region extending along the second direction.

4. The semiconductor device as described in claim 2, characterized in that, It also includes a first dielectric layer, which fills the bottom of the second trench and the bottom of the isolation trench, and the embedded wire is formed on the first dielectric layer.

5. The semiconductor device as claimed in claim 2, characterized in that, It also includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer being located between the gate and the fin, and the gate isolation layer filling the first trench, the second trench and the isolation trench to bury the gate therein.

6. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, and the semiconductor substrate is etched along a first direction and a second direction respectively to form an isolation trench extending along the first direction, a second trench extending along the second direction, and at least one fin. The fin has a horizontal fin portion extending along the second direction and vertical fin portions vertically disposed at both ends of the horizontal fin portion. A first trench extending along the first direction is defined between two of the vertical fin portions of the fin. The first trench, the isolation trench, and the second trench communicate on the sidewalls of the second trench. A first source / drain doped region, a second source / drain doped region, a buried conductor, and a gate are formed. The first source / drain doped region is formed in the top portion of the vertical fin portion. The second source / drain doped region is formed in the horizontal fin portion and extends along the second direction from a portion of the horizontal fin portion covered by one of the vertical fin portions to a portion covered by another vertical fin portion. The buried conductor is formed in the second trench and electrically connected to the second source / drain doped region. The gate surrounds the sidewall of the vertical fin portion. Wherein, the first direction is the word line direction of the semiconductor device, and the second direction is the bit line direction of the semiconductor device.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, Before or after forming the embedded wire, the second source / drain doped region is formed in the horizontal fin portion, and simultaneously the first source / drain doped region is formed in the top portion of the vertical fin portion; or, After forming the gate, a second source / drain doped region is formed in the horizontal fin portion, and a first source / drain doped region is formed in the top portion of the vertical fin portion; or, Before or after the formation of the embedded conductor, the second source / drain doped region is formed in the horizontal fin portion, and after the formation of the gate, the first source / drain doped region is formed in the top portion of the vertical fin portion.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The steps for forming the embedded conductor include: A first dielectric layer is filled in the second trench, the isolation trench, and the first trench; A portion of the first dielectric layer in the region corresponding to the second source / drain doped region is etched into the second trench to form a contact hole. The sidewall of one side of the contact hole is the exposed sidewall of the second source / drain doped region, and the sidewall of the opposite side is the sidewall of the remaining first dielectric layer in the second trench. A conductive contact structure is filled into the contact hole; The first dielectric layer in the second trench is etched to form a wire trench, wherein one sidewall of the wire trench is the sidewall that exposes the conductive contact structure away from the second source / drain doped region, and the other sidewall is the sidewall of the remaining first dielectric layer in the second trench. The embedded conductors are filled in the conductor trench, and the embedded conductors are insulated and isolated from the semiconductor substrate outside the second source / drain doped region by the first dielectric layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, When the first dielectric layer is filled into the second trench, the isolation trench, and the first trench, the first dielectric layer completely fills the second trench, the isolation trench, and the first trench. After filling the embedded conductor into the conductor trench, the top surface of the first dielectric layer, the conductive contact structure, and the embedded conductor to the portion of the horizontal fin located between the two vertical fin portions is etched back.

10. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The step of forming the gate includes: A gate dielectric layer is formed on the surfaces of the first trench, the isolation trench, and the second trench to cover the vertical fin portion, the second source / drain doped region, the embedded wire, and the conductive contact structure; The gate material is filled in the first trench, the isolation trench, and the second trench having the gate dielectric layer; The gate material in the first trench and the isolation trench is etched along the first direction to form a gate surrounding the sidewall of the vertical fin portion, wherein the top surface of the formed gate is lower than the top surface of the vertical fin portion; and, A gate isolation layer is filled in the first trench, the isolation trench, and the second trench to bury the gate and isolate the gate from the second source / drain doped region, the buried wire, and the conductive contact structure, respectively.

11. The method for fabricating a semiconductor device according to any one of claims 6 to 10, characterized in that, At least one fin is distributed on both sides of the second groove, and the fins on both sides of the second groove are aligned or staggered.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The semiconductor device is a memory, comprising a plurality of fins arranged in an array along the first direction and the second direction, wherein the gates surrounding the sidewalls of the plurality of vertical fin portions aligned and arranged in a straight line along the first direction are electrically connected to each other to form the word lines of the memory; and the second source / drain doped regions of the plurality of fins aligned and arranged in a straight line along the second direction are connected to the same buried wire, the buried wire forming the bit lines of the memory.

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