A cascade avalanche multiplication photodiode

Abstract

The invention discloses a cascade avalanche multiplication photodiode, wherein a substrate oxide layer is provided on a substrate, and a p-type electrode layer I, a p-type light absorption layer, an electric field regulation layer I, an avalanche multiplication layer I, an n-type transition layer, an electron traveling layer with a low impurity concentration, an electric field regulation layer II, an avalanche multiplication layer II, and an n-type electrode layer are provided on the substrate oxide layer from left to right, wherein the p-type electrode layer II is embedded in the electron traveling layer region with a low impurity concentration, and each layer arranged in sequence on the substrate oxide layer is surrounded by an electric field isolation ring layer, and an intrinsic layer is provided in the outer region of the electric field isolation ring layer, and a p-electrode I is provided on the p-type electrode layer I, a p-electrode II is provided on the p-type electrode layer II, and an n-electrode is provided on the n-type electrode layer. The advantages of the patent are that the structure of the invention avoids the curvature effect, eliminates edge breakdown, improves stability, and realizes multi-stage cascade avalanche multiplication monolithic integration at the same time, obtains a very high stable gain, and effectively suppresses the noise caused by hole avalanches.

Description

Technical Field

[0001] The present invention relates to the field of low-light-level photoelectric detection, and in particular to a cascade avalanche multiplication photodiode (avalanche multiplication photodiode, hereinafter referred to as APD). Background Art

[0002] There is a great demand for APD in basic science, aerospace, and commercial technology. APD has internal gain and can achieve extremely high sensitivity and time resolution, making APD important in basic science fields such as high-energy particle physics, high-resolution spectral measurement, astronomical photometry, and bioluminescence detection, and aerospace fields such as space remote sensing, high-speed target tracking, and dawn-dusk orbit detection, as well as key commercial technology fields such as optical communications, optical ranging, and vehicle-mounted lidar systems.

[0003] Figure 3 The traditional punch-through avalanche multiplication photodiode APD adopts a vertically stacked structure, in which the electric field modulation layer 26 requires a customized deep buried layer process. In addition, when the anode electrode 18 and the cathode electrode 20 are reverse biased, the edge area of ​​the high doping concentration N++ layer 22 will produce a higher electric field strength under the influence of the curvature effect, and the edge area of ​​the N++ layer 22 may experience edge breakdown earlier than the plane area. For this reason, the traditional punch-through APD must be designed with a high-voltage resistant guard ring structure to prevent edge breakdown, such as Figure 3 The NDwell type guard ring 25 is designed in the embodiment. In terms of the over-noise characteristic, it is known that the electron injection type APD is advantageous in principle. Figure 3 For example, in a single-stage multiplication APD structure, the higher electric field strength required to generate higher gain will deteriorate the ionization coefficient ratio k value of holes and electrons in the multiplication region 27, resulting in an increase in the excess noise factor F. At the same time, under the higher electric field strength required to generate higher gain, the impact ionization of electrons injected into the multiplication region 27 generates an excessive number of hole carriers and electron carriers. The space charge effect generated by the excessive hole carriers and electron carriers in the multiplication region 27 and the absorption region 28 will cause gain saturation. Summary of the invention

[0004] The purpose of the present invention is to provide a cascaded avalanche multiplication photodiode APD, which solves the problems of premature edge breakdown, excessive noise and gain saturation of the traditional punch-through avalanche multiplication photodiode APD, thereby improving the performance level of the avalanche multiplication photodiode APD. In order to achieve the above purpose, the cascaded avalanche multiplication photodiode APD of the present invention has the function of preventing the premature edge breakdown, suppressing the noise and gain saturation.

[0005] The technical solution of the present invention is as follows:

[0006] A cascade avalanche multiplication photodiode, characterized in that a substrate oxide layer 16 is provided on a substrate 17, and on the substrate oxide layer 16, from left to right, there are a p-type electrode layer I4, a p-type light absorption layer 5, an electric field regulation layer I6, an avalanche multiplication layer I7, an n-type transition layer 8, an electron traveling layer 9 with a low impurity concentration, an electric field regulation layer II12, an avalanche multiplication layer II13, and an n-type electrode layer 14, wherein the p-type electrode layer II11 is embedded in the region of the electron traveling layer 9 with a low impurity concentration, and the layers arranged in sequence on the substrate oxide layer 16 are surrounded by an electric field isolation ring layer 2, and an intrinsic layer 1 is provided in the outer region of the electric field isolation ring layer 2, a p-electrode I3 is provided on the p-type electrode layer I4, a p-electrode II10 is provided on the p-type electrode layer II11, and an n-electrode 15 is provided on the n-type electrode layer 14.

[0007] The n-type transition layer 8 is an n-type region with a high impurity concentration.

[0008] The electron transit layer 9 with low impurity concentration is a p-type region with low impurity concentration.

[0009] The thickness of the substrate oxide layer 16 on the substrate 17 is 0.1 μm to 1.0 μm.

[0010] The thickness of each layer on the substrate oxide layer 16 is consistent, and the thickness is 0.1 μm to 2.0 μm.

[0011] The principle of the present invention is as follows:

[0012] The first-level avalanche structure of the present invention is formed by a p-type electrode layer I4, a p-type light absorption layer 5, an electric field control layer I6, an avalanche multiplication layer I7, an n-type transition layer 8, an electron traveling layer 9 with a low impurity concentration, and a p-type electrode layer II11, and the second-level avalanche structure is formed by a p-type electrode layer II11, an electron traveling layer 9 with a low impurity concentration, an electric field control layer II12, an avalanche multiplication layer II13, and an n-type electrode layer 14. When the p-type electrode layer I4 and the p-type electrode layer II11 are reverse biased, and when the p-type electrode layer II11 and the n-type electrode layer 14 are reverse biased, the n-type transition layer 8 generates an incompletely depleted region.

[0013] The p-type electrode layer II11 of the present invention is embedded in the region of the electron traveling layer 9 with low impurity concentration, and the thickness of the p-type electrode layer II11 is less than the thickness of the electron traveling layer 9 with low impurity concentration, so as to ensure that electrons can be injected into the avalanche multiplication layer II13 along the electron traveling layer 9 with low impurity concentration. When the p-type electrode layer I4 and the p-type electrode layer II11 are reverse biased, and when the p-type electrode layer II11 and the n-type electrode layer 14 are reverse biased, the electric field strength in the region of the p-type light absorption layer 5 and the electron traveling layer 9 with low impurity concentration is lower than the electric field strength in the region of the avalanche multiplication layer I7 and the avalanche multiplication layer II13, respectively. Figure 4The diagram is a schematic diagram of the electric field intensity distribution of each layer on the cascade APD substrate oxide layer 16 of the present invention (including the p-type electrode layer II11). The present invention uses an electric field isolation ring layer 2 to ensure the isolation of two-stage avalanches.

[0014] The advantages of the present invention are:

[0015] The cascaded avalanche multiplication photodiode structure of the present invention avoids curvature effect, eliminates edge breakdown, and improves stability. The p-type electrode layer II11 is designed for avalanche hole extraction, which is beneficial to suppress the noise caused by hole avalanche and the gain saturation effect caused by space charge effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic cross-sectional view illustrating the APD using the p-type electrode layer II11 of the present invention.

[0017] Figure 2 1 is a schematic top view of an APD using a p-type electrode layer II11 according to the present invention.

[0018] Figure 3 is a schematic diagram illustrating a cross section of a conventional punch-through APD element.

[0019] Figure 4 It is a schematic diagram illustrating the electric field intensity distribution of each layer on the oxide layer 16 of the cascade APD substrate of the present invention (including the p-type electrode layer II11).

[0020] Among them, the figure marks are: 1: intrinsic layer; 2: electric field isolation ring layer; 3: p-electrode; 4: p-type electrode layer I; 5: light absorption layer; 6: electric field regulation layer I; 7: avalanche multiplication layer I; 8: n-type transition layer; 9: electron traveling layer with low impurity concentration; 10: p-electrode II; 11: p-type electrode layer II; 12: electric field regulation layer II; 13: avalanche multiplication layer II; 14: n-type electrode layer; 15: n-electrode; 16: substrate oxide layer; 17: substrate; 18: anode electrode; 19: fixed oxide layer; 20: cathode electrode; 21: SiO2; 22: N++ layer; 23: P++ layer; 24: Pwell; 25: NDwell; 26: p-type electric field modulation layer; 27: multiplication region; 28: absorption region; DETAILED DESCRIPTION

[0021] Hereinafter, the present invention will be described in detail with specific embodiments, but the invention of the present application is not limited to the following description. In addition, in this specification and the drawings, components with the same reference numerals represent the same parts.

[0022] Implementation Method 1

[0023] Figure 1It is a cross-sectional schematic diagram of the APD using the p-type electrode layer II11 of the present invention. There is a substrate oxide layer 16 on the substrate 17, and there are a p-type electrode layer I4, a p-type light absorption layer 5, an electric field control layer I6, an avalanche multiplication layer I7, an n-type transition layer 8, an electron traveling layer 9 with a low impurity concentration, an electric field control layer II12, an avalanche multiplication layer II13, and an n-type electrode layer 14 on the substrate oxide layer 16 from left to right. The p-type electrode layer II11 is embedded in the region of the electron traveling layer 9 with a low impurity concentration. The layers arranged in sequence on the substrate oxide layer 16 are surrounded by an electric field isolation ring layer 2. The outer region of the electric field isolation ring layer 2 is an intrinsic layer 1. There is a p-electrode I3 on ​​the p-type electrode layer I4, a p-electrode II10 on the p-type electrode layer II11, and an n-electrode 15 on the n-type electrode layer 14.

[0024] This example uses the Smart-cut process to thermally oxidize a silicon wafer at room temperature and inject a certain amount of H + , bond it to another silicon wafer, then perform low temperature annealing to allow the injected hydrogen ions to form bubbles to peel off the silicon wafer, then perform high temperature annealing to enhance the bonding strength, and then flatten the silicon surface to prepare a substrate oxide layer 16 with a thickness of 1um and an epitaxial layer with a thickness of 2um. In the epitaxial layer, an ion implantation process is used to prepare a 0.5um p-type electrode layer I4, a 2um p-type light absorption layer 5, a 0.2um electric field control layer I6, a 0.2um avalanche multiplication layer I7, a 0.5um n-type transition layer 8, a 1.7um low impurity concentration electron travel layer 9, a 0.2um electric field control layer II12, a 0.2um avalanche multiplication layer II13, and a 0.5um n-type electrode layer 14. The width of each layer is 2um and the depth is 2um. The p-type electrode layer II11 is located between the n-type transition layer 8 and the electric field control layer II12, and the distance between it and the n-type transition layer 8 is 0.5um. It is prepared by ion implantation process, with a width of 2um and a depth of 1um. Shallow trench isolation rings or LOCOS (Local Oxidation of Silicon) isolation are used in the electric field isolation ring layer 2, so as to effectively isolate the electric field of the two-stage avalanche structure and suppress the occurrence of edge breakdown.

[0025] Implementation Method 2

[0026] Figure 1It is a cross-sectional schematic diagram of the APD using the p-type electrode layer II11 of the present invention. The same structure as the first embodiment is used to prepare a substrate oxide layer 16 with a thickness of 0.5um and an epitaxial layer with a thickness of 1um. In the epitaxial layer, an ion implantation process is used to prepare a p-type electrode layer I4 with a length of 0.5um, a p-type light absorption layer 5 with a thickness of 2um, an electric field control layer I6 with a thickness of 0.2um, a avalanche multiplication layer I7 with a thickness of 0.5um, an n-type transition layer 8 with a length of 1.7um, an electron traveling layer 9 with a low impurity concentration of 0.2um, an electric field control layer II12 with a thickness of 0.2um, and an n-type electrode layer 14 with a thickness of 0.5um. The width of each layer is 2um and the depth is 1um. The p-type electrode layer II11 is located between the n-type transition layer 8 and the electric field control layer II12, and the distance between it and the n-type transition layer 8 is 0.5um. It is prepared by an ion implantation process, and has a width of 2um and a depth of 0.5um. Shallow trench isolation rings or LOCOS (Local Oxidation of Silicon) isolation are used in the electric field isolation ring layer 2, so as to effectively isolate the electric field of the two-stage avalanche structure and suppress the occurrence of edge breakdown.

[0027] Implementation 3

[0028] Figure 1 It is a cross-sectional schematic diagram of the APD using the p-type electrode layer II11 of the present invention. The same structure as the first embodiment is used to prepare a substrate oxide layer 16 with a thickness of 0.1um and an epitaxial layer with a thickness of 0.1um. In the epitaxial layer, a diffusion process is used to prepare a p-type electrode layer I4 with a length of 0.5um, a p-type light absorption layer 5 with a thickness of 2um, an electric field control layer I6 with a thickness of 0.2um, a avalanche multiplication layer I7 with a thickness of 0.5um, an n-type transition layer 8 with a length of 1.7um, an electron traveling layer 9 with a low impurity concentration, a 0.2um electric field control layer II12, a 0.2um avalanche multiplication layer II13, and a 0.5um n-type electrode layer 14. The width of each layer is 2um and the depth is 0.1um. The p-type electrode layer II11 is located between the n-type transition layer 8 and the electric field control layer II12, and the distance between it and the n-type transition layer 8 is 0.5um. It is prepared by ion implantation process, with a width of 2um and a depth of 0.05um. Shallow trench isolation rings or LOCOS (Local Oxidation of Silicon) isolation are used in the electric field isolation ring layer 2, so as to effectively isolate the electric field of the two-stage avalanche structure and suppress the occurrence of edge breakdown.

[0029] The present invention has been described above by means of specific embodiments, but the present invention is not limited to these specific embodiments. It should be understood by those skilled in the art that various modifications, material replacements, changes, etc. may be made to the present invention, and these changes should be within the scope of protection of the present invention as long as they do not deviate from the spirit of the present invention.

Claims

1. A cascade avalanche multiplication photodiode, characterized in that: A substrate oxide layer (16) is disposed on the substrate (17). From left to right, a p-type electrode layer I (4), a p-type light absorption layer (5), an electric field control layer I (6), an avalanche multiplication layer I (7), an n-type transition layer (8), an electron traveling layer (9) with a low impurity concentration, an electric field control layer II (12), an avalanche multiplication layer II (13), and an n-type electrode layer (14) are disposed on the substrate oxide layer (16). The p-type electrode layer II (11) is embedded in the region of the electron traveling layer (9) with a low impurity concentration. The layers arranged in sequence on the substrate oxide layer (16) are surrounded by an electric field isolation ring layer (2). An intrinsic layer (1) is disposed in the outer region of the electric field isolation ring layer (2). A p-electrode I (3) is disposed on the p-type electrode layer I (4), a p-electrode II (10) is disposed on the p-type electrode layer II (11), and an n-electrode (15) is disposed on the n-type electrode layer (14).

2. The cascade avalanche multiplication photodiode according to claim 1, characterized in that: The n-type transition layer (8) is an n-type region with a high impurity concentration.

3. The cascade avalanche multiplication photodiode according to claim 1, characterized in that: The electron travelling layer (9) with low impurity concentration is a p-type region with low impurity concentration.

4. The cascade avalanche multiplication photodiode according to claim 1, characterized in that: The thickness of the substrate oxide layer (16) on the substrate (17) is 0.1 μm to 1.0 μm.

5. The cascade avalanche multiplication photodiode according to claim 1, characterized in that: The thickness of each layer on the substrate oxide layer (16) is consistent, and the thickness is 0.1 μm to 2.0 μm.

Images