Display device

Abstract

A display device is provided. The display device includes: a base layer including: a first area in which a hole is defined; a second area surrounding the first area; and a third area surrounding the second area; a line portion provided in the second area and including a first line, a second line, a third line, and a fourth line provided on different layers from each other; a pixel provided in the third area; a first signal line electrically connected to the pixel and arranged in a first direction; and a second signal line electrically connected to the pixel and arranged in a second direction, wherein one second signal line is electrically connected to the first line, another second signal line is electrically connected to the second line, one first signal line is electrically connected to the third line, and another first signal line is electrically connected to the fourth line.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0150963, filed on November 29, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention relate generally to a display device, and more particularly, to a display device including an electronic module having improved sensing sensitivity and display quality. Background Art

[0003] The display device may be a device constructed of various electronic components such as a display panel for displaying an image, an input sensing member for sensing an external input, and an electronic module. The electronic components may be electrically connected to each other through signal lines arranged in various ways. The display panel includes a light-emitting element that generates light. The input sensing member may include a sensing electrode for sensing an external input. The electronic module may include a camera, an infrared sensing sensor, and / or a proximity sensor, etc. The electronic module may be arranged under the display panel.

[0004] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0005] A device constructed according to an exemplary embodiment of the invention provides a display device including an electronic module having improved sensing sensitivity and improved display quality.

[0006] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0007] According to one or more exemplary embodiments of the invention, a display device includes: a base layer including: a first area, in which a hole is defined; a second area, which is configured to surround the first area; and a third area, which is configured to surround the second area; a line portion, which is arranged in the second area and includes a first line, a second line, a third line and a fourth line arranged on different layers from each other; a pixel, which is arranged in the third area; a first signal line, which is electrically connected to the pixel and arranged along a first direction; and a second signal line, which is electrically connected to the pixel and arranged along a second direction intersecting the first direction, wherein one of the second signal lines is electrically connected to the first line, another of the second signal lines is electrically connected to the second line, one of the first signal lines is electrically connected to the third line, and another of the first signal lines is electrically connected to the fourth line.

[0008] The display device may further include: a first insulating layer arranged between the first line and the second line; a second insulating layer arranged between the second line and the third line; and a third insulating layer arranged between the third line and the fourth line, wherein the first line, the first insulating layer, the second line, the second insulating layer, the third line, the third insulating layer and the fourth line are sequentially arranged on the substrate layer.

[0009] Each pixel may include: a transistor, including: a control electrode, which is arranged on the same layer on which the first line is arranged; and an output electrode and an input electrode, which are arranged on the same layer on which the third line is arranged; a connecting electrode, which is arranged on the same layer on which the fourth line is arranged; and a light-emitting element, which is electrically connected to the connecting electrode.

[0010] In a plan view, the first line and the second line may not overlap, and the third line and the fourth line may not overlap.

[0011] The second line may be disposed between a layer on which the first line is disposed and a layer on which the third line is disposed, and the third line may be disposed between a layer on which the second line is disposed and a layer on which the fourth line is disposed.

[0012] In a plan view, the first line, the second line, the third line, and the fourth line may be repeatedly arranged in the order of the first line, the third line, the second line, and the fourth line.

[0013] In a plan view, a portion of the third line may overlap a portion of the first line, and another portion of the third line may overlap a portion of the second line.

[0014] In a plan view, a portion of the fourth line may overlap another portion of the first line, and another portion of the fourth line may overlap another portion of the second line.

[0015] In a plan view, the third line may overlap one of the first line and the second line, and the fourth line may overlap the other of the first line and the second line.

[0016] In a plan view, the first line, the second line, the third line, and the fourth line may be repeatedly arranged in the order of the second line, the third line, the first line, and the fourth line.

[0017] The first region may include a plurality of first regions, each of the plurality of first regions is separately provided, and the second region may surround the plurality of first regions.

[0018] The display device may further include: a non-luminescent pixel disposed in the second region between the plurality of first regions.

[0019] According to one or more exemplary embodiments of the invention, a display device includes: a base layer including: a first area, in which a hole is defined; a second area, which is configured to surround the first area; and a third area, which is configured to surround the second area; a pixel, which is arranged in the third area; a first signal line, which is electrically connected to the pixel; a second signal line, which is electrically connected to the pixel; a first line, which is arranged in the second area and is electrically connected to one of the second signal lines; a second line, which is arranged in the second area and is electrically connected to another of the second signal lines; a third line, which is arranged in the second area and is electrically connected to one of the first signal lines; and a fourth line, which is arranged in the second area and is electrically connected to another of the first signal lines, wherein the first line, the second line, the third line and the fourth line are arranged on different layers, and wherein the second line is arranged on a layer between the first line and the third line, the third line is arranged on a layer between the second line and the fourth line, and in a plan view, the first line does not overlap with the second line, and the third line does not overlap with the fourth line.

[0020] In a plan view, the first line, the second line, the third line, and the fourth line are repeatedly arranged in the order of the first line, the third line, the second line, and the fourth line.

[0021] In a plan view, a portion of the third line may overlap with a portion of the first line, and another portion of the third line may overlap with a portion of the second line, and in a plan view, a portion of the fourth line may overlap with another portion of the first line, and another portion of the fourth line may overlap with another portion of the second line.

[0022] In a plan view, the third line may overlap one of the first line and the second line, and the fourth line may overlap the other of the first line and the second line.

[0023] The base layer, the pixel, the first signal line, the second signal line, and the first line, the second line, the third line and the fourth line can constitute a display module, and the display module includes: a first module area, which is defined as overlapping with the first area; a second module area, which is defined as overlapping with the second area; and a third module area, which is defined as overlapping with the third area. The transmittance of the first module area can be higher than the transmittance of the third module area.

[0024] According to one or more exemplary embodiments of the invention, a display device includes: a display panel, in which a non-display area and a display area configured to surround the non-display area are defined, the display panel including: a base layer, in which a hole is defined in an area of ​​the base layer configured to correspond to the non-display area; a line portion arranged in a peripheral area of ​​the hole of the base layer, the line portion including a first line, a second line, a third line, and a fourth line arranged on different layers from each other; and a pixel electrically connected to the line portion, wherein, in a plan view, the first line and the second line are not overlapped, and the third line and the fourth line are not overlapped.

[0025] The second line may be disposed between a layer on which the first line is disposed and a layer on which the third line is disposed, and the third line may be disposed between a layer on which the second line is disposed and a layer on which the fourth line is disposed.

[0026] In a plan view, a portion of the third line may overlap with a portion of the first line, and another portion of the third line may overlap with a portion of the second line, and in a plan view, a portion of the fourth line may overlap with another portion of the first line, and another portion of the fourth line may overlap with another portion of the second line.

[0027] According to one or more exemplary embodiments of the invention, a display device includes: a display panel, in which a non-display area and a display area configured to surround the non-display area are defined, the non-display area including: a first area, in which a hole is defined; and a second area, which is configured to surround the first area, the display panel including: a line portion, which is arranged in the second area and includes a first line portion and a second line portion which are arranged on layers different from each other; a pixel, which is arranged in the display area; a first signal line, which is arranged in the display area, the first signal line is arranged along a first direction, and the first signal line is electrically connected to the pixel and the first line portion; and a second signal line, which is arranged in the display area, the second signal line is arranged along a second direction intersecting the first direction, and the second signal line is electrically connected to the pixel and the second line portion, wherein, in a plan view, the first line portion is arranged in an area between the second line portions.

[0028] The first line portion includes a first line and a second line disposed on different layers from each other, and the second line portion includes a third line and a fourth line disposed on different layers from each other.

[0029] The third line is disposed on a layer between the second line and the fourth line.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0032] Figure 1A is a perspective view of a display device according to an exemplary embodiment.

[0033] Figure 1B is an exploded perspective view of a display device according to an exemplary embodiment.

[0034] Figure 2 is a block diagram of a display device according to an exemplary embodiment.

[0035] Figure 3A is a plan view of a display panel according to an exemplary embodiment.

[0036] Figure 3B is an equivalent circuit diagram of a pixel according to an exemplary embodiment.

[0037] Figure 4 is a plan view of an input sensing unit according to an exemplary embodiment.

[0038] Figure 5 yes Figure 3A An enlarged plan view of the XX' region shown in FIG.

[0039] Figure 6 is a cross-sectional view of a display panel according to an exemplary embodiment.

[0040] Fig. 7A is a cross-sectional view of a display panel according to an exemplary embodiment.

[0041] Figure 7B is a cross-sectional view of a display panel according to an exemplary embodiment.

[0042] Fig. 8A is a cross-sectional view of a display panel according to an exemplary embodiment.

[0043] Figure 8B is a cross-sectional view of a display panel according to an exemplary embodiment.

[0044] Fig.9A is a cross-sectional view of a display panel according to an exemplary embodiment.

[0045] Fig. 9B is a cross-sectional view of a display panel according to an exemplary embodiment.

[0046] Fig. 10A is a cross-sectional view of a display panel according to an exemplary embodiment.

[0047] Fig. 10Bis a cross-sectional view of a display panel according to an exemplary embodiment.

[0048] Fig.11A is along Figure 5 0 is a cross-sectional view of the display panel taken along the section line II′ shown in FIG.

[0049] Fig. 11B yes Figure 5 An enlarged plan view of the YY' region shown in FIG.

[0050] Fig. 12A is along Figure 5 A cross-sectional view taken along the section line II' shown in FIG.

[0051] Fig. 12B yes Figure 5 An enlarged plan view of the YY' region shown in FIG.

[0052] Fig.13A is along Figure 5 A cross-sectional view taken along the section line II' shown in FIG.

[0053] Fig. 13B yes Figure 5 An enlarged plan view of the YY' region shown in FIG.

[0054] Fig.14A is along Figure 5 A cross-sectional view taken along the section line II' shown in FIG.

[0055] Fig. 14B yes Figure 5 An enlarged plan view of the YY' region shown in FIG.

[0056] Fig.15 is an exploded perspective view of a display device according to an exemplary embodiment.

[0057] Fig.16 yes Fig.15 An enlarged plan view of a portion of the display module is shown in FIG.

[0058] Fig.17A is a cross-sectional view of a display panel according to an exemplary embodiment.

[0059] Fig. 17B is a cross-sectional view of a display panel according to an exemplary embodiment.

[0060] Fig. 17C is a cross-sectional view of a display panel according to an exemplary embodiment.

[0061] Fig.18 is an exploded perspective view of a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0062] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid making various exemplary embodiments unnecessarily obscure, well-known structures and devices are shown in block diagram form. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0063] Unless otherwise specified, the illustrated exemplary embodiments will be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements" or "multiple elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0064] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or demand for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two continuously described processes may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0065] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intermediate elements or intermediate layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intermediate elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis, and the z-axis), and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be named as the second element.

[0067] For descriptive purposes, spatially relative terms such as "below," "beneath," "below," "above," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another (or other) element(s) as shown in the accompanying drawings. In addition to including the orientations depicted in the accompanying drawings, the spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, elements or features described as "below" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. In addition, the device may be positioned otherwise (e.g., rotated 90 degrees or at other orientations), so the spatially relative descriptors used herein are interpreted accordingly.

[0068] The terms used here are for the purpose of describing specific embodiments, and are not intended to be limiting. As used here, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used here, the terms "substantially", "about (approximately)" and other similar terms are used as approximate terms and not as degree terms, and are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0069] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but will include deviations in shapes due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0070] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings with functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units and / or modules by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs certain functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless so clearly defined herein.

[0072] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings.

[0073] Figure 1A is a perspective view of a display device according to an exemplary embodiment. Figure 1B is an exploded perspective view of a display device according to an exemplary embodiment. Figure 2 is a block diagram of a display device according to an exemplary embodiment. Figure 1A , Figure 1B and Figure 2 Exemplary embodiments are described.

[0074] The display device EA may be a device activated according to an electrical signal. The display device EA may include various embodiments. For example, the display device EA may include a tablet computer, a notebook computer, a computer, or a television, etc. According to an exemplary embodiment, the display device EA is exemplarily shown as a smart phone.

[0075] The display device EA may display an image IM toward a third direction DR3 on a display surface FS parallel to the first direction DR1 and the second direction DR2. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device EA and the front surface FS of the window 100. Hereinafter, the display surface FS and the front surface of the display device EA and the front surface FS of the window 100 will be denoted by the same reference numerals. The image IM may include a still image as well as a moving image. Figure 1A , a clock window and application icons are shown as examples of image IM.

[0076] According to an exemplary embodiment, based on the direction in which the image IM is displayed, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal directions of the front surface and the rear surface can be parallel to the third direction DR3. On the other hand, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are concepts relative to each other and can be changed to other directions. In the following, the first direction to the third direction are directions represented by the first direction to the third direction DR1, DR2, and DR3, respectively, and are represented by the same reference numerals.

[0077] The display apparatus EA may include a window 100, a display module 200, a driving circuit unit 300, a housing 400, and an electronic module 500. According to an exemplary embodiment, the window 100 and the housing 400 are combined to provide an external appearance of the display apparatus EA.

[0078] The window 100 may include an optically transparent insulating material. For example, the window 100 may include glass or plastic. The window 100 may have a multilayer structure or a single-layer structure. For example, the window 100 may include a plurality of plastic films bonded by an adhesive or a glass substrate and a plastic film bonded by an adhesive.

[0079] The window 100 may be divided into a transmission area TA and a frame area BZA on a plane. In the present specification, the expression "on a plane" may mean when viewed from a third direction DR3. In addition, "thickness direction" may mean the third direction DR3.

[0080] The transmission area TA may be an optically transparent area. The frame area BZA may have a relatively low optical transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA.

[0081] The bezel area BZA may have a specified color. The bezel area BZA may cover the peripheral area NAA of the display module 200 to prevent the peripheral area NAA from being visually recognized. On the other hand, these are shown exemplarily, and the bezel area BZA may be omitted in the window 100 according to the exemplary embodiment.

[0082] In an exemplary embodiment, the sensor areas SA1 and SA2 may be areas configured to overlap with the electronic module 500 to be described later. The display device EA may receive an external signal required by the electronic module 500 through the sensor areas SA1 and SA2, or provide a signal output from the electronic module 500 to the outside. In an exemplary embodiment, the sensor areas SA1 and SA2 may be defined to overlap with the transmission area TA. Therefore, a separate area for setting the sensor areas SA1 and SA2 may be omitted in an area other than the transmission area TA. Therefore, the area of ​​the bezel area BZA may be reduced.

[0083] Figure 1B The sensor areas SA1 and SA2 are exemplarily shown to be two, but the exemplary embodiment is not limited thereto. For example, the sensor areas SA1 and SA2 may be defined as three or more, or one of them may be omitted and defined as one. Figure 1B, the sensor areas SA1 and SA2 are exemplarily defined at the upper left side of the transmission area TA, but may be defined at various areas of the transmission area TA, such as the upper right side, the central portion, the lower left side, or the lower right side. In addition, one sensor area SA1 may be defined at the upper left side of the transmission area TA, and the other sensor area SA2 may be defined at the upper right side of the transmission area TA.

[0084] The display module 200 may be disposed under the window 100. In the present specification, "under" may mean a direction opposite to a direction in which the display module 200 provides an image IM. The display module 200 may display the image IM and sense an external input TC. The display module 200 includes a front surface IS including an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal.

[0085] According to an exemplary embodiment, the active area AA may be an area in which an image IM is displayed and an external input TC is sensed. The transmissive area TA at least overlaps the active area AA. For example, the transmissive area TA overlaps the entire surface or at least a portion of the active area AA. Therefore, a user may visually recognize the image IM through the transmissive area TA or provide an external input TC through the transmissive area TA.

[0086] The peripheral area NAA may be covered by the frame area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may surround the active area AA. In the peripheral area NAA, a driving circuit or a driving line for driving the active area AA may be provided.

[0087] According to an exemplary embodiment, the display module 200 is assembled in a planar state in which the active area AA and the peripheral area NAA face the window 100. However, this is merely exemplary, and a portion of the peripheral area NAA may be curved. At this time, a portion of the peripheral area NAA faces the rear surface of the display device EA, which reduces the area of ​​the border area BZA from the front surface of the display device EA. Optionally, the display module 200 may also be assembled in a state in which a portion of the active area AA is also curved. Optionally, in the display module 200 according to an exemplary embodiment, the peripheral area NAA may be omitted.

[0088] The display module 200 may include a display panel 210 and an input sensing unit 220 .

[0089] The display panel 210 may be a component configured to basically generate an image IM. The image IM generated by the display panel 210 is displayed on the front surface IS and is visually recognized by a user from the outside.

[0090] The input sensing unit 220 senses an external input TC applied externally. For example, the input sensing unit 220 may sense an external input TC provided to the window 100. The external input TC may be a user input. The user input includes various types of external inputs, such as a part of the user's body, light, heat, a pen, or pressure. According to an exemplary embodiment, the external input TC is shown as a user's hand applied to the front surface FS. However, this is merely exemplary, and as described above, the external input TC may be provided in various types. In addition, depending on the structure of the display device EA, an external input TC applied to the side surface or rear surface of the display device EA may also be sensed, and the embodiment is not limited thereto.

[0091] The driving circuit unit 300 may be electrically connected to the display panel 210 and the input sensing unit 220. The driving circuit unit 300 may include a main circuit board MB, a first flexible film CF1, and a second flexible film CF2.

[0092] The first flexible film CF1 is electrically connected to the display panel 210. The first flexible film CF1 may connect the display panel 210 with the main circuit board MB. The first flexible film CF1 may be connected to a pad (or "pad") (display pad) of the display panel 210 provided in the peripheral area NAA. The first flexible film CF1 provides an electrical signal for driving the display panel 210 to the display panel 210. The electrical signal may be generated from the first flexible film CF1 or the main circuit board MB.

[0093] The second flexible film CF2 is electrically connected to the input sensing unit 220. The second flexible film CF2 may connect the input sensing unit 220 to the main circuit board MB. The second flexible film CF2 may be connected to a pad (sensing pad) of the input sensing unit 220 disposed in the peripheral area NAA. The second flexible film CF2 provides an electrical signal for driving the input sensing unit 220 to the input sensing unit 220. The electrical signal may be generated from the second flexible film CF2 or the main circuit board MB.

[0094] The main circuit board MB may include various types of driving circuits for driving the display module 200 or a connector for supplying power, etc. The first flexible film CF1 and the second flexible film CF2 may be connected to the main circuit board MB. According to an exemplary embodiment, the display module 200 may be easily controlled by one main circuit board MB. However, this is merely exemplary, and in the display module 200 according to the exemplary embodiment, the display panel 210 and the input sensing unit 220 may be connected to different main circuit boards, or any one of the first flexible film CF1 and the second flexible film CF2 may not be connected to the main circuit board MB. The inventive concept is not limited to any one embodiment.

[0095] In an exemplary embodiment, one area of ​​the display module 200 corresponding to the sensor areas SA1 and SA2 may have a relatively high transmittance compared to the active area AA not overlapping the sensor areas SA1 and SA2. For example, at least a portion of the components of the display panel 210 and the components of the input sensing unit 220 may be removed. Therefore, the electronic module 500 disposed overlapping the sensor areas SA1 and SA2 may easily transmit and / or receive signals through the sensor areas SA1 and SA2.

[0096] Figure 1B It is exemplarily shown that designated holes MH1 and MH2 (hereinafter, referred to as module holes) are defined in one area of ​​the display module 200 corresponding to the sensor areas SA1 and SA2. The module holes MH1 and MH2 may be defined in the active area AA to penetrate the display module 200. The module holes MH1 and MH2 may penetrate the display panel 210 and the input sensing unit 220. In other words, the module holes MH1 and MH2 may be defined by removing all components of the display panel 210 that are overlapped with the sensor areas SA1 and SA2 and all components of the input sensing unit 220 that are overlapped with the sensor areas SA1 and SA2. The module holes MH1 and MH2 are defined in the active area AA, and thus the sensor areas SA1 and SA2 may be disposed in the transmissive area TA.

[0097] The electronic module 500 may include a first electronic module 501 and a second electronic module 502. On a plane, the first electronic module 501 and the second electronic module 502 may overlap the module holes MH1 and MH2 and the sensor areas SA1 and SA2. The first electronic module 501 and the second electronic module 502 may be disposed below the display module 200, or at least a portion of the first electronic module 501 and at least a portion of the second electronic module 502 may be accommodated in the module holes MH1 and MH2. The first electronic module 501 and the second electronic module 502 may receive an external input transmitted through the sensor areas SA1 and SA2, or provide an output through the sensor areas SA1 and SA2.

[0098] The housing 400 is coupled to the window 100. The housing 400 is coupled to the window 100 to provide an internal space. The display module 200 and the electronic module 500 may be accommodated in the internal space.

[0099] The housing 400 may include a material having a relatively high hardness. For example, the housing 400 may include a plurality of frames and / or plates including glass, plastic, metal, or a combination thereof. The housing 400 may stably protect the components of the display device EA housed in the internal space from external impacts.

[0100] about Figure 2, the display device EA may include a display module 200, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module 200, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0101] The power module PM supplies power required for general operations of the display apparatus EA. The power module PM may include a typical battery module.

[0102] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the display apparatus EA.

[0103] The first electronic module EM1 may be directly mounted in a mother board electrically connected to the display module 200 , or may be mounted in a separate board and electrically connected to the mother board through a connector or the like.

[0104] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, a sound (audio) input module AIM, a memory MM, and an external interface IF. Some modules are not mounted in the motherboard and may be electrically connected to the motherboard through a flexible circuit board.

[0105] The control module CM may control the general operation of the display device EA. The control module CM may be a microprocessor. For example, the control module CM may activate or deactivate the display module 200. The control module CM may control other modules such as the image input module IIM or the sound input module AIM based on a touch signal received from the display module 200.

[0106] The wireless communication module TM can use Bluetooth or Wi-Fi lines to receive wireless signals from another terminal or transmit wireless signals to another terminal. The wireless communication module TM can use typical communication lines to transmit / receive voice signals. The wireless communication module TM may include: a transmission unit TM1 that modulates the signal to be transmitted and transmits the modulated signal; and a receiving unit TM2 that demodulates the received signal.

[0107] The image input module IIM processes the image signal to convert the processed signal into image data displayable on the display module 200. The sound input module AIM receives an external sound signal through a microphone in a recording mode or a voice recognition mode to convert the sound signal into electrical voice data.

[0108] The external interface IF may function as an interface connected to an external charger, a wired / wireless data port, or a card slot (eg, of a memory card, a SIM / UIM card), and the like.

[0109] The second electronic module EM2 may include an audio output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, etc. The above components may be directly mounted in the motherboard, or mounted in a separate board to be electrically connected to the display module 200 or the first electronic module EM1 through a connector, etc.

[0110] The sound output module AOM converts sound data received from the wireless communication module TM or sound data stored in the memory MM, and outputs the converted sound data to the outside.

[0111] The light emitting module LM generates output light. The light emitting module LM may output infrared rays. The light emitting module LM may include an LED element. The light receiving module LRM may sense infrared rays. When infrared rays of a specified level or higher are sensed, the light receiving module LRM may be activated. The light receiving module LRM may include a CMOS sensor. After the infrared rays generated in the light emitting module LM are output, the infrared rays are reflected by an external object (e.g., a user's finger or face), and the reflected infrared rays are incident on the light receiving module LRM. The camera module CMM may capture external images.

[0112] Each of the first electronic module 501 and the second electronic module 502 according to an exemplary embodiment may include at least any one of the first electronic module EM1 and the second electronic module EM2. For example, each of the first electronic module 501 and the second electronic module 502 may include a sound output module AOM, a light emitting module LM, a light receiving module LRM, a camera module CMM, and a thermal sensing module. The first electronic module 501 and the second electronic module 502 may sense an external object by a signal received from the sensor areas SA1 and SA2, or may provide a sound signal such as voice or light such as infrared rays to the outside through the sensor areas SA1 and SA2.

[0113] In an exemplary embodiment, the power module PM, the first electronic module EM1, the second electronic module EM2 and / or one or more components thereof can be implemented via one or more general components and / or dedicated components (such as one or more discrete circuits, digital signal processing chips, integrated circuits, dedicated integrated circuits, microprocessors, processors, programmable arrays, field programmable gate arrays and / or instruction set processors, etc.).

[0114] According to one or more exemplary embodiments, the features, functions, processes, etc. described herein may be implemented via software, hardware (e.g., a general-purpose processor, a digital signal processing (DSP) chip, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.), firmware, or a combination thereof. In this manner, the power module PM, the first electronic module EM1, the second electronic module EM2, and / or one or more components thereof may include one or more memories, or be otherwise associated with one or more memories, the one or more memories including codes (e.g., instructions) configured to cause the power module PM, the first electronic module EM1, the second electronic module EM2, and / or one or more components thereof to perform one or more of the features, functions, processes, etc. described herein.

[0115] The memory can be any medium that participates in providing code for execution to one or more software, hardware and / or firmware components. Such memory can be implemented in any suitable form, including but not limited to non-volatile media, volatile media and transmission media. Non-volatile media include, for example, optical disks or disks. Volatile media include dynamic memory. Transmission media include coaxial cables, copper wiring and optical fibers. Transmission media can also take the form of sound waves, light waves or electromagnetic waves. Common forms of computer-readable media include, for example, floppy disks, floppy disks, hard disks, tapes, any other magnetic media, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), digital video disks (DVD), rewritable DVDs (DVD-RW), any other optical media, punch cards, paper tapes, optical marking paper, any other physical medium with hole patterns or other optically identifiable markings, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), FLASH-EPROM, any other memory chip or cassette tape, carrier wave or any other medium from which information can be read by, for example, a controller / processor.

[0116] Figure 3A is a plan view of a display panel according to an exemplary embodiment. Figure 3B is an equivalent circuit diagram of a pixel according to an exemplary embodiment.

[0117] about Figure 3A and Figure 3B , the display panel 210 may include a base layer BS, a plurality of pixels PX, a plurality of signal lines SNL1 , SNL2 , and PL, and a plurality of display pads PDD.

[0118] The active area AA of the display panel 210 may be a region in which the image IM is displayed, and the peripheral area NAA may be a region in which a driving circuit, a driving line, etc. are disposed. Figure 3A, an active area AA and a peripheral area NAA of the display panel 210 are shown. A plurality of pixels PX may be disposed in the active area AA.

[0119] The base layer BS may be a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0120] The base layer BS may include first areas AR1a and AR1b, a second area AR2, and a third area AR3. The first areas AR1a and AR1b may be defined as separate. In a plan view, the second area AR2 may surround the first areas AR1a and AR1b, and the third area AR3 may surround the second area AR2. The first areas AR1a and AR1b, the second area AR2, and the third area AR3 may be surrounded by the peripheral area NAA. The pixel PX may be disposed in the third area AR3. In other words, the third area AR3 may correspond to the active area AA.

[0121] At least a portion of the first areas AR1a and AR1b may be an area configured to overlap with the sensor areas SA1 and SA2 on a plane. The module holes MH1 and MH2 may be defined in the at least a portion of the first areas AR1a and AR1b. In other words, the components of the display panel 210 may be removed from the area configured to correspond to the sensor areas SA1 and SA2, or may be disposed not to overlap with the sensor areas SA1 and SA2. Each of the module holes MH1 and MH2 may include a hole configured to penetrate the front and rear surfaces of the base layer BS.

[0122] The first regions AR1a and AR1b may surround the module holes MH1 and MH2 on a plane. A structure such as a groove portion or a dam portion for blocking a permeation path of external moisture or oxygen may be provided in the first regions AR1a and AR1b, and a description thereof will be provided later.

[0123] The pixel PX providing the image IM may not be arranged in the first area AR1a and AR1b and the second area AR2 of the base layer BS. Therefore, the area including the first area AR1a and AR1b and the second area AR2 of the base layer BS in the display panel 210 may be defined as a non-display area. The pixel PX may be arranged in the third area AR3 of the base layer BS. Therefore, the area including the third area AR3 of the base layer BS may be defined as a display area. In other words, the display area of ​​the display panel 210 may correspond to the third area AR3 of the base layer BS, and the non-display area of ​​the display panel 210 may correspond to the first area AR1a and AR1b and the second area AR2 of the base layer BS.

[0124] According to an exemplary embodiment, a non-display area surrounded by the display area on a plane may be provided. The non-display area may be configured to be parallel to the first electronic module 501 and the second electronic module 502 (see Figure 1B ) overlapped area. Therefore, a separate area formed to provide a sensor area in the edge of the display area can be omitted to reduce the area of ​​the frame area. The frame area can refer to an area configured to surround the display area.

[0125] A plurality of signal lines SNL1, SNL2, and PL are connected to the pixel PX to transmit an electrical signal to the pixel PX. A first signal line SNL1, a second signal line SNL2, and a power line PL are exemplarily shown among the signal lines included in the display panel 210. The first signal line SNL1 may be referred to as a data line. The first signal line SNL1 may be provided in plurality, and the plurality of first signal lines SNL1 may be arranged along a first direction DR1. The second signal line SNL2 may include a scan line GL and an emission control line ECL. The scan line GL and the emission control line ECL may be arranged along a second direction DR2. However, these are merely exemplary, and the signal lines SNL1 and SNL2 may further include an initialization voltage line. Exemplary embodiments are not limited thereto.

[0126] The plurality of signal lines SNL1, SNL2, and PL may be disposed in the third region AR3. The plurality of signal lines SNL1, SNL2, and PL may not be disposed in the first regions AR1a and AR1b.

[0127] exist Figure 3B In FIG. 1 , an equivalent circuit diagram of one pixel PX among a plurality of pixels PX is exemplarily enlarged and shown. Figure 3B , a pixel PX connected to an i-th scan line GLi and an i-th emission control line ECLi is exemplarily shown.

[0128] The pixel PX may include a light emitting element ELD and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC controls the amount of current flowing through the light emitting element ELD in response to a data signal.

[0129] The light emitting element ELD may emit light at a designated brightness corresponding to the amount of current supplied from the pixel circuit CC. To this end, the level of the first power source ELVDD may be set to be higher than the level of the second power source ELVSS.

[0130] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience, in this specification, any one of the input electrode and the output electrode may be referred to as a first electrode, and the other may be referred to as a second electrode.

[0131] A first electrode of the first transistor T1 is connected to the first power source ELVDD via the fifth transistor T5, and a second electrode of the first transistor T1 is connected to the anode electrode of the light emitting element ELD via the sixth transistor T6. In this specification, the first transistor T1 may be referred to as a driving transistor.

[0132] The first transistor T1 controls the amount of current flowing through the light emitting element ELD corresponding to a voltage applied to a control electrode of the first transistor T1 .

[0133] The second transistor T2 is connected between the first signal line SNL1 and the first electrode of the first transistor T1. In addition, the control electrode of the second transistor T2 is connected to the i-th scan line GLi. The second transistor T2 is turned on when the i-th scan signal is supplied to the i-th scan line GLi, and electrically connects the first signal line SNL1 and the first electrode of the first transistor T1.

[0134] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the i-th scan line GLi. The third transistor T3 is turned on when the i-th scan signal is supplied to the i-th scan line GLi, and electrically connects the second electrode of the first transistor T1 and the control electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in a diode type.

[0135] The fourth transistor T4 is connected between the node ND and the initialization power generation unit. In addition, the control electrode of the fourth transistor T4 is connected to the (i-1)th scan line GLi-1. The fourth transistor T4 is turned on when the (i-1)th scan signal is supplied to the (i-1)th scan line GLi-1, and supplies the initialization voltage Vint to the node ND.

[0136] The fifth transistor T5 is connected between the power line PL and the first electrode of the first transistor T1. A control electrode of the fifth transistor T5 is connected to the i-th emission control line ECLi.

[0137] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode electrode of the light emitting element ELD. In addition, a control electrode of the sixth transistor T6 is connected to the i-th emission control line ECLi.

[0138] The seventh transistor T7 is connected between the initialization power generation unit and the anode electrode of the light emitting element ELD. In addition, the control electrode of the seventh transistor T7 is connected to the (i+1)th scan line GLi+1. In this way, the seventh transistor T7 is turned on when the (i+1)th scan signal is supplied to the (i+1)th scan line GLi+1, and supplies the initialization voltage Vint to the anode electrode of the light emitting element ELD.

[0139] The seventh transistor T7 can improve the black level representation capability of the pixel PX. In detail, when the seventh transistor T7 is turned on, the parasitic capacitor of the light emitting element ELD is discharged. Then, when black brightness is achieved, the light emitting element ELD does not emit light due to the leakage current from the first transistor T1, and thus the black level representation capability can be improved.

[0140] In addition, although Figure 3B The control electrode of the seventh transistor T7 is shown to be connected to the (i+1)th scan line GLi+1, but the exemplary embodiment is not limited thereto. In another exemplary embodiment, the control electrode of the seventh transistor T7 may be connected to the i-th scan line GLi or the (i-1)-th scan line GLi-1.

[0141] Although the PMOS shows Figure 3B , but the exemplary embodiment is not limited thereto. In another exemplary embodiment, the pixel circuit CC may be constructed by NMOS. In another exemplary embodiment, the pixel circuit CC may be constructed by a combination of NMOS and PMOS.

[0142] The capacitor CP is provided between the power line PL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on according to the voltage stored in the capacitor CP, the amount of current flowing through the first transistor T1 can be determined. The equivalent circuit of the pixel PX in the inventive concept is not limited to Figure 3B In another exemplary embodiment, the pixel PX may be implemented in various types to drive the light emitting element ELD.

[0143] Again about Figure 3A , the power pattern VDD is disposed in the peripheral area NAA. In an embodiment, the power pattern VDD is connected to a plurality of power lines PL. Therefore, the display panel 210 includes the power pattern VDD, and thus substantially the same first power signal can be provided to a plurality of pixels PX.

[0144] The display pad PDD may include a first pad D1 and a second pad D2. The first pad D1 may be provided in plural and connected to the first signal line SNL1. The second pad D2 may be connected to the power pattern VDD and thus electrically connected to the power line PL. The display panel 210 may provide an electrical signal provided from the outside through the display pad PDD to the pixel PX. On the other hand, in addition to the first pad D1 and the second pad D2, the display pad PDD may further include a pad for receiving other electrical signals, and is not limited to any one embodiment.

[0145] Figure 4 is a plan view of an input sensing unit according to an exemplary embodiment.

[0146] about Figure 4 , the input sensing unit 220 may be disposed on the display panel 210. For example, the input sensing unit 220 may be directly disposed on the display panel 210, or may be combined with the display panel 210 through an adhesive member. Figure 1B ), when the input sensing unit 220 is provided in a continuous process, the input sensing unit 220 may be referred to as an input sensing layer. In addition, when the input sensing unit 220 is combined with the display panel 210 by an adhesive member, the input sensing unit 220 may be referred to as an input sensing panel.

[0147] The input sensing unit 220 includes a first sensing electrode TE1, a second sensing electrode TE2, a plurality of sensing lines TL1, TL2, and TL3, and a plurality of sensing pads PDT.

[0148] The first sensing electrode TE1 and the second sensing electrode TE2 are disposed in the active area AA. The input sensing unit 220 can obtain information about the external input TC (see FIG. 1 ) through a change in electrostatic capacitance between the first sensing electrode TE1 and the second sensing electrode TE2. Figure 1A ) information.

[0149] The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. At least one first connection pattern BP1 may be connected to two adjacent first sensing patterns SP1. The second sensing electrode TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. At least one second connection pattern BP2 may be connected to two adjacent second sensing patterns SP2.

[0150] The sensing lines TL1, TL2, and TL3 are disposed in the peripheral area NAA. The sensing lines TL1, TL2, and TL3 may include a first sensing line TL1, a second sensing line TL2, and a third sensing line TL3.

[0151] The first sensing line TL1 is connected to the first sensing electrode TE1. The second sensing line TL2 is connected to one terminal of the second sensing electrode TE2. The third sensing line TL3 is connected to the other terminal of the second sensing electrode TE2. The other terminal of the second sensing electrode TE2 may be a portion opposite to the one terminal of the second sensing electrode TE2.

[0152] According to an exemplary embodiment, the second sensing electrode TE2 may be connected to the second sensing line TL2 and the third sensing line TL3. Therefore, for the second sensing electrode TE2 having a relatively longer length than that of the first sensing electrode TE1, the sensitivity according to the area may be uniformly maintained. However, this is merely exemplary, and the third sensing line TL3 may be omitted. The inventive concept is not limited to any one embodiment.

[0153] The sensing pad PDT is disposed in the peripheral area NAA. The sensing pad PDT may include a first sensing pad TD1, a second sensing pad TD2, and a third sensing pad TD3. The first sensing pad TD1 is connected to the first sensing line TL1 to be electrically connected to the first sensing electrode TE1. The second sensing pad TD2 is connected to the second sensing line TL2, and the third sensing pad TD3 is connected to the third sensing line TL3. Therefore, the second sensing pad TD2 and the third sensing pad TD3 may be electrically connected to the second sensing electrode TE2.

[0154] Some components of the input sensing unit 220 may be removed in an area corresponding to the sensor areas SA1 and SA2. For example, at least a portion between a portion of the first sensing electrode TE1 and a portion of the second sensing electrode TE2 may not be provided in the sensor areas SA1 and SA2. According to an exemplary embodiment, the first sensing electrode TE1 disposed overlapping the sensor areas SA1 and SA2 includes a first sensing pattern having a shape in which a portion thereof is removed, and the second sensing electrode TE2 may include a second sensing pattern having a shape in which a portion thereof is removed.

[0155] According to an exemplary embodiment, the electronic module 500 (see FIG. 1 ) may be prevented or suppressed by removing a portion of the first sensing electrode TE1 and the second sensing electrode TE2 in a region overlapping the sensor areas SA1 and SA2. Figure 1B ) is covered by the first sensing electrode TE1 or the second sensing electrode TE2. Therefore, the sensing sensitivity of the electronic module 500 can be improved.

[0156] Figure 5 yes Figure 3A An enlarged plan view of the XX' region shown in FIG.

[0157] about Figure 5 , the base layer BS may include first regions AR1a and AR1b, a second region AR2, and a third region AR3.

[0158] The first areas AR1a and AR1b may be separated from each other in the first direction DR1. A module hole MH1 is defined in the first area AR1a, and a module hole MH2 is defined in the first area AR1b. The first area AR1a surrounds the module hole MH1, and the first area AR1b surrounds the module hole MH2.

[0159] The second area AR2 may surround the first areas AR1a and AR1b. The non-luminescent pixel PX-N may be disposed in a portion of the second area AR2 between the first areas AR1a and AR1b. In order to distinguish it from the pixel PX, the non-luminescent pixel PX-N is shown with hatching. The non-luminescent pixel PX-N may be a pixel that does not emit light. In other words, the non-luminescent pixel PX-N may be a pixel that displays black.

[0160] The third area AR3 may surround the second area AR2. The third area AR3 may be adjacent to the display panel 210 (see FIG. Figure 3A ) effective area AA (see Figure 3A The pixel PX may be disposed in the third area AR3.

[0161] The first signal line SNL1 and the second signal line SNL2 may be disposed in the third area AR3. The first line SLa, the second line SLb, the third line SLc, and the fourth line SLd may be disposed in the second area AR2. The first line SLa, the second line SLb, the third line SLc, and the fourth line SLd may be disposed on different layers, and a description thereof will be provided later. The second area AR2 may be referred to as a peripheral portion of a hole. The hole represents one of the holes defined in the base layer BS configured to provide the module holes MH1 and MH2. The first line SLa, the second line SLb, the third line SLc, and the fourth line SLd may be included in a line portion. The line portion may include a first line portion and a second line portion. The first line portion may include the first line SLa and the second line SLb, and the second line portion may include the third line SLc and the fourth line SLd.

[0162] One of the first signal lines SNL1 may be electrically connected to the third line SLc, and the other of the first signal lines SNL1 may be electrically connected to the fourth line SLd. The first signal line SNL1 may be electrically connected to the second line portion. One of the second signal lines SNL2 may be electrically connected to the first line SLa, and the other of the second signal lines SNL2 may be electrically connected to the second line SLb. The second signal line SNL2 may be electrically connected to the first line portion.

[0163] A boundary BDa between the first and second regions AR1a and AR2 and a boundary BDb between the first and second regions AR1b and AR2 may have a circular shape. The first, second, third, and fourth lines SLa, SLb, SLc, and SLd may have shapes corresponding to those of the boundaries BDa and BDb and may extend.

[0164] Figure 6 is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 6 is a cross-sectional view of the display panel 210 including the third area AR3 of the base layer BS. Figure 6 It may be a cross-sectional view of a region in which one pixel is provided.

[0165] about Figure 6 The first insulating layer 10 is disposed on the base layer BS. The first insulating layer 10 may include a barrier layer 11 and a buffer layer 12.

[0166] The barrier layer 11 may include an inorganic material. The barrier layer 11 may prevent or inhibit oxygen or moisture that flows into the barrier layer 11 through the base layer BS from penetrating into the pixel PX (see Figure 5 ). The buffer layer 12 may include an inorganic material. The buffer layer 12 may provide the pixel PX with a surface energy lower than that of the base layer BS, so that the pixel PX is stably disposed on the base layer BS. Figure 6 , each of the barrier layer 11 and the buffer layer 12 is shown as a single layer. However, this is only exemplary, and the barrier layer 11 and the buffer layer 12 according to the exemplary embodiment are provided in plural and can be alternately stacked. Alternatively, at least any one of the barrier layer 11 and the buffer layer 12 can be provided in plural or omitted.

[0167] Each pixel PX may include a pixel circuit CC (see Figure 3B ) and a light emitting element ELD. The pixel circuit CC may include transistors T1 to T7 (see Figure 3B ) and capacitor CP (see Figure 3B ) etc. Figure 6 In FIG. 1 , only one transistor TR is shown. The transistor TR may be Figure 3B A first transistor T1 is described.

[0168] The transistor TR may be disposed on the first insulating layer 10. The transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. The control electrode CE is separated from the semiconductor pattern SP, and the second insulating layer 20 is interposed therebetween. The control electrode CE may be connected to one electrode of the capacitor CP.

[0169] The input electrode IE and the output electrode OE may be separated from the control electrode CE with the third insulating layer 30 and the fourth insulating layer 40 interposed therebetween. The input electrode IE and the output electrode OE pass through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 to be connected to one side and the other side of the semiconductor pattern SP, respectively.

[0170] The upper electrode UE may be disposed between the third insulating layer 30 and the fourth insulating layer 40. The upper electrode UE may be connected to the other electrode of the capacitor CP.

[0171] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the input electrode IE and the output electrode OE. The fourth insulating layer 40 may include an organic material and / or an inorganic material, and have a single layer structure or a multi-layer structure.

[0172] The connection electrode CNE may be disposed on the fifth insulating layer 50. The connection electrode CNE may be connected to the output electrode OE. The sixth insulating layer 60 may be disposed on the connection electrode CNE.

[0173] The transistor TR according to the exemplary embodiment may be provided in various structures without limitation. Figure 6 The embodiment shown in .

[0174] The light emitting element ELD is disposed on the sixth insulating layer 60. The light emitting element ELD may include a first electrode E1, an emission layer EL, and a second electrode E2. The first electrode E1 may penetrate the sixth insulating layer 60 to be electrically connected to the transistor TR through the connection electrode CNE.

[0175] The seventh insulating layer 70 may be disposed on the sixth insulating layer 60. An opening portion is defined in the seventh insulating layer 70, and the opening portion may expose at least a portion of the first electrode E1. The seventh insulating layer 70 may be a pixel defining layer.

[0176] The emission layer EL may be disposed on the first electrode E1 exposed by the opening portion defined in the seventh insulating layer 70. The emission layer EL may include a light-emitting material. For example, the emission layer EL may be provided with at least any one of a material emitting red light, green light, or blue light. The emission layer EL may include a fluorescent material or a phosphorescent material. The emission layer EL may include an organic light-emitting material and an inorganic light-emitting material. The emission layer EL may emit light in response to a potential difference between the first electrode E1 and the second electrode E2.

[0177] The second electrode E2 may be disposed on the emission layer EL. The second electrode E2 may have a width from the active area AA (see FIG. Figure 3A ) extends to the peripheral area NAA (see Figure 3A ) of an integrated shape. It can be a plurality of pixels PX (see Figure 3A ) The second electrode E2 is commonly provided. The light emitting elements ELD provided at the respective pixels PX receive a common second power supply voltage through the second electrode E2.

[0178] The second electrode E2 may include a transmissive conductive material or a semi-transmissive conductive material. Therefore, the light generated by the emission layer EL can be easily emitted toward the third direction DR3 through the second electrode E2. However, this is only exemplary, and the light emitting element ELD designed according to the exemplary embodiment can be driven in a bottom emission scheme in which the first electrode E1 includes a transmissive or semi-transmissive material, or can be driven in a dual emission scheme in which light is emitted toward both the front surface and the rear surface. The inventive concept is not limited to any one embodiment.

[0179] The eighth insulating layer 80 is disposed on the light emitting element ELD to encapsulate the light emitting element ELD. According to an exemplary embodiment, the eighth insulating layer 80 may be an encapsulation layer. The encapsulation layer 80 may have a thickness from the active area AA (see Figure 3A ) extends to the peripheral area NAA (see Figure 3A On the other hand, although not shown, a cap layer configured to cover the second electrode E2 may be provided between the second electrode E2 and the eighth insulating layer 80.

[0180] The eighth insulating layer 80 may include a first inorganic layer 81, an organic layer 82, and a second inorganic layer 83 sequentially stacked along the third direction DR3. According to an exemplary embodiment, each of the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 is shown as a single layer. However, this is only exemplary. At least one of the first inorganic layer 81, the organic layer 82, and the second inorganic layer 83 may be provided in plural or omitted. The inventive concept is not limited to any one embodiment.

[0181] The first inorganic layer 81 may cover the second electrode E2. The first inorganic layer 81 may prevent or inhibit external moisture or oxygen from penetrating into the light emitting element ELD. For example, the first inorganic layer 81 may include silicon nitride, silicon oxide, or a mixture thereof. The first inorganic layer 81 may be provided by a deposition process.

[0182] The organic layer 82 may be disposed on the first inorganic layer 81 to contact the first inorganic layer 81. The organic layer 82 may provide a flat surface on the first inorganic layer 81. In detail, the organic layer 82 may provide a flat surface in the active area AA.

[0183] The curve of the upper surface of the first inorganic layer 81 or particles existing on the first inorganic layer 81 may be covered by the organic layer 82 to prevent the surface state of the upper surface of the first inorganic layer 81 from affecting the components disposed on the organic layer 82. In addition, the organic layer 82 may relieve stress between layers in contact with each other. The organic layer 82 may include an organic material and may be disposed by a solution process such as spin coating, slit coating, or an inkjet process.

[0184] The second inorganic layer 83 is disposed on the organic layer 82 to cover the organic layer 82. Compared with being disposed on the first inorganic layer 81, the second inorganic layer 83 can be stably disposed on a relatively flat surface. The second inorganic layer 83 encapsulates moisture, etc. discharged from the organic layer 82 to prevent or inhibit moisture, etc. from flowing to the outside. The second inorganic layer 83 may include silicon nitride, silicon oxide, or a mixture thereof. The second inorganic layer 83 may be disposed by a deposition process.

[0185] Fig. 7A is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 7Ais a cross-sectional view of the display panel 210 including the second area AR2 of the base layer BS. Fig. 7A It may be a non-luminescent pixel PX-N (see Figure 5 ) area. Fig. 7A The same reference numerals are given as for Figure 6 The elements described are the same elements, and descriptions thereon will be omitted.

[0186] about Fig. 7A , compared with the typical pixel PX (see Figure 3A ), the non-luminescent pixel PX-N may not include some components. For example, the non-luminescent pixel PX-N may not include the emission layer EL (see Figure 6 ) and the second electrode E2 (see Figure 6 ). The non-luminescent pixel PX-N may include a transistor TR, a connection electrode CNE, and a first electrode E1. The non-luminescent pixel PX-N may not include some necessary elements for generating light. Therefore, the non-luminescent pixel PX-N does not emit light. The non-luminescent pixel PX-N may be understood as a pixel configured to display black.

[0187] Figure 7B is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 7B is a cross-sectional view of the display panel 210 including the second area AR2 of the base layer BS. Figure 7B It can be a non-luminescent pixel PX-N (see Figure 5 ) corresponds to a cross-sectional view of the region. Figure 7B The same reference numerals are given as for Figure 6 The elements described are the same elements, and descriptions thereon will be omitted.

[0188] about Figure 7B , compared with the typical pixel PX (see Figure 3A ), the non-luminescent pixel PX-N1 may not include some components. For example, the non-luminescent pixel PX-N1 may include a transistor TR, an emission layer EL, and a second electrode E2, but may not include a connection electrode CNE (see Figure 6 ) and the first electrode E1 (see Figure 6 ). Therefore, the non-luminescent pixel PX-N1 does not emit light.

[0189] exist Fig. 7A and Figure 7BIn the embodiment, non-luminescent pixels PX-N and PX-N1 are illustrated, but the configuration of non-luminescent pixels PX-N and PX-N1 is not limited thereto. For example, the non-luminescent pixel may include all components configured as a setting pixel, or may not include at least some components configured as a setting pixel. For example, when the non-luminescent pixel includes all components configured as a setting pixel, the non-luminescent pixel may be controlled not to emit light.

[0190] Fig. 8A is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 8A is a cross-sectional view of the display panel 210 including the first area AR1a and the second area AR2 of the base layer BS. Fig. 8A The peripheral portion of the module hole MH1 is shown. The module hole MH2 (see Figure 5 ) may also have a structure that is substantially the same as that of the peripheral portion of the module hole MH1.

[0191] about Figure 6 and Fig. 8A , the groove portions GV1 , GV2 , and GV3 may be defined in the first area AR1 a of the base layer BS around the module hole MH1 . In addition, the dam portion DMP may be provided in the first area AR1 a .

[0192] Each of the groove portions GV1, GV2, and GV3 may be defined by being recessed from the top surface of the base layer BS. Each of the groove portions GV1, GV2, and GV3 may be provided in such a manner that at least a portion of the base layer BS is removed. A deposition pattern ELP may be provided in each of the groove portions GV1, GV2, and GV3, and the deposition pattern ELP may be covered by at least any one of the first inorganic layer 81 and the second inorganic layer 83.

[0193] The display panel 210 according to the exemplary embodiment may further include groove portions GV1, GV2 and GV3 to block the continuity between the deposition pattern ELP and the light emitting element ELD. Thus, a permeation path of external moisture or oxygen is blocked to prevent or inhibit the active area AA (see FIG. Figure 3A ) is damaged.

[0194] In addition, the deposition pattern ELP provided in each of the groove portions GV1, GV2, and GV3 may be covered by the first inorganic layer 81 or the second inorganic layer 83 to prevent or inhibit the deposition pattern ELP from moving and affecting other elements in the manufacturing process of the display panel 210. Therefore, the process reliability of the display panel 210 can be improved. On the other hand, this is shown exemplarily, and in the display panel 210 according to the exemplary embodiment, the groove portions GV1, GV2, and GV3 may be provided as one body or omitted, and are not limited to any one embodiment.

[0195] The groove portions GV1, GV2, and GV3 may be defined to be separated from each other. The groove portions GV1, GV2, and GV3 are exemplarily shown to be separated from the second area AR2 and are sequentially arranged in a direction close to the module hole MH1. Each of the groove portions GV1, GV2, and GV3 may have a closed line shape configured to surround the module hole MH1 or a discontinuous line shape configured to surround at least a portion of the edge of the module hole MH1, and is not limited to any one embodiment.

[0196] The dam DMP is provided in the first region AR1a to separate the formation region of the organic layer 82 in a specified region and prevent or inhibit additional extension of the organic layer 82. The dam DMP is provided in plural to be provided between the groove portions GV1, GV2, and GV3. The dam DMP is shown to have a stacked structure including the first to third layers P11, P12, and P13. However, this is merely exemplary. The dam DMP may have a single-layer structure and is not limited to any one embodiment.

[0197] The cover layer FL may be disposed in the first region AR1a. For example, the cover layer FL may cover an uneven surface provided by the dam portion DMP or the groove portions GV1, GV2, and GV3 to provide a flat surface FL_SH. The flat surface FL_SH defined by the cover layer FL may define substantially the same plane as the flat surface 80_S defined by the eighth insulating layer 80.

[0198] The display panel 210 may further include a metal pattern MTL. The metal pattern MTL may be disposed in the first area AR1a. The metal pattern MTL may be disposed along an edge of the module hole MH1 to cover at least a portion of the cover layer FL. The metal pattern MTL may prevent the cover layer FL from being damaged by a laser beam or the like when the module hole MH1 is provided or protect the cover layer FL from being damaged by a laser beam or the like. In addition, the metal pattern MTL may press the cover layer FL to prevent the cover layer FL from being lifted or protect the cover layer FL from being lifted.

[0199] The signal lines SLa, SLb, SLc, and SLd may be disposed in the second area AR2 of the base layer BS. The signal lines SLa, SLb, SLc, and SLd may include a first line SLa, a second line SLb, a third line SLc, and a fourth line SLd.

[0200] Some of the first to fourth lines SLa, SLb, SLc, and SLd may be electrically connected to the first signal line SNL1 (see Figure 5 ), while the others may be electrically connected to the second signal line SNL2 (see Figure 5 ).

[0201] The first line SLa may be disposed between the second insulating layer 20 and the third insulating layer 30. The first line SLa may be disposed on the same layer as the control electrode CE. The second line SLb may be disposed between the third insulating layer 30 and the fourth insulating layer 40. The second line SLb may be disposed on the same layer as the upper electrode UE. The third line SLc may be disposed between the fourth insulating layer 40 and the fifth insulating layer 50. The third line SLc may be disposed on the same layer as the output electrode OE and the input electrode IE. The fourth line SLd may be disposed between the fifth insulating layer 50 and the sixth insulating layer 60. The fourth line SLd may be disposed on the same layer as the connection electrode CNE.

[0202] Figure 8B is a cross-sectional view of a display panel according to an exemplary embodiment. Figure 8B is a cross-sectional view of a display panel 210-1 including a first area AR1a and a second area AR2 of a base layer BS. Figure 8B , will describe Fig. 8A Different parts and the same reference numerals are given to Fig. 8A For components that are identical to those described above, repeated descriptions thereof will be omitted.

[0203] about Figure 8B , the display panel 210 - 1 may include a base layer BS- 1 and an encapsulation substrate 80 - 1 .

[0204] The encapsulation substrate 80-1 may be disposed on the second electrode E2. The encapsulation substrate 80-1 and the second electrode E2 may be separated from each other. The gap GAP between the encapsulation substrate 80-1 and the second electrode E2 may be filled with air or an inert gas. In addition, in an exemplary embodiment, the gap GAP may be filled with a filler such as a silicone polymer, an epoxy resin, or an acrylic resin.

[0205] The encapsulation substrate 80-1 may be combined with the base layer BS-1 through the sealing member PSL. The encapsulation substrate 80-1 may be disposed on the base layer BS-1 at a designated interval maintained by the sealing member PSL.

[0206] The sealing member PSL may be a component configured to define the inner surface of the module hole MH1. The sealing member PSL may include an organic material such as a photocurable resin or a photoplastic resin or an inorganic material such as a glass sealant, and is not limited to any one embodiment.

[0207] Fig.9A is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 9B is a cross-sectional view of a display panel according to an exemplary embodiment. Fig.9A and Fig. 9B Only some components of the display panel are shown, and some components that do not require description are not shown.

[0208] about Fig.9A The second line SLb may be electrically connected to the scan line GL. The scan line GL may be the second signal line SNL2 (see Figure 3A The scan line GL and the first line SLa may be disposed on the same layer.

[0209] about Fig. 9B , the first line SLa may be electrically connected to the emission control line ECL. The emission control line ECL may be the second signal line SNL2 (see Figure 3A The emission control line ECL may be disposed on the same layer as the second line SLb.

[0210] In an exemplary embodiment, the emission control line ECL may be omitted. In this case, the first line SLa may be electrically connected to one scan line GL, and the second line SLb may be electrically connected to another scan line GL. Figure 5 ) can be arranged on the same layer in the second area AR2 (see Figure 5 ) are arranged on different layers. Therefore, in a plane, the area of ​​the second region AR2 can be reduced.

[0211] Fig. 10A is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 10B is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 10A and Fig. 10B Only some components of the display panel are shown, and some components that do not require description are not shown.

[0212] about Fig. 10A and Fig. 10B , first signal lines SNL1a and SNL1b are shown. The first signal lines SNL1a and SNL1b may be data lines.

[0213] The first signal lines SNL1a and SNL1b may be disposed between the fifth insulating layer 50 and the sixth insulating layer 60. The first signal lines SNL1a and SNL1b may be disposed on the same layer as the fourth line SLd.

[0214] The first signal line SNL1a may penetrate the fifth insulating layer 50 to be electrically connected to the third line SLc. The first signal line SNL1b may be electrically connected to the fourth line SLd. The fourth line SLd and the first signal line SNL1b may have an integral shape. In other words, the fourth line SLd of the second area AR2 may extend from the first signal line SNL1b.

[0215] For example, similar to the first signal line SNL1a, the first signal lines connected to the pixels configured to emit red light and blue light, respectively, may be electrically connected to the third line SLc. Similar to the first signal line SNL1b, the first signal line connected to the pixel configured to emit blue light may be electrically connected to the fourth line SLd. However, this is merely exemplary, and exemplary embodiments are not limited thereto.

[0216] Fig.11A is along Figure 5 0 is a cross-sectional view of the display panel taken along the section line II′ shown in FIG. Fig. 11B yes Figure 5 An enlarged plan view of the YY' region shown in FIG.

[0217] about Fig.11A , showing a first line SLa, a second line SLb, a third line SLc, and a fourth line SLd. The third insulating layer 30 disposed between the first line SLa and the second line SLb may be referred to as a first insulating layer. The fourth insulating layer 40 disposed between the second line SLb and the third line SLc may be referred to as a second insulating layer. The fifth insulating layer 50 disposed between the third line SLc and the fourth line SLd may be referred to as a third insulating layer.

[0218] The first wire SLa, the third insulating layer 30 (or the first insulating layer), the second wire SLb, the fourth insulating layer 40 (or the second insulating layer), the third wire SLc, the fifth insulating layer 50 (or the third insulating layer), and the fourth wire SLd may be sequentially stacked on the base layer BS.

[0219] In a plan view, the first line SLa and the second line SLb may not overlap. In a plan view, the third line SLc and the fourth line SLd may not overlap. In a plan view, a portion of the third line SLc may overlap with a portion of the first line SLa, and another portion of the third line SLc may overlap with a portion of the second line SLb. In a plan view, a portion of the fourth line SLd may overlap with another portion of the first line SLa, and another portion of the fourth line SLd may overlap with another portion of the second line SLb. In a plan view, the first line SLa, the third line SLc, the second line SLb, and the fourth line SLd may be repeated and arranged periodically and alternately in the above order. In a plan view, the first line portion is disposed in a region located between the second line portions.

[0220] According to an exemplary embodiment, the parasitic capacitance between the third line SLc and the fourth line SLd connected to the first signal line SNL1 and the parasitic capacitance between the first line SLa and the second line SLb connected to the second signal line SNL2 can be reduced while reducing the area of ​​the second region AR2 on a plane. The parasitic capacitance generated between different lines may cause a decrease in display quality, such as degradation of image quality. According to an exemplary embodiment, the lines disposed on the most adjacent layers may not overlap. Therefore, the decrease in display quality caused by the parasitic capacitance can be prevented or suppressed. In addition, the display device EA (see Figure 1A ) display quality.

[0221] In addition, the second area AR2 (see Figure 5 ) is provided on the same layer in the embodiment of the present invention. For example, the first interval DT1 between two adjacent first lines SLa and the second interval DT2 between two adjacent third lines SLc may be about 3.5 μm or longer. For example, the first interval DT1 may be about 3.5 μm or longer, and the second interval DT2 may be about 4 μm or longer. According to an exemplary embodiment, even if a stringer defect of a metal film residue occurs in a process for providing the lines, the possibility that adjacent lines provided on the same layer may be short-circuited may be reduced.

[0222] In an exemplary embodiment, the widths of the first line SLa and the second line SLb and the widths of the third line SLc and the fourth line SLd may be different from each other. For example, each of the width of the first line SLa and the width of the second line SLb may be about 2 μm, and each of the width of the third line SLc and the width of the fourth line SLd may be about 2.5 μm. Each of the width WT1 of the area where the first line SLa and the third line SLc overlap, the width WT2 of the area where the second line SLb and the third line SLc overlap, the width WT3 of the area where the first line SLa and the fourth line SLd overlap, and the width WT4 of the area where the second line SLb and the fourth line SLd overlap may be about 0.75 μm. However, the numbers are exemplary only, and the exemplary embodiment is not limited thereto.

[0223] Fig. 12A is along with Figure 5 A cross-sectional view of a region cut along the section line II' shown in FIG. Fig. 12B is with Figure 5 The enlarged plan view of the area corresponding to the YY' area shown in FIG. Fig. 12A and Fig. 12B In the description of Fig.11A and Fig. 11B The different parts in the figure will be described below, and description about the rest will be omitted.

[0224] and Fig.11A and Fig. 11B compared to, Fig. 12A and Fig. 12B The arrangement order of the first line SLa and the second line SLb in the embodiment may be changed. Therefore, in a plan view, the second line SLb, the third line SLc, the first line SLa, and the fourth line SLd may be periodically and alternately repeated and arranged in the above order.

[0225] Fig.13A is along with Figure 5 A cross-sectional view of a region cut along the section line II' shown in FIG. Fig. 13B is with Figure 5 An enlarged plan view of the area corresponding to the YY' area shown in FIG.

[0226] about Fig.13A and Fig. 13B , the third line SLc may be disposed on the first line SLa, and the fourth line SLd may be disposed on the second line SLb. Therefore, in a plan view, the first line SLa and the third line SLc may overlap each other, and the second line SLb and the fourth line SLd may overlap each other. The overlapped first line SLa and the third line SLc and the overlapped second line SLb and the fourth line SLd may be periodically and alternately repeated and arranged in the above order. Fig.11A and Fig. 12A Compared with the embodiment shown in Fig.13A and Fig. 13B According to the exemplary embodiment shown in FIG. 1 , the area of ​​the second region AR2 can be further reduced in plane.

[0227] Fig.14A is along with Figure 5 A cross-sectional view of a region cut along the section line II' shown in FIG. Fig. 14B is with Figure 5 An enlarged plan view of the area corresponding to the YY' area shown in FIG.

[0228] about Fig.14A and Fig. 14B , the third line SLc may be disposed on the second line SLb, and the fourth line SLd may be disposed on the first line SLa. Therefore, in a plan view, the second line SLb and the third line SLc may overlap each other, and the first line SLa and the fourth line SLd may overlap each other. The overlapped first line SLa and the fourth line SLd and the overlapped second line SLb and the third line SLc may be periodically and alternately repeated and arranged in the above order.

[0229] Fig.15 is an exploded perspective view of a display device according to an exemplary embodiment. Fig.15 In the description of Figure 1BThe same reference numerals are given to different parts. Figure 1B The components described are the same components, and repeated descriptions thereon will be omitted.

[0230] about Fig.15 , the display device EA-T may include a window 100 , a display module 200_T, a driving circuit unit 300 -T, a housing 400 and an electronic module 500 .

[0231] The display module 200-T may be divided into first module regions MD1a and MD1b, a second module region MD2, and a third module region MD3. The first module regions MD1a and MD1b may be Figure 3A The second module region MD2 may be a region corresponding to the second region AR2 of the base layer BS, and the third module region MD3 may be a region corresponding to the third region AR3 of the base layer BS.

[0232] The first module regions MD1a and MD1b may be regions that overlap the first electronic module 501 and the second electronic module 502 one-to-one. The transmittance of the first module regions MD1a and MD1b may be higher than the transmittance of the third module region MD3. In order to improve the transmittance of the first module regions MD1a and MD1b, a specified component may not be provided in the first module regions MD1a and MD1b. For example, the signal lines SNL1, SNL2, and PL (see Figure 3A ) may be designed not to overlap with the first module regions MD1a and MD1b. In an exemplary embodiment, at least a portion of the components configuring the display module 200-T may not be disposed in the first module regions MD1a and MD1b. For example, the first electrode E1 (see Figure 6 ), the second electrode E2 (see Figure 6 ), emission layer EL (see Figure 6 ), transistor TR (see Figure 6 ), the first sensing electrode TE1 (see Figure 4 ) and the second sensing electrode TE2 (see Figure 4 ) may not be set in the first module areas MD1a and MD1b.

[0233] Therefore, the first electronic module 501 and the second electronic module 502 may easily and visually recognize an external object through the first module regions MD1a and MD1b, or output signals generated by the first electronic module 501 and the second electronic module 502 may be easily transmitted to the outside.

[0234] Fig.16 yes Fig.15An enlarged plan view of a portion of the display module is shown in FIG.

[0235] about Fig.16 , missing pixels PX-D may be provided in the first areas AR1a and AR1b of the base layer BS. The missing pixels PX-D may be pixels that do not include at least a portion of the elements of the pixel PX. Therefore, the transmittance of the area in which the missing pixels PX-D are provided may be higher than the transmittance of the area in which the pixel PX is provided. In order to distinguish from the pixel PX, the missing pixels PX-D are shown with shading.

[0236] Fig.16 It is exemplarily shown that only the missing pixel PX-D is provided in the first areas AR1a and AR1b, but the exemplary embodiment is not limited thereto. For example, in each of the first areas AR1a and AR1b, not only the missing pixel PX-D but also a typical pixel PX including the same elements as those of the pixel PX may be provided. The ratio between the missing pixel PX-D and the typical pixel PX may be adjusted differently.

[0237] In exemplary embodiments, portions corresponding to the first areas AR1a and AR1b may be removed later through a cutting process.

[0238] Fig.17A is a cross-sectional view of a display panel according to an exemplary embodiment. Fig.17A 2 is a cross-sectional view of the display panel 210 including the first area AR1a of the base layer BS. Fig.17A It may be a cross-sectional view of a region in which a missing pixel PX-D is disposed.

[0239] Compared with the typical pixel PX (see Figure 3A ), the missing pixel PX-D may not include some components. Therefore, the transmittance of the area in which the missing pixel PX-D is disposed may be higher than the transmittance of the area in which the pixel PX is disposed. For example, the missing pixel PX-D may include a transistor TR, a connection electrode CNE, and a first electrode E1, but may not include an emission layer EL (see Figure 6 ) and the second electrode E2 (see Figure 6 ).

[0240] Fig. 17B is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 17B 2 is a cross-sectional view of the display panel 210 including the first area AR1a of the base layer BS. Fig. 17B It may be a cross-sectional view of a region in which the missing pixel PX-D1 is disposed.

[0241] Compared with the typical pixel PX (see Figure 3A), the missing pixel PX-D may not include some components. For example, the missing pixel PX-D1 may include a transistor TR, an emission layer EL, and a second electrode E2, but may not include a connection electrode CNE (see Figure 6 ) and the first electrode E1 (see Figure 6 ).

[0242] Fig. 17C is a cross-sectional view of a display panel according to an exemplary embodiment. Fig. 17C 2 is a cross-sectional view of the display panel 210 including the first area AR1a of the base layer BS. Fig. 17C It may be a cross-sectional view of a region in which the missing pixel PX-D2 is disposed.

[0243] Compared with the typical pixel PX (see Figure 3A ), the missing pixel PX-D2 may not include some components. Therefore, the transmittance of the area in which the missing pixel PX-D2 is disposed may be higher than the transmittance of the area in which the pixel PX is disposed. For example, the missing pixel PX-D2 includes only the second electrode E2. To help understand, Fig. 17C The dotted line shows that the transistor TR is omitted (see Figure 6 ) regional TRA.

[0244] In addition, in another exemplary embodiment, the missing pixel PX-D2 may not include the second electrode E2. In this case, even if the expression that the missing pixel PX-D2 is disposed in the first region AR1a is used, only the base layer BS and the first to eighth insulating layers 10, 20, 30, 40, 50, 60, 70 and 80 may be disposed in the first region AR1a. In an exemplary embodiment, in order to increase the transmittance of the first region AR1a, at least a portion of the base layer BS and the first to eighth insulating layers 10, 20, 30, 40, 50, 60, 70 and 80 may also be omitted.

[0245] Fig.18 is an exploded perspective view of a display device according to an exemplary embodiment. Fig.18 In the description of Fig.15 The same reference numerals are given to different parts. Fig.15 The components described are the same components, and repeated descriptions thereon will be omitted.

[0246] about Fig.18 , the display device EA-T1 may include a window 100 , a display module 200 -T, a driving circuit unit 300 -T, a housing 400 , and an electronic module 500 .

[0247] The display module 200-T may be divided into first module regions MD1a and MD1b, a second module region MD2, and a third module region MD3. The first module regions MD1a and MD1b may be Figure 3A The second module region MD2 may be a region corresponding to the second region AR2 of the base layer BS, and the third module region MD3 may be a region corresponding to the third region AR3 of the base layer BS.

[0248] The first module regions MD1a and MD1b may be regions one-to-one overlapped on a plane with the first and second electronic modules 501 and 502. The transmittance of the first module regions MD1a and MD1b may be higher than the transmittance of the third module region MD3. The first module regions MD1a and MD1b may have different transmittances.

[0249] In an exemplary embodiment, a module hole MH may be defined in the first module region MD1a. The module hole MH may be defined by removing all components of the display module 200-T disposed to overlap the first sensor region SA1. Therefore, the transmittance of the first module region MD1a may be higher than the transmittance of the first module region MD1b.

[0250] The first electronic module 501 disposed to overlap the first module region MD1a may be a camera module, and the second electronic module 502 disposed to overlap the first module region MD1b may be a light emitting module, a light receiving module, or a thermal sensing module.

[0251] A display device according to an exemplary embodiment may include a base layer and first to fourth lines sequentially arranged on the base layer. The base layer may include a first area, a second area configured to surround the first area, and a third area configured to surround the second area. The first to fourth lines may be arranged in the second area. In a plan view, the first line and the second line may not overlap each other. In a plan view, the third line and the fourth line may not overlap each other. Therefore, the possibility of generating parasitic capacitance between adjacent lines can be reduced. Therefore, the degradation of display quality caused by parasitic capacitance can be prevented or suppressed.

[0252] Although the present invention has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to the described embodiments without departing from the spirit and technical field of the invention as defined by the appended claims and their equivalents. Therefore, the scope of the inventive concept shall not be restricted or limited by the foregoing description, but shall be determined by the broadest permissible interpretation of the claims.

[0253] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: A base layer comprising: a first region in which a hole is defined; a second region configured to surround the first region; and a third region configured to surround the second region; a line portion disposed in the second region, the line portion including a first line, a second line, a third line, and a fourth line disposed on different layers from each other; pixels, arranged in the third area; first signal lines electrically connected to the pixels, the first signal lines being arranged along a first direction; and a second signal line electrically connected to the pixel, the second signal line being arranged along a second direction intersecting the first direction, wherein one of the second signal lines is electrically connected to the first line, another of the second signal lines is electrically connected to the second line, one of the first signal lines is electrically connected to the third line, and another of the first signal lines is electrically connected to the fourth line. wherein the first line, the second line, the third line and the fourth line are sequentially arranged on the base layer, wherein, in a plan view, the first line and the second line do not overlap, and the third line and the fourth line do not overlap, and Wherein, in a plan view, each of the third line and the fourth line overlaps with at least a portion of the first line or at least a portion of the second line.

2. The display device according to claim 1, further comprising: a first insulating layer disposed between the first line and the second line; a second insulating layer disposed between the second line and the third line; as well as a third insulating layer, disposed between the third line and the fourth line, The first line, the first insulating layer, the second line, the second insulating layer, the third line, the third insulating layer and the fourth line are sequentially arranged on the base layer.

3. The display device according to claim 2, wherein: Each of the pixels comprises: a transistor including: a control electrode disposed on the same layer on which the first line is disposed; and an output electrode and an input electrode disposed on the same layer on which the third line is disposed; a connecting electrode disposed on the same layer on which the fourth line is disposed; and The light emitting element is electrically connected to the connection electrode.

4. The display device according to claim 1, wherein: The second line is disposed between a layer on which the first line is disposed and a layer on which the third line is disposed, and the third line is disposed between a layer on which the second line is disposed and a layer on which the fourth line is disposed.

5. The display device according to claim 1, wherein: In the plan view, the first line, the second line, the third line, and the fourth line are repeatedly arranged in the order of the first line, the third line, the second line, and the fourth line.

6. The display device according to claim 1, wherein: In the plan view, a portion of the third line overlaps a portion of the first line, and another portion of the third line overlaps a portion of the second line.

7. The display device according to claim 6, wherein: In the plan view, a portion of the fourth line overlaps another portion of the first line, and another portion of the fourth line overlaps another portion of the second line.

8. The display device according to claim 1, wherein: In the plan view, the third line overlaps one of the first line and the second line, and the fourth line overlaps the other of the first line and the second line.

9. The display device according to claim 1, wherein: In the plan view, the first line, the second line, the third line, and the fourth line are repeatedly arranged in the order of the second line, the third line, the first line, and the fourth line.

10. The display device according to claim 1, wherein: The first region includes a plurality of first regions, each of the plurality of first regions is separately arranged, and The second area surrounds the plurality of first areas.

11. The display device according to claim 10, further comprising: The non-luminescent pixel is arranged in the second region between the plurality of first regions.

12. A display device, comprising: A base layer comprising: a first region in which a hole is defined; a second region configured to surround the first region; and a third region configured to surround the second region; pixels, arranged in the third area; A first signal line electrically connected to the pixel; a second signal line electrically connected to the pixel; a first line disposed in the second region and electrically connected to one of the second signal lines; a second line disposed in the second region and electrically connected to another second signal line of the second signal lines; a third line disposed in the second region and electrically connected to one of the first signal lines; and a fourth line disposed in the second region and electrically connected to another first signal line among the first signal lines, wherein the first line, the second line, the third line and the fourth line are arranged on different layers, wherein the second line is disposed on a layer between the first line and the third line, the third line is disposed on a layer between the second line and the fourth line, and in a plan view, the first line does not overlap with the second line, and the third line does not overlap with the fourth line, and Wherein, in a plan view, each of the third line and the fourth line overlaps with at least a portion of the first line or at least a portion of the second line.

13. The display device according to claim 12, wherein: In the plan view, the first line, the second line, the third line, and the fourth line are repeatedly arranged in the order of the first line, the third line, the second line, and the fourth line.

14. The display device according to claim 12, wherein: In the plan view, a portion of the third line overlaps a portion of the first line, and another portion of the third line overlaps a portion of the second line, and In the plan view, a portion of the fourth line overlaps another portion of the first line, and another portion of the fourth line overlaps another portion of the second line.

15. The display device according to claim 12, wherein: In the plan view, the third line overlaps one of the first line and the second line, and the fourth line overlaps the other of the first line and the second line.

16. The display device according to claim 12, wherein: The base layer, the pixel, the first signal line, the second signal line, the first line, the second line, the third line and the fourth line constitute a display module, and the display module includes: a first module region defined as overlapping the first region; a second module region defined to overlap the second region; and a third module region, defined to overlap the third region, and The transmittance of the first module area is higher than the transmittance of the third module area.

17. A display device, comprising: A display panel, in which a non-display area and a display area configured to surround the non-display area are defined, the display panel comprising: a base layer having a hole defined in a region of the base layer configured to correspond to the non-display region; a wire portion disposed in a peripheral region of the hole of the base layer, the wire portion including first wires, second wires, third wires, and fourth wires disposed on different layers from each other; and pixels, electrically connected to the line portion, wherein the first line, the second line, the third line and the fourth line are sequentially arranged on the base layer, wherein, in a plan view, the first line and the second line do not overlap, and the third line and the fourth line do not overlap, and Wherein, in a plan view, each of the third line and the fourth line overlaps with at least a portion of the first line or at least a portion of the second line.

18. The display device according to claim 17, wherein: The second line is disposed between a layer on which the first line is disposed and a layer on which the third line is disposed, and the third line is disposed between a layer on which the second line is disposed and a layer on which the fourth line is disposed.

19. The display device according to claim 17, wherein: In the plan view, a portion of the third line overlaps a portion of the first line, and another portion of the third line overlaps a portion of the second line, and In the plan view, a portion of the fourth line overlaps another portion of the first line, and another portion of the fourth line overlaps another portion of the second line.

20. A display device, comprising: A display panel, in which a non-display area and a display area configured to surround the non-display area are defined, the non-display area includes: a first area in which a hole is defined; and a second area configured to surround the first area, the display panel includes: a line portion provided in the second area and including a first line portion and a second line portion provided on layers different from each other; a pixel provided in the display area; a first signal line provided in the display area, the first signal line is arranged in a first direction, and the first signal line is electrically connected to the pixel and the first line portion; and a second signal line provided in the display area, the second signal line is arranged in a second direction crossing the first direction, and the second signal line is electrically connected to the pixel and the second line portion, wherein, in a plan view, one of the first line portions is provided in an area between two adjacent second line portions among the second line portions, The first line portions are disposed at different layers from each other, the second line portions are disposed at different layers from each other, and the first line portions and the second line portions are disposed sequentially.

21. The display device according to claim 20, wherein: The first line portion includes a first line and a second line disposed on different layers from each other, and the second line portion includes a third line and a fourth line disposed on different layers from each other.

22. The display device according to claim 21, wherein: The third line is disposed on a layer between the second line and the fourth line.

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