Method for accelerating ufs protocol processing and storage controller

Abstract

Methods and storage controllers are provided to accelerate UFS protocol processing. A control component of a UFS storage device is provided, including a UPIU processing unit, a command slot allocation unit, a command memory, a processor, and a command processing unit. The UPIU processing unit extracts a first command from a UPIU as a command unit type, and provides the first command to the command slot allocation unit. The command slot allocation unit allocates an available command slot for the first command, stores a first part of the first command to a command cache unit associated with the command slot, and provides the command slot allocated for the first command to the processor. The processor generates one or more command descriptors according to the command slot and provides the command descriptors to the command processing unit. The command processing unit issues a UPIU through the UPIU processing unit according to the command descriptors.

Description

TECHNICAL FIELD

[0001] The present application relates to storage technology, and in particular, to a method and a storage controller for accelerating UFS processing by utilizing a hardware-software co-processing USF protocol. BACKGROUND

[0002] Figure 1 A block diagram of a storage device is shown. The storage device 102 is coupled to a host to provide storage capability for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to, through a connection such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), NVMe (NVM Express), UFS (Universal Flash Storage), eMMC (embedded MMC (MultiMediaCard)), Ethernet, Fibre Channel, a wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and optionally a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, UFS (Universal Flash Storage), Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transmission between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in various manners, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store an FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) coupled to the NVM chip 105 and configured to issue commands to the NVM chip 105 in a manner complying with an interface protocol of the NVM chip 105, to operate the NVM chip 105, and to receive command execution results output from the NVM chip 105. Known NVM chip interface protocols include “Toggle”, “ONFI”, etc.

[0007] UFS (Universal Flash Storage) is an interface standard for flash storage devices formulated by the JEDEC standard organization, with a standard number such as JESD220C. The UFS protocol exchanges commands between the host and the storage device in UPIU (UFS Protocol Information Unit) as a transmission unit. The UPIU includes various types, such as a command unit, an RTT unit, a read data unit, a write data unit, and a response unit, etc.

[0008] Figure 2A With Figure 2B A schematic diagram showing implementation of write and read commands by the UFS protocol through UPIU is shown.

[0009] Figure 2A A process for describing a write command is shown.

[0010] The host sends a UPIU of command unit type representing a write command to the device. In response, the device sends a UPIU of RTT unit type to the host to indicate that the device is ready to receive data to be written by the write command after the device has received the data to be written by the write command. The host, in response to receiving the UPIU of RTT unit type, sends a UPIU of write data unit type to the device. The device receives the UPIU of write data unit type and obtains the data carried by the UPIU. The device, in response to identifying that all data to be written by the write command has not been obtained, sends a UPIU of RTT unit type to the host to indicate that the device is ready to receive data to be written by the write command after the device has received the data to be written by the write command. The host, in response to receiving the UPIU of RTT unit type, sends a UPIU of write data unit type to the device. The device receives the UPIU of write data unit type and obtains the data carried by the UPIU. The device, in response to identifying that all data to be written by the write command has been obtained, sends a UPIU of response unit type to the host. The host, upon receiving the UPIU of response unit type, knows that the write command has been processed.

[0011] Figure 2B A process for processing a read command is described.

[0012] The host sends a UPIU of command unit type representing a read command to the device. In response, the device sends a UPIU of read data unit type to the host to provide the host with data to be read by the read command after the device has obtained the data to be read by the read command. The device also identifies whether all data to be read by the read command has been provided to the host. If there is still other data to be read by the read command to be provided to the host, the device also sends one or more UPIUs of read data unit type to the host until all data to be read by the read command has been provided to the host. The device, in response to identifying that all data to be read by the read command has been provided to the host, also sends a UPIU of response unit type to the host. The host, upon receiving the UPIU of response unit type, knows that the read command has been processed.

[0013] The control component of the storage device complying with the UFS protocol obtains and provides UPIUs to the host to complete processing of a command according to the command issued by the host and the processing capability of the storage device and according to the requirements of the UFS protocol.

[0014] In addition to read commands and write commands, the UFS protocol also defines task management commands, inquiry commands, eject commands, and null commands. SUMMARY

[0015] The UFS protocol is commonly used in portable memory cards or embedded storage modules in smart mobile terminals. Such UFS protocol enabled storage devices are small devices, usually with less computing resources and lower power consumption. Usually, the control part of the storage device extracts UPIU by hardware, the extracted UPIU is identified by the software executed by the processor core to understand its meaning and process it. Thus, the processing capability of the software or the CPU core executing the software often becomes the performance bottleneck of such devices. It is desirable to distribute part of the work of the software by hardware.

[0016] According to embodiments of the present application, at least the following works of the software are shared by the hardware of the UFS protocol enabled storage device: (1) identifying the number of commands that the control part can handle concurrently, ensuring that the number of commands accepted by the control part does not exceed the specified range, and rejecting additional received commands when the number of commands handled by the control part concurrently is saturated; (2) providing the software with the commands issued by the host and accepted to be processed, and providing the host with UPIU as the process or result in response to the indication of the software; (3) automatically generating part of the UPIU, so that the software is not provided with an indication to the hardware for each UPIU sent to the host.

[0017] According to a first aspect of the present application, a control part of a first UFS storage device according to the first aspect of the present application is provided, comprising a UPIU processing unit, a command slot allocation unit, a command memory, a processor and a command processing unit; the UPIU processing unit extracts a first command from a UPIU as a command unit type, and provides the first command to the command slot allocation unit; the command slot allocation unit allocates an available command slot for the first command, and stores a first part of the first command to a command cache unit associated with the command slot, and provides the command slot allocated for the first command to the processor; the processor generates one or more command descriptors according to the command slot and provides them to the command processing unit; the command processing unit issues UPIU through the UPIU processing unit according to the command descriptors.

[0018] The control part of the first UFS storage device according to the first aspect of the present application is provided, and the control part of the second UFS storage device according to the first aspect of the present application further comprises a command queue and one or more command slot queues; the UPIU processing unit adds the extracted first command to the command queue; the command slot allocation unit obtains the first command from the command queue; the command slot allocation unit adds the allocated command slot to one of the one or more command slot queues; the processor obtains the command slot from the one or more command slot queues.

[0019] According to the second UFS storage device control component of the first aspect of the present application, the third UFS storage device control component of the first aspect of the present application is provided, wherein the command slot queue has a priority, and the command slot allocation unit adds the command slot allocated for the first command to one of the one or more command slot queues having a corresponding priority according to the priority of the first command.

[0020] According to one of the first to third UFS storage device control components of the first aspect of the present application, the fourth UFS storage device control component of the first aspect of the present application is provided, wherein if there is no available command slot allocated to the first command, the command slot allocation unit issues a UPIU as a response type UPIU through the UPIU processing unit to indicate that the storage device is currently unable to process the first command.

[0021] According to one of the first to fourth UFS storage device control components of the first aspect of the present application, the fifth UFS storage device control component of the first aspect of the present application is provided, wherein the control component includes a plurality of preset command slots, wherein the command slots can be associated with commands, the command slots have types, and the control component has one or more command slots of a specified type; and wherein the command slots not associated with commands are available command slots that can be allocated to commands; the command slots already associated with commands are unavailable command slots; and the command slot allocation unit allocates available command slots of the same type to the first command according to the type of the first command.

[0022] According to one of the first to fifth UFS storage device control components of the first aspect of the present application, the sixth UFS storage device control component of the first aspect of the present application is provided, wherein the first part of the first command includes header information of the UPIU from which the first command is extracted; and the command slot allocation unit adds the second part of the first command to the command slot, wherein the second part of the second command is related to the processing of the command by the processor.

[0023] According to one of the first to sixth UFS storage device control components of the first aspect of the present application, the seventh UFS storage device control component of the first aspect of the present application is provided, wherein the command slot is a command identifier uniquely identifying the command.

[0024] According to one of the first to seventh UFS storage device control components of the first aspect of the present application, the eighth UFS storage device control component of the first aspect of the present application is provided, further comprising a command descriptor register; the processor provides the command descriptor to the command processing unit by writing the generated command descriptor to the command descriptor register; and the command processing unit updates the command descriptor register to indicate to the processor that the processing of the command descriptor is complete in response to issuing the UPIU through the UPIU processing unit according to the command descriptor.

[0025] According to the eighth UFS storage device control component of the first aspect of the present application, the ninth UFS storage device control component of the first aspect of the present application is provided, wherein the command descriptor register further comprises an automatic response flag; if the automatic response flag is set, the command processing unit, after issuing the first UPIU according to the command descriptor through the UPIU processing unit, further issues the second UPIU as a response unit type through the UPIU processing unit to indicate that the command associated with the first UPIU is processed and completed.

[0026] According to the eighth or ninth UFS storage device control component of the first aspect of the present application, the tenth UFS storage device control component of the first aspect of the present application is provided, wherein the processor, in response to identifying that data is to be obtained through N UPIUs as a write data unit type or a read data unit type according to the command slot, generates a corresponding command descriptor for the first N-1 UPIUs and writes it into the command descriptor register, but does not set the automatic response flag, and generates a corresponding command descriptor for the Nth UPIU and writes it into the command descriptor register, and sets the automatic response flag, wherein N is a positive integer greater than 1.

[0027] According to one of the eighth to tenth UFS storage device control components of the first aspect of the present application, the eleventh UFS storage device control component of the first aspect of the present application is provided, wherein the command descriptor register further comprises a trigger flag; in response to the trigger flag being set, the command processing unit processes the command descriptor obtained from the command descriptor register.

[0028] According to the eleventh UFS storage device control component of the first aspect of the present application, the twelfth UFS storage device control component of the first aspect of the present application is provided, wherein in response to reading data associated with the command descriptor of the command descriptor register from the storage medium, the trigger flag of the command descriptor register is set.

[0029] According to the eleventh or twelfth UFS storage device control component of the first aspect of the present application, the thirteenth UFS storage device control component of the first aspect of the present application is provided, wherein the processor generates a command descriptor added to the command descriptor register according to the command slot, but the trigger flag is in an unset state, and the processor further reads data from the storage medium; in response to reading data associated with the command descriptor of the command descriptor register from the storage medium, the trigger flag of the command descriptor register is set.

[0030] According to the control component of the thirteenth UFS storage device of the first aspect of the present application, the control component of the fourteenth UFS storage device of the first aspect of the present application is provided, wherein the processor generates a command descriptor added by the command slot to the command descriptor register, but makes the trigger flag in the unset state, and the processor further instructs the media interface controller to read data from the storage medium; in response to the media interface controller reading out the data associated with the command descriptor of the command descriptor register from the storage medium, the processor or the media interface controller sets the trigger flag of the command descriptor register.

[0031] According to one of the control components of the first to fourteenth UFS storage devices of the first aspect of the present application, the control component of the fifteenth UFS storage device of the first aspect of the present application is provided, further comprising: a response generation unit, an RTT generation unit and a write data unit coupled with the command processing unit; in response to the command descriptor indicating that the data to be written by the write command is to be obtained, the command processing unit instructs the RTT generation unit to indicate the length of the data to be obtained, the position of the data to be obtained in all the data to be written by the write command, the cache address of receiving the data to be written and the UPIU header information obtained from the command memory according to the command slot as the RTT unit type UPIU issued by the UPIU processing unit in response.

[0032] According to the control component of the fifteenth UFS storage device of the first aspect of the present application, the control component of the sixteenth UFS storage device of the first aspect of the present application is provided, wherein in response to the RTT generation unit issuing the UPIU as the RTT unit type by the UPIU processing unit, the command processing unit further sets the state to wait for receiving the UPIU as the write data unit type, and does not instruct the processor to indicate that the processing of the command descriptor is completed.

[0033] According to the control component of the sixteenth UFS storage device of the first aspect of the present application, the control component of the seventeenth UFS storage device of the first aspect of the present application is provided, wherein the UPIU processing unit provides the UPIU as the write data unit type to the write data unit; the write data unit responds to obtaining the UPIU as the write data unit type, and moves the data carried by the UPIU as the write data unit type to the position indicated by the cache address of receiving the data to be written in the memory, and in response, the command processing unit updates the state of the command descriptor register to indicate that the processing of the command descriptor is completed.

[0034] According to the seventeenth UFS storage device control component of the first aspect of the present application, the eighteenth UFS storage device control component of the first aspect of the present application is provided, wherein if the automatic response flag is set in the command descriptor register, in response to the write data unit, the data carried by the UPIU of the write data unit type is moved to the position indicated by the cache address receiving the write data, the command processing unit further issues a second UPIU of the response unit type through the UPIU processing unit to indicate that the command associated with the first UPIU is processed and completed, and the state of the command descriptor register is updated in response to indicate that the command descriptor processing is completed.

[0035] According to one of the fifteenth to eighteenth UFS storage device control components of the first aspect of the present application, the nineteenth UFS storage device control component of the first aspect of the present application is provided, further comprising a read data unit coupled to the command processing unit; in response to the command descriptor indicating the data to be read by the output read command, the command processing unit indicates to the read data generation unit the length of the data to be output, the position of the data to be output in all the data to be read by the read command, the cache address to cache the data to be output, and the UPIU header information obtained from the command memory according to the command slot, in response, the read data generation unit issues a UPIU of the read data unit type through the UPIU processing unit.

[0036] According to one of the fifteenth to nineteenth UFS storage device control components of the first aspect of the present application, the twentieth UFS storage device control component of the first aspect of the present application is provided, wherein the command processing unit obtains the UPIU header information from the command memory according to the command slot and provides it to the response generation unit, the RTT generation unit, the write data unit and / or the read data unit.

[0037] According to one of the fifteenth to twentieth UFS storage device control components of the first aspect of the present application, the twenty-first UFS storage device control component of the first aspect of the present application is provided, wherein the command processing unit, in response to issuing a UPIU of the response unit type indicating that the command processing is completed through the UPIU processing unit, further cancels the association of the command slot corresponding to the UPIU of the response unit type with the command.

[0038] According to the second aspect of the present application, the first UFS storage device according to the second aspect of the present application is provided, comprising an NVM chip and one of the first to twenty-first UFS storage device control components according to the first aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained based on these drawings.

[0040] Figure 1 is a block diagram of a storage device in the prior art;

[0041] Figure 2A and Figure 2B a schematic diagram showing that the USF protocol implements a write command and a read command through a UPIU is shown;

[0042] Figure 3A a block diagram showing a command extraction part of a control component of a storage device according to an embodiment of the present application is shown;

[0043] Figure 3B a flow chart showing that a command slot is allocated to a command indicated by a UPIU according to an embodiment of the present application is shown;

[0044] Figure 4 a block diagram showing a control component of a storage device according to an embodiment of the present application is shown;

[0045] Figure 5 a block diagram showing a control component of a storage device according to another embodiment of the present application is shown;

[0046] Figure 6 a block diagram showing a control component of a storage device according to still another embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0048] Figure 3A a block diagram showing a command extraction part of a control component of a storage device according to an embodiment of the present application is shown.

[0049] The control component acquires a UPIU provided by a host through a host interface 310, and provides the UPIU to a UPIU processing unit 320 coupled thereto. The UPIU processing unit 320 identifies the type of the UPIU, extracts a command sent by the host to the storage device from the UPIU as a command unit type, and fills the command into a command queue 330. The command queue 330 is coupled to a command slot allocation unit 340.

[0050] According to embodiments of the present application, a plurality of command slots are provided to represent the commands that the control unit can process concurrently. The control unit has a specified number of command slots. For example, 32 command slots for accepting IO commands, 8 command slots for accepting management commands, 1 command slot for accepting advisory commands, etc. Still as an example, a command slot is uniquely identified by a command identifier of the command being processed. The command slot assignment unit 340 associates a command fetched from the command queue 330 with an available command slot according to the type of the command. If there is no available command slot of the type corresponding to the command, the control unit rejects the command and sends a UPIU to the host to inform the host that the storage device is temporarily unable to process the command. The command remains associated with the command slot during the process of the control unit processing the command, so that an occupied command slot represents a command that the control unit is processing concurrently, and an available command slot represents a command that the control unit can accept. Each command slot also uniquely indexes a command cache unit. The command memory 350 contains a plurality of command cache units. For example, a command slot has a sequence number, according to which a command cache unit in the command memory 350 is indexed. So that during the process of subsequently processing a command, the command (content) can be fetched from the command memory 350 according to the command slot associated with the command.

[0051] The command slot assignment unit 340 fetches a command from the command queue 330 and assigns an available command slot to the command according to the type of the command. If there is no available command slot of the type corresponding to the command, the command slot assignment unit 340 optionally generates a UPIU of the response unit type according to the content of the command and sends the UPIU to the host through the UPIU processing unit 320 to indicate to the host that the storage device is currently unable to process the type of command. If an available command slot is successfully assigned, the command slot assignment unit 340 moves the content of the fetched command to a command cache unit in the command memory 350 indicated by the assigned command slot, and fills the command slot into one of the command slot queues. Obviously, a command slot is different from the command associated with it, Figure 3A In an example, the command queue 330 stores the commands extracted from the UPIU, and the entries in the command slot queue are command slots.

[0052] According to embodiments of the present application, by providing a specified number of command slots and assigning a command slot to a command, the number of commands that the control unit can process concurrently is identified, the number of commands accepted by the control unit is ensured not to exceed the number of command slots, and when the control unit processes the commands concurrently is saturated (there is no available command slot of the type), the additional received command is rejected. These operations are implemented by hardware without software intervention, thereby reducing the software workload and improving the processing speed of the storage device.

[0053] Figure 3AA plurality of command slot queues are also shown. Optionally, the command slot queues each have a priority. For example, command slots associated with read commands are filled into a high priority command slot queue, while command slots associated with write commands are associated with a low priority queue. Optionally, a single command slot queue is used.

[0054] The content of a command includes a variety of information. Some information is related to the processing of the command, such as the type of command, the data address to be accessed, etc. Other information is not related to the processing of the command, such as the UPIU header. In an optional embodiment, the command slot allocation unit 340 records the information of the command that is related to the processing of the command in the allocated command slot, thereby reducing the storage capacity required for the command slot queue and the CPU 360 can process the command based on the command fetched from the command slot queue without having to access the command memory 350 again. The command slot allocation unit 340 moves the information of the command that is not related to the processing of the command to the command cache unit of the command memory indexed by the allocated command slot. The command cache unit is then accessed to fetch, for example, the UPIU header to generate the corresponding UPIU when sending the UPIU corresponding to the command to the host. In a further optional embodiment, the command slot only includes the command identification number, and other information of the corresponding command is stored in the command cache unit to minimize the size of the command slot itself.

[0055] The CPU 360 executes software to fetch a command slot from the command slot queue and process the command based on the information carried by the command slot. During or after the software processes the command, the hardware is also operated to generate one or more UPIUs sent to the host, which is described in detail later.

[0056] Figure 3B A flowchart of allocating a command slot for a UPIU indicated command according to an embodiment of the present application is shown.

[0057] In response to fetching an IO command from a UPIU provided by the host, it is determined whether there is an available command slot. If none of the command slots of the control space applicable to the type of the fetched IO command is currently associated with other IO commands and there is no available command slot, the processing of the fetched IO command is rejected. A UPIU of the response unit type is sent to the host to indicate that the IO command cannot be processed at the current time.

[0058] If there is an available command slot, the fetched IO command is parsed, the IO command is associated with one of the available command slots, the content of the IO command is stored in the command cache unit indicated by the associated command slot, and the command slot is added to the command slot queue. Optionally, the priority of the IO command is also fetched, and the command slot associated with the command is added to the command slot queue corresponding to the fetched priority.

[0059] The CPU of the control component fetches a command slot from the command slot queue and processes it by executing software.

[0060] When the command corresponding to the command slot is processed, the association of the command with the command slot is cancelled, and the command slot becomes available to be associated with another command.

[0061] Figure 4 A block diagram of a control component of a storage device according to an embodiment of the application is shown.

[0062] The control component includes a host interface 410, a UPIU processing unit 420, a command queue 430, a command slot allocation unit 440, one or more command slot queues, a command memory 450, and a CPU 460.

[0063] The control component also includes a command processing unit 480, a command descriptor register 485 coupled to the command processing unit 480, a response generation unit 482, a read data unit 484, an RTT generation unit 486, and a write data unit 488, and a memory 490.

[0064] The control component fetches a UPIU provided by the host through the host interface 410 and provides it to the UPIU processing unit 420 coupled thereto. The UPIU processing unit 420 identifies the type of the received UPIU, extracts a command sent by the host to the storage device from the UPIU as a command unit type, and fills the command into the command queue 430. The UPIU processing unit 420 provides a UPIU as a write data unit type to the write data unit 488. The UPIU processing unit 420 also provides a UPIU to the host through the host interface. For example, the response generation unit 482 generates a UPIU as a response unit type and provides it to the host through the UPIU processing unit 420 to indicate the status of the command processing to the host. The read data unit 482 generates a UPIU as a read data unit type and provides it to the host through the UPIU processing unit 420 to provide the data to be fetched by the read command to the host.

[0065] The command slot assignment unit 440 associates the command fetched from the command queue 430 with an available command slot according to the type of the command. If there is no available command slot for the type of the command, the control unit rejects the command and sends a UPIU to the host to inform the host that the storage device is temporarily unable to process the command. The command remains associated with the command slot during the processing of the command by the control unit, so that an occupied command slot represents a command being concurrently processed by the control unit, and an available command slot represents a command that can be accepted by the control unit. Each command slot also uniquely indexes a command cache unit. The command memory 450 contains a plurality of command cache units. For example, the command slots have serial numbers that index the command cache units in the command memory 450. Thus, during the subsequent processing of the command, the command (content) can be fetched from the command memory 450 according to the command slot associated with the command.

[0066] The command slot assignment unit 440 fetches the command from the command queue 430 and assigns an available command slot to the command according to the type of the command. If there is no available command slot for the type of the command, the command slot assignment unit 440 optionally provides the command to the response generation unit 482, which generates a UPIU as a response unit type according to the content of the command and sends the UPIU to the host through the UPIU processing unit 420 to indicate to the host that the storage device is currently unable to process the type of the command. The control unit does not further process the command. It is understood that the command slots have specified types, and the command slots of various types have specified quantities. Thus, the command slots of a type can be exhausted, while the command slots of other types can still be available, so that an available command slot can be obtained for the type of the command.

[0067] According to embodiments of the present application, when an available command slot cannot be obtained for a command, the command is rejected instead of being temporarily stored for processing when an available command slot becomes available, which reduces the complexity of the control unit.

[0068] The command slot assignment unit 440 moves the content of the command to the command cache unit in the command memory 450 indicated by the assigned command slot and fills the command slot into one of the command slot queues in response to obtaining an available command slot for the command.

[0069] The CPU 460 executes software to fetch a command slot from the command slot queues and processes the command corresponding to the command slot.

[0070] The CPU 460 generates a command descriptor according to the command to be processed, and fills the generated command descriptor into the command descriptor register 485. The command descriptor is an "instruction" for the CPU to operate the command processing unit 480. The CPU 460 provides the instruction to the command processing unit 480 by filling the generated command descriptor into the command descriptor register 485. The CPU 460 also acquires the processing result of the instruction by the command processing unit 480 from the command descriptor register 485.

[0071] As an example, the command to be processed is a write command. The CPU 460 instructs the command processing unit 480 to generate one or more UPIUs of the RTT unit type to instruct the host to provide data to be written. To receive the data to be written, the CPU 460 needs to allocate a cache address to receive the data and the length of the data to be received, and the host also needs to know which command the data to be received is for.

[0072] The CPU 460 acquires the content of the command from the command memory 450 according to the command slot, determines how many UPIUs of the write data unit type are to be used to acquire the data to be written, and allocates a cache of a specified size in the memory 490 for each UPIU of the write data unit type. To obtain a UPIU of the write data unit type from the host, the storage device sends a UPIU of the RTT unit type to the host. The CPU 460 generates a command descriptor according to the UPIU of the write data unit type to be obtained from the host, using the allocated cache address, data length, command slot, and the like, and writes the command descriptor into the command descriptor register 485.

[0073] The command processing unit 480 processes according to the command descriptor in the command descriptor register 485, and writes the processing result into the command descriptor register 485.

[0074] The CPU 460 knows that the previous command descriptor has been processed according to the command descriptor register 485, and as an example, has obtained a UPIU of the write data unit type. The CPU 460 determines whether there are still one or more UPIUs of the write data unit type to be used to acquire the data corresponding to the write command from the host according to the write command, and generates a descriptor again and writes it into the command descriptor register 485.

[0075] The CPU 460, in response to the completion of the processing of the command, optionally generates a descriptor to provide to the command processing unit 480 to instruct the command processing unit 480 to generate a UPIU of the response unit type to indicate to the host that the processing of the command is complete.

[0076] The command processing unit 480, in response to the instructions obtained from the command descriptor register 485, generates UPIUs to be sent to the host through the UPIU processing unit 420 via one or more of the response generation unit 482, the read data unit 484, and the RTT generation unit 486. The command processing unit 480 also obtains UPIUs provided by the UPIU processing unit 420 from the host as write data unit types to identify that the host has provided data to be written by a write command and updates the command descriptor register 485 to inform the CPU 460.

[0077] As an example, if the command descriptor of the command descriptor register 485 indicates that the command processing unit 480 is to obtain data from the host to be written by a write command, the command processing unit 480 provides the RTT generation unit 486 with information such as the length of the data to be obtained, the location of the data to be obtained in the data to be written by the write command, and the like. The command processing unit 480 also obtains UPIU header information from the command buffer unit of the command memory 450 according to the command slot and provides the RTT generation unit 486 with the UPIU header information. The RTT generation unit 486 generates a UPIU as an RTT unit type according to the obtained information and sends the UPIU to the host through the UPIU processing unit 420.

[0078] In response, the command processing unit 480 also sets a state to wait for a response from the host to the aforementioned UPIU as an RTT unit type. The response from the host is a UPIU as a write data unit type. The write data unit 488 obtains the UPIU as a write data unit type from the UPIU processing unit 420 and moves the data to be written by the host to the memory 490 at the address indicated by the previous command descriptor. The command processing unit 480 updates the command descriptor register 485 in response to the data provided by the host through the UPIU as a write data unit type being moved to the memory 490 to indicate to the CPU 460 that the processing of the previous command descriptor is complete. Thus, the CPU 460 provides the command processing unit 480 with a command descriptor associated with a write command, the command processing unit 480 sends a UPIU as an RTT unit type to the host, and receives a corresponding UPIU as a write data unit type from the host. If the write command requires more UPIUs to obtain data to be written, the CPU 460 provides the command processing unit 480 with more command descriptors.

[0079] As another example, for a read command, CPU 460 fetches the data to be read from the storage medium and stores it in memory 490. If CPU 460 indicates to command processing unit 480 a command descriptor associated with the read command, command processing unit 480 only issues a UPIU of type read data unit to the host. Command processing unit 480 provides read data unit 484 with the length of data to be transmitted to the host, the location of the data to be transmitted in the data to be read by the read command, and other information. Command processing unit 480 also fetches the UPIU header information from the command buffer unit of command memory 450 according to the command slot and provides it to read data unit 484. Read data unit 484 generates a UPIU of type read data unit according to the information it has fetched and sends it to the host through UPIU processing unit 420. In response to sending the UPIU of type read data unit to the host, command processing unit 480 also updates command descriptor register 485 to indicate to CPU 460 that the previous command descriptor has been processed.

[0080] If more UPIUs are needed for the read command to transmit the read data to the host, CPU 460 provides command processing unit 480 with more command descriptors.

[0081] CPU 460 also recognizes that a command has been processed. For example, for a write command, all the data to be written has been fetched from the host, meaning that the write command has been processed; or for a read command, all the data to be read has been provided to the host, meaning that the write command has been processed. CPU 460 also provides command processing unit with a command descriptor indicating that a UPIU of type response unit is to be generated. In response, command processing unit 480 fetches the UPIU header information from command memory 450 according to the indication of the command slot and instructs response generation unit 482 to provide a UPIU of type response unit to the host. If the UPIU of type response unit indicates that the command has been processed, response generation unit 482 also disassociates the command slot corresponding to the UPIU of type response unit from the command, so that the command slot can be used to accept a new command.

[0082] It is understood that for other kinds of commands, CPU 460 generates corresponding command descriptors to instruct command processing unit 480 to generate corresponding UPIUs and obtains the processing results from the updates of the command descriptors by command processing unit 480.

[0083] According to FIG. 3 and Figure 4 The embodiments shown are implemented in cooperation of hardware and software. For each command, CPU generates one or more command descriptors. It is desired to reduce the number of command descriptors that CPU interacts with hardware to reduce the burden on CPU during command processing.

[0084] Figure 5 A block diagram of a control component of a storage device according to yet another embodiment of the application is shown.

[0085] Figure 5 A portion of the control component for processing a write command is shown.

[0086] The control component includes a host interface 510, a UPIU processing unit 520, a command queue 530, a command slot assignment unit 540, one or more command slot queues, a command memory 550, and a CPU 560.

[0087] The control component also includes a command processing unit 580, a command descriptor register 585 coupled to the command processing unit 580, a response generation unit 582, an RTT generation unit 486, and a write data unit 488, and a memory 590. The command descriptor register 585 also includes an automatic response flag.

[0088] The control component obtains a UPIU provided by the host through the host interface 510 and provides it to the UPIU processing unit 520 coupled thereto. The UPIU processing unit 420 identifies the type of the received UPIU, extracts the command sent by the host to the storage device from the UPIU as a command unit type, and fills the command into the command queue 530.

[0089] The command slot assignment unit 540 associates the command obtained from the command queue 530 with an available command slot according to the type of the command.

[0090] The command slot assignment unit 540, in response to obtaining an available command slot for the command, moves the content of the command to a command cache unit in the command memory 550 indicated by the assigned command slot, and fills the command slot into one of the command slot queues.

[0091] The CPU 560 executes software to obtain a command slot from the command slot queues, and processes the command corresponding to the command slot. In the example, the command is a write command. Figure 5

[0092] The CPU 560 instructs the command processing unit 580 to generate one or more UPIUs as RTT unit types to instruct the host to provide data to be written. The CPU 560 determines how many write data unit type UPIUs are to be obtained from the host to obtain the data to be written, allocates a specified size cache in the memory 590 for each write data type UPIU. The CPU 560 generates a command descriptor according to the write data unit type UPIUs to be obtained from the host with the allocated cache address, data length, command slot, etc., and writes the command descriptor into the command descriptor register 585.

[0093] According to Figure 5 ​In some embodiments, the command descriptor also includes an auto-respond flag. In response to processing a write command, CPU 560 recognizes that the data to be written is to be obtained by N (N is a positive integer) write data unit type UPIUs. To obtain the first N-l write data unit type UPIUs, CPU 560 provides the command descriptor to command processing unit 580 without setting the auto-respond flag (e.g., setting the flag to 0). To obtain the Nth write data unit type UPIU, CPU 560 provides the command descriptor to command processing unit 580 with the auto-respond flag set (e.g., setting the flag to 1). In response to the auto-respond flag, command processing unit 580 generates a response unit type UPIU to indicate to CPU 560 that the command processing unit 580 has obtained the data to be written. Figure 5 In some embodiments, in response to completion of processing of a command, CPU 560 no longer generates a descriptor to command processing unit 580 to indicate that command processing unit 580 is to generate a response unit type UPIU. Command processing unit 580 generates a response unit type UPIU in response to the auto-respond flag.

[0094] Command processing unit 580 processes the command descriptor in command descriptor register 585 and writes the results of the processing to command descriptor register 585.

[0095] As an example, if the command descriptor in command descriptor register 585 indicates that command processing unit 580 is to obtain data from the host to be written in response to a write command, command processing unit 580 provides RTT generation unit 586 with information about the length of the data to be obtained, the location of the data to be obtained in the data to be written in response to the write command, etc. Command processing unit 580 also obtains UPIU header information from command buffer unit of command memory 550 in response to the command slot and provides the information to RTT generation unit 586. RTT generation unit 586 generates a UPIU of the RTT unit type in response to the information obtained and sends the UPIU to the host via UPIU processing unit 520.

[0096] In response, command processing unit 580 also sets a state to wait for a response from the host to the aforementioned UPIU of the RTT unit type. The response from the host is a UPIU of the write data unit type. Write data unit 588 obtains the UPIU of the write data unit type from UPIU processing unit 520 and moves the data to be written by the host to memory 590. In response to the data provided by the host in the UPIU of the write data unit type being moved to memory 590, command processing unit 580 updates command descriptor register 585 to indicate to CPU 560 that the processing of the previous command descriptor is complete.

[0097] Optionally, if the command descriptor in the command descriptor register 585 also sets the automatic response flag, in response to the data provided by the host through the UPIU as the write data unit type being moved to the memory 590, the command processing unit 580 does not update the descriptor register 585, but also acquires the UPIU header information from the command memory 550 according to the command slot, and instructs the response generation unit 582 to provide the host with the UPIU as the response unit type, to indicate to the host that the write command processing is completed, and the response generation unit 582 also cancels the association of the UPIU as the response unit type with the command of the command slot, so that the command slot can be used to accept a new command. Next, in response to the UPIU as the response unit type being sent to the host, the command processing unit 580 updates the command descriptor register 585 to indicate to the CPU 560 that the processing of the previous command descriptor is completed.

[0098] It can be understood that if the command descriptor in the command descriptor register 585 does not set the automatic response flag, in response to the data provided by the host through the UPIU as the write data unit type being moved to the memory 590, the command processing unit 580 updates the command descriptor register 585 to indicate to the CPU 560 that the processing of the previous command descriptor is completed.

[0099] Figure 6 A block diagram of a control component of a storage device according to yet another embodiment of the application is shown. Figure 6 The part of the control component for processing a write command is shown.

[0100] The control component includes a host interface 610, a UPIU processing unit 620, a command queue 630, a command slot allocation unit 640, one or more command slot queues, a command memory 650, and a CPU 660.

[0101] The control component further includes a command processing unit 680, a command descriptor register 685 coupled to the command processing unit 680, a response generation unit 682, a read data unit 684, and a memory 690. The command descriptor register 685 further includes an automatic response flag.

[0102] The CPU 660 executes software to acquire a command slot from the command slot queue, and processes the command corresponding to the command slot. In the example of Figure 6 The command is a read command.

[0103] The CPU 660 instructs the command processing unit 680 to generate one or more UPIUs of the data unit type to provide the host with the data to be read by the read command. The CPU 660 obtains the data to be read from the storage medium of the storage device and buffers the data in the memory 690. The CPU 660 determines how many UPIUs of the read data unit type are to be used to transfer the data to be read to the host, generates a command descriptor from the address of the data in the memory 690, the length of the data, the command slot, and the like for each UPIU of the read data unit type to be sent to the host, and writes the command descriptor to the command descriptor register 685.

[0104] According to an embodiment of the application, the command descriptor further includes an automatic response flag. If the CPU 660 determines that N (N is a positive integer) UPIUs of the read data unit type are to be used to transfer the data to be read to the host in order to process the read command, the CPU 660 provides the command descriptor to the command processing unit 680 without setting the automatic response flag (e.g., setting the flag to 0) for the first N-1 UPIUs of the read data unit type to be transmitted and sets the automatic response flag (e.g., setting the flag to 1) for the Nth UPIU of the read data unit type to be transmitted. Figure 6 According to an embodiment of the application, the CPU 660 generates a descriptor to provide to the command processing unit 680 in response to the completion of processing of the command, but no longer instructs the command processing unit 680 to generate a UPIU of the response unit type. The command processing unit 680 generates a UPIU of the response unit type based on the automatic response flag. Figure 6

[0105] The command processing unit 680 processes the command descriptor in the command descriptor register 685 and writes the results of the processing to the command descriptor register 685.

[0106] As an example, if the command descriptor in the command descriptor register 685 instructs the command processing unit 680 to transfer the data to be read by the read command to the host, the command processing unit 680 provides the read data unit 684 with the length of the data to be obtained, the location of the data to be transferred in the data to be read by the read command, the address of the data to be transferred in the memory 690, and the like. The command processing unit 680 also obtains the UPIU header information from the command buffer unit of the command memory 650 based on the command slot and provides the read data unit 684 with the information. The read data unit 684 generates a UPIU of the read data unit type based on the obtained information and sends the UPIU to the host via the UPIU processing unit 620.

[0107] ​The command processing unit 680, in response to the data moving the host through the UPIU as the read data unit type, updates the command descriptor register 685 to indicate to the CPU 660 that the previous command descriptor is processed.

[0108] Optionally, if the command descriptor in the command descriptor register 685 also sets the automatic response flag, in response to the data moving the host through the UPIU as the read data unit type, the command processing unit 680 does not update the descriptor register 685, but also acquires the UPIU header information from the command memory 650 according to the command slot, and instructs the response generating unit 682 to provide the UPIU as the response unit type to the host to indicate to the host that the read command processing is completed, and the response generating unit 682 also cancels the association of the UPIU as the response unit type to the corresponding command slot of the command, so that the command slot can be used to accept a new command. Next, the command processing unit 680, in response to sending the UPIU as the response unit type to the host, updates the command descriptor register 685 to indicate to the CPU 660 that the previous command descriptor is processed.

[0109] It can be understood that if the command descriptor in the command descriptor register 685 does not set the automatic response flag, the command processing unit 680, in response to the data moving the host through the UPIU as the read data unit type, updates the command descriptor register 685 to indicate to the CPU 660 that the previous command descriptor is processed.

[0110] Optionally or further, the command descriptor register 685 further includes a trigger flag (not shown in the figure) indicating whether the command processing unit 680 is triggered to process the command. Figure 6In processing the read command, CPU 660 is required to read the data required by the read command from the storage medium and cache in memory 690, which takes a long time and causes a long and uncertain time interval between when CPU 660 processes the read command and when the command descriptor(s) corresponding to the read command can be processed by command processing unit 680, and introduces further work load to CPU 660. According to embodiments of the present application, the command descriptor further includes a trigger flag. CPU 660 generates the command descriptor and writes it into command descriptor register 685 upon obtaining the read command, but does not set the trigger flag. In response to the trigger flag not being set, command processing unit 680 does not process the command descriptor in descriptor register 685. Instead, in response to the data being read from the storage medium and cached in memory 690, the trigger flag of command descriptor register 685 is set. In response to the trigger flag being set, command processing unit 680 starts processing the command descriptor. In one implementation, CPU 660 operates the medium interface controller to read the data from the storage medium, and the medium interface controller notifies CPU 660 that the data movement is complete in response to the read data being moved to memory 690, and then CPU 660 sets the trigger flag of command descriptor register 685. In another implementation, CPU 660 operates the medium interface controller to read the data from the storage medium, and the medium interface controller directly sets the trigger flag of descriptor register 685 in response to the read data being moved to memory 690, thereby further reducing the work load of CPU.

[0111] According to embodiments of the present application, there is also provided a storage device including a controller and a non-volatile memory chip, wherein the controller performs any of the processing methods provided by embodiments of the present application.

[0112] According to embodiments of the present application, there is also provided a program stored on a readable medium, which when executed by a controller of a storage device, causes the storage device to perform any of the processing methods provided by embodiments of the present application.

[0113] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the application. It should be apparent that the application can be embodied in a variety of forms other than those specifically described, without departing from the spirit or essential characteristics of the application. Thus, although the application has been described based upon the preferred embodiments, it would be apparent to those of skill in the art that a variety of modifications, alterations, and improvements can be made to the preferred embodiments without departing from the spirit and scope of the application. In particular, those skilled in the art will recognize that the application can be practiced with more than one memory device, and that the memory device can be any of a variety of memory devices. Thus, the application is not intended to be limited to the embodiments described herein but can be practiced with a variety of modifications.

Claims

1. A control component of a UFS storage device, comprising a UPIU processing unit, a command slot assignment unit, a command memory, a processor and a command processing unit; the UPIU processing unit extracts a first command from a UPIU as a command unit type, and provides the first command to the command slot assignment unit; the command slot assignment unit assigns an available command slot to the first command, stores a first part of the first command to a command cache unit associated with the command slot, and provides the command slot assigned to the first command to the processor; the processor generates one or more command descriptors according to the command slot and provides the command descriptors to the command processing unit; the command processing unit issues a UPIU as a UPIU unit type through the UPIU processing unit according to the command descriptors; the control component further comprises a response generation unit, an RTT generation unit and a write data unit coupled with the command processing unit; in response to the command descriptors indicating data to be written by a write command, the command processing unit indicates to the RTT generation unit a length of the data to be acquired, a position of the data to be acquired in all data to be written by the write command, a cache address to receive the data to be written, and UPIU header information acquired from the command memory according to the command slot, and in response, the RTT generation unit issues a UPIU as an RTT unit type through the UPIU processing unit; wherein in response to the RTT generation unit issuing a UPIU as an RTT unit type through the UPIU processing unit, the command processing unit further sets a state to wait for receiving a UPIU as a write data unit type, and does not indicate to the processor that processing of the command descriptors is complete.

2. The control component of claim 1, further comprising a command queue and one or more command slot queues; the UPIU processing unit adds the extracted first command to the command queue; the command slot assignment unit acquires the first command from the command queue; the command slot assignment unit adds the assigned command slot to one of the one or more command slot queues; the processor acquires the command slot from the one or more command slot queues.

3. The control component of claim 1 or 2, wherein if there is no available command slot assigned to the first command, the command slot assignment unit issues a UPIU as a response type through the UPIU processing unit to indicate that the storage device is currently unable to process the first command.

4. The control component of claim 3, wherein the first part of the first command comprises header information of the UPIU from which the first command is extracted; the command slot assignment unit adds a second part of the first command to the command slot, wherein the second part of the second command is related to processing of the command by the processor.

5. The control component of claim 4, further comprising a command descriptor register; the processor provides the command descriptors to the command processing unit by writing the generated command descriptors to the command descriptor register; the command processing unit, in response to issuing a UPIU through the UPIU processing unit according to the command descriptors, further updates the command descriptor register to indicate to the processor that processing of the command descriptors is complete.

6. The control component of claim 4, wherein the command descriptor register further comprises an automatic response flag; If the automatic response flag is set, the command processing unit, after issuing the first UPIU according to the command descriptor through the UPIU processing unit, also issues a second UPIU as a response unit type through the UPIU processing unit to indicate that the command associated with the first UPIU is processed completed.

7. The control component of claim 5, wherein The processor, in response to identifying according to the command slot that data is to be acquired through N UPIUs as the write data unit type or the read data unit type, generates and writes the corresponding command descriptor into the command descriptor register for the first N-1 UPIUs without setting the automatic response flag, and generates and writes the corresponding command descriptor into the command descriptor register for the Nth UPIU and sets the automatic response flag, where N is a positive integer greater than 1.

8. A UFS storage device comprising an NVM chip and the control component of the UFS storage device according to any one of claims 1-7.

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