A magnetic latching relay drive circuit for an AC charging pile

Abstract

The invention discloses a driving circuit for a magnetic latching relay of an AC charging pile, which includes a logic chip U2 and a two-input exclusive-OR gate U3. The pin 2 of the logic chip U2 is connected to the resistor R45 after being connected in series with the resistor R11, and the resistor R45 is connected to the pin 1 of the triode Q2. The pin 3 of the logic chip U2 is connected to the pin 4 of the two-input exclusive-OR gate U3 after being connected in series with the resistor R13. The pin 5 of the logic chip U2 is connected to the resistor R44 after being connected in series with the resistor R16, and the resistor R44 is connected to the pin 1 of the triode Q1. The pin 9 of the logic chip U2 is connected to the reset relay signal terminal K1_CLOSED_CTR after being connected in series with the resistor R18, and the pin 10 of the logic chip U2 is connected to the open relay signal terminal K_OPEN_CTR after being connected in series with the resistor R17. The novel driving circuit for the magnetic latching relay of the AC charging pile simplifies the software control process and enables hardware interlocking. All functions of the traditional magnetic latching relay can be achieved only by switching the open relay signal terminal K_OPEN_CTR and the reset relay signal terminal K1_CLOSED_CTR.

Description

Technical Field

[0001] The present invention relates to the technical field of relays, and in particular to a drive circuit for a magnetic latching relay of an AC charging pile. Background Art

[0002] Compared with ordinary relays, traditional magnetic latching relays only require pulse drive and have a magnetic latching function, which can reduce coil loss, reduce the heat generation of the relay, and are suitable for applications with large current and low heat requirements; it has two coil drives, one side is the turn-on coil, and the other side is the reset coil, that is, the turn-on coil drive can connect the contacts and turn on the relay; the turn-on and reset drive, which is the turn-off coil drive, can disconnect the contacts and turn off the relay.

[0003] In the traditional drive method, four control signals are used to directly control the opening and closing of relay K1 and the opening and closing of K2. Its disadvantages are: the control signals occupy many IO ports, require software switch signals to be complementary, and the logic is complex. Summary of the Invention

[0004] The purpose of the present invention is to provide a drive circuit for a magnetic latching relay of an AC charging pile, which simplifies the software control process and enables hardware interlocking. All functions of the traditional magnetic latching relay can be realized only by the relay signal terminal K_OPEN_CTR for turning on the switch and the relay signal terminal K1_CLOSED_CTR for resetting the relay, thus solving the problems in the prior art.

[0005] To achieve the above object, the present invention provides the following technical solution: An AC charging pile magnetic latching relay drive circuit, including a logic chip U2 and a two-input exclusive-OR gate U3. The pin 2 of the logic chip U2 is connected to the resistor R45 after being serially connected with the resistor R11, and the resistor R45 is connected to the pin 1 of the triode Q2. The pin 3 of the logic chip U2 is connected to the pin 4 of the two-input exclusive-OR gate U3 after being serially connected with the resistor R13. The pin 5 of the logic chip U2 is connected to the resistor R44 after being serially connected with the resistor R16, and the resistor R44 is connected to the pin 1 of the triode Q1. The pin 9 of the logic chip U2 is connected to the reset relay signal terminal K1_CLOSED_CTR after being serially connected with the resistor R18. The pin 10 of the logic chip U2 is connected to the open relay signal terminal K_OPEN_CTR after being serially connected with the resistor R17. The pin 13 of the logic chip U2 is connected to the output signal terminal K_SIG after being serially connected with the resistor R15. The pin 14 of the logic chip U2 is connected to the resistor R54 after being serially connected with the resistor R14, and the resistor R54 is connected to the pin 1 of the triode Q3. The pin 15 of the logic chip U2 is connected to the resistor R55 after being serially connected with the resistor R12, and the resistor R55 is connected to the pin 1 of the triode Q4. The pin 1 of the two-input exclusive-OR gate U3 is connected to the circuit interface of the resistor R17 after being serially connected with the resistor R22, and the pin 2 of the two-input exclusive-OR gate U3 is connected to the circuit interface of the resistor R18 after being serially connected with the resistor R23. A resistor R46 is connected in parallel across the two ends of the pins 1 and 2 of the triode Q1, and the pin 3 of the triode Q1 is connected to the open relay terminal K1_OPEN. A resistor R47 is connected in parallel across the two ends of the pins 1 and 2 of the triode Q2, and the pin 3 of the triode Q2 is connected to the reset relay terminal K1_CLOSED. A resistor R56 is connected in parallel across the two ends of the pins 1 and 2 of the triode Q3, and the pin 3 of the triode Q3 is connected to the open relay terminal K2_OPEN. A resistor R57 is connected in parallel across the two ends of the pins 1 and 2 of the triode Q4, and the pin 3 of the triode Q4 is connected to the reset relay terminal K2_CLOSED.

[0006] Preferably, the model of the two-input exclusive-OR gate U3 is SN74LVC1G86DCKR.

[0007] Preferably, the model of the logic chip U2 is CD4052BM96.

[0008] Preferably, the models of the triodes Q1, Q2, and Q3 are all MMBT440ILT1G.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0010] The novel alternating current charging pile magnetic latching relay driving circuit, through the combination of the logic chip U2, only requires two control signals, namely the relay opening signal K_OPEN_CTR and the relay reset signal K_CLOSED_CTR, to achieve the synchronous opening or synchronous shutdown of two relays, and ensures that the two coil signals of the same relay are complementary, making the software processing flow simple. Description of the Drawings

[0011] Figure 1 It is the circuit diagram of the logic chip and the two-input exclusive-OR gate of the present invention;

[0012] Figure 2 It is the circuit diagram of the triode Q1 of the present invention;

[0013] Figure 3 It is the circuit diagram of the triode Q2 of the present invention;

[0014] Figure 4 It is the circuit diagram of the triode Q3 of the present invention;

[0015] Figure 5 It is the circuit diagram of the triode Q4 of the present invention. Detailed Embodiment

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] Please refer to Figures 1-5, An alternating current charging pile magnetic latching relay drive circuit, including a logic chip U2 of model CD4052BM96 and a two-input exclusive-OR gate U3 of model SN74LVC1G86DCKR; pin 2 of the logic chip U2 is connected to resistor R45 after being connected in series with resistor R11, resistor R45 is connected to pin 1 of transistor Q2, pin 3 of the logic chip U2 is connected to pin 4 of the two-input exclusive-OR gate U3 after being connected in series with resistor R13, pin 5 of the logic chip U2 is connected to resistor R44 after being connected in series with resistor R16, resistor R44 is connected to pin 1 of transistor Q1, pin 9 of the logic chip U2 is connected to the reset relay signal terminal K1_CLOSED_CTR after being connected in series with resistor R18, pin 10 of the logic chip U2 is connected to the open relay signal terminal K_OPEN_CTR after being connected in series with resistor R17, pin 13 of the logic chip U2 is connected to the output signal terminal K_SIG after being connected in series with resistor R15, pin 14 of the logic chip U2 is connected to resistor R54 after being connected in series with resistor R14, resistor R54 is connected to pin 1 of transistor Q3, pin 15 of the logic chip U2 is connected to resistor R55 after being connected in series with resistor R12, resistor R55 is connected to pin 1 of transistor Q4; pin 1 of the two-input exclusive-OR gate U3 is connected to the circuit interface of resistor R17 after being connected in series with resistor R22, pin 2 of the two-input exclusive-OR gate U3 is connected to the circuit interface of resistor R18 after being connected in series with resistor R23; resistors R46 are connected in parallel across the two ends of pins 1 and 2 of transistor Q1, and pin 3 of transistor Q1 is connected to the open relay terminal K1_OPEN; resistors R47 are connected in parallel across the two ends of pins 1 and 2 of transistor Q2, and pin 3 of transistor Q2 is connected to the reset relay terminal K1_CLOSED; resistors R56 are connected in parallel across the two ends of pins 1 and 2 of transistor Q3, and pin 3 of transistor Q3 is connected to the open relay terminal K2_OPEN; resistors R57 are connected in parallel across the two ends of pins 1 and 2 of transistor Q4, and pin 3 of transistor Q4 is connected to the reset relay terminal K2_CLOSED; since the models of transistors Q1, Q2, and Q3 are all MMBT440ILT1G, only when the open relay signal K_OPEN_CTR and the reset relay signal K_CLOSED_CTR are complementary, the output signal Y pin of the two-input exclusive-OR gate U3 will have a high level. When combined with the logic chip U2, a high level is output, and the current is amplified and driven through transistors Q1, Q2, and Q3. Otherwise, at a low level, it does not participate in the control of the subsequent stage drive signal.

[0018] In this new alternating current charging pile magnetic latching relay drive circuit, since the logic chip U2 can combine the A open relay signal and the B close relay signal into 2 - 4 groups of unique decoding signals, when A = 1 and B = 0 are satisfied, the drive of the open relay is enabled. When B = 1 and A = 0 are satisfied, the drive of the reset relay is enabled. When A = 1 and B = 1 or when A = 0 and B = 0 are satisfied, the current state is maintained and no new control logic is participated in.

[0019] The novel AC charging pile magnetic latching relay drive circuit, through the combination of logic chip U2, only requires two control signals, namely the relay opening signal K_OPEN_CTR and the relay reset signal K_CLOSED_CTR, to achieve the synchronous opening or synchronous shutdown of two relays, and ensures that the two coil signals of the same relay are complementary, making the software processing flow simple.

[0020] In summary: The novel AC charging pile magnetic latching relay drive circuit simplifies the software control process and enables hardware interlocking. All functions of the traditional magnetic latching relay can be achieved only by switching the relay opening signal terminal K_OPEN_CTR and the relay reset signal terminal K1_CLOSED_CTR, thus effectively solving the problems in the prior art.

[0021] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device.

[0022] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A magnetic latching relay drive circuit for an AC charging pile, comprising a logic chip U2 and a two-input exclusive OR gate U3, characterized in that: Pin 2 of the logic chip U2 is connected to resistor R45 after being serially connected with resistor R11. Resistor R45 is connected to pin 1 of transistor Q2. Pin 3 of the logic chip U2 is connected to pin 4 of the two-input exclusive-OR gate U3 after being serially connected with resistor R13. Pin 5 of the logic chip U2 is connected to resistor R44 after being serially connected with resistor R16. Resistor R44 is connected to pin 1 of transistor Q1. Pin 9 of the logic chip U2 is connected to the reset relay signal terminal K1_CLOSED_CTR after being serially connected with resistor R18. Pin 10 of the logic chip U2 is connected to the open relay signal terminal K_OPEN_CTR after being serially connected with resistor R17. Pin 13 of the logic chip U2 is connected to the output signal terminal K_SIG after being serially connected with resistor R15. Pin 14 of the logic chip U2 is connected to resistor R54 after being serially connected with resistor R14. Resistor R54 is connected to pin 1 of transistor Q3. Pin 15 of the logic chip U2 is connected to resistor R55 after being serially connected with resistor R12. Resistor R55 is connected to pin 1 of transistor Q4; Pin 1 of the two-input exclusive-OR gate U3 is connected to the circuit interface of resistor R17 after being serially connected with resistor R22. Pin 2 of the two-input exclusive-OR gate U3 is connected to the circuit interface of resistor R18 after being serially connected with resistor R23; Resistor R46 is connected in parallel across pins 1 and 2 of transistor Q1. Pin 3 of transistor Q1 is connected to the open relay terminal K1_OPEN; Resistor R47 is connected in parallel across pins 1 and 2 of transistor Q2. Pin 3 of transistor Q2 is connected to the reset relay terminal K1_CLOSED; Resistor R56 is connected in parallel across pins 1 and 2 of transistor Q3. Pin 3 of transistor Q3 is connected to the open relay terminal K2_OPEN; Resistor R57 is connected in parallel across pins 1 and 2 of transistor Q4. Pin 3 of transistor Q4 is connected to the reset relay terminal K2_CLOSED. The model of the logic chip U2 is CD4052BM96. The model of the two-input exclusive-OR gate U3 is SN74LVC1G86DCKR. The models of transistors Q1, Q2, and Q3 are all MMBT440ILT1G.

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