Display Devices

Abstract

The present invention relates to a display device. The display device comprises: a substrate; an active layer arranged on the substrate and comprising an active pattern; a first conductive layer arranged on the active layer; a second conductive layer arranged on the first conductive layer and comprising a data line; a third conductive layer arranged on the second conductive layer; and a light emitting element arranged on the third conductive layer, wherein the first conductive layer comprises a first voltage line, a second voltage line and a scan line, the third conductive layer comprises a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2018-0158345 filed on December 10, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a display device. Background Art

[0004] A display device is a device used to display images. Some display devices require a separate light source to display images, while other display devices are self-luminous. For example, a light-emitting diode display is a self-luminous display device.

[0005] Since the light emitting diode display is self-luminous, the light emitting diode display does not need a separate light source; therefore, the thickness and weight of the light emitting diode display can be reduced. In addition, the light emitting diode display has characteristics such as low power consumption, high brightness and high response speed.

[0006] Generally, a light emitting diode display includes a substrate, a plurality of thin film transistors arranged on the substrate, a plurality of insulating layers arranged between wirings configuring the thin film transistors, and a light emitting element connected to the thin film transistor. The light emitting element may include an organic light emitting element. Summary of the invention

[0007] A display device according to an exemplary embodiment of the present invention includes: a substrate; an active layer, which is arranged on the substrate and includes a plurality of active patterns including a semiconductor material; a first conductive layer, which is arranged on the active layer; a second conductive layer, which is arranged on the first conductive layer and includes a data line for transmitting a data signal; a third conductive layer, which is arranged on the second conductive layer; and a light emitting element, which is arranged on the third conductive layer, wherein the first conductive layer includes a first voltage line, a second voltage line and a scan line for transmitting a scan signal, the third conductive layer includes a third voltage line electrically connected to the first voltage line and a fourth voltage line electrically connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction intersecting the first direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

[0008] The second conductive layer may include a first connection member electrically connected to the first voltage line and a second connection member electrically connected to the second voltage line, the third voltage line may be electrically connected to the first connection member, and the fourth voltage line may be electrically connected to the second connection member.

[0009] The light emitting element may include a pixel electrode disposed on the third conductive layer, an emission layer disposed on the pixel electrode, and a common electrode disposed on the emission layer, and a width of the third voltage line in the first direction may be greater than a width of the pixel electrode in the first direction.

[0010] A width of a space in the first direction between the third voltage line and the fourth voltage line adjacent to each other may be smaller than a width of the third voltage line in the first direction.

[0011] The third conductive layer may further include a third connection member separated from the third voltage line and the fourth voltage line, and the pixel electrode may be electrically connected to the third connection member.

[0012] The third connection member may be disposed in the opening of the third voltage line.

[0013] The first voltage lines and the second voltage lines may be alternately disposed in the second direction, the scan lines may be repeatedly disposed in the second direction, and the first voltage lines and the second voltage lines may be arranged between two adjacent scan lines.

[0014] The first conductive layer may include a driving gate electrode disposed between the scan line and the first voltage line, and the second conductive layer may include a capacitor electrode overlapping the driving gate electrode in a plan view to form a first capacitor.

[0015] A lower pattern that is conductive and disposed between the substrate and the active layer may be further included in the display device, the lower pattern may overlap the driving gate electrode in a plan view to form a second capacitor, and the lower pattern may be electrically connected to the capacitor electrode.

[0016] The active pattern may include a first active pattern of the first transistor, a second active pattern of the second transistor, and a third active pattern of the third transistor, the driving gate electrode may be electrically connected to the conductive area of ​​the second active pattern, the capacitor electrode may be electrically connected to the conductive area of ​​the first active pattern, and the third active pattern may be electrically connected to the capacitor electrode.

[0017] The second conductive layer may further include an initialization voltage line extending in the second direction, and the conductive region of the third active pattern may be electrically connected to the initialization voltage line.

[0018] The active layer may further include a lateral initialization voltage line that is conductive and electrically connected to the initialization voltage line, and the lateral initialization voltage line may be connected to the third active pattern and extend in the first direction.

[0019] The insulating layer arranged on the third conductive layer may be further included in the display device, the light emitting element may include a pixel electrode arranged on the third conductive layer, an emission layer arranged on the pixel electrode, a common electrode arranged on the emission layer, and a common layer arranged between the pixel electrode and the common electrode, the common layer and the insulating layer may have a contact hole arranged on the fourth voltage line, and the common electrode may be electrically connected to the fourth voltage line through the contact hole.

[0020] A fourth conductive layer arranged on the third conductive layer may be further included in a display device, the third conductive layer may further include a connecting member separated from the third voltage line and the fourth voltage line, the fourth conductive layer may include a first contact member contacting the fourth voltage line and a second contact member contacting the connecting member, the common electrode may be electrically connected to the fourth voltage line through the first contact member, and the pixel electrode may be electrically connected to the connecting member through the second contact member.

[0021] A display device according to an exemplary embodiment of the present invention includes: a pixel group including a first pixel, a second pixel, and a third pixel arranged in a first direction and adjacent to each other; a scan line, a first voltage line, and a second voltage line extending in the first direction; a data line corresponding to the first pixel, the second pixel, and the third pixel, respectively, and extending in a second direction crossing the first direction; a third voltage line extending in the second direction and electrically connected to the first voltage line; a fourth voltage line extending in the second direction and electrically connected to the second voltage line; and a light emitting element including a common electrode electrically connected to the fourth voltage line.

[0022] The third voltage lines and the fourth voltage lines may be alternately disposed in the first direction.

[0023] The light emitting element may further include an emission layer and a pixel electrode facing the common electrode, and a width of the third voltage line in the first direction may be greater than a width of the pixel electrode corresponding to the second pixel in the first direction.

[0024] A display device according to an exemplary embodiment of the present invention includes: a first scan line and a second scan line; a plurality of data lines and an initialization voltage line crossing the first scan line and the second scan line; a first voltage line and a second voltage line crossing the plurality of data lines; a first transistor including a first gate electrode arranged between the first scan line and the first voltage line, and a first active pattern crossing the first gate electrode and electrically connected to the first voltage line; a second transistor including a second active pattern electrically connected to the first gate electrode, and a second gate electrode included in the first scan line; a third transistor including a third active pattern electrically connected to the first active pattern, and a third gate electrode included in the second scan line; and a light emitting element including a common electrode, an emission layer, and a pixel electrode electrically connected to the first transistor and the third transistor, wherein the common electrode is electrically connected to the second voltage line.

[0025] A third voltage line and a fourth voltage line crossing the first scan line and the second scan line may be further included in the display device, the third voltage line may be electrically connected to the first voltage line and arranged in a different layer from the first voltage line, and the fourth voltage line may be electrically connected to the second voltage line and arranged in a different layer from the second voltage line.

[0026] The third voltage line may overlap the first active pattern, the second active pattern, and the third active pattern in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 , Figure 3 and Figure 4 is a layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, wherein Figure 4 Shows Figure 2 The configuration shown in Figure 3 The configuration shown in;

[0029] Figure 5 It is taken along the line Va-Vb Figure 4 A cross-sectional view of a display device shown in ;

[0030] Figure 6 It is taken along the line Vc-Vd and the line Vd'-Ve Figure 4 A cross-sectional view of a display device shown in ;

[0031] Figure 7 It is taken along the line Vf-Vg Figure 4 A cross-sectional view of a display device shown in FIG. DETAILED DESCRIPTION

[0032] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways and therefore should not be limited to the embodiments set forth herein.

[0033] Like reference numerals may refer to like elements throughout the specification.

[0034] In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity.

[0035] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0036] Throughout this specification, a plan view may mean a view of observing a surface parallel to two directions intersecting each other (e.g., the x-direction and the y-direction), and a cross-sectional view may mean a view of observing a surface cut in a direction perpendicular to the surface parallel to the x-direction and the y-direction (e.g., the z-direction). In addition, overlapping two constituent elements may mean that the two constituent elements overlap in the z-direction (e.g., a direction perpendicular to the upper surface of the substrate).

[0037] Figure 1 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment of the present invention.

[0038] refer to Figure 1 , a display device according to an exemplary embodiment of the present invention includes a plurality of pixels, and each pixel includes a plurality of transistors T1, T2 and T3, a capacitor Cst and at least one light emitting diode (LED) ED. In the present exemplary embodiment, an example in which one pixel includes one light emitting diode (LED) ED is described.

[0039] The plurality of transistors T1, T2 and T3 may include a first transistor T1, a second transistor T2 and a third transistor T3. A source electrode and a drain electrode described below refer to two electrodes located on either side of a channel of each of the transistors T1, T2 and T3, and the two terms may be interchanged.

[0040] The gate electrode G1 of the first transistor T1 is connected to the first terminal of the capacitor Cst, the source electrode S1 of the first transistor T1 is connected to a driving voltage line for transmitting a driving voltage ELVDD, and the drain electrode D1 of the first transistor T1 is connected to an anode of a light emitting diode (LED) ED and a second terminal of the capacitor Cst. The driving voltage ELVDD may be a predetermined voltage. The first transistor T1 receives the data voltage DAT according to a switching operation of the second transistor T2, and may supply a driving current to the light emitting diode (LED) ED depending on a voltage stored in the capacitor Cst.

[0041] The gate electrode G2 of the second transistor T2 is connected to the first scan line 151 for transmitting the first scan signal SC, the source electrode S2 of the second transistor T2 is connected to the data line 171 for transmitting the data voltage DAT or the reference voltage, and the drain electrode D2 of the second transistor T2 is connected to the first terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on according to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and the first terminal of the capacitor Cst.

[0042] The gate electrode G3 of the third transistor T3 is connected to the second scan line 152 for transmitting the second scan signal SS, the source electrode S3 of the third transistor T3 is connected to the second terminal of the capacitor Cst, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode (LED) ED, and the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line 173 for transmitting the initialization voltage INIT. In addition to transmitting the initialization voltage INIT in the driving period, the initialization voltage line 173 can also sense the voltage of the anode of the light emitting diode (LED) ED connected to the source electrode S3 of the third transistor T3. Herein, the initialization voltage line 173 may be referred to as a sensing line, and the third transistor T3 may be referred to as a sensing transistor.

[0043] The third transistor T3 is turned on according to the second scan signal SS and transmits the initialization voltage INIT to the anode of the light emitting diode (LED) ED and the second terminal of the capacitor Cst to initialize the voltage of the anode of the light emitting diode (LED) ED and to sense the voltage of the anode of the light emitting diode (LED) ED.

[0044] A first terminal of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and a second terminal of the capacitor Cst is connected to the source electrode S3 of the third transistor T3 and an anode electrode of a light emitting diode (LED) ED.

[0045] The cathode of the light emitting diode (LED) ED is connected to a common voltage line for transmitting a common voltage ELVSS. The common voltage ELVSS may be a voltage of a different magnitude from the driving voltage ELVDD. The common voltage ELVSS may be a predetermined voltage. The light emitting diode (LED) ED may emit light according to a driving current formed by the first transistor T1.

[0046] Figure 2 , Figure 3 and Figure 4 is a layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, wherein Figure 4 Shows Figure 2 The configuration shown in Figure 3 The configuration shown in Figure 5 It is taken along the line Va-Vb Figure 4 A cross-sectional view of a display device shown in FIG. Figure 6 It is taken along the line Vc-Vd and the line Vd'-Ve Figure 4 A cross-sectional view of a display device shown in FIG. Figure 7 It is taken along the line Vf-Vg Figure 4 A cross-sectional view of a display device shown in FIG.

[0047] Included in Figure 2 , Figure 3and Figure 4 The plurality of pixels PX1, PX2 and PX3 in one pixel group shown in FIG. 1 may be repeatedly arranged in the first direction DR1 and the second direction DR2. For convenience, most reference numerals are shown only for constituent elements of one pixel PX1, but the same reference numerals and corresponding descriptions for corresponding constituent elements of the other two pixels PX2 and PX3 are also applicable.

[0048] In a plan view, the two pixels PX1 and PX2 have substantially the same structure, and the pixel PX3 may have a structure in which the structure of the pixel PX1 or the pixel PX2 is symmetrical on the right and left sides thereof, but is not limited thereto.

[0049] Hereinafter, a cross-sectional structure of a display device according to an exemplary embodiment of the present invention is described, and a layout form of each constituent element is described.

[0050] refer to Figure 5 , Figure 6 and Figure 7 , a display device according to an exemplary embodiment of the present invention may include a substrate 110. The substrate 110 may include an insulating material such as glass, plastic, or the like, and may have flexibility.

[0051] refer to Figure 2 , Figure 4 , Figure 5 and Figure 6 , a plurality of lower patterns 111 as a first conductive layer may be arranged on the substrate 110. The lower patterns 111 are conductive and may include a semiconductor material having various metals or conductive properties.

[0052] The buffer layer 120 as an insulating layer may be disposed on the lower pattern 111. In other words, the lower pattern 111 may be disposed between the substrate 110 and the buffer layer 120.

[0053] An active layer including a plurality of active patterns may be disposed on the buffer layer 120. In other words, a lower pattern 111 may be disposed between the substrate 110 and the active layer.

[0054] The active pattern of each of the pixels PX1, PX2, and PX3 may include channel regions 134a, 134b, and 134c forming each channel of the transistors T1, T2, and T3 and a conductive region connected thereto. The conductive region of the active pattern may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of each of the transistors T1, T2, and T3.

[0055] The active pattern may further include a transverse initialization voltage line 153 that may transmit an initialization voltage INIT. Each transverse initialization voltage line 153 is disposed corresponding to a plurality of pixels PX1, PX2, and PX3 included in one pixel group that repeats along the first direction DR1 and the second direction DR2. For example, one transverse initialization voltage line 153 may be provided for each pixel group in a plan view.

[0056] The horizontal initialization voltage line 153 may be connected to the drain region 135c of the active pattern of the plurality of third transistors T3 included in the plurality of pixels PX1, PX2, and PX3. The horizontal initialization voltage line 153 may be included in the conductive region of the active pattern and may have conductivity. In a plan view, the horizontal initialization voltage line 153 may extend longitudinally in the first direction DR1.

[0057] The direction in which the active pattern of the third transistor T3 extends may be different from the direction in which the transverse initialization voltage line 153 extends. For example, the active pattern of the third transistor T3 and the transverse initialization voltage line 153 may intersect to be perpendicular to each other.

[0058] The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, an oxide semiconductor, or the like.

[0059] The first insulating layer 140 may be disposed on the active layer. The first insulating layer 140 may be patterned so as not to overlap with the conductive region of the active pattern.

[0060] The second conductive layer may be disposed on the first insulating layer 140 .

[0061] The second conductive layer may include first scan lines 151 and 151p for transmitting a first scan signal SC, a second scan line 152 for transmitting a second scan signal SS, a driving gate electrode 155, a second gate electrode 154b, a third gate electrode 154c, a horizontal driving voltage line 172a for transmitting a driving voltage ELVDD, and a horizontal common voltage line 170a for transmitting a common voltage ELVSS. Figure 1 In the circuit diagram shown in , the gate electrode G1 , the gate electrode G2 , and the gate electrode G3 may correspond to the driving gate electrode 155 , the second gate electrode 154 b , and the third gate electrode 154 c , respectively.

[0062] In a plan view, the first scan lines 151 and 151 p , the second scan line 152 , the transverse driving voltage line 172 a , and the transverse common voltage line 170 a may extend in the first direction DR1 , and may be formed in parallel so as not to intersect each other.

[0063] exist Figure 2 and Figure 4, the first scan line 151p is a first scan line of a previous stage of the first scan line 151. For example, the first scan line 151p may transmit a first scan signal SC of a previous stage of the first scan signal SC transmitted by the first scan line 151. One pixel row PXR may be located between the first scan lines 151 and 151p. In other words, an area starting from the first scan line 151 and reaching the first scan line 151p may be one pixel row PXR. This pixel row PXR may be repeatedly arranged in the second direction DR2.

[0064] In a plan view, the driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152. For example, the driving gate electrode 155 may be disposed between the first scan line 151 and the transverse driving voltage line 172a, and the second scan line 152 may be disposed between the transverse driving voltage line 172a and the transverse common voltage line 170a. In a plan view, the transverse initialization voltage line 153 may be disposed between the second scan line 152 and the transverse common voltage line 170a.

[0065] One transverse driving voltage line 172a and one transverse common voltage line 170a may be arranged in each pixel row PXR. In other words, the spacing of the transverse common voltage lines 170a repeatedly arranged in the second direction DR2 and the spacing of the transverse driving voltage lines 172a repeatedly arranged in the second direction DR2 are equal to the spacing of the pixels PX1, PX2 and PX3 in the second direction DR2.

[0066] The second gate electrode 154b may be connected to the first scan line 151, and, for example, may have a shape protruding on the first scan line 151. The third gate electrode 154c may be included in the second scan line 152.

[0067] The driving gate electrode 155 arranged in each of the pixels PX1 , PX2 , and PX3 may include an extension portion 155 a protruding downward and extending substantially in the second direction DR2 , and a first gate electrode 154 a protruding upward and extending substantially in the second direction DR2 .

[0068] The first gate electrode 154a may intersect the active pattern of the first transistor T1 and may overlap the channel region 134a of the active pattern of the first transistor T1. The second gate electrode 154b may intersect the active pattern of the second transistor T2 and may overlap the channel region 134b of the active pattern of the second transistor T2. The second scan line 152 including the third gate electrode 154c may intersect the active pattern of the third transistor T3 and may overlap the channel region 134c of the active pattern of the third transistor T3.

[0069] The second insulating layer 160 may be disposed on the second conductive layer. The second insulating layer 160, the second insulating layer 160 and the first insulating layer 140, or the second insulating layer 160, the first insulating layer 140 and the buffer layer 120 may include a plurality of contact holes 61, 62, 63, 64, 65, 66, 67, 68, 69, 69a and 70.

[0070] The third conductive layer may be disposed on the second insulating layer 160. The third conductive layer may include a plurality of data lines 171a, 171b, and 171c, initialization voltage lines 173a and 173b, a capacitor electrode 175, and a plurality of connection members 71, 72, 74, and 78 respectively corresponding to and disposed adjacent to each of the pixels PX1, PX2, and PX3.

[0071] The data lines 171a, 171b, and 171c and the initialization voltage lines 173a and 173b may extend in the second direction DR2 to cross the first scan lines 151 and 151p, the second scan line 152, the transverse driving voltage line 172a, and the transverse common voltage line 170a.

[0072] The initialization voltage lines 173a and 173b are arranged on the left and right sides of an area in which a plurality of pixels PX1, PX2, and PX3 of a pixel group and a plurality of data lines 171a, 171b, and 171c connected to the pixel group are arranged. In other words, one of the initialization voltage lines 173a and 173b may be decoupled for each of the plurality of pixels PX1, PX2, and PX3 of a pixel group. For example, Figure 2 The initialization voltage line 173a in FIG. 1 may not be connected to the plurality of pixels PX1, PX2, and PX3 on the right side of the initialization voltage line 173a. Figure 2 and Figure 4 In the exemplary embodiment shown in FIG. 1 , the initialization voltage line 173 b disposed on the right side of the plurality of pixels PX1 , PX2 , and PX3 may be connected to the transverse initialization voltage line 153 connected to the plurality of pixels PX1 , PX2 , and PX3 .

[0073] Two driving gate electrodes 155 included in two pixels PX2 and PX3 may be disposed between data lines 171 b and 171 c corresponding to two pixels PX2 and PX3 among three pixels PX1 , PX2 , and PX3 of one pixel group.

[0074] Each of the data lines 171 a , 171 b , and 171 c is electrically connected to the source region 133 b of the active pattern of the second transistor T2 through the contact hole 61 of the first insulating layer 140 and the second insulating layer 160 .

[0075] Each of the initialization voltage lines 173a and 173b is electrically connected to the transverse initialization voltage line 153 of the active layer through the contact hole 69a of the first insulating layer 140 and the second insulating layer 160. Therefore, the transverse initialization voltage line 153 can transmit the initialization voltage INIT along the initialization voltage lines 173a and 173b. Therefore, even if the initialization voltage lines 173a and 173b are formed one by one for each of the three pixels PX1, PX2, and PX3, the initialization voltage INIT can be transmitted to all three pixels PX1, PX2, and PX3 through the transverse initialization voltage line 153.

[0076] One capacitor electrode 175 may be disposed at each pixel PX1, PX2, and PX3. The capacitor electrode 175 may overlap most of the driving gate electrode 155 with the second insulating layer 160 therebetween to form a capacitor Cst2.

[0077] The capacitor electrode 175 may include a connection portion 175a protruding upward. The connection portion 175a of the capacitor electrode 175 may be electrically connected to the drain region 135a of the active pattern of the first transistor T1 through the contact hole 65 of the first insulating layer 140 and the second insulating layer 160. The connection portion 175a of the capacitor electrode 175 may extend upward to be electrically connected to the source region 133c of the active pattern of the third transistor T3 through the contact hole 68 of the first insulating layer 140 and the second insulating layer 160. In addition, the connection portion 175a of the capacitor electrode 175 may be electrically connected to the lower pattern 111 through the contact hole 64 of the buffer layer 120, the first insulating layer 140 and the second insulating layer 160.

[0078] The lower pattern 111 may be arranged one by one for each pixel PX1, PX2, and PX3. In a plan view, the lower pattern 111 may include a portion overlapping a majority of the driving gate electrode 155 and the capacitor electrode 175. The driving gate electrode 155 may overlap a majority of the lower pattern 111 with the buffer layer 120 and the first insulating layer 140 between the driving gate electrode 155 and the lower pattern 111 to form a capacitor Cst1.

[0079] The lower pattern 111 and the capacitor electrode 175 electrically connected to each other can transmit the same voltage as each other. In addition, the two capacitors Cst1 and Cst2 formed by overlapping the driving gate electrode 155 with the lower pattern 111 and overlapping the two sides of the driving gate electrode 155 and the capacitor electrode 175 have the same function as each other. The two capacitors Cst1 and Cst2 together form a capacitor Cst. Therefore, sufficient capacitance of the capacitor Cst can be ensured. Therefore, display quality defects such as crosstalk caused by voltage fluctuations of the driving gate electrode 155 of the first transistor T1 caused by signal coupling can be prevented.

[0080] The connection member 71 may be electrically connected to the lateral initialization voltage line 153 through the contact hole 69 of the first and second insulating layers 140 and 160 .

[0081] The connection member 72 may be electrically connected to the transverse common voltage line 170 a through the contact holes 70 of the first and second insulating layers 140 and 160 .

[0082] The connection member 74 may extend longitudinally in the second direction DR2. In each of the pixels PX1, PX2, and PX3, the connection member 74 may be electrically connected to the source region 133a of the active pattern of the first transistor T1 through the contact hole 66 of the first insulating layer 140 and the second insulating layer 160. In addition, the connection member 74 may be electrically connected to the transverse driving voltage line 172a through the contact hole 67 of the second insulating layer 160. Therefore, the source region 133a of the active pattern of the first transistor T1 may be electrically connected to the transverse driving voltage line 172a to receive the driving voltage ELVDD.

[0083] In each of the pixels PX1, PX2, and PX3, the connection member 78 may be electrically connected to the drain region 135b of the active pattern of the second transistor T2 through the contact hole 62 of the first insulating layer 140 and the second insulating layer 160. In addition, the connection member 78 may be electrically connected to the extension portion 155a of the driving gate electrode 155 through the contact hole 63 of the second insulating layer 160. Therefore, the drain region 135b of the active pattern of the second transistor T2 and the driving gate electrode 155 may be electrically connected to each other.

[0084] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 may receive a driving voltage ELVDD from a lateral driving voltage line 172a through a connection member 74.

[0085] The lower pattern 111 of the first transistor T1 overlaps the channel region 134a and is located between the channel region 134a of the first transistor T1 and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and characteristic degradation of the first transistor T1.

[0086] The lower pattern 111 is electrically connected to the drain region 135a of the first transistor T1 through the connection portion 175a of the capacitor electrode 175. Since the lower pattern 111 is electrically connected to the drain region 135a and overlaps with the channel region 134a, the current change rate in the saturation region of the voltage-current characteristic curve of the first transistor T1 is reduced, so that the range of the region in which the output current of the first transistor T1 is constant can be widened. Therefore, even if the source-drain voltage (Vds) of the first transistor T1 changes, the output current of the first transistor T1 remains constant, thereby improving the output saturation characteristics of the first transistor T1. Therefore, the brightness deviation between the pixels PX1, PX2 and PX3 depending on the output current of the first transistor T1 is reduced, thereby improving the image quality.

[0087] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 can be electrically connected to the data lines 171a, 171b, and 171c to receive the data voltage DAT or the reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a of the first transistor T1 through the driving gate electrode 155.

[0088] The third transistor T3 includes a channel region 134 c , a source region 133 c , a drain region 135 c , and a third gate electrode 154 c . The drain region 135 c of the third transistor T3 may receive an initialization voltage INIT from the lateral initialization voltage line 153 .

[0089] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer. Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , the third insulating layer 181 may include a plurality of contact holes 81 a , 81 b , 81 c , 88 , and 89 .

[0090] The fourth conductive layer may be disposed on the third insulating layer 181. The fourth conductive layer may include a driving voltage line 172b, a common voltage line 170b, and a connecting member 178.

[0091] Each of the driving voltage line 172 b and the common voltage line 170 b extends in the second direction DR2 , and the driving voltage line 172 b and the common voltage line 170 b may be alternately disposed in the first direction DR1 .

[0092] Since the signal lines or voltage lines arranged on the fourth conductive layer and extending in the second direction DR2 include only the driving voltage line 172b and the common voltage line 170b, for example, other signal lines do not exist, there can be great freedom in the line width of the driving voltage line 172b and the common voltage line 170b.

[0093] For example, the width of each of the driving voltage line 172b and the common voltage line 170b in the first direction DR1 may be significantly greater than the width of signal lines (eg, data lines 171a, 171b, and 171c, initialization voltage lines 173a and 173b, etc.) arranged in another conductive layer in the first direction DR1.

[0094] For example, the width of the driving voltage line 172b along the first direction DR1 may be measured continuously from the approximate middle of the pixel PX1 and through the pixel PX2 to the approximate middle of the pixel PX3. In other words, the width of the driving voltage line 172b in the first direction DR1 may be greater than the width of one pixel PX2 in the first direction DR1, so that the driving voltage line 172b may overlap the entire pixel PX2.

[0095] The width of the common voltage line 170b in the first direction DR1 may be continuously measured from approximately the middle of one pixel PX3 of one pixel group to approximately the middle of an adjacent pixel PX1 of an adjacent pixel group. In a plan view, the common voltage line 170b may overlap the initialization voltage lines 173a and 173b.

[0096] Therefore, the voltage drops of the common voltage ELVSS and the driving voltage ELVDD are greatly reduced, thereby preventing image quality degradation due to uneven voltages.

[0097] The width of the driving voltage line 172b in the first direction DR1 may be greater than the width of the common voltage line 170b in the first direction DR1. In addition, the width of the space between the driving voltage line 172b and the common voltage line 170b adjacent to each other in the first direction DR1 may be smaller than the width of the driving voltage line 172b in the first direction DR1 or the width of the common voltage line 170b in the first direction DR1.

[0098] The driving voltage line 172b can be electrically connected to the connection member 74 of the third conductive layer through the contact hole 88 of the third insulating layer 181. Therefore, the lateral driving voltage line 172a and the driving voltage line 172b can transmit the driving voltage ELVDD together. Therefore, the driving voltage ELVDD is transmitted in a grid form in the first direction DR1 and the second direction DR2 throughout the display device. Therefore, the voltage drop depending on the position of the driving voltage ELVDD can be prevented. For example, the restriction on the line width of the driving voltage line 172b extending in the second direction DR2 is greatly reduced, so that a large line width can be provided. Therefore, the wiring resistance of the driving voltage line 172b can be greatly reduced, and the voltage drop of the driving voltage ELVDD can be greatly reduced. Therefore, the display quality of the image can be improved.

[0099] The common voltage line 170b may be electrically connected to the connection member 72 of the third conductive layer through the contact hole 89 of the third insulating layer 181. Therefore, the lateral common voltage line 170a and the common voltage line 170b may transmit the common voltage ELVSS together. Therefore, the common voltage ELVSS is transmitted in a grid form in the first direction DR1 and the second direction DR2 throughout the display device. Therefore, a voltage drop depending on the position of the common voltage ELVSS may be prevented. For example, the restriction on the line width of the common voltage line 170b extending in the second direction DR2 is greatly reduced, so that the wiring resistance of the common voltage line 170b may be greatly reduced, and the voltage drop of the common voltage ELVSS may be greatly reduced. Therefore, the display quality of the image may be improved.

[0100] The connecting member 178 may be located in a space between the driving voltage line 172b and the common voltage line 170b adjacent to each other, and spaced apart from the driving voltage line 172b and the common voltage line 170b. A plurality of openings may be formed in an inner region of the driving voltage line 172b, and an island-shaped connecting member 178 may be formed in the opening of the driving voltage line 172b to be spaced apart from the driving voltage line 172b.

[0101] The connection member 178 may be electrically connected to the capacitor electrode 175 of the third conductive layer through the contact hole 81a, 81b or 81c. Thus, the connection member 178 may be electrically connected to the drain region 135a of the active pattern of the first transistor T1 through the capacitor electrode 175.

[0102] At least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may include at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), alloys thereof, etc. Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a single layer or a plurality of layers.

[0103] The fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer. The fourth insulating layer 182 may include a plurality of contact holes 82a, 82b, 82c, and 85.

[0104] The fifth conductive layer may be disposed on the fourth insulating layer 182. The fifth conductive layer may include a plurality of contact members 190a, 190b, 190c, and 190d.

[0105] Each of the contact members 190a, 190b, and 190c may be disposed in each of the pixels PX1, PX2, and PX3 and overlap the connection member 178 in a plan view. Each of the contact members 190a, 190b, and 190c may contact the connection member 178 of the fourth conductive layer through the contact holes 82a, 82b, and 82c to be electrically connected to the connection member 178.

[0106] The contact member 190d may overlap the common voltage line 170b of the fourth conductive layer and make contact with the common voltage line 170b through the contact hole 85 to be electrically connected to the common voltage line 170b.

[0107] Each of the contact members 190a, 190b, 190c and 190d improves the adhesion of the fourth conductive layer and the overlying conductive layer in contact with each other, and prevents oxidation of the fourth conductive layer. Specifically, when the fourth conductive layer includes copper, oxidation can be prevented. To do this, the fifth conductive layer may include a conductive material that can prevent corrosion of the fourth conductive layer and cover the fourth conductive layer to prevent corrosion. For example, the fifth conductive layer may include a conductive material, for example, a metal oxide such as ITO or IZO. The fifth conductive layer may be omitted.

[0108] The fifth insulating layer 183 may be disposed on the fourth insulating layer 182 and the fifth conductive layer. Figure 6 and Figure 7 , the fifth insulating layer 183 may include a contact hole 83a disposed on the contact members 190a, 190b, and 190c, and a contact hole 86 disposed on the contact member 190d.

[0109] At least one of the buffer layer 120, the first insulating layer 140, the second insulating layer 160, the third insulating layer 181, the fourth insulating layer 182, and the fifth insulating layer 183 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) and / or an organic insulating material. The fifth insulating layer 183 may include an inorganic insulating material and / or an organic insulating material such as polyimide, an acrylic polymer, a siloxane polymer, or the like, and may have a substantially flat upper surface.

[0110] A pixel electrode layer including a plurality of pixel electrodes 191 a , 191 b , and 191 c and a contact member 191 d as a sixth conductive layer are disposed on the fifth insulating layer 183 .

[0111] like Figures 2 to 4 As shown, each pixel electrode 191a, 191b and 191c can be arranged corresponding to each pixel PX1, PX2 and PX3 respectively. The plane size and shape of the pixel electrodes 191a, 191b and 191c arranged in adjacent pixels PX1, PX2 and PX3 of a pixel group can be different or similar. For example, the pixel electrode 191a of the pixel PX1 and the pixel electrode 191c of the pixel PX3 can have a right / left symmetrical shape and can be a rectangle with a chamfer. The pixel electrode 191b of the pixel PX2 can be approximately rectangular. The pixel PX1 represents red, the pixel PX2 represents green, and the pixel PX3 represents blue, but is not limited to this.

[0112] The driving voltage line 172 b may have a width in the first direction DR1 greater than a width in the first direction DR1 of a pixel electrode 191 b disposed at one pixel PX2 , and may overlap the entire pixel electrode 191 b in a plan view.

[0113] Each pixel electrode 191a, 191b, and 191c may respectively contact each contact member 190a, 190b, and 190c through the contact hole 83a to be electrically connected to each contact member 190a, 190b, and 190c, and may be electrically connected to the connection member 178 and the capacitor electrode 175 through the contact members 190a, 190b, and 190c. Therefore, each pixel electrode 191a, 191b, and 191c may be electrically connected to the drain region 135a of the first transistor T1 to receive a voltage from the first transistor T1.

[0114] The contact member 191d may make contact with the contact member 190d disposed in the fifth conductive layer through the contact hole 86 to be electrically connected with the contact member 190d.

[0115] The pixel electrode layer may include a semi-transmissive conductive material or a reflective conductive material.

[0116] The sixth insulating layer 350 may be disposed on the pixel electrode layer and the fifth insulating layer 183. Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The sixth insulating layer 350 may have openings 355a, 355b, and 355c disposed in each of the pixel electrodes 191a, 191b, and 191c. The sixth insulating layer 350 may include an organic insulating material such as polyacrylic resin, polyimide resin, or the like.

[0117] The emission layer 370 and the common layer 360 may be disposed on the sixth insulating layer 350 and the pixel electrode layer.

[0118] The emission layer 370 may include portions disposed in the openings 355a, 355b, and 355c of the sixth insulating layer 350. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material.

[0119] The common layer 360 may include a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. The common layer 360 may also be disposed on the sixth insulating layer 350 and in the openings 355a, 355b, and 355c. The common layer 360 may include an organic material. Figure 5 , Figure 6 and Figure 7 In the embodiment, the common layer 360 is arranged on the emission layer 370, and the pixel electrodes 191a, 191b and 191c are below the emission layer 370, however, the present invention is not limited thereto, and the common layer 360 may include a portion arranged between the emission layer 370 and the pixel electrodes 191a, 191b and 191c. For example, the hole injection layer and the hole transport layer may be arranged between the emission layer 370 and the pixel electrodes 191a, 191b and 191c, and the electron transport layer and the electron injection layer may be arranged between the emission layer 370 and the common electrode 270.

[0120] refer to Figure 7 , the sixth insulating layer 350 and the common layer 360 may include a contact hole 35 disposed on the contact member 191d.

[0121] The common electrode 270 may be disposed on the common layer 360. The common electrode 270 may be continuously formed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 contacts the contact member 191d via the contact hole 35 to be electrically connected to the common voltage line 170b through the contact member 190d to receive the common voltage ELVSS.

[0122] The common electrode 270 may include a transparent conductive material.

[0123] Each pixel electrode 191a, 191b, and 191c in each pixel PX1, PX2, and PX3, the emission layer 370, the common layer 360, and the common electrode 270 together form a light emitting diode (LED) ED. For example, one of the pixel electrodes 191a, 191b, and 191c and the common electrode 270 becomes a cathode, and the other of the pixel electrodes 191a, 191b, and 191c and the common electrode 270 becomes an anode. In the previous example, the pixel electrodes 191a, 191b, and 191c are anodes.

[0124] Exemplary embodiments of the present invention improve display quality by greatly reducing a voltage drop of a voltage line connected to a pixel included in a display device.

[0125] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: substrate; an active layer disposed on the substrate and including a plurality of active patterns including a semiconductor material; A first conductive layer is disposed on the active layer; a second conductive layer, disposed on the first conductive layer and comprising a data line for transmitting a data signal; a third conductive layer, disposed on the second conductive layer; as well as a light emitting element arranged on the third conductive layer, The first conductive layer includes a first voltage line, a second voltage line and a scan line for transmitting a scan signal. The third conductive layer includes a third voltage line electrically connected to the first voltage line and a fourth voltage line electrically connected to the second voltage line, The first voltage line and the second voltage line extend in a first direction, The third voltage line and the fourth voltage line extend in a second direction crossing the first direction, The third voltage lines and the fourth voltage lines are alternately arranged in the first direction, The light emitting element includes a pixel electrode disposed on the third conductive layer, and A width of the third voltage line in the first direction is greater than a width of the pixel electrode in the first direction.

2. The display device according to claim 1, wherein: The second conductive layer includes a first connection member electrically connected to the first voltage line and a second connection member electrically connected to the second voltage line, The third voltage line is electrically connected to the first connection member, and The fourth voltage line is electrically connected to the second connection member.

3. The display device according to claim 2, wherein: The light emitting element further includes an emission layer disposed on the pixel electrode and a common electrode disposed on the emission layer.

4. The display device according to claim 3, wherein: A width of a space in the first direction between the third voltage line and the fourth voltage line adjacent to each other is smaller than a width of the third voltage line in the first direction.

5. The display device according to claim 4, wherein: The third conductive layer further includes a third connection member separated from the third voltage line and the fourth voltage line, and The pixel electrode is electrically connected to the third connection member.

6. The display device according to claim 5, wherein: The third connection member is disposed in the opening of the third voltage line.

7. The display device according to claim 1, wherein: The first voltage lines and the second voltage lines are alternately arranged in the second direction, The scan lines are repeatedly arranged in the second direction, and The first voltage line and the second voltage line are arranged between two adjacent scan lines.

8. The display device according to claim 1, wherein: The first conductive layer includes a driving gate electrode disposed between the scan line and the first voltage line, and The second conductive layer includes a capacitor electrode overlapping the driving gate electrode in a plan view to form a first capacitor.

9. The display device according to claim 8, further comprising: a lower pattern, the lower pattern being conductive and arranged between the substrate and the active layer, wherein the lower pattern overlaps the driving gate electrode in the plan view to form a second capacitor, and The lower pattern is electrically connected to the capacitor electrode.

10. The display device according to claim 9, wherein: The active pattern includes a first active pattern of the first transistor, a second active pattern of the second transistor, and a third active pattern of the third transistor, The driving gate electrode is electrically connected to the conductive area of ​​the second active pattern, The capacitor electrode is electrically connected to the conductive region of the first active pattern, and The third active pattern is electrically connected to the capacitor electrode.

11. The display device according to claim 10, wherein: The second conductive layer further includes an initialization voltage line extending in the second direction, and The conductive region of the third active pattern is electrically connected to the initialization voltage line.

12. The display device according to claim 11, wherein: The active layer further includes a lateral initialization voltage line that is conductive and electrically connected to the initialization voltage line, and The lateral initialization voltage line is connected to the third active pattern and extends in the first direction.

13. The display device according to claim 1, further comprising: an insulating layer disposed on the third conductive layer, The light emitting element includes a pixel electrode arranged on the third conductive layer, an emission layer arranged on the pixel electrode, a common electrode arranged on the emission layer, and a common layer arranged between the pixel electrode and the common electrode. The common layer and the insulating layer have a contact hole arranged on the fourth voltage line, and The common electrode is electrically connected to the fourth voltage line through the contact hole.

14. The display device according to claim 13, further comprising: a fourth conductive layer, arranged on the third conductive layer, wherein the third conductive layer further includes a connection member separated from the third voltage line and the fourth voltage line, The fourth conductive layer includes a first contact member contacting the fourth voltage line and a second contact member contacting the connecting member, The common electrode is electrically connected to the fourth voltage line through the first contact member, and The pixel electrode is electrically connected to the connection member through the second contact member.

15. A display device comprising: a pixel group, comprising a first pixel, a second pixel and a third pixel arranged in a first direction and adjacent to each other; A scan line, a first voltage line, and a second voltage line extending in the first direction; data lines corresponding to the first pixel, the second pixel and the third pixel respectively and extending in a second direction crossing the first direction; a third voltage line extending in the second direction and electrically connected to the first voltage line; a fourth voltage line extending in the second direction and electrically connected to the second voltage line; as well as a light emitting element comprising a common electrode electrically connected to the fourth voltage line, The light emitting element further comprises a pixel electrode facing the common electrode, and A width of the third voltage line in the first direction is greater than a width of the pixel electrode corresponding to the second pixel in the first direction.

16. The display device according to claim 15, wherein: The third voltage lines and the fourth voltage lines are alternately arranged in the first direction.

17. The display device according to claim 16, wherein: The light emitting element further includes an emission layer.

18. A display device comprising: a first scan line and a second scan line; A plurality of data lines and initialization voltage lines intersecting the first scan line and the second scan line; A first voltage line and a second voltage line intersecting the plurality of data lines; a first transistor including a first gate electrode disposed between the first scan line and the first voltage line, and a first active pattern crossing the first gate electrode and electrically connected to the first voltage line; a second transistor including a second active pattern electrically connected to the first gate electrode, and a second gate electrode included in the first scan line; a third transistor including a third active pattern electrically connected to the first active pattern, and a third gate electrode included in the second scan line; a light emitting element comprising a common electrode, an emission layer, and a pixel electrode electrically connected to the first transistor and the third transistor; as well as A third voltage line and a fourth voltage line intersect the first scan line and the second scan line, wherein the common electrode is electrically connected to the second voltage line, The third voltage line is electrically connected to the first voltage line and is arranged in a different layer from the first voltage line, and the fourth voltage line is electrically connected to the second voltage line and is arranged in a different layer from the second voltage line, and A width of the third voltage line in a direction parallel to the first scan line is greater than a width of the pixel electrode in the direction.

19. The display device according to claim 18, wherein: The third voltage line overlaps the first active pattern, the second active pattern, and the third active pattern in a plan view.

Images