Storage unit device and method for operating a storage unit device

Abstract

A memory cell arrangement and a method for operating the memory cell arrangement are provided. The memory cell arrangement may include at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic device configured to selectively place the first switch into at least one of at least three operating states by activating or deactivating a first subcircuit of the switch control logic device: an on state, an off state, and a conducting state, in which the conductivity is less than in the on state and greater than in the off state.

Description

Technical Field

[0001] The invention relates to a memory cell arrangement and a method for operating a memory cell arrangement. Background Art

[0002] The present invention relates to a memory circuit, in particular a memory circuit that provides a low-energy mode. A low-energy mode is understood to be an operating mode with low energy consumption. This is also referred to as a low-power mode or standby mode in some applications. For electronic data storage, the term "Memory" (and terms derived therefrom) is also commonly used in German.

[0003] The memory cell device or the associated circuit may be a memory cell device or an associated circuit for volatile data storage, such as an SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) memory circuit. In order to maintain the stored data, a predetermined retention voltage must be provided to the memory circuit on its power supply node.

[0004] Products with low energy consumption are based on or contain integrated circuits which themselves can in turn be operated in a low energy mode.

[0005] Wireless products (i.e. electronic devices configured for cable-free data exchange, such as mobile phones, laptops or tablets), chip card products (e.g. cards for identification, such as identity cards, insurance cards, such as for example health insurance cards or payment cards, such as for example credit cards), products in the automotive field (e.g. engine control devices for engines that are responsible for driving the vehicle (e.g. internal combustion engines or electric motors) and / or engine control devices for other engines, such as for example window lifts), or devices or apparatus for automated driving, and products for energy management are examples of such products that can provide a low-energy mode.

[0006] Most integrated circuits have a memory circuit for storing data. In order to be able to provide a product with a low-power mode, the memory circuit should be able to be operated with correspondingly low power consumption.

[0007] A portion of the energy consumption in memory circuits is caused by leakage currents. In microcontroller products in the automotive field, the number of SRAM memory cells has roughly doubled when transitioning from 40nm technology to 28nm technology. At the same time, the leakage current per bit occurring in the SRAM has increased (e.g., nearly doubled). This means that the leakage current contribution of the SRAM memory has increased by approximately four times.

[0008] The memory circuit is to provide a technology or process for reducing leakage currents and to enable a low-energy mode which is robust, adjustable, advantageous and simple to implement with respect to the required (chip) area and in this case ensures that the stored data are maintained.

[0009] Furthermore, high peak currents are to be avoided when switching from low energy mode to normal mode (also called active mode, active power mode or active run mode).

[0010] exist Figure 2A Schematically shown are multiple memory cell devices known in the prior art, more specifically in a variant form in which a positive supply voltage VDD is connected (in this case, a PFET transistor is turned on, shown in the "VDD switching" column, based on an NFET) and in a variant form in which a negative supply voltage or ground terminal VSS is connected (in this case, an NFET transistor is turned on, shown in the "VSS switching" column, based on an NFET).

[0011] In the relatively simple structure of the storage unit device 200a, 200b (in Figure 2A As shown in the first row of FIG. 1 , indicated by “energy supply switched off”, the supply voltage VDD or VSS of the memory cell array 100 can be switched on or off by means of a transistor 220 connected between the memory cell array 100 and the voltage supply VSS or VDD. However, this means that in the case of a volatile memory cell array 100, the information stored in the memory cell array 100 is lost in the switched-off state.

[0012] The possibility of providing the memory cell array 100 with a reduced operating voltage for the low energy mode can be designed using diodes.

[0013] exist Figure 2A In the row denoted by "diode mode", memory cell arrangements 201a, 201b are shown in which a transistor used as a diode 222 is connected in parallel with a voltage supply VSS or VDD which can be switched on and off by means of a switch (transistor) 220. If the switch 220 is switched off, a reduced operating voltage for the memory cell array 100 is provided via the diode 222 in the low-energy mode, whereby leakage currents can be reduced.

[0014] An example of such a storage unit arrangement 201a, 201b is known from US Pat. Figure 2B(middle). Koji Nii et al. in their article “A dynamic / static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs” (Digest of Technical Papers–IEEE Symposium on VLSI Technology, September 21, 2016) Figure 3 In, here Figure 2B (top) describes and shows an example in which a reduced operating voltage can be provided by means of a diode 222 connected in series with the main switch 220.

[0015] However, this configuration using a main switch 220 and an additional diode 222 means that, although chip surface must be available for both components (main switch 220 and diode 222), the diode 222 still only makes a small contribution to the voltage supply of the memory cell array 100 in active mode (i.e., in normal operation). In addition, the voltage (VSSC or VDDC) provided by means of the diode cannot be set in the low-energy mode. In addition, the configuration has the disadvantage that the voltage supply of the memory cell array 100 is caused by the series connection of the components, which results in an undesirably increased voltage drop across the series connection, which in turn can only be compensated by increasing the chip surface.

[0016] exist Figure 2A In the third row, the so-called “sustaining mode” is shown. In this case, a sustaining voltage VDDRET (or an increased sustaining voltage VSSRET) which is reduced compared to the operating voltage VDD (or VSS) for normal operation can be switched via transistor 224 .

[0017] However, a separate VDDRET voltage supply (or VSSRET voltage supply) is required on the chip for the "maintain mode", which consumes chip real estate and increases wiring complexity. In addition, real estate for circuits generating the VDDRET voltage (or VSSRET voltage) is required.

[0018] However, when the circuit for generating the VSSRET voltage or the VSSRET voltage is used together (eg, a plurality of memory cells), it is not possible to provide a situation-dependent setting of the VSSRET voltage by means of the configuration.

[0019] The relatively expensive configuration is Figure 2A In the last row for the memory circuits 203a, 203b (denoted by “regulator mode”), a control circuit 228 is provided for actuating the gate of the main switch 220.

[0020] Control circuit 228 is complex in this configuration, is sensitive to changes / fluctuations, and consumes chip area and additional energy.

[0021] According to US 2009 / 0189684 A1, a corresponding embodiment of the memory circuit 203a is described in Figure 2B (lower) shown. Summary of the invention

[0022] In various embodiments, a memory cell arrangement is provided which has a low energy mode for its memory elements. The memory cell arrangement may have at least one switching element which provides more than two modes, for example on / off / diode.

[0023] In contrast, the prior art discloses combinations of switching elements, each of which provides only one mode (diode) or two modes (on / off).

[0024] In various embodiments, a memory cell arrangement is provided. The memory cell arrangement may have at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic device configured to selectively place the first switch in one of at least three operating states by activating or deactivating a first subcircuit of the switch control logic device: an on state; an off state; and a conducting state, in which the conductivity is less than in the on state and greater than in the off state.

[0025] The conducting state can be provided by means of a diode, for example, in that the first switch has a transistor which can be switched on for the on state and switched off for the off state and which is operated in a diode mode for the conducting mode.

[0026] At least three operating states (on state, off state, conducting state) can therefore be realized by means of a single switch, so that chip area can be saved.

[0027] In different embodiments, the memory cell device may have a second switch connected between at least one memory cell and a reference potential, wherein the switch control logic device may also be configured to selectively place the second switch in one of at least three operating states by activating or deactivating a second subcircuit of the switch control logic device: an on state; an off state; and a conduction state, in which the conductivity is less than in the on state and higher than in the off state.

[0028] In various embodiments, it is thereby possible, for example, to adapt the voltage level of VSSC (or VDDC) during the low-energy mode to characteristic properties of the memory cells within the memory array, for example by placing only one of the switches in one state and the other switches in another state.

[0029] Furthermore, in various embodiments, the occurrence of high peak currents when switching the storage cell arrangement from a low-energy mode into an active (“on”) mode can be reduced, for example by first switching on a first switching element and before that a further (for example a second) switching element.

[0030] In various embodiments, all switching elements can contribute to the voltage supply in active mode (“on mode”).

[0031] The “off mode” can be realized by placing all switching elements in the “off” mode.

[0032] In various embodiments, the ground voltage supply may be switchably configured, or the positive voltage supply, or both. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Exemplary embodiments of the invention are shown in the drawings and are explained in more detail below.

[0034] The accompanying drawings show:

[0035] Figure 1 A schematic diagram showing a storage unit device according to the prior art;

[0036] Figure 2A shows an overview of different schematically illustrated storage unit arrangements according to the prior art;

[0037] Figure 2B An example of a storage unit device according to the prior art is shown;

[0038] Figure 3 Schematic diagrams showing storage unit arrangements according to various embodiments;

[0039] Figure 4 Schematic diagrams showing storage unit arrangements according to various embodiments;

[0040] Figure 5 Schematic diagrams showing storage unit arrangements according to various embodiments;

[0041] Figure 6 Schematic diagrams showing switching states in a memory cell arrangement according to various embodiments; and

[0042] Figure 7A flow chart of a method for operating a memory cell arrangement according to various exemplary embodiments is shown. DETAILED DESCRIPTION

[0043] In the detailed description below, reference is made to the accompanying drawings, which form a part of the description and in which specific embodiments are shown for illustration, in which the present invention can be implemented. In this respect, directional terms are used with reference to the orientation of the (multiple) drawings described, such as, for example, "upper", "lower", "front", "back", "front", "back", etc. Because the components of the embodiments can be positioned in a plurality of different orientations, the directional terms are used for illustration and are not limited in any way. It should be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of protection of the present invention. It should be understood that the features of the different exemplary embodiments described herein can be combined with each other, as long as no special instructions are given. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of protection of the present invention is defined by the appended claims.

[0044] In the context of this specification, the terms "connect", "couple" and "couple" are used to describe direct and indirect connections, direct or indirect couplings and direct or indirect couplings. In the drawings, identical or similar elements are provided with identical reference numerals whenever this is appropriate.

[0045] Different embodiments are described herein for an apparatus, and different embodiments are described herein for a method. It is to be understood that features and characteristics described in conjunction with the apparatus also apply to the method, and vice versa.

[0046] Figures 3 to 5 Schematic diagrams of storage unit devices 300 according to different embodiments are shown respectively. Figure 3 , Figure 4 and Figure 5 The exemplary embodiments of the present invention are distinguished as storage unit arrangements 300a, 300b or 300c. As long as no special features of the respective exemplary embodiment are involved, the general reference numeral 300 is used for the storage unit arrangement.

[0047] A memory cell arrangement 300 as described herein may be used, for example, in the automotive field, for example using a 28 nm process.

[0048] The memory cell arrangement 300 may have at least one memory cell 102, for example in the form of a memory cell array 100 (also referred to as memory array 100). The memory cell 102 may be a conventional memory cell 102, for example an RRAM, MRAM, PC-RAM, ROM or flash memory cell, in particular a conventional volatile memory cell 102, for example a DRAM or SRAM memory cell. The memory cell array 100 may accordingly be a conventional memory cell array 100, as for example in Figure 1 As shown in and described in connection with this description, for example, a memory cell array 100, such as an SRAM, DRAM, RRAM, MRAM, PC-RAM, ROM, or flash memory array.

[0049] In order to operate the memory cell array 100, operating voltages 108, 110 may be provided at its input terminals. Figures 3 to 5 Also represented in the middle is a positive or very positive operating voltage 108 and a negative or very negative operating voltage 110 or ground.

[0050] The memory cell arrangement 300 may also represent a positive or much more positive reference potential 106 (at Figures 3 to 5 VDD is also used in the positive supply voltage. DD ) and a negative or much negative or ground reference potential 104 provides (at Figures 3 to 5 VSS is used in the representation, according to the common expression V for negative supply voltages, usually GND. SS ).

[0051] In the case where a constant reference potential is applied to one of the input terminals of the memory cell array 100, the operating voltage 108 or 110 may be equal to the corresponding reference potential 104 or 106 (at Figures 3 to 5 , where is the reference potential 106).

[0052] In various exemplary embodiments, the memory cell arrangement 300 may include a first switch S1 connected between at least one memory cell 102 and the reference potential 104 or 106 and a switch control logic device 330. The control logic device may be as described in Figure 4 and Figure 5 As shown in FIG. 3 , the control logic device 330 is multi-part and has, for example, a first part 330_1 for actuating a first switch S1, a second part 330_2 for actuating a second switch S2, etc. In order to improve the clarity, only the reference numerals of the parts of the control logic device 330 that are important for the described functions are indicated when describing the functionality of the control logic device 330. It should be understood that by indicating only these reference numerals, no conclusions can be drawn about the functions (especially idle states, etc.) of other parts of the control logic device 330, if any.

[0053] The control logic device 330_1 may be configured to selectively activate or deactivate the first sub-circuit 330_1T of the control logic device 330_1 by switching the control logic device 330_1 (see Figure 5 ) Place the first switch S1 in one of at least three operating states. The at least three operating states may include an on state, an off state, and a conducting state in which the conductivity is lower than in the on state and higher than in the off state.

[0054] In this case, the switch control logic device 330_1 can be designed in different embodiments to put the first switch S1 into a conducting state when the subcircuit 330_1T is activated. For example, the first switch S1 can be a (first) transistor, such as a (first) field effect transistor, such as an NFET, as in Figure 5 , or PEET (not shown). The switch control logic device 330_1 can be designed so that when activated, the subcircuit 330_1T produces a conductive connection between the controlled output terminal of the first switch S1 and the gate of the first switch S1, so that the first switch S1 (transistor) is connected as a diode, which is also called diode mode or diode mode state. In diode mode, the conductivity of the transistor (and thus the first switch S1) is lower than in the fully conductive (closed) state of the transistor and higher than in the insulating (open) state of the transistor.

[0055] If the subcircuit 330_1T is disabled, the first switch S1 can be placed in a disconnected state (e.g., OFF state) or in a connected state (e.g., ON state). For switching between the conducting state and the disconnected state of the first switch S1, further switches 550, 552 can be provided in the switch control logic device 330_1, by means of which the gate of the first switch S1 can be selectively connected to the positive reference potential 106 or to the negative reference potential 104.

[0056] The switch control logic device 330_1 can be configured such that, in the switched-on state, the gate is connected to the reference potential 104 or 106, which closes or causes the first switch S1 to close and thus the at least one storage cell 102 to the reference potential 104 or 106 (in the switched-on state). Figures 3 to 5 and in the off state, the gate is connected to another reference potential 104 or 106, which disconnects the first switch S1 or disconnects the first switch S1, thereby preventing at least one storage unit 102 from being connected to the reference potential 104 or 106 (in Figures 3 to 5 Chinese: 104) connection.

[0057] For example, in the on state, the gate of the first transistor (i.e., the first switch S1), also referred to as the first gate, can be connected to the positive voltage supply terminal 106 (positive reference potential such as VDD). In the off state, the first gate can be connected to the ground terminal 104 (negative reference potential such as VSS), and in the conducting state, the first gate can be connected to the virtual voltage supply terminal 110.

[0058] Here, the first field effect transistor may be an NFET transistor, and the virtual voltage supply terminal 110 may be a ground terminal.

[0059] In order to enable switching of the connection of the gate to the positive reference potential 106 , the negative reference potential 104 and the virtual voltage supply terminal 110 , the switch control logic 330 may have further switches, for example transistors.

[0060] For example, the switch control logic device 330 may include a gate control circuit or may be formed by the gate control circuit. Figure 5 In the embodiment of , the gate control circuit for the first switch S1 corresponds to the first part 330_1 of the switch control logic device 330. The gate control circuit may have a fourth field effect transistor 550 between the first gate and the positive voltage supply terminal 106. The gate of the fourth field effect transistor may be provided or supplied with the first switching voltage conb1.

[0061] The gate control circuit may further have a fifth field effect transistor 552 between the first gate and the ground terminal 104. The gate of the fifth field effect transistor 552 may be provided or supplied with a second switching voltage coff1.

[0062] The gate control circuit may also have a sixth field effect transistor TG1 (or a pair of two field effect transistors TG1) between the first gate and the virtual voltage supply terminal 110. A third switching voltage cdiode1 may be provided or provided on the gate of the sixth field effect transistor TG1 (or on the gates of the two field effect transistors TG1 of the pair). The two field effect transistors of the pair may here include an NFET transistor and a PFET transistor, in particular a pair of two field effect transistors connected in parallel.

[0063] In various embodiments, a PFET transistor can be used instead of an NFET transistor for the first switch S1, for example. In this case, the first switch S1 and the switch control logic device 330 can be connected between the positive reference potential 106 and the at least one memory cell 102. The negative reference potential 110 (for example the ground terminal VSS) can in this case be provided directly as the supply voltage 104 or can be provided directly as the supply voltage 104.

[0064] The gate control circuit may be configured, in the case not shown, to connect the first gate to the ground terminal in the on state, to connect the first gate to the positive voltage supply terminal in the off state, and to connect the first gate to the virtual voltage supply terminal in the conducting state. The virtual voltage supply terminal may be a positive voltage supply terminal.

[0065] The described embodiment makes it possible to provide a storage cell arrangement 300 with a low-energy mode, wherein the first switch S1 contributes to the voltage supply of at least one storage cell 102 in the switched-on state and in the conducting state, and wherein components connected in parallel with the switch S1 are omitted, which components are inactive in one of the switching states. Furthermore, the switch control logic device 330 can have a simple design, be robust, and be designed to be very small.

[0066] In various embodiments, the memory cell arrangement 300 , 300 b , 300 c may further include a second switch S2 connected between the at least one memory cell 102 and the reference potential 104 or 106 .

[0067] The switch control logic device 330, 330_2 can also be configured to selectively place the second switch S2 in one of at least three operating states by activating or deactivating the second subcircuit 330_2T of the switch control logic device 330_2: an on state; an off state; and a conducting state, in which the conductivity is less than in the on state and higher than in the off state.

[0068] In other words, a second switch S2 having a similar function to the first switch S1 may be provided. The construction of the second switch S2 may be the same or similar to the construction of the first switch S1. For example, the second switch S2 may be a (second) transistor, such as a (second) field effect transistor.

[0069] The switch control logic device 330 may include or be formed by a second gate control circuit for controlling the gate of the second switch S2. Figure 5In the embodiment of the invention, the control circuit for the second switch S2 corresponds to the second part 330_2 of the switch control logic device 330. The gate control circuit can have a seventh field effect transistor 554, an eighth field effect transistor 556 and a ninth field effect transistor TG2 (or a pair of two field effect transistors TG2), the functions of which correspond to the field effect transistors 550, 552 or TG1 of the first gate control circuit. The fourth, fifth or sixth switching voltage conb2, boff2 or cdiode2 can be provided or provided for the respective gates of the seventh, eighth and ninth field effect transistors 554, 556, TG2. The pair of two field effect transistors TG2 can include NFET transistors and PFET transistors, in particular a pair of two field effect transistors connected in parallel.

[0070] The first switch S1 and the second switch S2 may be connected in parallel with each other, as in Figure 4 Neutralization Figure 5 As shown in .

[0071] The storage cell devices 300, 300b, 300c may also have other switches (not shown) connected between at least one storage cell 102 and the reference potential 104 or 106, which have the same function as the first switch S1 and the second switch S2, and in particular can be placed in one of at least three operating states (on state; off state; and conduction state, in which the conductivity is less than in the on state and higher than in the off state) with the aid of the switch control logic device 330.

[0072] In various embodiments, the first switch S1 and the second switch S2 may be configured to be in one of their three operating states independently of each other. In other words, the two switches S1, S2 may be in an on state, the two switches S1, S2 may be in an off state, the two switches S1, S2 may be in a conducting state, one of the switches may be in an on state and the other may be in an off state, one of the switches may be in an on state and the other may be in a conducting state, or one of the switches may be in a conducting state and the other may be in an off state.

[0073] In the storage cell device 300, in different embodiments, the switch control logic device 330 can be configured to selectively place the storage cell device 300 in one of at least three power levels by placing the first switch S1 and the second switch S2 in one of their three operating states (on state, off state, conduction state), respectively: a fully-on state, in which the first switch and the second switch are in the on state; a partial power state, in which at least one of the first switch and the second switch is in the conduction state; and a fully-off state, in which the first switch and the second switch are in the off state.

[0074] The fully open state may be set for normal operation of the storage unit device 300 .

[0075] The fully-off state may be provided for completely shutting down the memory cell arrangement 300 , ie, a state in which a loss of data stored in at least one memory cell 102 is tolerated.

[0076] The partial power state can be used for standby operation, i.e., for example, for a state in which, although no active use of the memory cell 300 occurs, i.e., not normal operation, in which, for example, writing to and / or reading from at least one memory cell 102 occurs, it is nevertheless desired to maintain data stored in at least one memory cell 102, e.g., in the memory cell array 100.

[0077] In various embodiments, at least three power stages may also have a partially on state in which the first switch S1 is in an on state and the second switch S2 is in an off state.

[0078] The partially on state can be used as an intermediate switching stage for the transition from the fully off state or the partial power state to the fully on state, because high peak currents can be reduced or avoided thereby. For example, individual switches can be switched from the off state to the on state in sequence and thus high peak currents can be avoided.

[0079] In various embodiments, the partial off state and / or the partial power state may be configured such that the value of the voltage dropped across the at least one memory cell 102 is high enough to ensure continued data storage.

[0080] All (main) switches S1, S2, ..., i.e. switches S1, S2, ... configured to directly connect the supply voltage of at least one storage cell 102, are configured to contribute to the voltage supply of at least one storage cell 102, for example, the storage cell array 100, in a normal operating mode (active mode) of the storage cell arrangement 300, in which all switches S1, S2, ... are placed in the on state or are in the on state (i.e. in the fully open state). In this case, the series connection of voltage supply switches, which deteriorate the conductivity, as is done in the prior art, can be omitted. Figure 2B As shown in (top).

[0081] In various embodiments, the storage cell arrangement 300, 300b, 300c may further include a third switch S3 connected between at least one storage cell 102 and the reference potential 104 or 106. The switch control logic 330 may be configured to selectively place the third switch S3 in exactly one of two operating states, namely in an on state or an off state.

[0082] In other words, the third switch S3 can be provided with a limited functionality (on / off only) relative to the first switch S1 (and, if present, relative to the second switch S2). The third switch S3 can be connected in parallel with the first switch S1 (and possibly with the second switch S2 and possibly further switches), as in Figure 4 and Figure 5 The third switch S3 can be formed as a transistor (also referred to as a third transistor), for example as a field effect transistor, for example as an NFET, as shown in Figure 5 as shown in , or as a PFET (not shown).

[0083] The gate of the third switch S3 can be selectively connected to the positive reference potential 106 or to the negative (ground) reference potential 104. For the selective connection, for example for switching between the two connections, a tenth transistor 558 can be provided between the gate and the positive reference potential 106 and an eleventh transistor 560 can be provided between the gate and the negative (ground) reference potential 104. A common seventh switching voltage conb3 can be provided or provided at the gates of the tenth and eleventh transistors 558, 560.

[0084] The third switch S3 can be regarded as the main supply switch. Since in normal operation mode, in addition to the main supply switch S3, the first switch S1 and possibly the second switch S2 and possibly further switches also contribute to the supply of energy to the at least one storage unit, the third switch S3 can be designed to be smaller.

[0085] Similar to the storage cell devices 300, 300b having the first switch S1 and the second switch S2 described above, the switch control logic device 330 of the storage cell device 300c can be configured to selectively place the storage cell device 300c in one of at least three power levels by placing the first switch S1 and the second switch S2 in one of their three operating states, respectively, and placing the third switch S3 in one of its two operating states: a fully-on state, in which the first switch, the second switch, and the third switch are in the on state; a partial power state, in which at least one of the first switch and the second switch is in the conducting state; and a fully-off state, in which the first switch, the second switch, and the third switch are in the off state.

[0086] exist Figure 5 In the embodiment of the invention, the off state can be realized, for example, by connecting the respective gate of the first or second or third switch S1, S2 or S3, respectively formed as an NFET transistor, to the negative reference potential 104, for example VSS. This can be realized, for example, as described below.

[0087] In various embodiments, at least three power stages may also have a partially open state in which at least one of the first switch S1 , the second switch S2 , and the third switch S3 is in an on state and at least one of the other two switches is in an off state.

[0088] The use of these power stages may correspond in meaning to what was described above for the storage cell arrangement 300 b having two switches S1 , S2 .

[0089] The fully closed state is in different embodiments (such as in Figure 5 As shown in the figure; where for the fully off state, the three switches S1, S2 and S3 are placed in the off state) can be achieved as follows: a negative (ground) reference potential is provided as a virtual reference potential, i.e. as cdiode1 or cdiode2, a positive reference potential (conb1, conb2 or conb3, for example VDD) is provided at the gates of the fourth transistor 550, the seventh transistor 554 and the tenth transistor 558, respectively, and a positive reference potential (coff1, coff2, for example VDD) is also provided at the gates of the fifth transistor 552 and the eighth transistor 556, respectively.

[0090] In various embodiments, the first switch S1 may have a higher conductivity in the conducting state than the second switch S2 in the conducting state. This may be achieved as a simple form of technical implementation, for example, in the following manner: the first switch S1 is a first field effect transistor, and the second switch S2 is a second field effect transistor, wherein the first field effect transistor has a larger transistor width than the second field effect transistor.

[0091] In various exemplary embodiments, as a further simple implementation of different conductivities, alternatively or additionally, the first field effect transistor, ie the first switch S1 , has a lower threshold voltage than the second field effect transistor, ie the second switch S2 .

[0092] This allows for more different configurations / settings to be implemented for the low-energy mode (eg, partial power mode; if necessary, the partial power mode can also be considered as a low-energy mode).

[0093] For illustration purposes, Figure 6 It is shown in Figure 5 The different combinations of operating states of the three switches S1, S2 and S3 of the exemplary embodiment result in the power levels represented at the lower edge, which range from "active on" to "off" and have three power levels called "low energy" (weak / medium / strong) as intermediate levels, "weak on" and "medium on" (these correspond to the above-mentioned partial on modes).

[0094] As per Figure 6 As can be seen by way of example, the power level "medium low energy" differs from the power level "strong low energy" even though in both power levels one of the switches S1, S2 is in diode mode and the other switch is off. This difference can be achieved precisely by the different configurations of the switches described above, for example in terms of their conductivity. In the present case, the first switch S1 has a higher conductivity than the second switch S2.

[0095] The operating voltage 110 or 108 provided for the at least one storage cell 102 in the low-energy mode may accordingly be precisely set using a plurality of switches S1 , S2 , . . . , for example of different designs, and may be coordinated with the requirements of the at least one storage cell 102 , for example the memory array 100 .

[0096] In different embodiments, during a test phase, for example, the requirements of at least one memory cell 102 can be determined, which operating voltage is required for data maintenance, and the conduction state of the first and / or second switch S1, S2 and / or the combination of power levels to be achieved can be configured or configured such that a certain operating voltage can be ensured also in low-energy mode.

[0097] This flexibility can be advantageous because fluctuations during the manufacture of semiconductor devices may result in memory cells 102 or memory arrays 100 having different characteristics. In particular, some memory arrays 100 may have different requirements for a higher sustaining voltage (VDDC-VSSC) than other memory arrays. For example, one memory array 100 may require 0.6V in order to ensure that data stored therein is maintained, while another memory array 100 may only require 0.5V.

[0098] A sustain voltage for the entire memory array 100 that is set based on the memory array 100 requiring the highest voltage may unnecessarily increase power consumption for a portion of the memory array 100 because a memory array 100 that actually requires a lower voltage operates at an unnecessarily high voltage during the low voltage mode (e.g., it could actually operate at 0.5V, but uses 0.6V).

[0099] In various embodiments, a configurable voltage supply (ie, VDDC, VSSC, or both) is provided. In this case, configuration can be performed, for example, during manufacturing tests, ie, the voltage can be maintained to match fluctuations in the manufacturing process.

[0100] In various embodiments, the matching or coordination can be performed at the wafer level, ie all chips on a wafer are provided with the same settings, but each chip receives its own settings.

[0101] In various embodiments, matching or coordination may be performed at the chip level, ie, so that all memory arrays 100 of a chip are provided with the same settings, but each chip obtains its own settings.

[0102] In various embodiments, matching or coordination may be performed at the memory level, ie, such that each memory array 100 of a chip is provided with its own settings.

[0103] In various embodiments, the power consumption of the memory cell arrangement 300 is reduced.

[0104] The reduction in the required chip area and the reduced energy consumption lead directly or indirectly (for example, the reduced energy consumption leads to cost savings in the chip package, the voltage supply device and / or the cooling device) to a cost reduction.

[0105] Furthermore, the possibility of relatively finely coordinated setting of the holding voltage after testing can increase the yield in manufacturing.

[0106] Figure 7 A flow chart of a method 700 for operating a memory cell arrangement according to various exemplary embodiments is shown.

[0107] Method 700 may include providing a memory cell arrangement having at least one memory cell, a first switch connected between the at least one memory cell and a reference potential, and a switch control logic arrangement having a first subcircuit (at 710 ).

[0108] Method 700 may also include selectively placing the first switch in one of at least three operating states by activating or deactivating the first subcircuit: an on state; an off state; and a conducting state, in which the conductivity is less than in the on state and higher than in the off state (in 720).

[0109] Some embodiments are briefly described below.

[0110] Embodiment 1 is a memory cell device. The memory cell device may include: at least one memory cell; a first switch connected between the at least one memory cell and a reference potential; and a switch control logic device, wherein the switch control logic device is configured to selectively place the first switch in one of at least three operating states by activating or deactivating a first subcircuit of the switch control logic device: an on state; an off state, and a conducting state, in which the conductivity is less than in the on state and higher than in the off state.

[0111] Embodiment 2 is a storage cell device according to embodiment 1, wherein the storage cell device also has a second switch connected between the at least one storage cell and the reference potential; wherein the switch control logic device is also configured to selectively place the second switch in one of at least three operating states by activating or deactivating a second subcircuit of the switch control logic device: an on state; an off state; and a conduction state, in which the conductivity is less than in the on state and higher than in the off state.

[0112] Embodiment 3 is a storage cell device according to Embodiment 1 or 2, wherein the storage cell device further comprises: a third switch connected between the at least one storage cell and the reference potential, wherein the switch control logic device is further configured to selectively place the third switch in exactly one of two operating states: an on state; and an off state.

[0113] Embodiment 4 is the memory cell device of embodiment 2 or 3, wherein the first switch in the conducting state has a higher conductivity than the second switch in the conducting state.

[0114] Embodiment 5 is the memory cell device according to any one of embodiments 1 to 4, wherein the first switch comprises a first field effect transistor.

[0115] Embodiment 6 is the memory cell device of embodiment 5, wherein the conduction state of the first field effect transistor is a diode mode state of the first field effect transistor.

[0116] Embodiment 7 is the memory cell device according to any one of embodiments 2 to 6, wherein the second switch comprises a second field effect transistor.

[0117] Embodiment 8 is the memory cell device of embodiment 7, wherein the conduction state of the second field effect transistor is a diode mode state of the second field effect transistor.

[0118] Embodiment 9 is the memory cell device according to embodiment 7 or 8, wherein the first field effect transistor has a larger transistor width than the second field effect transistor.

[0119] Embodiment 10 is the memory cell device according to any one of embodiments 7 to 9, wherein the first field effect transistor has a lower threshold voltage than the second field effect transistor.

[0120] Embodiment 11 is a storage cell device according to any one of Embodiments 5 to 10, wherein the first field effect transistor has a first gate, wherein the switch control logic device has a first gate control circuit, and the first gate control circuit is configured to connect the first gate to a positive voltage supply terminal in an on state, connect the first gate to a ground terminal in an off state, and connect the first gate to a virtual voltage supply terminal in a conducting state.

[0121] Embodiment 12 is the memory cell device according to embodiment 11, wherein the first field effect transistor is an NFET transistor; and wherein the virtual voltage supply terminal is a ground terminal.

[0122] Embodiment 13 is a storage cell device according to any one of Embodiments 5 to 10, wherein the first field effect transistor has a first gate, wherein the switch control logic device has a first gate control circuit, and the first gate control circuit is configured to connect the first gate to the ground terminal in the on state, connect the first gate to the positive voltage supply terminal in the off state, and connect the first gate to the virtual voltage supply terminal in the conduction state.

[0123] Embodiment 14 is the memory cell device of embodiment 13, wherein the first field effect transistor is a PFET transistor; and wherein the virtual voltage supply terminal is a positive voltage supply terminal.

[0124] Embodiment 15 is the memory cell device of any one of embodiments 11 to 14, wherein the gate control circuit has a third field effect transistor between the first gate and the positive voltage supply terminal.

[0125] Embodiment 16 is the memory cell device according to any one of embodiments 11 to 15, wherein the gate control circuit has a fourth field effect transistor between the first gate and the ground terminal.

[0126] Embodiment 17 is the memory cell device of any one of embodiments 11 to 16, wherein the gate control circuit has a fifth field effect transistor between the first gate and the virtual voltage supply terminal.

[0127] Embodiment 18 is a storage unit device according to Embodiment 2, wherein the switch control logic device is configured to selectively place the storage unit device in one of at least three power levels by placing the first switch and the second switch in one of their three operating states, respectively: a fully-on state, in which the first switch and the second switch are in an on state; a partial power state, in which at least one of the first switch and the second switch is in a conducting state; and a fully-off state, in which the first switch and the second switch are in an off state.

[0128] Embodiment 19 is the storage cell arrangement according to embodiment 18, wherein the at least three power stages further have a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

[0129] Embodiment 20 is a storage unit device according to Embodiment 3, wherein the switch control logic device is configured to selectively place the storage unit device in one of at least three power levels by placing the first switch and the second switch in one of their three operating states, respectively, and placing the third switch in one of its two operating states: a fully-on state, in which the first switch, the second switch, and the third switch are in an on state; a partial power state, in which at least one of the first switch and the second switch is in a conducting state; and a fully-off state, in which the first switch, the second switch, and the third switch are in an off state.

[0130] Embodiment 21 is a storage unit device according to embodiment 20, wherein the at least three power stages also have a partially open state, in which at least one of the first switch, the second switch and the third switch is in an on state, and at least one of the other two switches is in an off state.

[0131] Embodiment 22 is a memory cell device according to any one of embodiments 18 to 21, wherein the partial power state and / or the partial open state is configured so that the value of the voltage dropped across the at least one memory cell is high enough to ensure continuous data storage.

[0132] Embodiment 23 is the memory cell arrangement according to any one of embodiments 1 to 22, wherein the memory cell arrangement forms a volatile data memory.

[0133] Embodiment 24 is the memory cell device according to any one of embodiments 1 to 23, wherein the memory cell device forms a SRAM, DRAM, RRAM, MRAM, PC-RAM, ROM or flash data storage.

[0134] Embodiment 25 is a method for operating a storage cell device, the storage cell device having: at least one storage cell; a first switch connected between the at least one storage cell and a reference potential; and a switch control logic device, the switch control logic device having a first subcircuit, the method comprising: selectively placing the first switch in one of at least three operating states by activating or deactivating the first subcircuit: an on state; an off state, and a conduction state, in which the conductivity is less than in the on state and higher than in the off state.

[0135] Embodiment 26 is a method according to embodiment 25, wherein the storage cell device also has a second switch connected between the at least one storage cell and the reference potential, and has a second subcircuit in the switch control logic device, and the method further includes: selectively placing the second switch in one of at least three operating states by activating or deactivating the second subcircuit: an on state; an off state; and a conduction state, in which the conductivity is less than in the on state and higher than in the off state.

[0136] Embodiment 27 is a method according to embodiment 25 or 26, wherein the memory cell device also has a third switch connected between the at least one memory cell and the reference potential, and the method further comprises: selectively placing the third switch in exactly one of two operating states: an on state; and an off state.

[0137] Embodiment 28 is a method according to embodiment 26, and the method further includes: placing the first switch and the second switch in one of their three operating states respectively so as to selectively place the storage unit device in one of at least three power levels: a fully-on state, in which the first switch and the second switch are in an on state; a partial power state, in which at least one of the first switch and the second switch is in a conducting state; and a fully-off state, in which the first switch and the second switch are in an off state.

[0138] Embodiment 29 is a method according to embodiment 28, wherein the at least three power stages further have: a partially on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

[0139] Embodiment 30 is a method according to embodiment 27, and the method further includes: placing the first switch and the second switch in one of their three operating states, respectively, and placing the third switch in one of its two operating states, so as to selectively place the storage unit device in one of at least three power levels: a fully-on state, in which the first switch, the second switch, and the third switch are in an on state; a partial power state, in which at least one of the first switch and the second switch is in a conducting state; and a fully-off state, in which the first switch, the second switch, and the third switch are in an off state.

[0140] Embodiment 31 is the method according to embodiment 30,

[0141] The at least three power stages further have a partially open state in which at least one of the first switch, the second switch and the third switch is in an on state and at least one of the other two switches is in an off state.

[0142] Embodiment 32 is a method according to any one of embodiments 28 to 31, the method further comprising: placing the storage unit device in a fully open state for active operation.

[0143] Embodiment 33 is a method according to any one of embodiments 28 to 32, the method further comprising: placing the storage unit device in a partial power state for standby operation.

[0144] Embodiment 34 is a method according to Embodiment 29 or 31, and the method further includes: when placing the storage unit device from a fully closed state to a fully open state, first placing the storage unit device from the fully closed state to a partially open state, and then placing the storage unit device from the partially open state to the fully open state.

Claims

1. A storage unit device, comprising: at least one storage unit; A first switch connected between the at least one storage unit and a reference potential, wherein the first switch is configured to be selectively placed in one of at least three operating states, wherein the at least three operating states include: • connected state; • Off state, and • a conducting state in which the conductivity is less than in the on-state and higher than in the off-state; as well as A second switch connected between the at least one storage unit and the reference potential, wherein the second switch is configured to be selectively placed in one of at least three operating states independently of the first switch, wherein the at least three operating states include: • connected state; • Off state; and • a conducting state in which the conductivity is lower than in the on state and higher than in the off state, The first switch and the second switch are connected in parallel.

2. The storage unit device according to claim 1, further comprising: a switch control logic device configured to selectively place the first switch in one of the at least three operating states by activating or deactivating a first subcircuit of the switch control logic device; and The second switch is selectively placed in one of the at least three operating states by activating or deactivating the second subcircuit of the switch actuation logic.

3. A memory cell arrangement according to claim 1 or 2, wherein the conduction state into which the first switch can be placed is a static conduction state, and wherein the conduction state into which the second switch can be placed is a static conduction state.

4. The storage unit device according to claim 2, Also features: a third switch connected between the at least one storage unit and the reference potential; The switch control logic device is further configured to selectively place the third switch in exactly one of two operating states, wherein the two operating states include: • connected state; and • Off state.

5. The storage unit device according to claim 1 or 2, The first switch in the conducting state has a higher conductivity than the second switch in the conducting state.

6. The storage unit device according to claim 2, The first switch has a first field effect transistor.

7. The storage unit device according to claim 6, Wherein the conduction state of the first field effect transistor is a diode mode state of the first field effect transistor.

8. The storage unit device according to claim 2, The second switch has a second field effect transistor.

9. The storage unit device according to claim 6, The second switch has a second field effect transistor.

10. The storage unit device according to claim 9, Wherein the conduction state of the second field effect transistor is a diode mode state of the second field effect transistor.

11. The storage unit device according to claim 9 or 10, The first field effect transistor has a larger transistor width than the second field effect transistor.

12. The storage unit device according to claim 9 or 10, The first field effect transistor has a lower threshold voltage than the second field effect transistor.

13. The storage unit arrangement according to any one of claims 6 to 7 and 9 to 10, wherein the first field effect transistor has a first gate, The switch control logic device has a gate control circuit, which is configured to connect the first gate to the positive voltage supply terminal in the on state, connect the first gate to the ground terminal in the off state, and connect the first gate to the virtual voltage supply terminal in the conducting state.

14. The storage unit device according to claim 13, • wherein the first field effect transistor is an NFET transistor; and • Wherein the virtual voltage supply terminal is a ground terminal.

15. The storage unit arrangement according to any one of claims 6 to 7 and 9 to 10, • wherein the first field effect transistor has a first gate, • The switch control logic device has a gate control circuit, which is configured to connect the first gate to the ground terminal in the on state, connect the first gate to the positive voltage supply terminal in the off state, and connect the first gate to the virtual voltage supply terminal in the conducting state.

16. The storage unit device according to claim 15, • wherein the first field effect transistor is a PFET transistor; and • Wherein the virtual voltage supply terminal is a positive voltage supply terminal.

17. The storage unit device according to claim 13, The gate control circuit has a third field effect transistor between the first gate and the positive voltage supply terminal.

18. The storage unit device according to claim 13, The gate control circuit has a fourth field effect transistor between the first gate and the ground terminal.

19. The storage unit device according to claim 13, The gate control circuit has a fifth field effect transistor between the first gate and the virtual voltage supply terminal.

20. The storage unit device according to claim 2, The switch control logic device is configured to selectively place the storage unit device in one of at least three power levels by placing the first switch and the second switch in one of their three operating states, wherein the at least three power levels include: • a fully-on state, in which the first switch and the second switch are in an on state; • a partial power state in which at least one of the first switch and the second switch is in a conducting state; and • A fully-off state, in which the first switch and the second switch are in an off state.

21. The storage unit device according to claim 20, The at least three power stages further have a partial on state in which the first switch is in an on state and the second switch is in an off state, or vice versa.

22. The storage unit device according to claim 4, The switch control logic device is configured to selectively place the storage unit device in one of at least three power levels by placing the first switch and the second switch in one of their three operating states and placing the third switch in one of its two operating states, wherein the at least three power levels include: • a fully-on state, in which the first switch, the second switch and the third switch are in an on state; • a partial power state in which at least one of the first switch and the second switch is in a conducting state; and • A fully-off state, in which the first switch, the second switch, and the third switch are in an off state.

23. The storage unit device according to claim 22, The at least three power stages further have a partially open state, in which at least one of the first switch, the second switch and the third switch is in an on state, and at least one of the other two switches is in an off state.

24. The storage unit arrangement according to any one of claims 20 to 23, The partial power state and / or the partial open state is configured in such a way that the value of the voltage dropped across the at least one storage cell is sufficiently high in order to ensure continuous data storage.

25. The storage unit device according to claim 1 or 2, The memory cell arrangement forms a volatile data memory.

26. The storage unit device according to claim 1 or 2, The memory cell device forms an SRAM data memory, a DRAM data memory, an RRAM data memory, an MRAM data memory, a PC-RAM data memory, a ROM data memory or a flash memory data memory.

27. A method for operating a memory cell arrangement, the memory cell arrangement comprising: at least one memory cell; a first switch connected between the at least one memory cell and a reference potential; a second switch connected between the at least one storage unit and the reference potential; A switch control logic device, wherein the switch control logic device has a first subcircuit; and a second sub-circuit, wherein the first switch and the second switch are connected in parallel, the method comprising: selectively placing the first switch in one of at least three operating states by activating or deactivating the first subcircuit, wherein the three operating states include: • connected state; • Off state, and • a conducting state in which the conductivity is less than in the on-state and higher than in the off-state; and selectively placing the second switch in one of at least three operating states by activating or deactivating the second subcircuit, wherein the at least three operating states include: • connected state; • Off state; and • A conducting state in which the conductivity is lower than in the on-state and higher than in the off-state.

28. Method for operating a storage unit arrangement according to claim 27, wherein the conduction state into which the first switch can be placed is a quiescent conduction state, and wherein the conduction state into which the second switch can be placed is a quiescent conduction state.

29. The method for operating a memory cell arrangement according to claim 27 or 28, wherein the memory cell arrangement further comprises a third switch connected between the at least one memory cell and the reference potential, the method further comprising: The third switch is selectively placed in exactly one of two operating states, wherein the two operating states include: • connected state; and • Off state.

30. The method for operating a storage unit device according to claim 27, the method further comprising: Placing the first switch and the second switch in one of their three operating states respectively so as to selectively place the storage cell arrangement in one of at least three power levels, wherein the at least three power levels include: • a fully-on state, in which the first switch and the second switch are in an on state; • a partial power state in which at least one of the first switch and the second switch is in a conducting state; and • A fully-off state, in which the first switch and the second switch are in an off state.

31. The method for operating a storage unit arrangement according to claim 30, The at least three power stages further include: • A partially open state in which the first switch is in an on-state and the second switch is in an off-state, or vice versa.

32. The method for operating a storage unit device according to claim 29, the method further comprising: placing the first switch and the second switch in one of their three operating states, respectively, and placing the third switch in one of its two operating states, so as to selectively place the storage cell arrangement in one of at least three power levels, wherein the at least three power levels include: • a fully-on state, in which the first switch, the second switch and the third switch are in an on state; • a partial power state in which at least one of the first switch and the second switch is in a conducting state; and • A fully-off state, in which the first switch, the second switch, and the third switch are in an off state.

33. The method for operating a storage unit arrangement according to claim 32, The at least three power stages further include: • A partially open state in which at least one of the first switch, the second switch and the third switch is in an on state, and at least one of the other two switches is in an off state.

34. The method for operating a storage unit device according to claim 30 or 31, the method further comprising: The memory cell arrangement is placed in a partial power state for standby operation.

35. The method for operating a storage unit device according to claim 30, further comprising: When the storage cell device is placed from the fully closed state to the fully open state, the storage cell device is first placed from the fully closed state to the partially open state, and then the storage cell device is placed from the partially open state to the fully open state.

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