Light Emitting Diode Display Devices

Abstract

A light emitting diode display device includes: a substrate, a first layer arranged on the substrate, a first transistor arranged on the first layer and including a first gate electrode, and a light emitting diode connected to the first transistor, wherein: the first layer may overlap with the first gate electrode and may include: a first region including a first material and a second region including a second material different from the first material, the first material may include amorphous silicon doped with impurities, and the second material may include amorphous silicon.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0167472, filed on December 21, 2018, and all benefits derived therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of the present invention relate to a light emitting diode display device. Background Art

[0003] Recently, light emitting diode display devices have attracted attention as devices for displaying images.

[0004] Because the light emitting diode display device has a self-emitting characteristic and does not require an additional light source, the thickness and weight of the light emitting diode display device can be reduced, unlike the liquid crystal display device. Further, the light emitting diode display device has high quality characteristics such as low power consumption, high brightness and high response speed.

[0005] Generally, a light emitting diode display device includes a substrate, a plurality of transistors arranged on the substrate, a plurality of insulating films arranged between wirings included in the transistors, and light emitting diodes connected to the transistors. Summary of the invention

[0006] Exemplary embodiments of the present invention provide a light emitting diode display device that can be manufactured by a simple manufacturing process, has excellent transistor performance, and improves afterimage.

[0007] An exemplary embodiment of the present invention provides a light emitting diode display device, comprising: a substrate, a first layer arranged on the substrate, a first transistor arranged on the first layer and including a first gate electrode, and a light emitting diode connected to the first transistor, wherein: the first layer may overlap with the first gate electrode and may include: a first region including a first material and a second region including a second material different from the first material, the first material may include amorphous silicon doped with impurities, and the second material may include amorphous silicon.

[0008] In exemplary embodiments, the first region may have conductivity.

[0009] In an exemplary embodiment, a light emitting diode display device may include a first gate conductor disposed on a first layer, and the first gate conductor may include a second scan line, a first scan line, a light emitting control line, and a first gate electrode.

[0010] In exemplary embodiments, the first region may have a plan shape substantially the same as a plan shape of the first gate conductor.

[0011] In an exemplary embodiment, the first region may include at least one of a first subregion overlapping the second scan line, a second subregion overlapping the first scan line, a third subregion overlapping the first gate electrode, and a fourth subregion overlapping the light emitting control line.

[0012] In exemplary embodiments, the first sub-region, the second sub-region, and the fourth sub-region may extend along the first direction.

[0013] In exemplary embodiments, a light emitting diode display device may include a second gate conductor disposed on the first layer, and the second gate conductor may include a parasitic capacitor control pattern, a storage line, and an initialization voltage line.

[0014] In exemplary embodiments, the first region may have substantially the same plan shape as that of the second gate conductor.

[0015] In exemplary embodiments, the first region may include at least one of a first sub-region overlapping the initialization voltage line, a second sub-region overlapping the parasitic capacitor control pattern, and a third sub-region overlapping the storage line.

[0016] In exemplary embodiments, the first sub-region and the third sub-region may extend along the first direction.

[0017] In exemplary embodiments, the first region may overlap with the first transistor.

[0018] In exemplary embodiments, the first region may receive a predetermined voltage.

[0019] In exemplary embodiments, a driving voltage may be applied to the first region.

[0020] In exemplary embodiments, the thickness of the first region may decrease toward an end of the first region.

[0021] In exemplary embodiments, the thickness of the first region may be smaller than the thickness of the first layer.

[0022] In exemplary embodiments, the thickness of the first region may be equal to the thickness of the first layer.

[0023] Another exemplary embodiment of the present invention provides a light emitting diode display device, comprising: a substrate, a first layer arranged on the substrate, a first transistor arranged on the first layer, and a light emitting diode connected to the first transistor, wherein: the first layer may include a first region overlapping the first transistor and having conductivity and a second region surrounding the first region and including a semiconductor material.

[0024] In an exemplary embodiment, the substrate may include a display area in which the light emitting device is arranged and a peripheral area surrounding the display area, and the first region may receive the constant voltage in the peripheral area.

[0025] In an exemplary embodiment, a first region including amorphous silicon doped with impurities may be formed by a mask for forming a gate conductor. In an exemplary embodiment, a separate mask for forming the first region does not need to be manufactured, so that a process for forming the first region may be simplified and the cost required for the process may be reduced. In addition, in an exemplary embodiment, since the first region may be formed only at a necessary position, a light emitting diode display device having an excellent afterimage improvement effect without affecting other transistors may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other exemplary embodiments, advantages and features of the present disclosure will become more apparent by further describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:

[0027] Figure 1 An equivalent circuit diagram of an exemplary embodiment of one pixel of a light emitting diode display device is illustrated.

[0028] Figure 2 A timing diagram illustrating an exemplary embodiment of signals applied to one pixel of a light emitting diode display device.

[0029] Figure 3 A plan view illustrating an exemplary embodiment of a partial area of ​​a light emitting diode display device.

[0030] Figure 4 A plan view of an exemplary embodiment of a first floor is illustrated.

[0031] Figure 5 The diagram is along Figure 3 A cross-sectional view taken along line V-V'.

[0032] Figure 6 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0033] Figure 7 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0034] Figure 8 A plan view illustrating an exemplary embodiment of a partial area of ​​a light emitting diode display device.

[0035] Fig. 9 A plan view of an exemplary embodiment of a first floor is illustrated.

[0036] Fig.10 The diagram is along Figure 8 A cross-sectional view taken along line XX'.

[0037] Fig.11 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0038] Fig.12 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0039] Fig.13 A schematic plan view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0040] Fig.14 A schematic plan view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0041] Fig.15 A schematic plan view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0042] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 Cross-sectional views of a light emitting diode display device according to manufacturing processes are respectively illustrated. DETAILED DESCRIPTION

[0043] The present invention will be described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the present invention are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0044] In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals designate the same elements throughout the specification.

[0045] Further, in the drawings, the size and thickness of each element are arbitrarily illustrated for ease of description, and the present invention is not necessarily limited to those elements illustrated in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thickness of some layers and regions are exaggerated for ease of description.

[0046] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly" "on" another element, there are no intervening elements. Further, in the specification, the words "on" or "above" mean being above or below a target portion, and do not necessarily mean being on the upper side of a target portion based on the direction of gravity.

[0047] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0048] Further, throughout the specification, the phrase "in a plan view" means viewing a target portion from the top, and the phrase "in a cross section" means viewing a cross section formed by vertically cutting the target portion from the side.

[0049] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value or within ±30%, 20%, 10%, 5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that those terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0051] Exemplary embodiments are described herein with reference to schematic cross-sectional illustrations that are schematic illustrations of idealized embodiments. Therefore, deformations of the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the zones as illustrated herein, but rather to include deviations in shapes, for example, caused by manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. Moreover, illustrated sharp angles may be rounded. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to be the precise shapes of the illustrated zones and are not intended to limit the scope of the claims.

[0052] In the following, reference will be made to Figure 1 and Figure 2 Exemplary embodiments of a light emitting diode display device are described. Figure 1 An equivalent circuit diagram of an exemplary embodiment of a pixel of a light emitting diode display device is illustrated, and Figure 2 A timing diagram illustrating an exemplary embodiment of signals applied to one pixel of a light emitting diode display device.

[0053] Reference Figure 1 , a pixel PX of the light emitting diode display device includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7 connected to a plurality of signal lines 127, 151, 152, 153, 158, 171, 172 and 741, a storage capacitor Cst and a light emitting diode LED.

[0054] In an exemplary embodiment, the first layer may be arranged in Figure 1 The first layer includes a first region and a second region, and the first region may overlap with the position where the first transistor T1 is arranged. Figures 3 to 5 Describe the first layer in detail.

[0055] The light emitting diode display device includes a display area in which an image is displayed, and in the display area, pixels PX are arranged in various shapes.

[0056] The plurality of transistors T1, T2, T3, T4, T5, T6 and T7 include a driving transistor T1, a switching transistor (that is, a second transistor T2 and a third transistor T3) connected to the first scan line 151, and other transistors are transistors for performing operations required to drive the light emitting diode LED (hereinafter also referred to as compensation transistors). The compensation transistors T4, T5, T6 and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0057] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a first scan line 151, a second scan line 152, a light emitting control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be a part of the second scan line 152 or may be electrically connected to the second scan line 152.

[0058] The first scan line 151 is connected to the gate driver to transmit the scan signal Sn to the second transistor T2 and the third transistor T3. The second scan line 152 is connected to the gate driver and transmits the front scan signal Sn-1 applied to the pixel PX arranged at the previous stage to the fourth transistor T4. The light emission control line 153 is connected to the light emission control part and transmits the light emission control signal EM for controlling the light emission time of the light emitting diode LED to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits the bypass signal GB to the seventh transistor T7.

[0059] The data line 171 is a wiring for transmitting a data voltage Dm generated in a data driver, and the brightness emitted by the light emitting diode LED (also referred to as a light emitting element) changes according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD. The initialization voltage line 127 transmits an initialization voltage Vint for initializing the driving transistor T1. The common voltage line 741 applies a common voltage ELVSS. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be constant.

[0060] Hereinafter, a plurality of transistors will be described.

[0061] The driving transistor T1 is a transistor that adjusts the output current according to the applied data voltage Dm. The output driving current I d Applied to the light emitting diode LED to adjust the brightness of the light emitting diode LED according to the data voltage Dm. To this end, the first electrode S1 of the driving transistor T1 is arranged to receive the driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 (output electrode) of the driving transistor T1 is arranged to be able to output current to the light emitting diode LED. The second electrode D1 of the driving transistor T1 is connected to the anode of the light emitting diode LED via the sixth transistor T6. The gate electrode G1 of the driving transistor T1 is connected to one electrode (the second storage electrode E2) of the storage capacitor Cst. Therefore, the voltage of the gate electrode G1 changes depending on the voltage stored in the storage capacitor Cst, and thus the driving current I output by the driving transistor T1 d Change.

[0062] The second transistor T2 is a transistor for receiving a data voltage Dm in the pixel PX. The gate electrode G2 of the second transistor T2 is connected to the first scan line 151, and the first electrode S2 of the second transistor T2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on depending on the first scan signal Sn transmitted through the first scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0063] The third transistor T3 is a transistor that allows a compensation voltage (voltage of Dm+Vth), wherein the data voltage Dm is changed when it is transmitted to the second storage electrode E2 of the storage capacitor Cst through the driving transistor T1. The gate electrode G3 of the third transistor T3 is connected to the first scan line 151, and the first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is connected to the gate electrode G1 and the second electrode D1 of the driving transistor T1 depending on the scan signal Sn received through the first scan line 151, and it is also connected to the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0064] The fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the second scan line 152, and the first electrode S4 of the fourth transistor T4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst depending on the pre-scan signal Sn-1 received through the second scan line 152. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value, so it can be a voltage that can turn on the driving transistor T1.

[0065] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 of the fifth transistor T5 is connected to the light emission control line 153, and the first electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0066] The sixth transistor T6 is used to convert the driving current I outputted from the driving transistor T1 into d The gate electrode G6 of the sixth transistor T6 is connected to the light emitting control line 153, and the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0067] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on by the light emitting control signal EM received through the light emitting control line 153, and when the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current I according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second storage electrode E2 of the storage capacitor Cst). d The output drive current I d The current I led When current flows through the light emitting diode LED, the light emitting diode LED emits light.

[0068] The seventh transistor T7 is used to initialize the anode of the light emitting diode LED. The gate electrode G7 of the seventh transistor T7 is connected to the bypass control line 158, the first electrode S7 of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and the second electrode D7 of the seventh transistor T7 is connected to the initialization voltage line 127. In an exemplary embodiment, the bypass control line 158 can be connected to the second scan line 152, and the bypass signal GB can be the same timing signal as the front scan signal Sn-1. In an exemplary embodiment, the bypass control line 158 is not connected to the second scan line 152, and a separate signal different from the front scan signal Sn-1 can be transmitted. When the seventh transistor T7 is turned on by the bypass signal GB, the initialization voltage Vint is applied to the anode of the light emitting diode LED to initialize it.

[0069] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1, and it receives the data voltage Dm through the second electrode D3 of the third transistor T3, or receives the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0070] An anode of the light emitting diode LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 , and a cathode of the light emitting diode LED is connected to a common voltage line 741 for transmitting a common voltage ELVSS.

[0071] exist Figure 1 In the exemplary embodiment of FIG. 1 , the pixel circuit includes seven transistors T1 to T7 and one capacitor Cst, but is not limited thereto, and the number of transistors and the number of capacitors and their connections may be variously changed.

[0072] Now refer to Figure 1 and Figure 2 The operation of one pixel of the light emitting diode display device in the exemplary embodiment is described.

[0073] During the initialization period, the low-level pre-scan signal Sn-1 is supplied to the pixel PX through the second scan line 152. In this case, the fourth transistor T4 to which the low-level pre-scan signal Sn-1 is applied is turned on, so that the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. Therefore, the driving transistor T1 and the storage capacitor Cst are initialized. The voltage of the initialization voltage Vint is low, so that the driving transistor T1 can be turned on.

[0074] In addition, during the initialization period, a low-level bypass signal GB is applied to the seventh transistor T7. The seventh transistor T7 to which the low-level bypass signal GB is applied is turned on so that the initialization voltage Vint is applied to the anode of the light emitting diode LED through the seventh transistor T7. Therefore, the anode of the light emitting diode LED is also initialized.

[0075] Thereafter, during a data writing period, a low-level scan signal Sn is supplied to the pixel PX through the first scan line 151. The second transistor T2 and the third transistor T3 are turned on by the low-level scan signal Sn.

[0076] When the second transistor T2 is turned on, the data voltage Dm is input to the first electrode S1 of the driving transistor T1 through the second transistor T2.

[0077] In addition, during the data writing period, the third transistor T3 is turned on so that the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 of the driving transistor T1 is diode-connected to the second electrode D1. Further, because a low voltage (initialization voltage Vint) is applied to the gate electrode G1 during the initialization period, the driving transistor T1 is in a conducting state. Therefore, the data voltage Dm input to the first electrode S1 of the driving transistor T1 is output from the second electrode D1 through the channel of the driving transistor T1, and is then stored in the second storage electrode E2 of the storage capacitor Cst through the third transistor T3.

[0078] In this case, the voltage applied to the second storage electrode E2 changes according to the threshold voltage Vth of the driving transistor T1, the data voltage Dm is applied to the first electrode S1 of the driving transistor T1, and when the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output at the second electrode D1 may be "Vgs+Vth". Herein, Vgs is the difference between the voltages applied to the gate electrode G1 and the first electrode S1 of the driving transistor T1, so it may be "Dm-Vint". Therefore, the voltage output from the second electrode D1 and stored in the second storage electrode E2 may be "Dm-Vint+Vth".

[0079] Thereafter, during the light emission period, because the light emission control signal EM supplied from the light emission control line 153 is at a low level, the fifth transistor T5 and the sixth transistor T6 are turned on. As a result, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the light emitting diode LED. The driving transistor T1 outputs a driving current I according to the difference between the voltage of the gate electrode G1 and the voltage of the first electrode S1 (i.e., the driving voltage ELVDD). d The driving current I of the driving transistor T1 d It may have a value proportional to the square value of "Vgs-Vth". In this article, Vgs is the difference between the voltages applied to both terminals of the storage capacitor Cst, and because Vgs is "Vg-Vs", it may be "Dm-Vint+Vth-ELVDD". In this article, when "Vgs-Vth" is obtained by subtracting Vth, it is "Dm-Vint-ELVDD". That is, the driving current I of the driving transistor T1 d It may be a current that is independent of the threshold voltage Vth of the driving transistor T1.

[0080] Therefore, even if the driving transistors T1 disposed in the respective pixels PX have different threshold voltages Vth due to process dispersion, the output current of the driving transistor T1 may be outputted to be constant, thereby improving non-uniformity of characteristics of the driving transistor T1 .

[0081] In the above calculation formula, when the transistor is a p-type transistor using a polycrystalline semiconductor, Vth may be a value slightly greater than 0 or a negative value. In addition, the signs of + and - may change depending on the direction of the calculated voltage. However, even in this case, the driving current I which is the output current of the driving transistor T1 d It may also have a value independent of the threshold voltage Vth.

[0082] When the above-mentioned light emission period ends, the same operation is repeated from the initialization period.

[0083] Depending on the direction in which voltage or current is applied, one of the first and second electrodes of each of the multiple transistors T1, T2, T3, T4, T5, T6 and T7 may be a source electrode, and the other of the first and second electrodes of each of the multiple transistors T1, T2, T3, T4, T5, T6 and T7 may be a drain electrode.

[0084] In some exemplary embodiments, when the seventh transistor T7 initializes the anode of the light emitting diode LED in the initialization period, it can even prevent a small amount of current emitted under the condition that the driving transistor T1 is not actually turned on from flowing to the light emitting diode LED. In this case, the small amount of current is used as the bypass current I bp Discharged to the terminal providing the initialization voltage Vint through the seventh transistor T7. Therefore, the light emitting diode LED does not emit unnecessary light, so that the black grayscale can be displayed more clearly and the contrast can be improved. In this case, the bypass signal GB can be a signal having a timing different from that of the front scanning signal Sn-1. In some exemplary embodiments, the seventh transistor T7 can be omitted.

[0085] In the pixel PX operated as described above, the first layer may not be operated specifically and may be in a state where a constant voltage is applied or in a base state. The application of a constant voltage is intended to prevent a potential change when a specific charge is injected into the first layer itself. The first layer may suppress a change in the characteristics of the first transistor T1 and have a desired characteristic when overlapping with the first transistor T1.

[0086] In the following, reference will be made to Figures 3 to 5 Exemplary embodiments of a pixel and a first layer 31 of a light emitting diode display device are described. Figure 3 A plan view illustrating an exemplary embodiment of a partial area of ​​a light emitting diode display device, Figure 4 A plan view of an exemplary embodiment of the first layer 31 is shown, and Figure 5 The diagram is along Figure 3 A cross-sectional view taken along line V-V'.

[0087] Reference Figure 3 The light emitting diode display device in the exemplary embodiment includes a first scan line 151 extending along a first direction D1 and transmitting a scan signal Sn, a second scan line 152 for transmitting a previous scan signal Sn-1, a light emitting control line 153 for transmitting a light emitting control signal EM, and an initialization voltage line 127 for transmitting an initialization voltage Vint. The bypass signal GB is transmitted through the second scan line 152.

[0088] The light emitting diode display device includes a data line 171 extending in a second direction D2 perpendicular to the first direction D1 and transmitting a data voltage Dm, and a driving voltage line 172 for transmitting a driving voltage ELVDD.

[0089] The light emitting diode display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode LED.

[0090] The channel of each of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is located in the semiconductor layer 130 (refer to Figure 5 ). In addition, at least some of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are also located in the semiconductor layer 130. The semiconductor layer 130 ( Figure 3 The semiconductor layer 130 may include a polycrystalline semiconductor such as polysilicon or an oxide semiconductor.

[0091] The semiconductor layer 130 includes a channel doped with n-type impurities or p-type impurities, and the first doping region and the second doping region located at opposite sides of the channel have a doping concentration higher than the doping concentration of the impurities doped in the channel. The first doping region and the second doping region correspond to the first electrode and the second electrode of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7, respectively. When one of the first doping region and the second doping region is a source region, the other is a drain region. In addition, in the semiconductor layer 130, the region between the first electrode and the second electrode of two different transistors is also doped so that the two transistors can be electrically connected to each other.

[0092] Each of the channels of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7 overlaps with the gate electrode of each of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7, and is located between the first electrode and the second electrode of each of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7. The plurality of transistors T1, T2, T3, T4, T5, T6 and T7 may have substantially the same stacked structure. Hereinafter, the driving transistor T1 will be mainly described in detail, and the remaining transistors T2, T3, T4, T5, T6 and T7 will be briefly described.

[0093] The driving transistor T1 includes a channel, a first gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is between the first electrode S1 and the second electrode D1, and overlaps with the first gate electrode 155 in a plan view. The channel is curved so as to form a long channel in a limited area. The driving range of the gate voltage Vg applied to the first gate electrode 155 of the driving transistor T1 widens as the length of the channel increases, and the driving current I dAccording to the gate voltage Vg, it increases steadily. Therefore, the grayscale of the light emitted from the light emitting diode LED can be finely controlled by changing the gate voltage Vg, and the display quality of the light emitting diode display device can also be improved. In addition, because the channel extends in several directions rather than in one direction, the influence caused by the directionality is offset in the manufacturing process, thereby reducing the influence of the process dispersion. Therefore, it is possible to prevent the degradation of image quality such as point defects (for example, brightness differences that occur depending on pixels, even when the same data voltage Dm is applied) that can occur due to the characteristics of the driving transistor T1, and the characteristics of the driving transistor T1 change according to the area of ​​the display device due to the process dispersion. The shape of the channel is not limited to the illustrated horseshoe shape (Ω shape), and the channel can have various shapes.

[0094] In a plan view, the first gate electrode 155 overlaps the channel. The first electrode S1 and the second electrode D1 are arranged at opposite sides of the channel. The extended portion of the storage line 126 is insulated and arranged on the first gate electrode 155. In a plan view, the extended portion of the storage line 126 overlaps the first gate electrode 155 to form a storage capacitor Cst, and the second gate insulating film is between the extended portion of the storage line 126 and the first gate electrode 155. The extended portion of the storage line 126 is the first storage electrode ( Figure 1 , and the first gate electrode 155 is a second storage electrode ( Figure 1 The extension portion of the storage line 126 is provided with an opening 56 so that the first gate electrode 155 can be connected to the first data connection member 71. In the opening 56, the upper surface of the first gate electrode 155 and the first data connection member 71 are electrically connected through the contact hole 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the first gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0095] The gate electrode of the second transistor T2 may be a portion of the first scan line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 may be disposed on the semiconductor layer 130.

[0096] The third transistor T3 may be configured by two transistors adjacent to each other. Figure 3In the pixel PX of FIG. 1 , the symbol T3 is illustrated at the left and lower sides relative to the bent portion of the semiconductor layer 130. The two parts are used as the third transistor T3, and the first electrode S3 of one third transistor T3 is connected to the second electrode D3 of the other third transistor T3. The gate electrodes of the two transistors T3 may be a part of the first scan line 151, or a part protruding upward from the first scan line 151. This structure may be regarded as a double-gate structure, and the leakage current may be blocked from flowing. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connecting member 71 through the contact hole 63.

[0097] The fourth transistor T4 includes two fourth transistors T4, and the two fourth transistors T4 are arranged at the position where the second scan line 152 and the semiconductor layer 130 intersect. The gate electrode of the fourth transistor T4 may be a part of the second scan line 152. The first electrode S4 of one fourth transistor T4 is connected to the second electrode D4 of another fourth transistor T4. This structure may be regarded as a double-gate structure and may be used to block leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0098] As described above, the third transistor T3 and the fourth transistor T4 may be provided to have a double gate structure to effectively prevent leakage current from being generated by blocking an electron moving path of a channel in an off state.

[0099] The gate electrode of the fifth transistor T5 may be a part of the light emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0100] The gate electrode of the sixth transistor T6 may be a part of the light emission control line 153. The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0101] The gate electrode of the seventh transistor T7 may be a portion of the second scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and the second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0102] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 overlapping each other, and a second gate insulating film 142 is between the first storage electrode E1 and the second storage electrode E2. The second storage electrode E2 corresponds to the first gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. Herein, the second gate insulating film 142 becomes a dielectric, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 as the second storage electrode E2, it is possible to ensure a space in which the storage capacitor Cst can be formed in a space that is narrowed due to the large area occupied by the channel of the driving transistor T1 in the pixel.

[0103] The driving voltage line 172 is connected to the first storage electrode E1 through the contact hole 68. Therefore, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the first gate electrode 155.

[0104] The second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64. An electrode referred to as a pixel electrode is connected to the third data connection member 73 through the contact hole 81.

[0105] The parasitic capacitor control pattern 79 may be arranged between the dual gate electrodes of the third transistor (also referred to as a "switching transistor") T3. A parasitic capacitor exists in the pixel, and the image quality characteristics may change when the voltage applied to the parasitic capacitor changes. The drive voltage line 172 is connected to the parasitic capacitor control pattern 79 through the contact hole 66. Therefore, the image quality characteristics may be prevented from changing by applying the drive voltage ELVDD, which is a constant direct current ("DC") voltage, to the parasitic capacitor. The parasitic capacitor control pattern 79 may be arranged in an area different from the area shown, and a voltage other than the drive voltage ELVDD may be applied.

[0106] One end of the first data connection member 71 is connected to the first gate electrode 155 through the contact hole 61 , and the other end of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63 .

[0107] One end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65 , and the other end of the second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64 .

[0108] The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69 .

[0109] Reference Figure 4 , the first layer 31 will be described in detail.

[0110] The light emitting diode display device in the exemplary embodiment includes a first layer 31. The first layer 31 may overlap a front surface of the substrate 110. The first layer 31 is disposed between the substrate 110 and a semiconductor layer 130 described later.

[0111] The first layer 31 includes a first region 31a and a second region 31b having conductivity. The first layer 31 may include: a first region 31a including a first material and a second region 31b including a second material. The first material and the second material may be different materials that can be distinguished from each other. The first layer 31 may include a semiconductor material. In an exemplary embodiment, the first material included in the first region 31a may include amorphous silicon doped with impurities, and the second material included in the second region 31b may include amorphous silicon. The impurities doped in the first region 31a may be a Group 5 element, and the first region 31a may be an n+ doped region.

[0112] The first region 31a may have a planar shape substantially the same as that of the first gate conductor. Impurities may be doped on the amorphous silicon layer by the same mask as that used in the process of forming the first gate conductor. Therefore, the impurity-doped first region 31a may have a shape substantially the same as that of the first gate conductor. The edge of the first region 31a may be substantially aligned with the edge of the first gate conductor.

[0113] exist Figure 3 , the first gate conductor is shown as a thick line. The first gate conductor may include a first gate electrode 155, a first scan line 151, a second scan line 152, and a light emitting control line 153.

[0114] The first region 31a includes at least one of a first sub-region 31a-1 overlapping the second scan line 152, a second sub-region 31a-2 overlapping the first scan line 151, a third sub-region 31a-3 overlapping the first gate electrode 155, and a fourth sub-region 31a-4 overlapping the light emitting control line 153. The first region 31a in an exemplary embodiment may include all of the first sub-region 31a-1 overlapping the second scan line 152, the second sub-region 31a-2 overlapping the first scan line 151, the third sub-region 31a-3 overlapping the first gate electrode 155, and the fourth sub-region 31a-4 overlapping the light emitting control line 153, but the present invention is not limited thereto, and the first region 31a may be modified by the configuration of the first gate conductor.

[0115] The first sub-region 31a-1 may have a planar shape substantially the same as that of the second scan line 152. Edges of the first sub-region 31a-1 and the second scan line 152 may be substantially aligned. Similar to the second scan line 152, the first sub-region 31a-1 may have a shape extending along the first direction D1.

[0116] The first sub-region 31 a - 1 may overlap the semiconductor layer 130 between the first electrode S4 and the second electrode D4 of the fourth transistor T4 and between the first electrode S7 and the second electrode D7 of the seventh transistor T7 .

[0117] The first sub-region 31a-1 may overlap the data line 171 and the driving voltage line 172 extending in the second direction D2. In addition, the first sub-region 31a-1 may overlap the second data connection member 72.

[0118] The second sub-region 31a-2 may have a planar shape substantially the same as that of the first scan line 151. Edges of the second sub-region 31a-2 and the first scan line 151 may be substantially aligned. Similar to the first scan line 151, the second sub-region 31a-2 may have a shape extending along the first direction D1, and a portion of the second sub-region 31a-2 may have a shape protruding along the second direction D2.

[0119] The second sub-region 31 a - 2 may overlap the semiconductor layer 130 between the first electrode S2 and the second electrode D2 of the second transistor T2 and between the first electrode S3 and the second electrode D3 of the third transistor T3 .

[0120] The second sub-region 31a-2 may overlap the data line 171 and the driving voltage line 172 extending in the second direction D2. In addition, the second sub-region 31a-2 may overlap the first data connection member 71.

[0121] The third sub-region 31a-3 may have substantially the same plan shape as that of the first gate electrode 155. Edges of the third sub-region 31a-3 and the first gate electrode 155 may be substantially aligned.

[0122] The third sub-region 31a-3 may overlap the semiconductor layer 130 forming the first transistor T1. The third sub-region 31a-3 may overlap the first and second electrodes S1 and D1 of the first transistor T1 and a channel disposed between the first and second electrodes S1 and D1 of the first transistor T1.

[0123] In addition, the third sub-region 31 a - 3 may overlap the driving voltage line 172 extending in the second direction D2 , and may overlap a portion of the first data connection member 71 .

[0124] The fourth subregion 31a-4 may have substantially the same planar shape as that of the light emission control line 153. Edges of the fourth subregion 31a-4 and the light emission control line 153 may be substantially aligned. Similar to the light emission control line 153, the fourth subregion 31a-4 may have a shape extending along the first direction D1.

[0125] The fourth sub-region 31 a - 4 may overlap the semiconductor layer 130 between the first electrode S5 and the second electrode D5 of the fifth transistor T5 and between the first electrode S6 and the second electrode D6 of the sixth transistor T6 .

[0126] In addition, the fourth sub-region 31 a - 4 may overlap the data line 171 and the driving voltage line 172 extending in the second direction D2 , and may overlap a portion of the third data connection member 73 .

[0127] In the following, except Figure 5 In addition, reference will be made to Figure 3 and Figure 4 An exemplary embodiment of a cross-sectional structure of a light emitting diode display device is described.

[0128] The light emitting diode display device in the exemplary embodiment includes a substrate 110 .

[0129] The substrate 110 may include a plastic layer and a barrier layer, and the plastic layer and the barrier layer may be alternately stacked.

[0130] In an exemplary embodiment, the plastic layer may include at least one of polyethersulfone ("PES"), polyacrylate ("PAR"), polyetherimide ("PEI"), polyimide, polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyarylate, polyimide ("PI"), polycarbonate ("PC"), poly(arylene ether sulfone) and combinations thereof.

[0131] The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide, but is not limited thereto, and may include any inorganic material.

[0132] The adhesive layer 111 is disposed on the substrate 110. The adhesive layer 111 may be provided for bonding the substrate 110 and the first layer 31, and in another exemplary embodiment, the adhesive layer 111 may be omitted.

[0133] The first layer 31 is disposed on the adhesive layer 111. The first layer 31 includes a first region 31a and a second region 31b having conductivity.

[0134] The thickness of the first region 31a may become smaller toward the end of the first region 31a. Figure 5As shown in , an end portion of the first region 31 a may have an inclined shape with respect to one surface of the substrate 110 .

[0135] Because the above reference Figure 4 Other descriptions of the first layer 31 are given, so a detailed description of the first layer 31 will be omitted below.

[0136] The buffer layer 112 is disposed on the first layer 31. In exemplary embodiments, the buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide, or may include an organic insulating material such as polyimide acrylate.

[0137] A semiconductor layer 130 including channels of a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , a first electrode, and a second electrode is disposed on the buffer layer 112 .

[0138] The first gate insulating film 141 is disposed on the semiconductor layer 130. A first gate conductor including a first gate electrode 155, a first scan line 151, a second scan line 152, and a light emission control line 153 is disposed on the first gate insulating film 141.

[0139] In an exemplary embodiment, the first gate conductor and the first region 31a may have substantially the same planar shape. An end of the first region 31a may be aligned with an end of the first gate conductor. In a plan view, the first region 31a and the first gate conductor may completely overlap each other.

[0140] A second gate insulating film 142 covering the first gate conductor is disposed on the first gate conductor. In exemplary embodiments, the first and second gate insulating films 141 and 142 may include an inorganic insulating material such as silicon nitride, silicon oxide, or aluminum oxide, or may include an organic insulating material.

[0141] A second gate conductor including a storage line 126 , an initialization voltage line 127 , and a parasitic capacitor control pattern 79 is disposed on the second gate insulating film 142 .

[0142] An interlayer insulating film 160 covering the second gate conductor is disposed on the second gate conductor. In exemplary embodiments, the interlayer insulating film 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, or aluminum oxide, or may include an organic insulating material.

[0143] Data conductors including data lines 171, driving voltage lines 172, first, second and third data connection members 71, 72 and 73 are disposed on the interlayer insulating film 160. The first data connection member 71 may be connected to the first gate electrode 155 through the contact hole 61.

[0144] A passivation film 180 covering the data conductor is disposed on the data conductor. In an exemplary embodiment, the passivation film 180 may be a planarization film, and may include an organic insulating material or an inorganic insulating material.

[0145] The pixel electrode 191 is disposed on the passivation film 180 . The pixel electrode 191 is connected to the third data connection member 73 through a contact hole 81 defined in the passivation film 180 .

[0146] The partition wall 350 is disposed on the passivation film 180 and the pixel electrode 191. The partition wall 350 has an opening 351 overlapping the pixel electrode 191. The light emitting layer 370 is disposed in the opening 351. The common electrode 270 is disposed on the light emitting layer 370 and the partition wall 350. The pixel electrode 191, the light emitting layer 370 and the common electrode 270 form a light emitting diode LED.

[0147] In some exemplary embodiments, the pixel electrode may be an anode as a hole injection electrode, and the common electrode may be a cathode as an electron injection electrode. Conversely, the pixel electrode may be a cathode, and the common electrode may be an anode. When holes and electrons are injected into the light-emitting layer from the pixel electrode and the common electrode, respectively, light is emitted when the excitons of the injected holes and electrons recombined therein enter the ground state from the excited state.

[0148] An encapsulation layer 400 for protecting the light emitting diode LED is disposed on the common electrode 270. The encapsulation layer 400 may contact the common electrode 270 as shown, and in some exemplary embodiments, it may be spaced apart from the common electrode 270.

[0149] The encapsulation layer 400 may be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and may include three layers including an inorganic film, an organic film, and an inorganic film. In some exemplary embodiments, a capping layer and a functional layer may be disposed between the common electrode 270 and the encapsulation layer 400 .

[0150] In the following, reference will be made to Figure 6 and Figure 7 Exemplary embodiments of a light emitting diode display device are described. Figure 6 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is shown, and Figure 7 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0151] Description of constituent elements that are the same as or similar to those of the above-described exemplary embodiment will be omitted.

[0152] Reference Figure 6, the maximum thickness ta of the first region 31a in the first layer 31 may be less than the maximum thickness t1 of the first layer 31. The first region 31a may be provided by doping only a portion of the first layer 31 with impurities in the thickness direction D3. The first region 31a may be provided by adjusting the doping depth of the impurities doped in the first layer 31.

[0153] Reference Figure 7 , the first regions 31a may have substantially the same thickness. The thickness ta of the first regions 31a and the thickness t1 of the first layer 31 may be the same. In addition, in an exemplary embodiment, the first regions 31a may have a uniform thickness. The end of the first region 31a may be aligned with the end of the first gate conductor.

[0154] In the following, reference will be made to Figures 8 to 10 Exemplary embodiments of a light emitting diode display device are described. Figure 8 A plan view illustrating an exemplary embodiment of a partial area of ​​a light emitting diode display device, Fig. 9 A plan view of an exemplary embodiment of a first layer is shown, and Fig.10 The diagram is along Figure 8 Description of constituent elements that are the same as or similar to those of the above-described exemplary embodiment will be omitted.

[0155] exist Figure 8 , a region where the second gate conductor is arranged is indicated by a bold line. The second gate conductor may include a storage line 126 including a first storage electrode, an initialization voltage line 127, and a parasitic capacitor control pattern 79.

[0156] like Fig. 9 As shown in , the first layer 31 includes a first region 31a and a second region 31b having conductivity. The first layer 31 may include a semiconductor material, and for example, the first region 31a may include amorphous silicon doped with impurities, and the second region 31b may include amorphous silicon. The second region 31b may also include some impurities, but the concentration of the impurities doped in the first region 31a may be greater than the concentration of the impurities doped in the second region 31b. The first region 31a may have a conductivity similar to that of a metal.

[0157] The first region 31a may have a planar shape substantially the same as that of the second gate conductor. The first region 31a may be provided by the same mask as that used in the process of forming the second gate conductor. Specifically, the first region 31a having a planar shape substantially the same as that of the second gate conductor may be provided by arranging the mask used in the process of forming the second gate conductor on the amorphous silicon layer and doping impurities.

[0158] The first region 31a includes at least one of a fifth sub-region 31a-5 overlapping the initialization voltage line 127, a sixth sub-region 31a-6 overlapping the parasitic capacitor control pattern 79, and a seventh sub-region 31a-7 overlapping the storage line 126. Herein, an exemplary embodiment in which the first region 31a includes all of the fifth sub-region 31a-5 overlapping the initialization voltage line 127, the sixth sub-region 31a-6 overlapping the parasitic capacitor control pattern 79, and the seventh sub-region 31a-7 overlapping the storage line 126 is illustrated, but the present invention is not limited thereto, and the first region 31a may be modified by the configuration of the second gate conductor.

[0159] The fifth subregion 31a-5 may have substantially the same planar shape as the initialization voltage line 127. Edges of the fifth subregion 31a-5 and the initialization voltage line 127 may be substantially aligned. Similar to the initialization voltage line 127, the fifth subregion 31a-5 may have a shape extending along the first direction D1.

[0160] The fifth sub-region 31 a - 5 may overlap the semiconductor layer 130 between the first electrode S4 and the second electrode D4 of the fourth transistor T4 , and may overlap the first electrode S7 of the seventh transistor T7 .

[0161] The fifth sub-region 31a-5 may overlap the data line 171 and the driving voltage line 172 extending in the second direction D2. In addition, the fifth sub-region 31a-5 may partially overlap the second data connection member 72.

[0162] The sixth sub-region 31a-6 may have a plan shape substantially the same as that of the parasitic capacitor control pattern 79. Edges of the sixth sub-region 31a-6 and the parasitic capacitor control pattern 79 may be substantially aligned.

[0163] The sixth subregion 31a-6 may overlap the data line 171 and the driving voltage line 172 extending along the second direction D2. In addition, in the semiconductor layer 130, the sixth subregion 31a-6 may overlap a portion of the third transistor T3, the first electrode S2 of the second transistor T2, and the second electrode D4 of the fourth transistor T4.

[0164] The seventh subregion 31a-7 may have substantially the same planar shape as that of the storage line 126. Edges of the seventh subregion 31a-7 and the storage line 126 may be substantially aligned. Similar to the storage line 126, the seventh subregion 31a-7 may extend along the first direction D1 and may include an extension region and a removal region.

[0165] The seventh subregion 31a-7 may overlap the data line 171 and the driving voltage line 172 extending along the second direction D2. Also, the seventh subregion 31a-7 may overlap the first data connection member 71 and the first gate electrode 155. The seventh subregion 31a-7 may overlap the first transistor T1.

[0166] In the following, additional reference will be made to Fig.10 1 and 2. The cross-sectional structure of the first layer 31 will be described below. Description of the same configuration as that described above will be omitted.

[0167] The first layer 31 is disposed on the adhesive layer 111. The first layer 31 includes a first region 31a and a second region 31b having conductivity.

[0168] The thickness of the first region 31a may become smaller toward the end of the first region 31a. Fig.10 As shown in , an end portion of the first region 31 a may have an inclined shape with respect to one surface of the substrate 110 .

[0169] In an exemplary embodiment, the second gate conductor and the first region 31a may have substantially the same planar shape. An end portion of the first region 31a may be aligned with an end portion of the second gate conductor.

[0170] In the following, reference will be made to Fig.11 and Fig.12 Exemplary embodiments of a light emitting diode display device are described. Fig.11 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is shown, and Fig.12 A cross-sectional view illustrating an exemplary embodiment of a light emitting diode display device is illustrated.

[0171] Reference Fig.11 , the maximum thickness ta of the first region 31a in the first layer 31 may be less than the maximum thickness t1 of the first layer 31. The first region 31a may be provided by doping only a portion of the first layer 31 with impurities in the thickness direction D3 of the first layer 31. The first region 31a thinner than the first layer 31 may be provided by adjusting the doping depth of the first region 31a.

[0172] Reference Fig.12 , the first region 31a may have a thickness substantially the same as that of the first layer 31. The first region 31a may have a substantially uniform thickness. An end of the first region 31a may be perpendicular to the substrate 110. The end of the first region 31a having a vertical shape may be aligned with an end of the second gate conductor.

[0173] In the following, reference will be made to Figures 13 to 15 Exemplary embodiments of a light emitting diode display device are described. Fig.13 , Fig.14 and Fig.15Schematic plan views of exemplary embodiments of a light emitting diode display device are respectively illustrated. Description of constituent elements that are the same as or similar to those of the above-described exemplary embodiments will be omitted.

[0174] Reference Fig.13 The substrate 110 includes a display area DA including a light emitting diode and a peripheral area PA surrounding the display area DA. In an exemplary embodiment, the first region 31a arranged in the display area DA may extend in the first direction D1 to be arranged in the peripheral area PA.

[0175] The first region 31a disposed in the peripheral area PA may be connected to the signal line SL disposed in the same layer or another layer and may be connected through a contact hole. The signal line SL is disposed in the peripheral area PA and may connect ends of the first region 31a to each other.

[0176] The signal line SL may be connected to the pad and to a power source or ground. A predetermined voltage may be applied to the first region 31a through the signal line SL. In the specification, a configuration is illustrated in which the pad is arranged in a region parallel to the long side of the display device, but the present invention is not limited thereto, and the pad may be arranged in a region parallel to the short side of the display device.

[0177] In an exemplary embodiment, the first region 31 a may receive the driving voltage ELVDD, but is not limited thereto, and for example, the first region 31 a may receive the common voltage ELVSS, a data voltage, a gate voltage, or another constant voltage.

[0178] The threshold voltage Vth of the channel of the transistor overlapping with the first region 31a (see Figure 1 ) can be shifted according to the voltage applied to the first region 31a. When the applied voltage is the driving voltage ELVDD and when the applied voltage is the initialization voltage Vint, the threshold voltage Vth of the transistor can be shifted in the opposite direction. Therefore, the transistor can be compensated by applying various voltages to the first region 31a according to the characteristics of the transistor to be compensated by utilizing this characteristic. In addition, the voltage applied to the first region 31a can be determined by considering whether the channel of the transistor is p-type or n-type.

[0179] Specifically, refer to Fig.14 , the first sub-region 31a-1 overlapping the second scan line 152 may extend along the first direction D1 and may extend to the peripheral area PA arranged outside the display area DA. In this case, the first sub-region 31a-1 arranged in the peripheral area PA may be connected to the signal line SL through the first contact hole CNT1.

[0180] The signal line SL can be as shown in Fig.13The first sub-region 31a-1 is connected to the signal line SL at both ends of the first sub-region 31a-1, but the present invention is not limited thereto, and the first sub-region 31a-1 may be connected to the signal line SL only at any one end of the first sub-region 31a-1.

[0181] The second sub-region 31a-2 overlapping the first scan line 151 may extend along the first direction D1 and may extend to the peripheral area PA arranged outside the display area DA. In this case, the second sub-region 31a-2 arranged in the peripheral area PA may be connected to the signal line SL for applying a predetermined voltage through the second contact hole CNT2.

[0182] The fourth sub-region 31a-4 overlapping the light emitting control line 153 may extend along the first direction D1 and may extend to the peripheral area PA arranged outside the display area DA. In this case, the fourth sub-region 31a-4 arranged in the peripheral area PA may be connected to the signal line SL for applying a predetermined voltage through the third contact hole CNT3.

[0183] In addition, the third sub-region 31a-3 overlapping the first gate electrode 155 may have an island shape. The plurality of third sub-regions 31a-3 may not be connected to each other and may not extend to the peripheral area PA. The plurality of third sub-regions 31a-3 may not be directly supplied with separate voltages.

[0184] The plurality of pixels PX may be repeatedly arranged along the first direction D1 and the second direction D2, and in the specification, although only one row PX1 in which the plurality of pixels PX are repeatedly arranged along the first direction D1 is shown, the plurality of pixels PX may be repeatedly arranged in the second direction D2.

[0185] Reference Fig.15 , the fifth sub-region 31a-5 overlapping the initialization voltage line 127 may extend along the first direction D1, and may cross the display area DA to extend to the peripheral area PA arranged outside the display area DA. In this case, the fifth sub-region 31a-5 arranged in the peripheral area PA may be connected to the signal line SL for applying a predetermined voltage through the fourth contact hole CNT4.

[0186] The seventh sub-region 31a-7 overlapping the storage line 126 may extend along the first direction D1, and may cross the display area DA to extend to the peripheral area PA arranged outside the display area DA. In this case, the seventh sub-region 31a-7 arranged in the peripheral area PA may be connected to the signal line SL for applying a predetermined voltage through the fifth contact hole CNT5.

[0187] The sixth sub-region 31a-6 overlapping the parasitic capacitor control pattern 79 may have an island shape. The plurality of sixth sub-regions 31a-6 may not be connected to each other and may not extend to the peripheral area PA. The sixth sub-region 31a-6 may not be directly supplied with a separate voltage.

[0188] Even in Fig.15 In an exemplary embodiment, a plurality of pixels PX may be repeatedly arranged along the first direction D1 and the second direction D2, and in the specification, although only one row PX1 in which a plurality of pixels PX are repeatedly arranged along the first direction D1 is shown, a plurality of pixels PX may be repeatedly arranged in the second direction D2.

[0189] In the following, reference will be made to Figures 16 to 21 An exemplary embodiment of a method of manufacturing a light emitting diode display device is described. Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 Cross-sectional views of a light emitting diode display device according to manufacturing processes are respectively illustrated. Description of constituent elements that are the same as or similar to those of the above-described exemplary embodiment will be omitted.

[0190] Reference Fig.16 , the adhesive layer 111 is disposed on the substrate 110, and the amorphous silicon layer 30 is disposed on the adhesive layer 111. The amorphous silicon layer 30 may overlap with the front surface of the substrate 110.

[0191] The substrate 110 may include plastic layers 110a and 110c and a barrier layer 110b. The plastic layers 110a and 110c and the barrier layer 110b may be alternately stacked.

[0192] Then, if Fig.17 As shown in FIG. 1 , a photosensitive resin composition PR is coated on the amorphous silicon layer 30 and is exposed using a mask MASK for a gate conductor. In this case, the photosensitive resin composition PR may be a negative photosensitive resin composition.

[0193] Then, if Fig.18As shown in , a patterned photosensitive resin layer PR1 is provided. The patterned photosensitive resin layer PR1 may be provided by developing the exposed photosensitive resin composition PR. Fig.17 In the process, the photosensitive resin composition arranged in the area not overlapping with the mask MASK is cured to form Fig.18 The patterned photosensitive resin layer PR1.

[0194] Subsequently, the first layer 31 including the first region 31a and the second region 31b is provided using the patterned photosensitive resin layer PR1 as a mask. The first region 31a may be a region that does not overlap with the patterned photosensitive resin layer PR1 and is doped with impurities. The second region 31b overlaps with the patterned photosensitive resin layer PR1 and includes amorphous silicon that is not doped with impurities.

[0195] Thereafter, the patterned photosensitive resin layer PR1 is removed.

[0196] Then, if Fig.19 As shown in FIG. 1 , a buffer layer 112, a semiconductor layer 130, and a first gate insulating film 141 are sequentially arranged on the first layer 31. In addition, a first metal layer 150 is stacked on the first gate insulating film 141. The first metal layer 150 is a layer for forming a first gate conductor and may overlap with the front surface of the substrate 110.

[0197] Then, if Fig. 20 As shown in FIG. , the second photosensitive resin pattern PR2 is formed by Fig.17 The mask MASK used in is arranged on the first metal layer 150 .

[0198] The second photosensitive resin pattern PR2 may be provided by coating a photosensitive resin composition, exposing it using a mask MASK, and developing it. In this case, the photosensitive resin composition may be a positive photosensitive resin composition, and a portion of the photosensitive resin composition exposed by the mask MASK may be removed.

[0199] Subsequently, the exposed first metal layer 150 may be etched using the second photosensitive resin pattern PR2 to form a Fig.21 The light emitting control line 153 and the first gate electrode 155 of the first gate conductor shown in FIG. In an exemplary embodiment, the mask used in the process of forming the first gate conductor and the first region may be the same mask. The process may be simplified and the process cost may be reduced.

[0200] Subsequently, in an exemplary embodiment, the remaining components are stacked to be able to provide a light emitting diode display device.

[0201] In an exemplary embodiment, a mask used in a process of forming a first gate conductor or a second gate conductor can be used to form a first layer including a first region and a second region. Therefore, the number of masks used in the manufacturing process does not increase, and thus the process can be simplified. In addition, a first region in which impurities are not doped in a region overlapping with the front side of the substrate and impurities are doped only in a region that requires partial blocking can be provided. By including such a first layer, a transistor with excellent performance and a light-emitting diode display device with an afterimage improvement effect can be provided.

[0202] While the invention has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A light emitting diode display device, comprising: substrate; a first layer disposed on the substrate; a first transistor disposed on the first layer and comprising a first gate electrode; as well as a light emitting diode electrically connected to the first transistor, wherein: the first layer overlaps with the first gate electrode and comprises: a first region comprising a first material and a second region comprising a second material different from the first material, The first material includes amorphous silicon doped with impurities, and the second material includes amorphous silicon.

2. The light emitting diode display device according to claim 1, further comprising: a first gate conductor disposed on the first layer, Wherein: the first gate conductor includes a first scan line, a second scan line, a light emitting control line and the first gate electrode.

3. The light emitting diode display device according to claim 2, wherein: The first region has the same planar shape as that of the first gate conductor.

4. The light emitting diode display device according to claim 2, wherein: The first region includes at least one of the following: a first sub-area overlapping with the second scan line, a second sub-area overlapping the first scan line, a third sub-region overlapping the first gate electrode, and A fourth sub-area overlapping the light emitting control line, wherein: The first sub-region, the second sub-region, and the fourth sub-region extend along a first direction.

5. The light emitting diode display device according to claim 1, wherein: The light emitting diode display device includes a second gate conductor arranged on the first layer, and The second gate conductor includes a parasitic capacitor control pattern, a storage line, and an initialization voltage line.

6. The light emitting diode display device according to claim 5, wherein: The first region has the same planar shape as that of the second gate conductor.

7. The light emitting diode display device according to claim 5, wherein: The first region includes at least one of the following: a first sub-region overlapping the initialization voltage line, a second sub-region overlapping the parasitic capacitor control pattern, and a third sub-area overlapping the storage line, in: The first sub-region and the third sub-region extend along a first direction.

8. The light emitting diode display device according to claim 1, wherein: The first region overlaps the first transistor.

9. The light emitting diode display device according to claim 1, wherein: A driving voltage is applied to the first region.

10. The light emitting diode display device according to claim 1, wherein: The thickness of the first region decreases toward an end of the first region.

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