MOS tube output current circuit for low voltage electric drive power calculation

Abstract

The present invention discloses a MOS transistor output current circuit for low-voltage electric drive power calculation, comprising a first level signal input terminal, a first driver module, a first switch module, a second level signal input terminal, a second driver module, a second switch module, a high voltage blocking module, a first output terminal, and a second output terminal. The present invention increases the voltage signal output to the MCU as the inverter output signal increases. Based on the relationship between the MOS transistor and the output current, the MCU can calculate the output current at that time using the voltage signal output to the MCU. Simultaneously, the PWM output high and low levels can be controlled to protect the MOS transistor from damage due to overcurrent. This eliminates the need for a voltage-type current sensor or the use of a shunt, saving design space and reducing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS tube output current circuits for calculating power, and more specifically to a MOS tube output current circuit for calculating power with a low-voltage electric drive. Background Art

[0002] Currently, in 48-72V voltage electric drives, whether using voltage-type current sensors or shunt sampling, they both account for a considerable cost proportion in the market. However, the above solutions all have the problems of large design space and high cost. Summary of the Invention

[0003] The purpose of the present invention is to overcome the defects of the prior art and provide a MOS tube output current circuit for low-voltage electric drive calculation power.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] A MOS tube output current circuit for low-voltage electric drive power calculation includes a first level signal input terminal, a first drive module, a first switch module, a second level signal input terminal, a second drive module, a second switch module, a high voltage blocking module, a first output terminal, and a second output terminal; the first level signal input terminal is connected to the first drive module and the high voltage blocking module, the first switch module is connected to the first drive module, the second level signal input terminal is connected to the second drive module, the second switch module is connected to the second drive module, the first output terminal and the high voltage blocking module are both connected to the first switch module and the second switch module, and the second output terminal is connected to the high voltage blocking module.

[0006] Its further technical solution is: the first driving module includes a voltage input terminal, a capacitor C1, a capacitor C2, a diode D1, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a transistor Q1, a transistor Q2, a transistor Q3, and a transistor Q4; pin 1 of the capacitor C1, pin 1 of the capacitor C2, and an anode of the diode D1 are all connected to the voltage input terminal, pin 2 of the capacitor C1 and pin 2 of the capacitor C2 are grounded, the cathode of the diode D1 is connected to pin 1 of the capacitor C3, pin 2 of the resistor R3, pin 1 of the resistor R4, the collector of the transistor Q1, and the emitter of the transistor Q3, pin 2 of the capacitor C3 and pin 1 of the resistor R3 are grounded; pin 2 of the resistor R4 and the transistor Q3 are connected The bases of the transistors are all connected to the first level signal input end, the collector of the transistor Q3 is connected to the base of the transistor Q1, pin 2 of the resistor R8, and the base of the transistor Q4, and pin 1 of the resistor R8 and the collector of the transistor Q4 are grounded; the emitter of the transistor Q1 is connected to pin 2 of the resistor R1, pin 1 of the resistor R1 is connected to pin 2 of the resistor R5, the emitter of the transistor Q2, pin 2 of the capacitor C4, pin 2 of the resistor R6, and pin 1 of the resistor R2, the emitter of the transistor Q4 is connected to pin 1 of the resistor R5, and the base of the transistor Q2; the collector of the transistor Q2, pin 1 of the capacitor C4, and pin 1 of the resistor R6 are all grounded; pin 2 of the resistor R2 is connected to pin 1 of the resistor R7 and the first switch module, pin 2 of the resistor R7 is connected to pin 1 of the capacitor C5, and pin 2 of the capacitor C5 is grounded.

[0007] A further technical solution is: the model of the diode D1 is BAV21W.

[0008] Its further technical solution is: the first switch module is an insulated gate bipolar transistor M1, the gate of the insulated gate bipolar transistor M1 is connected to pin 2 of the resistor R2 and pin 1 of the resistor R7, the emitter of the insulated gate bipolar transistor M1 is connected to the positive electrode of the battery, and the collector of the insulated gate bipolar transistor M1 is connected to the second switch module, the high voltage blocking module, and the first output end.

[0009] Its further technical solution is: the second driving module includes a voltage input terminal, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a transistor Q5, a transistor Q7, a transistor Q8, and a transistor Q9; pin 1 of the capacitor C6, pin 2 of the capacitor C7, pin 1 of the resistor R11, the collector of the transistor Q5, and the emitter of the transistor Q7 are all connected to the voltage input terminal, pin 2 of the capacitor C6 and pin 1 of the capacitor C7 are grounded, the second level signal input terminal is connected to pin 2 of the resistor R11 and the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q5, Pin 2 of the resistor R15 is connected to the base of the transistor Q9, and pin 1 of the resistor R15 is grounded; the collector of the transistor Q9 is grounded, the emitter of the transistor Q9 is connected to pin 2 of the resistor R12 and the base of the transistor Q8, the collector of the transistor Q8 is grounded, the emitter of the transistor Q5 is connected to pin 1 of the resistor R9, pin 2 of the resistor R9 is connected to pin 1 of the resistor R12, the emitter of the transistor Q8, pin 1 of the capacitor C8, pin 1 of the resistor R14, and pin 1 of the resistor R10, pin 2 of the capacitor C8 and pin 2 of the resistor R14 are grounded, pin 2 of the resistor R10 is connected to pin 1 of the resistor R13 and the second switch module, pin 2 of the resistor R13 is connected to pin 1 of the capacitor C9, and pin 2 of the capacitor C9 is grounded.

[0010] A further technical solution is as follows: the transistors Q1, Q2, Q3, Q4, Q5, Q7, Q8, and Q9 are of the same model, SS8550.

[0011] Its further technical solution is: the second switch module is an insulated gate bipolar transistor M2, the gate of the insulated gate bipolar transistor M2 is connected to pin 2 of the resistor R10 and pin 1 of the resistor R13, the collector of the insulated gate bipolar transistor M2 is connected to the negative electrode of the battery, and the emitter of the insulated gate bipolar transistor M1 is connected to the collector of the insulated gate bipolar transistor M1, the high voltage blocking module, and the first output end.

[0012] A further technical solution is as follows: the insulated gate bipolar transistor M1 and the insulated gate bipolar transistor M2 are of the same model, CRST045N10N.

[0013] A further technical solution is as follows: the high-voltage blocking module includes a MOS transistor Q6, a MOS transistor Q10, a resistor R16, and a capacitor C10; the drain of the MOS transistor Q6 is connected to the collector of the insulated gate bipolar transistor M1 and the emitter of the insulated gate bipolar transistor M2, the source of the MOS transistor Q6 is connected to the source of the MOS transistor Q10, the first level signal input terminal is connected to the gate of the MOS transistor Q6 and the gate of the MOS transistor Q10, the drain of the MOS transistor Q10 is connected to pin 1 of the resistor R16, pin 1 of the capacitor C10, and the second output terminal, and pin 2 of the resistor R16 and pin 2 of the capacitor C10 are grounded.

[0014] Its further technical solution is as follows: the first level signal input end is PWM_U+ signal; the second level signal input end is PWM_U- signal; the first output end is an inverter output signal for connecting to a motor; the second output end is a voltage signal output to the MCU; when the PWM_U+ signal and the PWM_U- signal are high level, the transistors Q3 and Q1 are turned off, the transistors Q4 and Q2 are turned on, the gate of the insulated gate bipolar transistor M1 is low level, so the insulated gate bipolar transistor M1 is turned off, and the transistors Q7 and Q5 are turned on. When the PWM_U+ signal is low and the PWM_U- signal is high, transistors Q3 and Q1 are turned on, transistors Q4 and Q2 are turned off, and the gate of the insulated gate bipolar transistor M1 is low, so the insulated gate bipolar transistor M2 is turned off. At this time, MOS tube Q6 is turned on, MOS tube Q10 is turned on inverted, and the voltage signal output to the MCU is 0 voltage; when the PWM_U+ signal is low and the PWM_U- signal is high, transistors Q3 and Q1 are turned on, transistors Q4 and Q2 are turned off, and the gate of the insulated gate bipolar transistor M1 is low and high, so the insulated gate bipolar transistor M1 is turned on, and transistor Q 7 and transistor Q5 are turned off, transistor Q9 and transistor Q8 are turned on, the gate of the insulated gate bipolar transistor M2 is low level, so the insulated gate bipolar transistor M2 is cut off, at this time MOS tube Q6 is cut off, MOS tube Q10 is cut off, and the voltage signal output to the MCU is 0 voltage; when the PWM_U+ signal is high level and the PWM_U- signal is low level, transistor Q3 and transistor Q1 are cut off, transistor Q4 and transistor Q2 are turned on, the gate of the insulated gate bipolar transistor M1 is low level, so the insulated gate bipolar transistor M1 is cut off , transistors Q7 and Q5 are turned on, transistors Q9 and Q8 are turned off, and the gate of the insulated gate bipolar transistor M2 is at a low high level, so the insulated gate bipolar transistor M1 is turned on. As the output current of the insulated gate bipolar transistor M2 increases, the inverter output signal increases. At this time, the MOS tube Q6 is turned on, and the MOS tube Q10 is turned on inverted. The voltage signal output to the MCU increases as the inverter output signal increases. According to the relationship between the MOS tube and the output current, the MCU can calculate the output current at this time through the voltage signal output to the MCU.

[0015] Compared with the prior art, the present invention has the following advantages: the voltage signal output to the MCU increases as the inverter output signal increases. According to the relationship between the MOS tube and the output current, the MCU can calculate the output current at this time through the voltage signal output to the MCU. At the same time, the high and low levels of the PWM output can be controlled to protect the MOS tube from damage due to overcurrent. The voltage-type current sensor or the use of a shunt is eliminated, which saves design space and reduces costs.

[0016] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram of a MOS tube output current circuit for calculating power of a low-voltage electric drive according to the present invention;

[0018] Figure 2 This is a specific circuit diagram of the MOS tube output current circuit for calculating power of the low-voltage electric drive of the present invention. DETAILED DESCRIPTION

[0019] To illustrate the concept and purpose of the present invention, the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0022] In addition, in the present invention, descriptions such as "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] like Figures 1 to 2 The specific embodiment shown, wherein Figure 1 As shown, a block diagram of a MOS tube output current circuit for calculating power of a low-voltage electric drive according to the present invention includes a first level signal input terminal 10, a first driving module 20, a first switch module 30, a second level signal input terminal 40, a second driving module 50, a second switch module 60, a high voltage blocking module 70, a first output terminal 80, and a second output terminal 90; the first level signal input terminal 10 is connected to the first driving module 20 and the high voltage blocking module 70, the first switch module 30 is connected to the first driving module 20, the second level signal input terminal 40 is connected to the second driving module 50, the second switch module 60 is connected to the second driving module 50, the first output terminal 80 and the high voltage blocking module 70 are both connected to the first switch module 30 and the second switch module 60, and the second output terminal 90 is connected to the high voltage blocking module 70.

[0024] Specifically, if Figure 2As shown, the first driving module 20 includes a voltage input terminal (in this embodiment, a voltage of +15V is provided to provide the voltage required to drive the MOS tube), a capacitor C1, a capacitor C2, a diode D1, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a transistor Q1, a transistor Q2, a transistor Q3, and a transistor Q4; pin 1 of the capacitor C1, pin 1 of the capacitor C2, and an anode of the diode D1 are all connected to the voltage input terminal, pin 2 of the capacitor C1 and pin 2 of the capacitor C2 are grounded, a cathode of the diode D1 is connected to pin 1 of the capacitor C3, pin 2 of the resistor R3, pin 1 of the resistor R4, the collector of the transistor Q1, and the emitter of the transistor Q3, and pin 2 of the capacitor C3 and pin 1 of the resistor R3 are grounded; Pin 2 of resistor R4 and the base of transistor Q3 are both connected to the first level signal input end, the collector of transistor Q3 is connected to the base of transistor Q1, pin 2 of resistor R8, and the base of transistor Q4, and pin 1 of resistor R8 and the collector of transistor Q4 are grounded; the emitter of transistor Q1 is connected to pin 2 of resistor R1, pin 1 of resistor R1 is connected to pin 2 of resistor R5, the emitter of transistor Q2, pin 2 of capacitor C4, pin 2 of resistor R6, and pin 1 of resistor R2, the emitter of transistor Q4 is connected to pin 1 of resistor R5 and the base of transistor Q2; the collector of transistor Q2, pin 1 of capacitor C4, and pin 1 of resistor R6 are all grounded; pin 2 of resistor R2 is connected to pin 1 of resistor R7 and the first switch module, pin 2 of resistor R7 is connected to pin 1 of capacitor C5, and pin 2 of capacitor C5 is grounded.

[0025] In this embodiment, the diode D1 is of type BAV21W and is used to provide a stable voltage.

[0026] Specifically, if Figure 2 As shown, the first switch module 30 is an insulated gate bipolar transistor M1, and the gate of the insulated gate bipolar transistor M1 (corresponding to Figure 2 Pin 1 of the resistor R2 is connected to Pin 2 of the resistor R2 and Pin 1 of the resistor R7. The emitter of the insulated gate bipolar transistor M1 (corresponding to Figure 2 Pin 2 in the diagram) is connected to the positive terminal of the battery, and the collector of the insulated gate bipolar transistor M1 (corresponding to Figure 2 Pin 3 in the circuit) is connected to the second switch module, the high voltage blocking module, and the first output terminal.

[0027] Specifically, if Figure 2As shown, the second driving module 50 includes a voltage input terminal (in this embodiment, a voltage of +15V is provided to provide the voltage required to drive the MOS tube), a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a transistor Q5, a transistor Q7, a transistor Q8, and a transistor Q9; pin 1 of the capacitor C6, pin 2 of the capacitor C7, pin 1 of the resistor R11, the collector of the transistor Q5, and the emitter of the transistor Q7 are all connected to the voltage input terminal, pin 2 of the capacitor C6 and pin 1 of the capacitor C7 are grounded, the second level signal input terminal is connected to pin 2 of the resistor R11 and the base of the transistor Q7, and the pin 1 of the transistor Q7 is connected to the base of the transistor Q7. The collector is connected to the base of the transistor Q5, pin 2 of the resistor R15, and the base of the transistor Q9, and pin 1 of the resistor R15 is grounded; the collector of the transistor Q9 is grounded, the emitter of the transistor Q9 is connected to pin 2 of the resistor R12 and the base of the transistor Q8, the collector of the transistor Q8 is grounded, the emitter of the transistor Q5 is connected to pin 1 of the resistor R9, pin 2 of the resistor R9 is connected to pin 1 of the resistor R12, the emitter of the transistor Q8, pin 1 of the capacitor C8, pin 1 of the resistor R14, and pin 1 of the resistor R10, pin 2 of the capacitor C8 and pin 2 of the resistor R14 are grounded, pin 2 of the resistor R10 is connected to pin 1 of the resistor R13 and the second switch module, pin 2 of the resistor R13 is connected to pin 1 of the capacitor C9, and pin 2 of the capacitor C9 is grounded.

[0028] Among them, the transistors Q1, Q2, Q3, Q4, Q5, Q7, Q8, and Q9 are of the same model, all SS8550, which is a low-voltage, high-current, small-signal PNP silicon transistor.

[0029] Specifically, if Figure 2 As shown, the second switch module 60 is an insulated gate bipolar transistor M2, the gate of the insulated gate bipolar transistor M2 (corresponding to Figure 2 Pin 1 of the resistor R10 is connected to Pin 2 of the resistor R10 and Pin 1 of the resistor R13. The collector of the insulated gate bipolar transistor M2 (corresponding to Figure 2 Pin 3 in the figure is connected to the negative terminal of the battery, and the emitter of the insulated gate bipolar transistor M1 (corresponding to Figure 2 Pin 2 in the circuit) is connected to the collector of the insulated gate bipolar transistor M1, the high voltage blocking module, and the first output terminal.

[0030] The insulated gate bipolar transistor M1 and the insulated gate bipolar transistor M2 are of the same model, CRST045N10N.

[0031] Specifically, if Figure 2As shown, the high-voltage blocking module 70 includes a MOS transistor Q6, a MOS transistor Q10, a resistor R16, and a capacitor C10; the drain of the MOS transistor Q6 is connected to the collector of the insulated gate bipolar transistor M1 and the emitter of the insulated gate bipolar transistor M2, the source of the MOS transistor Q6 is connected to the source of the MOS transistor Q10, the first level signal input terminal is connected to the gate of the MOS transistor Q6 and the gate of the MOS transistor Q10, the drain of the MOS transistor Q10 is connected to pin 1 of the resistor R16, pin 1 of the capacitor C10, and the second output terminal, and pin 2 of the resistor R16 and pin 2 of the capacitor C10 are grounded.

[0032] In this embodiment, the first level signal input terminal 10 is a PWM_U+ signal; the second level signal input terminal 40 is a PWM_U- signal; the first output terminal 80 is an inverter output signal (an output signal of a certain phase of the inverter output, corresponding to Figure 2 U in the motor is connected to the motor); the second output terminal 90 is a voltage signal output to the MCU (corresponding to Figure 2V_VCE in, connected to MCU); when the PWM_U+ signal and the PWM_U- signal are high, the transistors Q3 and Q1 are turned off, the transistors Q4 and Q2 are turned on, the gate of the insulated gate bipolar transistor M1 is low, so the insulated gate bipolar transistor M1 is cut off, the transistors Q7 and Q5 are cut off, the transistors Q9 and Q8 are turned on, the gate of the insulated gate bipolar transistor M2 is low, so the insulated gate bipolar transistor M2 is cut off, at this time the MOS tube Q6 is turned on, the MOS tube Q10 is turned on inverted, and the voltage signal output to the MCU is 0 voltage; when When the PWM_U+ signal is low and the PWM_U- signal is high, transistors Q3 and Q1 are turned on, transistors Q4 and Q2 are turned off, and the gate of the insulated gate bipolar transistor M1 is low-high, so the insulated gate bipolar transistor M1 is turned on, transistors Q7 and Q5 are turned off, transistors Q9 and Q8 are turned on, and the gate of the insulated gate bipolar transistor M2 is low, so the insulated gate bipolar transistor M2 is turned off. At this time, MOS tube Q6 is turned off, MOS tube Q10 is turned off, and the voltage signal output to the MCU is 0 voltage; when the PWM_U+ signal is high, When the PWM_U- signal is low, transistors Q3 and Q1 are turned off, transistors Q4 and Q2 are turned on, and the gate of the insulated gate bipolar transistor M1 is low, so the insulated gate bipolar transistor M1 is cut off, transistors Q7 and Q5 are turned on, transistors Q9 and Q8 are turned off, and the gate of the insulated gate bipolar transistor M2 is low-high, so the insulated gate bipolar transistor M1 is turned on. As the output current of the insulated gate bipolar transistor M2 increases, the inverter output signal increases. At this time, MOS tube Q6 is turned on, and MOS tube Q10 is turned on inverted, and the voltage signal output to the MCU is The signal increases with the increase of the inverter output signal. According to the relationship between the MOS tube and the output current (the MOS tube has a parameter called on-resistance, generally represented by RDS(on). When the MOS tube has a larger current output, the V_VCE voltage is equivalent to the product of the current and RDS(on). It can be seen that when the current increases, V_VCE will also increase). The MCU can calculate the output current at this time through the voltage signal output to the MCU. At the same time, it can control the high and low levels of the PWM output to protect the MOS tube from damage due to overcurrent, eliminating the need for a voltage-type current sensor or a shunt, saving design space and reducing costs.

[0033] In this embodiment, the components and their models and connection relationships that are not shown are Figure 2 The specific circuit diagram has been marked and will not be described here.

[0034] The above examples are merely provided to further illustrate the technical content of the present invention for easier understanding by the reader, but do not limit the implementation of the present invention to these examples. Any extension or re-creation of the technology based on the present invention shall be protected by the present invention. The scope of protection of the present invention shall be determined by the claims.

Claims

1. The MOS tube output current circuit for calculating power of low-voltage electric drive is characterized by: The invention comprises a first level signal input terminal, a first driving module, a first switch module, a second level signal input terminal, a second driving module, a second switch module, a high voltage blocking module, a first output terminal, and a second output terminal; the first level signal input terminal is connected to the first driving module and the high voltage blocking module, the first switch module is connected to the first driving module, the second level signal input terminal is connected to the second driving module, the second switch module is connected to the second driving module, the first output terminal and the high voltage blocking module are both connected to the first switch module and the second switch module. The first driving module includes a voltage input terminal, a capacitor C1, a capacitor C2, a diode D1, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a transistor Q1, a transistor Q2, a transistor Q3, and a transistor Q4; pin 1 of the capacitor C1, pin 1 of the capacitor C2, and the anode of the diode D1 are all connected to the voltage input terminal, and pin 2 of the capacitor C1 and pin 2 of the capacitor C2 are all connected to the voltage input terminal. The cathode of the diode D1 is connected to the 1st pin of the capacitor C3, the 2nd pin of the resistor R3, the 1st pin of the resistor R4, the collector of the transistor Q1, and the emitter of the transistor Q3. The 2nd pin of the capacitor C3 and the 1st pin of the resistor R3 are grounded. The 2nd pin of the resistor R4 and the base of the transistor Q3 are both connected to the first level signal input terminal. The collector of the transistor Q3 is connected to the base of the transistor Q1, the 2nd pin of the resistor R8, and the base of the transistor Q4. The 1st pin of the resistor R8 and the collector of the transistor Q4 are grounded. The emitter of the transistor Q1 is connected to the 2nd pin of the resistor R1. Pin 1 of the resistor R1 is connected to pin 2 of the resistor R5, the emitter of the transistor Q2, pin 2 of the capacitor C4, pin 2 of the resistor R6, and pin 1 of the resistor R2. The emitter of the transistor Q4 is connected to pin 1 of the resistor R5 and the base of the transistor Q2. The collector of the transistor Q2, pin 1 of the capacitor C4, and pin 1 of the resistor R6 are all grounded. Pin 2 of the resistor R2 is connected to pin 1 of the resistor R7 and the first switch module. Pin 2 of the resistor R7 is connected to pin 1 of the capacitor C5, and pin 2 of the capacitor C5 is grounded. The model of the diode D1 is BAV21W. The first switch module is an insulated gate bipolar transistor M1, the gate of the insulated gate bipolar transistor M1 is connected to pin 2 of the resistor R2 and pin 1 of the resistor R7, the emitter of the insulated gate bipolar transistor M1 is connected to the positive electrode of the battery, and the collector of the insulated gate bipolar transistor M1 is connected to the second switch module, the high voltage blocking module, and the first output end.

2. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 1, characterized in that: The second driving module includes a voltage input terminal, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a transistor Q5, a transistor Q7, a transistor Q8, and a transistor Q9; pin 1 of the capacitor C6, pin 2 of the capacitor C7, pin 1 of the resistor R11, the collector of the transistor Q5, and the emitter of the transistor Q7 are all connected to the voltage input terminal, pin 2 of the capacitor C6 and pin 1 of the capacitor C7 are grounded, the second level signal input terminal is connected to pin 2 of the resistor R11 and the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q5, pin 2 of the resistor R15, and the base of the transistor Q9, and pin 1 of the resistor R15 is grounded; The collector of the transistor Q9 is grounded, the emitter of the transistor Q9 is connected to pin 2 of the resistor R12 and the base of the transistor Q8, the collector of the transistor Q8 is grounded, the emitter of the transistor Q5 is connected to pin 1 of the resistor R9, pin 2 of the resistor R9 is connected to pin 1 of the resistor R12, the emitter of the transistor Q8, pin 1 of the capacitor C8, pin 1 of the resistor R14, and pin 1 of the resistor R10 are connected, pin 2 of the capacitor C8 and pin 2 of the resistor R14 are grounded, pin 2 of the resistor R10 is connected to pin 1 of the resistor R13 and the second switch module, pin 2 of the resistor R13 is connected to pin 1 of the capacitor C9, and pin 2 of the capacitor C9 is grounded.

3. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 2, characterized in that: The transistors Q1 , Q2 , Q3 , Q4 , Q5 , Q7 , Q8 , and Q9 are of the same model, SS8550.

4. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 2, characterized in that: The second switch module is an insulated gate bipolar transistor M2, the gate of the insulated gate bipolar transistor M2 is connected to pin 2 of the resistor R10 and pin 1 of the resistor R13, the collector of the insulated gate bipolar transistor M2 is connected to the negative electrode of the battery, and the emitter of the insulated gate bipolar transistor M1 is connected to the collector of the insulated gate bipolar transistor M1, the high voltage blocking module, and the first output end.

5. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 4, characterized in that: The insulated gate bipolar transistor M1 and the insulated gate bipolar transistor M2 are of the same model, CRST045N10N.

6. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 4, characterized in that: The high-voltage blocking module includes a MOS transistor Q6, a MOS transistor Q10, a resistor R16, and a capacitor C10; the drain of the MOS transistor Q6 is connected to the collector of the insulated gate bipolar transistor M1 and the emitter of the insulated gate bipolar transistor M2, the source of the MOS transistor Q6 is connected to the source of the MOS transistor Q10, the first level signal input terminal is connected to the gate of the MOS transistor Q6 and the gate of the MOS transistor Q10, the drain of the MOS transistor Q10 is connected to pin 1 of the resistor R16, pin 1 of the capacitor C10, and the second output terminal, and pin 2 of the resistor R16 and pin 2 of the capacitor C10 are grounded.

7. The MOS tube output current circuit for calculating power of a low-voltage electric drive according to claim 6, characterized in that: The first level signal input end is PWM_U+ signal; the second level signal input end is PWM_U- signal; the first output end is the inverter output signal for connecting to the motor; the second output end is the voltage signal output to the MCU; when the PWM_U+ signal and the PWM_U- signal are high level, the transistor Q3 and the transistor Q1 are turned off, the transistor Q4 and the transistor Q2 are turned on, the gate of the insulated gate bipolar transistor M1 is low level, so the insulated gate bipolar transistor M1 is turned off, the transistor Q7 and the transistor Q5 are turned off, and the transistor Q9 is turned on. When the PWM_U+ signal is low and the PWM_U- signal is high, the transistors Q3 and Q1 are turned on, the transistors Q4 and Q2 are turned off, and the gate of the insulated gate bipolar transistor M1 is low, so the insulated gate bipolar transistor M1 is turned on, the transistor Q7 and Q8 are turned on, and the gate of the insulated gate bipolar transistor M1 is low, so the insulated gate bipolar transistor M1 is turned on, the transistor Q7 and Q10 are turned on, and the voltage signal output to the MCU is 0 voltage; when the PWM_U+ signal is low and the PWM_U- signal is high, the transistors Q3 and Q1 are turned on, the transistors Q4 and Q2 are turned off, and the gate of the insulated gate bipolar transistor M1 is low and high, so the insulated gate bipolar transistor M1 is turned on, the transistors ... on, and the transistor Q7 and Q10 are turned on, Q5 is turned off, transistor Q9 and transistor Q8 are turned on, and the gate of the insulated gate bipolar transistor M2 is at a low level, so the insulated gate bipolar transistor M2 is cut off. At this time, MOS tube Q6 is cut off, MOS tube Q10 is cut off, and the voltage signal output to the MCU is 0 voltage; when the PWM_U+ signal is high and the PWM_U- signal is low, transistor Q3 and transistor Q1 are cut off, transistor Q4 and transistor Q2 are turned on, and the gate of the insulated gate bipolar transistor M1 is at a low level, so the insulated gate bipolar transistor M1 is cut off, and the transistor Transistor Q7 and transistor Q5 are turned on, transistor Q9 and transistor Q8 are turned off, and the gate of insulated gate bipolar transistor M2 is at a low-high level, so insulated gate bipolar transistor M1 is turned on. As the output current of insulated gate bipolar transistor M2 increases, the inverter output signal increases. At this time, MOS transistor Q6 is turned on, and MOS transistor Q10 is turned on inverted. The voltage signal output to the MCU increases as the inverter output signal increases. According to the relationship between the MOS transistor and the output current, the MCU can calculate the output current at this time through the voltage signal output to the MCU.

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