Semiconductor package with sidewall connection

Abstract

Embodiments of the present disclosure relate to a semiconductor package with sidewall connections. A fan-out wafer-level package is provided including a semiconductor die having a redistribution layer on its sidewalls. The redistribution layer located above the die includes an extension extending along the sidewalls. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is located between the extension of the redistribution layer and the sidewalls of the semiconductor die. Solder contacts for electrically connecting a semiconductor device to an electronic circuit board are located on the redistribution layer. The solder contacts and the sidewalls of the redistribution layer can provide electrical contact at two different locations. Thus, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

Description

Technical Field

[0001] The present disclosure relates to a wafer-level package having an extended redistribution layer formed on a sidewall of a semiconductor die for providing additional input / output terminals in the package. Background Art

[0002] A typical semiconductor package includes input / output connections for connecting the semiconductor package to other various external circuits on the top surface. These various external circuits may include other semiconductor packages or printed circuit boards or any kind of external circuits.

[0003] In conventional wafer level chip scale packaging (WLCSP), which is a technology for packaging integrated circuits (ICs) at the wafer level, the WLCSP generally provides I / O connections only on the top side of the package through solder balls mounted on the semiconductor die. Such WLCSP packaging limits the number of I / O connections in the package, and since I / O connections are only provided on the top side of the package, the way in which the package can be stacked is limited.

[0004] Due to such limited applications in conventional WLCSP structures, the size of the package cannot meet the industry's growing demand for providing a minimized size package. Summary of the invention

[0005] The present disclosure relates to a semiconductor package that utilizes the sidewall area of ​​a WLCSP package to provide additional I / O connections and reduce the package size. Therefore, a semiconductor package and a method of manufacturing such a semiconductor package are provided, which has additional I / O connections and minimizes the overall size of the semiconductor package. That is, by expanding the number of I / O connections in the package, the semiconductor package can be stacked horizontally and vertically with other semiconductor packages or circuits using the proposed sidewall I / O connections.

[0006] Another aspect of the present disclosure is to provide a semiconductor package capable of providing improved interconnectivity between semiconductor packages.

[0007] Yet another aspect of the present disclosure is to provide a semiconductor package that can be stacked vertically and horizontally to increase connectivity in various directions.

[0008] Still another aspect of the present disclosure is to provide a semiconductor package that can be stacked in a 3D structure that occupies a minimum space and thus reduces the overall size of the semiconductor device.

[0009] Another aspect of the present disclosure is to provide a method for manufacturing a semiconductor package with additional I / O connections by using a conventional wafer level chip scale package bump formation process without adding additional manufacturing stages. This helps to maintain the cost of the entire manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To better understand the embodiments, reference is now made to the accompanying drawings by way of example only. In the accompanying drawings, the same reference numerals identify similar elements or actions. The sizes and relative positions of the elements in the accompanying drawings are not necessarily drawn to scale. For example, the shapes and angles of the various elements are not necessarily drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawings. Further, the particular shapes of the elements depicted are not necessarily intended to convey any information about the actual shape of the particular element, and may be selected only for ease of identification in the drawings.

[0011] Figure 1 is a cross-sectional view of an exemplary embodiment of a semiconductor structure having an extended redistribution layer on a sidewall of a semiconductor die according to the present disclosure;

[0012] Figure 2 According to an exemplary embodiment of the present disclosure Figure 1 A top view of a semiconductor structure;

[0013] Figure 3A and Figure 3B An example of providing a mold protection layer according to an embodiment of the present disclosure is shown;

[0014] Figure 4 shows a cross-sectional view of two semiconductor structures having connections using solder balls according to one embodiment of the present disclosure;

[0015] Figure 5 shows a cross-sectional view of two semiconductor structures having connections using wire bonding according to another embodiment of the present disclosure;

[0016] FIG. 6A to FIG. 6I is a cross-sectional view illustrating an exemplary method of fabricating an extended redistribution layer according to an exemplary embodiment of the present disclosure;

[0017] Figure 7 A cross-sectional view of a scribed adjacent semiconductor structure is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known structures associated with chip packaging or wafer-level chip scale packaging (WLCSP) have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0019] Unless the context requires otherwise, throughout the following specification and claims, the word "include" and variations thereof (such as "comprising" and "having") should be interpreted in an open inclusive sense, that is, as "including but not limited to". Further, unless the context clearly indicates otherwise, the terms "first", "second" and similar sequence indicators should be interpreted as interchangeable.

[0020] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner.

[0021] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its broadest sense, that is, "and / or", unless the content clearly dictates otherwise.

[0022] Dashed lines in the drawings are used to indicate that further elements exist but are omitted for simplicity.

[0023] Figure 1 1 is a cross-sectional view of a portion of a semiconductor structure 100 according to an exemplary embodiment of the present disclosure. In this embodiment, the semiconductor structure 100 includes a semiconductor die 110 having a semiconductor substrate, which includes a variety of active and passive circuits, such as transistors, resistors, capacitors, logic, etc. The semiconductor structure 100 also includes a contact pad 120, a passivation layer 130, a first dielectric layer 140, a redistribution layer 150, a second dielectric layer 160, and a conductive structure 171 including a metallization layer 170. The conductive structure 171 can be any suitable structure capable of conducting an electrical signal, and can be, but is not limited to, an under-bump metal structure (UBM) as the metallization layer 170, and a solder bump or solder ball 180. These conductive structures form the basis for providing electrical contacts, which will be described in detail below. However, other embodiments may include fewer or more elements of the semiconductor structure according to specific design requirements.

[0024] The semiconductor die 110 is disposed on a carrier substrate of a wafer (not shown). The semiconductor die 110 may have a first surface 111, a second surface 113, and a third surface 115. In one embodiment, the first surface 111 may refer to Figure 1The top surface of the semiconductor die 110 arranged in the wafer. The first surface may be, for example, a planar surface. The contact pad 120 may be disposed on the top surface of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which may refer to a side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 are transverse to each other. In another embodiment, the first surface 111 and the second surface 113 are perpendicular to each other. The semiconductor die 110 also includes a third surface 115, which may refer to the bottom surface of the semiconductor die 110. The third surface 115 of the semiconductor die 110 may contact the carrier substrate of the wafer. The first surface 111 and the third surface 115 are opposite to each other and may be parallel to each other. The semiconductor die 110 may be made of a material including but not limited to silicon (Si) or gallium arsenide (GaAs).

[0025] The contact pad 120 is located on the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is disposed on the top surface of the semiconductor die 110. In this embodiment, the contact pad 120 may overlap an area of ​​the semiconductor die 110 and does not necessarily have a surface coplanar with the first surface 111 of the semiconductor die 110. However, in some embodiments, in order to minimize the overall height and thickness of the semiconductor structure 100, the contact pad 120 may be embedded or recessed in the semiconductor die 110 and may have a top surface 111 coplanar with the semiconductor die 110. Embedding the contact pad 120 in the semiconductor die 110 may include etching the semiconductor die 110 and depositing the contact pad 120 on the etched portion of the die 110. The contact may be part of a processing step for forming active and passive circuits in the die. Thus, the contact pad 120 may be deposited on the semiconductor die 110 to a position below the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is a metal pad and may be made of a conductive material including, but not limited to, metals such as copper (Cu), aluminum (Al), and the like.

[0026] The passivation layer 130 is located on the semiconductor die 110. In one embodiment, the passivation layer 130 is disposed on the semiconductor die 110 and on the first portion 117 of the contact pad 120. For example, the passivation layer 130 overlaps and contacts the two edge portions of the contact pad 120. The passivation layer 130 can be made of an inorganic dielectric material. For example, the passivation layer 130 can be made of silicon nitride (SiN), silicon dioxide (SiO2), other dielectrics, or any compound using a combination of Si and N or Si and O. The passivation layer 130 is used to protect the semiconductor die 110. Depending on the design, the passivation layer 130 can be omitted.

[0027] The first dielectric layer 140 is located on the passivation layer 130. In one embodiment, the first dielectric layer 140 is disposed on the passivation layer 130 and on the second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlaps and contacts the second portion 119 of the contact pad 120. In one embodiment, the first dielectric layer 140 is made of an insulating material including, but not limited to, polybenzoxazole (PBO) or polyimide (PI).

[0028] The redistribution layer 150 is located on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is disposed on the first dielectric layer 140 and the contact pad 120. For example, the redistribution layer 150 contacts the third portion 121 of the contact pad 120 and overlaps the passivation layer 130 and the first dielectric layer 140. In one embodiment, the redistribution layer 150 includes an extension portion 152. For example, the extension portion 152 extends to the side of the semiconductor die 110 to cover the side of the passivation layer 130 and the first dielectric layer 140. The semiconductor die 110 may include a plurality of redistribution layers 150 formed around the perimeter of the die and associated with other solder balls 180 located around the semiconductor die 110. In different applications, the redistribution layer 150 extends along each side of the semiconductor die 110 to provide electrical contact on some of the sidewalls.

[0029] To explain in more detail, the extended portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., the sidewall of the semiconductor die 110) and covers the side surfaces of the passivation layer 130 and the first dielectric layer 140, so that the passivation layer 130 and the first dielectric layer 140 are prevented from being directly exposed.

[0030] In one embodiment, the extended portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 to expose the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 does not extend all the way down along the second surface 113 (e.g., the sidewall) and may cover the side surface of the passivation layer 130 and the side surface of the first dielectric layer 140 while exposing the top surface and the side surface of the lip portion 112 of the semiconductor die 110. In another embodiment, as Figure 1 As shown, an outer surface of the extended redistribution layer 150 may be coplanar with an outer surface of the lip portion 112 of the semiconductor die 110 .

[0031] In another embodiment, the extended portion 152 of the redistribution layer 150 extends all the way down along the second surface 113 of the semiconductor die 110. For example, the redistribution layer 150 extends all the way down along the sidewall and may cover the side of the passivation layer 130, the side of the first dielectric layer 140, and the side of the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may cover over the lip portion 112 of the semiconductor die 110 to provide the entire surface as an electrical contact. Although not shown, if the extended redistribution layer 150 covers over the lip portion 112 of the semiconductor die 110, the extended redistribution layer 150 will form a step shape in the side of the semiconductor die 110 due to the lip portion 112.

[0032] In yet another embodiment, the semiconductor die 110 may not have the lip portion 112, and the extension portion 152 of the redistribution layer 150 may extend all the way down along the second surface 113 of the semiconductor die 110 to reach the third surface 115 of the semiconductor die 110, see Figure 3B For example, the side of the semiconductor die 110, the side of the passivation layer 130, and the side of the first dielectric layer 140 may be coplanar, and the redistribution layer 150 may extend along the sidewalls to completely cover the side of the passivation layer 130, the side of the first dielectric layer 140, and the side of the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may extend until reaching the third surface 115 (e.g., the bottom surface of the semiconductor die 110) to provide an electrical contact including the entire second surface 113.

[0033] The second dielectric layer 160 is located on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps the contact pad 120, the passivation layer 130, the first dielectric layer 140, and the redistribution layer 150. In one embodiment, the second dielectric layer 160 may only contact a certain area of ​​the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, including but not limited to PBO or PI,

[0034] An under-bump metal structure (UBM) 170 is located on the second dielectric layer 160. The UBM 170 is included as one of the conductive structures 171 for conducting electrical signals. In one embodiment, the UBM 170 is in direct contact with the redistribution layer 150 in a position spaced apart from the contact pad 120. The redistribution layer 150 can be electrically and physically connected to the contact pad 120. The connection enables the conductive structure 171 to provide electrical signals to other input / output terminals, such as a printed circuit board (PCB) or other circuits (not shown). In this embodiment, the UBM 170 is located on the second dielectric layer 160 that does not overlap with the contact pad 120. However, in another embodiment, the position of the UBM 170 may overlap with the contact pad 120, or may be located at a different position according to any design requirements. The UBM 170 may be made of a metal including, but not limited to, nickel (Ni), Al, Cu, chromium (Cr), titanium (Ti), or any combination thereof.

[0035] Solder balls 180 are located on UBM 170. Solder balls 180 are also included in conductive structures 171 for conducting electrical signals. Solder balls 180 may be collectively referred to as solder balls, solder bumps, solder joints, etc. Any structure capable of conducting electrical signals will suffice and is not limited to solder balls.

[0036] In integrated circuit packaging, solder balls provide electrical contacts between the chip package and the PCB, which provides one electrical contact via the solder balls. However, according to the present disclosure, the redistribution layer 150 on the first dielectric layer 140 extends along the side of the semiconductor die 110 to provide a second electrical contact on the sidewall of the semiconductor die 110. With this configuration, the chip package can be stacked vertically and horizontally. This design will improve the interconnectivity between chip modules and save area consumption.

[0037] Additionally, due to this configuration, another electrical contact is provided on the side of the semiconductor die 110, which avoids the use of through silicon vias (TSVs) or chip vias as vertical electrical connections through the silicon die. While TSVs also provide interconnectivity in 3D packaging and 3D integrated circuits, the manufacturing processes involved in forming TSVs in silicon dies are complex, difficult, and expensive. Therefore, the extended redistribution layer 150 can provide a configuration that consumes less area, involves less cost, consumes less power, and maintains higher interconnection speeds due to the shortened connection length. Figure 4 and Figure 5 Vertical connections are described in more detail in .

[0038] In another embodiment, the electrical signal output to the solder ball 180 and the electrical signal output to the extension portion 152 of the redistribution layer 150 may be different. The semiconductor structure may be configured to provide two significantly different electrical signals. For example, the semiconductor structure 100 provides at least two output terminals, and each of the signals output through the solder ball 180 and the extension portion of the redistribution layer 150 may be different according to design requirements.

[0039] Alternatively, in some embodiments, the electrical signals output from the solder ball 180 and the extension 152 will be the same.

[0040] Figure 2 According to an exemplary embodiment of the present disclosure Figure 1 FIG. 1 is a top view of a semiconductor structure 100 .

[0041] Reference Figure 2 , the semiconductor structure 100 according to the embodiment of the present disclosure may have an extended portion of the redistribution layer 150. Figure 1 , a cross-sectional view of the semiconductor structure 100 along the dashed line has been explained. The top view of the semiconductor structure 100 shows only one ball, however the package will include multiple balls, some or all of which may have an extension of the redistribution layer 150 .

[0042] exist Figure 2 In the embodiment, solder balls 180 and a redistribution layer 150 are formed on a semiconductor die 110. The redistribution layer 150 is extended to the side of the semiconductor die 110 to cover a portion of the sidewall of the die 110. Although the sidewall area overlapped with the extended redistribution layer 150 is completely covered on the side, the extended redistribution layer 150 may not cover the remaining side area of ​​the semiconductor die 110.

[0043] In one embodiment, the sidewall area covered by the extended redistribution layer 150 may be narrow, thereby providing a small-sized contact area. However, in another embodiment, the sidewall area covered by the extended redistribution layer 150 may be wide, thereby providing a large-sized contact area. Therefore, based on design requirements, different sizes of contact areas may be provided.

[0044] In other embodiments not shown, the extended redistribution layer 150 may be rerouted to provide contacts at different portions of the semiconductor die 110. By stretching the extended redistribution layer 150 to different locations in the semiconductor die 110, the second contacts provided by the extended redistribution layer 150 do not necessarily have to be located at the same locations as those in FIG. Figure 1 and Figure 2 On the side shown.

[0045] Figure 3A and Figure 3BAn example of providing a mold protection layer in combination with the semiconductor die 110 and the extension portion 152 of the redistribution layer 150 according to an embodiment of the present disclosure is shown.

[0046] exist Figure 3A In the embodiment, a mold protection layer 190 is provided to cover the side surfaces of the semiconductor die 110, the side surfaces of the passivation layer 130, and the side surfaces of the first dielectric layer 140. The mold protection layer 190 is located between the extension portion 152 of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140.

[0047] refer to Figure 3A , the semiconductor die 110 has a lip portion 112 on a carrier substrate of a wafer (not shown). The semiconductor die 110 may have a first surface 111 and a second surface 113. The lip may extend through the second surface 113.

[0048] In one embodiment, the first surface 111 may refer to the top surface of the semiconductor die 110, and the contact pad 120 may be deposited on the first surface 111 of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which may refer to the side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 may be transverse to each other. For example, the first surface 111 and the second surface 113 do not need to be perpendicular to each other. In this way, the first surface 111 and the second surface 113 may form an inclined angle with each other. However, in another embodiment, the first surface 111 and the second surface 113 may be perpendicular to each other. The semiconductor die 110 may be made of a material including but not limited to Si or GaAs.

[0049] The contact pad 120 is deposited on the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is located on the top surface of the semiconductor die 110. In this embodiment, the contact pad 120 can be positioned so that the surface of the contact pad 120 is coplanar with the first surface 111 of the semiconductor die 110. However, in different embodiments, the surface of the contact pad 120 and the semiconductor die 110 do not necessarily have to be coplanar. In some embodiments, in order to minimize the overall height and thickness of the semiconductor structure 300, the contact pad 120 can be embedded in the semiconductor die 110 and can have a top surface that is coplanar with the semiconductor die 110. For example, the contact pad 120 can be a metal pad and can be made of a conductive material including but not limited to Cu, Al, etc.

[0050] The passivation layer 130 is deposited on the semiconductor die 110. In one embodiment, the passivation layer 130 is located on the semiconductor die 110 and overlaps with the first portion 117 of the contact pad 120. For example, the passivation layer 130 overlaps the two edge portions of the contact pad 120 and contacts the contact pad 120. In this embodiment, the passivation layer 130 is deposited on the semiconductor die 110, but does not extend to the lip portion 112 of the semiconductor die 110. The passivation layer 130 can be made of an inorganic or organic dielectric material. For example, the passivation layer 130 can be made using SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The passivation layer 130 is used to protect the semiconductor die 110. According to the design, the passivation layer 130 can be omitted.

[0051] The first dielectric layer 140 is deposited on the passivation layer 130. In one embodiment, the first dielectric layer 140 is located on the passivation layer 130 and overlaps the second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlaps the second portion 119 of the contact pad 120 and contacts both the contact pad 120 and the passivation layer 130. In this embodiment, the first dielectric layer 140 is deposited on the passivation layer 130, but does not extend to the lip portion 112 of the semiconductor die 110. The first dielectric layer 140 may be made of, for example, but not limited to, PBO or PI.

[0052] The redistribution layer 150 is deposited on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is located on the contact pad 120, the first dielectric layer 140, and the mold protection layer 190. For example, the redistribution layer 150 contacts the third portion 121 of the contact pad 120 and overlaps the passivation layer 130, the first dielectric layer 140, and the mold protection layer 190. In one embodiment, the redistribution layer 150 includes an extension portion 152, which extends along the sidewall or the second surface 113 of the semiconductor die 110. In another embodiment, the other end of the redistribution layer 150 does not have to extend to the other side surface of the semiconductor die 110. That is, according to the circuit design requirements, the redistribution layer 150 can be formed on only one side of the semiconductor die 110. However, in different applications, the redistribution layer 150 can extend along both sides of the semiconductor die 110 to provide electrical contacts on both sidewalls of the semiconductor die 110.

[0053] The extended portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 including the lip portion 112. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., the sidewall of the semiconductor die 110) and covers the top surface of the first dielectric layer 140 and the top and side surfaces of the mold protection layer 190, so that the passivation layer 130, the first dielectric layer 140, and the mold protection layer 190 are prevented from being directly exposed.

[0054] In one embodiment, the extended portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 but does not cover the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 may not extend all the way down along the second surface 113 (e.g., the sidewall of the semiconductor die 110) and may cover the mold protection layer 190 until it reaches the top surface of the lip portion 112 of the semiconductor die 110.

[0055] In another embodiment, the extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 to expose the lip portion 112 of the semiconductor die 110. For example, the extension portion 152 of the redistribution layer 150 may be coplanar with the lip portion 112 of the semiconductor die 110. That is, the side surface of the lip portion 112 of the semiconductor die 110 may be coplanar with the extension portion 152 of the redistribution layer 150 extending along the second surface 113 (e.g., sidewall) of the semiconductor die 110.

[0056] A mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protection layer 190 can provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between the extended portion 152 of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protection layer 190 is disposed adjacent to the outer periphery of the semiconductor die. In one embodiment, the mold protection layer 190 surrounds the semiconductor die 110 to provide protection on the sidewalls of the semiconductor structure 300.

[0057] A compression molding process may be used to form the mold protection layer 190 to encapsulate the die with a molding compound. However, other methods may be used and are not necessarily limited to this molding process. The mold protection layer 190 may provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between the side of the semiconductor die 110, the side of the passivation layer 130, the side of the first dielectric layer 140, and the extended portion of the redistribution layer 150 so that the electrical contact area on the sidewall of the semiconductor die 110 is not reduced.

[0058] In further embodiments, the mold protection layer 190 may be positioned to cover a portion of the extension portion 152 of the redistribution layer 150. With this configuration, the electrical contact area provided on the sidewall of the semiconductor die 110 using the extension portion 152 of the redistribution layer 150 may be reduced. For example, the mold protection layer 190 may be formed between the lip portion 112 of the semiconductor die 110 and the extension portion 152 of the redistribution layer 150 to partially cover the lower extension portion of the redistribution layer 150. However, in different embodiments, the mold protection layer 190 may be provided to cover the upper extension portion of the redistribution layer 150 or the middle extension portion of the redistribution layer 150 according to design requirements.

[0059] The second dielectric layer 160 is deposited on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps the contact pad 120, the passivation layer 130, the first dielectric layer 140, and the redistribution layer 150. For example, the second dielectric layer 160 is positioned such that the layer contacts a portion of the first dielectric layer 140 and a portion of the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, including but not limited to PBO or PI.

[0060] The UBM 170 is deposited on the second dielectric layer 160. The conductive structure 171 according to the present disclosure also includes, among other things, the UBM 170, solder balls 180, etc., which are capable of conducting electrical signals. In one embodiment, the UBM 170 is in direct contact with the redistribution layer 150 in a position that does not overlap with the contact pad 120. The redistribution layer 150 can be electrically or physically connected to the contact pad 120, and the connection enables the conductive structure 171 to provide electrical signals to other input / output terminals, such as a PCB or other external circuit (not shown). In this embodiment, the UBM 170 is located on the second dielectric layer 160 that does not overlap with the contact pad 120. However, in another embodiment, the position of the UBM 170 can overlap with the contact pad 120 or be located at a different position according to any design requirements. The UBM 170 can be made of a metal including, but not limited to, for example, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0061] Solder balls 180 are mounted on UBM 170. Solder balls 180 are also included in conductive structures 171 for conducting electrical signals. Solder balls 180 may be collectively referred to as solder balls, solder bumps, solder joints, etc. Any structure capable of conducting electrical signals will suffice and is not limited to solder balls.

[0062] According to the current circuit packaging, the solder balls can provide the first electrical contact to the chip package or PCB, but the extended redistribution layer 150 can also provide the second electrical contact on the sidewall of the semiconductor die 110. With this configuration, the chip package can be stacked vertically and horizontally. This design will improve the interconnectivity between chip modules and save area occupation.

[0063] In addition, this configuration enhances interconnectivity in 3D packaging and 3D integrated circuits, and reduces the complexity involved in the manufacturing process, because the formation of the extended redistribution layer 150 can be used in a traditional bump formation process without adding additional manufacturing stages. For example, the extended redistribution layer 150 can be easily formed using a traditional WLCSP bump process. Therefore, the complexity involved in forming the extended redistribution layer 150 is reduced and the cost is low. Further, due to the shortened connection length between chip packages or with the PCB, the extended redistribution layer 150 can provide a configuration that occupies less area, consumes less power, and still maintains a high interconnection speed. Figure 4 and Figure 5 Vertical connections will be explained in more detail in the following.

[0064] In another embodiment, the electrical signal output to the solder ball 180 and the electrical signal output to the extension portion 152 of the redistribution layer 150 may be different. The semiconductor structure may be configured to provide two significantly different electrical signals. For example, the semiconductor structure 100 provides at least two output terminals, and each of the signals output through the solder ball 180 and the extension portion of the redistribution layer 150 may be different according to design requirements.

[0065] exist Figure 3B In the present invention, a mold protection layer 190 is provided to cover the side of the semiconductor die 110, the side of the passivation layer 130 and the side of the first dielectric layer 140. The mold protection layer 190 is located between the extended portion of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130 and the first dielectric layer 140.

[0066] Reference Figure 3B , the semiconductor die 110 has no lip portion. The semiconductor die 110 without the lip portion is disposed on a carrier substrate of a wafer (not shown). For the purpose of clarity and to avoid obscuring the subject matter of the present disclosure, the semiconductor die 110 is not shown in the figure. Figure 1 and Figure 3A Those descriptions that can be easily found are omitted.

[0067] A mold protection layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protection layer 190 can provide additional protection on top of the extended redistribution layer 150 for the semiconductor die 110. The mold protection layer 190 is located between the extended portion of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protection layer 190 is disposed adjacent to the outer periphery of the semiconductor die. In one embodiment, the mold protection layer 190 surrounds the semiconductor die 110 to provide protection on the sidewalls of the semiconductor structure 320.

[0068] Only features related to the mold protection layer 190 are described in detail. The mold protection layer 190 may be formed using a compression molding process to encapsulate the die with a molding compound. However, as mentioned, another suitable molding process may be used. The mold protection layer 190 is located between the side 113 of the semiconductor die 110, the side of the passivation layer 130, the side of the first dielectric layer 140, and the extended portion 152 of the redistribution layer 150 so as not to reduce the electrical contact area on the sidewall of the semiconductor die 110. Figure 3B If the semiconductor die 110 in the embodiment has no lip portion, the mold protection layer 190 may be formed to cover all the way down until it reaches the third surface 115 of the semiconductor die 110. For example, the mold protection layer 190 may be formed to cover the entire second surface 113 of the semiconductor die 110.

[0069] The extended portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 and covers the mold protection layer 190. In one embodiment, the redistribution layer 150 extends to the sidewalls of the semiconductor die 110 on top of the mold protection layer 190 so that the mold protection layer 190 is not directly exposed. This configuration allows the mold protection layer 190 to protect the semiconductor die 110 and the outer boundary of the extended redistribution layer 150 to have a wide contact surface on the sidewalls of the semiconductor die 110.

[0070] In another embodiment, the extended portion 152 of the redistribution layer 150 extends downward along the second surface 113 of the semiconductor die 110 to reach the third surface 115 of the semiconductor die 110. For example, the redistribution layer 150 may extend downward along the sidewalls covering the mold protection layer 190 and the bottom surface of the mold protection layer 190. If the extended redistribution layer 150 covers the mold protection layer 190 and reaches the third surface 115 of the semiconductor die 110, it will provide connectivity to all directions (e.g., through the top direction of the solder ball 180, using the side direction of the extended redistribution layer 150) and increase the surface that can provide electrical contact. This will improve vertical and horizontal interconnections between chip packages or with other external circuits.

[0071] Figure 4 A cross-sectional view of two semiconductor structures connected in a stack and having solder balls on lateral surfaces according to an embodiment of the present disclosure is shown.

[0072] exist Figure 4 , a portion of the package 400 includes a first semiconductor die 110 and a second semiconductor die 410 attached together via an adhesive layer 498. The adhesive layer 498 can be any suitable material for attaching silicon dies together. For example, an adhesive including, but not limited to, polyimide or epoxy can be used to bond the two silicon dies. The first semiconductor die 110 includes a first contact pad 120, a first passivation layer 130, a first dielectric layer 140, a first redistribution layer 150, a second dielectric layer 160, a first conductive structure 171 including a first UBM 170, and a first solder ball 180. The second semiconductor die 410 includes a second contact pad 420, a second passivation layer 430, a third dielectric layer 440, a second redistribution layer 450, a fourth dielectric layer 460, a second conductive structure 471 including a second UBM 470, and a second solder ball 480. However, other embodiments may include fewer or more elements of the semiconductor structure depending on specific design requirements.

[0073] The first semiconductor die 110 and other elements of the first semiconductor die 110 are similar to those of the Figure 1 or Figure 3A Therefore, repeated description of the same elements is omitted.

[0074] The first semiconductor die 110 having the first solder balls 180 may be connected to a printed circuit board (PCB) 494 using a conductive layer 492. The conductive layer 492 may provide an electrical connection between the first solder balls 180 and the PCB 494. The conductive layer 492 may be made of, for example, any metal capable of conducting a signal, including but not limited to Cu, Al, and the like.

[0075] The second semiconductor die 410 may have a fourth surface 411, a fifth surface 413, and a sixth surface 415. In one embodiment, the fourth surface 411 may refer to a bottom surface, the fifth surface 413 may refer to a side surface, and the sixth surface 415 may refer to a top surface of the second semiconductor die 410, which faces a downward direction in the figure.

[0076] The second contact pad 420 may be disposed on the top surface of the second semiconductor die 410. In one embodiment, the fifth surface 413 and the sixth surface 415 may be lateral to each other. In another embodiment, the fifth surface 413 and the sixth surface 415 may be perpendicular to each other.

[0077] The second semiconductor die 410 also includes a sixth surface 415, which may correspond to the top surface of the second semiconductor die 410. In one embodiment, the fourth surface 411 and the sixth surface 415 may be opposite to each other. For example, the fourth surface 411 and the sixth surface 415 may be located on opposite sides facing each other. In another embodiment, the fourth surface 411 and the sixth surface 415 may be parallel to each other. The second semiconductor die 410 may be made of a material including, but not limited to, Si or GaAs.

[0078] In this embodiment, the third surface 115 of the first semiconductor die 110 (e.g., the bottom surface of the first semiconductor die 110) and the fourth surface 411 of the second semiconductor die 410 (e.g., the bottom surface of the second semiconductor die 410) may face each other. For example, the third surface 115 of the first semiconductor die 110 and the fourth surface 411 of the second semiconductor die 410 may be located on opposite sides and may be glued to each other using an adhesive layer 498. In other embodiments, the adhesive layer 498 may be omitted.

[0079] The second contact pad 420 is located on the sixth surface 415 of the second semiconductor die 410. In one embodiment, the second contact pad 420 is disposed on the top surface of the second semiconductor die 410. In this embodiment, the second contact pad 420 may overlap an area of ​​the second semiconductor die 410 and does not necessarily have to have a surface coplanar with the sixth surface 415 of the second semiconductor die 410. However, in some embodiments, in order to minimize the overall height and thickness of the semiconductor structure 400, the second contact pad 420 may be embedded in the second semiconductor die 410 and may have a top surface coplanar with the second semiconductor die 410. Embedding the second contact pad 420 in the second semiconductor die 410 may include etching the second semiconductor die 410 and depositing the second contact pad 420 on the second semiconductor die 410. Thus, the second contact pad 420 may be deposited on the second semiconductor die 410 to a position lower than the top surface of the second semiconductor die 410. In one embodiment, the second contact pad 420 is a metal pad and is made of a conductive material, including but not limited to Cu, Al, etc.

[0080] The second passivation layer 430 is located on the second semiconductor die 410. In one embodiment, the second passivation layer 430 is disposed on the second semiconductor die 410 and on the first portion 417 of the second contact pad 420. For example, the second passivation layer 430 overlaps and contacts both edge portions of the second contact pad 420. The second passivation layer 430 may be made of SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The second passivation layer 430 is used to protect the second semiconductor die 410. Depending on the design, the second passivation layer 430 may be omitted.

[0081] The third dielectric layer 440 is located on the second passivation layer 430. In one embodiment, the third dielectric layer 440 is disposed on the second passivation layer 430 and on the second portion 419 of the second contact pad 420. For example, the third dielectric layer 440 overlaps and contacts the second portion 419 of the second contact pad 420. In one embodiment, the third dielectric layer 440 is made of, but not limited to, PBO or PI.

[0082] The second redistribution layer 450 is located on the third dielectric layer 440. In one embodiment, the second redistribution layer 450 is disposed on the third dielectric layer 440 and the second contact pad 420. For example, the second redistribution layer 450 contacts the third portion 421 of the second contact pad 420 and overlaps the second passivation layer 430 and the third dielectric layer 440. In one embodiment, the second redistribution layer 450 includes an extension portion 452. In another embodiment, the other end of the second redistribution layer 450 does not have to extend to the other side surface of the second semiconductor die 410. That is, the second redistribution layer 450 may be formed only on one side of the second semiconductor die 410. However, in different applications, the second redistribution layer 450 may extend along both sides of the second semiconductor die 410 to provide electrical contact on both sidewalls.

[0083] The extension portion 452 of the second redistribution layer 450 extends along the fifth surface 413 (e.g., the side surface) of the second semiconductor die 410. In one embodiment, the second redistribution layer 450 extends to the fifth surface 413 of the second semiconductor die 410 (e.g., the sidewall of the second semiconductor die 410) and covers the side surfaces of the second passivation layer 430 and the third dielectric layer 440, so that the second passivation layer 430 and the third dielectric layer 440 are prevented from being directly exposed.

[0084] In one embodiment, the extension portion 452 of the second redistribution layer 450 extends along the fifth surface 413 of the second semiconductor die 410 to expose the lip portion 412 of the semiconductor die 410. For example, the second redistribution layer 450 does not extend all the way down along the fifth surface 413 and may cover the side surfaces of the second passivation layer 430 and the third dielectric layer 440, but leaves the lip portion 412 of the second semiconductor die 410 open.

[0085] In another embodiment, in a semiconductor die without the lip portion 412 (eg, both the first semiconductor die 110 and the second semiconductor die 410 are connected to the semiconductor die 110 and the second semiconductor die 410), Figure 3B The die structure 320 seen in FIG. 1 similarly does not have a lip portion), the surface of the extended second redistribution layer 450 and the surface of the extended first redistribution layer 150 may be coplanar. However, due to the adhesive layer 498 between the two semiconductor dies, the extended second redistribution layer 450 and the extended first redistribution layer 150 may be electrically insulated from each other.

[0086] In an additional embodiment, the extended portion 452 of the second redistribution layer 450 extends all the way down along the fifth surface 413 of the second semiconductor die 410. For example, the second redistribution layer 450 extends all the way down along the sidewalls and may cover the sides of the second passivation layer 430, the sides of the third dielectric layer 440, and the sides of the second semiconductor die 410. In this embodiment, the extended second redistribution layer 450 may cover the lip portion 412 of the second semiconductor die 410 to provide the entire surface as an electrical contact. Although not shown, if the extended second redistribution layer 450 covers the lip portion 412 of the second semiconductor die 410, it will form a step shape in the side of the second semiconductor die 410 due to the lip portion 412. The extended second redistribution layer 450 and the extended first redistribution layer 150 may still be electrically insulated from each other due to the adhesive layer 498 between the two semiconductor dies.

[0087] The fourth dielectric layer 460 is located on the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 overlaps the second contact pad 420, the second passivation layer 430, the third dielectric layer 440, and the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 may contact only a certain area of ​​the second redistribution layer 450. The fourth dielectric layer 460 may be made of, but is not limited to, the same material as the third dielectric layer 140 (e.g., PBO or PI).

[0088] The second UBM 470 is located on the fourth dielectric layer 460. The second UBM 470 is included as one of the conductive structures 471 for conducting electrical signals. In one embodiment, the second UBM 470 is in direct contact with the second redistribution layer 450 in a position spaced apart from the second contact pad 420. The second redistribution layer 450 may be electrically and physically connected to the second contact pad 420. In this embodiment, the second UBM 470 is located on the fourth dielectric layer 460 that does not overlap with the second contact pad 420. However, in another embodiment, the position of the second UBM 470 may overlap with the second contact pad 420 or be located at a different position according to any design requirements. The second UBM 470 may be made of, but not limited to, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0089] The second solder ball 480 is located on the second UBM 470. The second solder ball 480 is also included in the conductive structure 471 for conducting electrical signals. The second solder ball 480 may be collectively referred to as a solder ball, a solder bump, a solder joint, etc. Any structure capable of conducting electrical signals will suffice and is not limited to a solder ball. Conductive structures such as the second solder ball 480 may provide electrical signals to other input / output terminals such as a PCB or other circuits. Although not shown in FIG. Figure 4 , the first solder balls 180 mounted on the first semiconductor die 110 are connected to the PCB 494 to provide input / output terminals. An additional PCB may be attached to the second solder balls 480 mounted on the second semiconductor die 410 according to design requirements.

[0090] In wafer-level packaging, solder balls can be used to electrically connect to a chip package or a PCB. However, according to the wafer-level packaging of the present disclosure, the first semiconductor die 110 and the second semiconductor die 410 are stacked vertically with each other, and additional electrical contacts are also provided on the second surface of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by a conductive connection. The conductive connection can be any material that can conduct electrical signals, such as a metal. In one embodiment, the conductive connection includes but is not limited to a solder joint, a solder bump, a solder ball 496, or a bonding wire 510 ( Figure 5 As shown in FIG. 1 ), or any similar structure providing electrical contacts on the side. With this configuration, the chip packages can be stacked vertically and can also be connected horizontally due to the electrical contacts on the side walls. This design will improve the interconnectivity between chip modules and save area.

[0091] exist Figure 4In the embodiment of the double stacked semiconductor structure 400, the conductive connection 496 connects the first extended redistribution layer 150 and the second extended redistribution layer 450 to form a large single contact. However, in other embodiments, a separate conductive connection 496 can be used for each extended redistribution layer in the extended redistribution layers 150 and 450. For example, a solder ball can be installed separately on the first extended redistribution layer 150 to form an electrical contact, and a second solder ball can be installed separately on the second extended redistribution layer 450 to form another electrical contact. This configuration not only increases the number of electrical contacts on the side of the double stacked semiconductor structure 400, but also provides a basis for retrieving two different signals from the first extended redistribution layer 150 and the second extended redistribution layer 450. In the previous embodiment where the solder ball 496 overlaps the first extended redistribution layer 150 and the second extended redistribution layer 450, since the solder ball 496 is connected to both the first extended redistribution layer 150 and the second extended redistribution layer 450, the electrical contact provided by the solder ball 496 may have only one same signal. However, if a separate solder ball is connected to each of the first and second extended redistribution layers 150 and 450 , there can be two separate electrical signals that can be obtained from each of the first and second extended redistribution layers 150 and 450 .

[0092] In addition, this configuration enhances the interconnectivity in 3D packaging and 3D integrated circuits. The manufacturing process involved in forming the extended redistribution layer is not complicated, difficult or expensive because it utilizes the traditional WLCSP process. The additional process involved is to stack two semiconductor dies together and provide solder joints 496 on the sides of the stacked semiconductor dies. Solder joints 496 provide side connections for two semiconductor dies 110, 410 stacked vertically. Solder joints 496 can be further used to horizontally connect any semiconductor package or external circuit in the horizontal direction of semiconductor structure 400. This allows the formation of a 3D package that occupies less area and also involves lower cost. In addition, this allows the interconnectivity to be extended in the vertical and horizontal directions. In addition, due to the shortened connection length, it consumes less power and maintains a higher interconnection speed.

[0093] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 may be different from the electrical signals output through the solder joint 496. The semiconductor structure 400 may be configured to provide significantly different electrical signals according to different design requirements.

[0094] Figure 5 A cross-sectional view of a semiconductor package having connections using wire bonding according to an embodiment of the present disclosure is shown. Figure 5 In, already Figure 4The corresponding elements are explained and not repeated.

[0095] Reference Figure 5 , the first semiconductor die 110 and the second semiconductor die 410 in the vertically stacked semiconductor structure 500 may be connected together using wire bonding 510 .

[0096] In vertically stacking two semiconductor dies (e.g., the first semiconductor die 110 and the second semiconductor die 410), the electrical connection between the top semiconductor die 110 and the bottom semiconductor die 410 can be accomplished using wire bonding 510. For example, the material used for the wire bonding 510 may include any metal capable of conducting electrical signals, such as Cu, Al, etc. Figure 4 In contrast to the solder joints 496 used in the embodiment of the present invention, the wire bonds 510 can electrically connect the extended first redistribution layer 150 of the top die 110 and the extended second redistribution layer 450 of the bottom die 410. In other embodiments, the wire bonds 510 can be used to connect the semiconductor die to other semiconductor packages or other external circuits (not shown).

[0097] The vertical stacking of the semiconductor structure 500 not only improves the interconnectivity in the 3D package and the 3D integrated circuit, but also saves space, which minimizes the total package size. The semiconductor structure 500 also improves horizontal connectivity by providing additional electrical contacts on the second surface 113 of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by wire bonding 510, and the wire can be used to connect to an external circuit or PCB according to industrial needs. With this configuration, the chip package can be stacked vertically and can be connected horizontally. This design improves the interconnectivity between chip modules and saves area occupancy. It also allows the formation of such a 3D package, which consumes less power due to the shortened connection length, but maintains a higher interconnection speed.

[0098] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 may be different from the electrical signals output through the wire bonding 510. The semiconductor structure 500 may be configured to provide significantly different electrical signals according to different design requirements.

[0099] FIG. 6A to FIG. 6I is a cross-sectional view illustrating an exemplary method of fabricating an extended redistribution layer according to an embodiment of the present disclosure.

[0100] In this embodiment, Fig. 6AIn the method, the method starts with a carrier substrate 602. A semiconductor die 604 is placed on the carrier substrate 602. For example, the semiconductor die 604 is attached to the carrier substrate 602 so that it is attached to the carrier substrate 602. The semiconductor die 604 includes a first surface 605, a second surface 607 that is transverse to the first surface 605, and a third surface 609 that is opposite to the first surface 605. The first surface 605 may refer to the top surface of the semiconductor die 604. The second surface 607 may refer to the side surface of the semiconductor die 604. In another embodiment, the first surface 605 and the second surface 607 may be perpendicular to each other. In other embodiments, the angle formed by the first surface 605 and the second surface 607 may be an inclined angle. In addition, in some embodiments, the first surface 605 and the third surface 609 may be located on opposite sides. For example, the first surface 605 and the third surface 609 may be parallel to each other, but they do not necessarily have to be parallel. In addition, the third surface 609 and the second surface 607 may be transverse to each other. Semiconductor die 604 may be made of, but is not limited to, a material such as Si or GaAs.

[0101] exist Figure 6B In the embodiment, a contact pad 606 is provided on a first surface 605 of a semiconductor die 604. In one embodiment, the contact pad 606 is disposed on a top surface of the semiconductor die 604. In this embodiment, the contact pad 606 may overlap an area of ​​the semiconductor die 604 and does not necessarily have a surface coplanar with the first surface 605 of the semiconductor die 604. However, in some embodiments, in order to minimize the overall height and thickness of the semiconductor structure, the contact pad 606 may be embedded in the semiconductor die 604 and may have a top surface coplanar with the semiconductor die 604. Embedding the contact pad 606 in the semiconductor die 604 may include: etching the semiconductor die 604 and depositing the contact pad 606 on the die 604. Therefore, in some embodiments, the contact pad 606 may be deposited on the semiconductor die 604 to a position below the top surface of the semiconductor die 604. In one embodiment, the contact pad 606 is a metal pad and is made of a conductive material including but not limited to Cu, Al, etc.

[0102] exist Figure 6C In the embodiment of the present invention, a passivation layer 608 is provided on the semiconductor die 604 and the contact pad 606. The passivation layer 608 can be deposited on the semiconductor die 604 and the contact pad 606 using various deposition methods known in the art. For example, the passivation layer 608 is made of SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The passivation layer 608 is used to protect the semiconductor die 604. Depending on the design, the passivation layer 608 can be omitted.

[0103] exist Fig.6D 6, the passivation layer 608 is partially removed to expose a portion of the contact pad 606. This partial removal of the passivation layer 608 creates an opening 610 and partially exposes the contact pad 606. By this removal, the passivation layer 608 overlaps the first portion 617 of the contact pad 606.

[0104] exist Fig. 6E In the embodiment, a first dielectric layer 612 is provided on the passivation layer 608 and in the opening 610 created by the partial removal of the passivation layer 608. The first dielectric layer 612 may be deposited using any deposition method known in the art. For example, the first dielectric layer 612 is disposed along the passivation layer 130 and the shape made by the opening 610. The first dielectric layer 612 is made of, but not limited to, PBO or PI.

[0105] exist Fig. 6F , a redistribution layer 616 is provided on the first dielectric layer 612. Before the redistribution layer 616 is deposited on the first dielectric layer 612, the first dielectric layer 612 is etched and removed to expose a portion of the contact pad 606. As a result of the removal, in one embodiment, the first dielectric layer 612 is disposed on the passivation layer 608 and on the second portion 619 of the contact pad 606. For example, the first dielectric layer 612 overlaps and contacts the second portion 619 of the contact pad 606.

[0106] In addition, after providing the first dielectric layer 612 and partially removing the first dielectric layer 612 to expose the contact pad 606, a mold protection layer 614 can be provided on the second surface 607 of the semiconductor die 604. The mold protection layer 614 is provided adjacent to the outer periphery of the semiconductor die 604. In one embodiment, the mold protection layer 614 surrounds the semiconductor die 604 to provide protection on the sidewalls of the semiconductor structure. For example, as shown, the mold protection layer 614 is positioned to cover the second surface 607 of the semiconductor die 604, the side of the passivation layer 608, and the side of the first dielectric layer 612. The process of forming the mold protection layer 614 can be performed using, for example, a compression molding process. The process is used to encapsulate the semiconductor die 604 by a molding compound while protecting the active surface of the die. For example, the molding compound can surround all exposed silicon die surfaces, while ignoring certain surfaces of the die. In some embodiments, the process of forming the mold protection layer 614 can be omitted based on industrial design requirements.

[0107] Return to reference Fig. 6F, a redistribution layer 616 is provided on a portion of the contact pad 606 and the first dielectric layer 612. In one embodiment, the redistribution layer 616 is disposed on the contact pad 606, the first dielectric layer 612, and the mold protection layer 614. For example, the redistribution layer 616 contacts the third portion 621 of the contact pad 606 and overlaps the passivation layer 608, the first dielectric layer 612, and the mold protection layer 614. The second portion 619 of the contact pad 606 is located between the first portion 617 and the third portion 621 of the pad 606. In one embodiment, the redistribution layer 616 includes an extension portion 626. In this embodiment, the redistribution layer 616 extends on the mold protection layer 614, completely covers the mold protection layer 614, and contacts the carrier substrate 602. The extended portion 626 of the redistribution layer 616 extends along the second surface 607 of the semiconductor die 604 so as to prevent the passivation layer 608 , the first dielectric layer 612 , and the mold protection layer 614 from being directly exposed.

[0108] In one embodiment, the redistribution layer 616 may be formed on one side of the semiconductor die 604. However, in different embodiments, the other end of the redistribution layer 616 may extend to the other side surface of the semiconductor die 604. That is, the redistribution layer 616 may extend along both sides of the semiconductor die 604 to provide electrical contacts on both sidewalls.

[0109] exist Fig. 6F , the extended portion 626 of depositing the redistribution layer 616 has been explained with respect to a semiconductor die 604 without a lip portion (not shown). However, the same process of forming the layer on the semiconductor die 604 can be applied to a die with a lip portion. In some embodiments, where the semiconductor die has a lip portion, the redistribution layer 616 can extend along the second surface of the semiconductor die 604, and for the sidewalls, just above the lip portion, so that the lip portion of the semiconductor die 604 is exposed. For example, the redistribution layer 616 may not extend all the way down along the second surface 607 (e.g., the sidewalls) and cover the lip portion of the semiconductor die 604. It can extend to cover the sides of the mold protection layer 614, which covers the sides of the passivation layer 608 and the sides of the first dielectric layer 612, but leaves the lip portion of the semiconductor die 604 open.

[0110] exist Figure 6GIn the embodiment, a second dielectric layer 618 is provided on the redistribution layer 616. In one embodiment, the second dielectric layer 618 overlaps the contact pad 606, the passivation layer 608, the first dielectric layer 612, and the redistribution layer 616. In one embodiment, the second dielectric layer 160 may only contact a portion of the redistribution layer 616. The second dielectric layer 618 may be made of the same material as the first dielectric layer 612 and may be deposited using the same method. The second dielectric layer 618 may be made of, but is not limited to, a material such as PBO or PI.

[0111] exist Figure 6H In the embodiment, a UBM 620 is provided on the second dielectric layer 618. In one embodiment, the UBM 620 is in direct contact with the redistribution layer 616 in a position spaced apart from the contact pad 606. For example, the redistribution layer 616 can be electrically and physically connected to the contact pad 606. This connection enables a conductive structure such as the UBM 620 to provide electrical signals to other input / output terminals such as a PCB or other external circuit (not shown). In this embodiment, the UBM 620 is located on the second dielectric layer 618 that does not overlap with the contact pad 606. However, in another embodiment, the position of the UBM 620 can overlap with the contact pad 606, or be located at a different position according to any design requirements. For example, the UBM 620 can be made of a metal, which includes, but is not limited to, for example, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0112] exist Fig.6I , solder balls 622 are provided on UBM 620. Solder balls 622 may include any conductive material capable of conducting electrical signals, and may include, for example, solder bumps, solder joints, wire bonds, etc. Any structure capable of conducting electrical signals will suffice and is not limited to solder balls.

[0113] Figure 7 A cross-sectional view of a scribed adjacent semiconductor structure is shown according to an embodiment of the present disclosure.

[0114] exist Figure 7 , a semiconductor structure 700 having two silicon dies is shown, with a first semiconductor die 704 and a second semiconductor die 804 placed adjacent to each other. It is obvious to a person skilled in the art that a plurality of semiconductor dies are mounted on a carrier substrate 702, 802 of a wafer. In this embodiment, as shown in FIG. Figure 7As shown, two silicon dies are attached to a carrier substrate. A first semiconductor die 704 is attached to a first carrier substrate 702, and a second semiconductor die 804 is attached to a second carrier substrate 802. The first carrier substrate 702 and the second carrier substrate 802 can be identical and can form a large single carrier substrate. The carrier substrate can have multiple semiconductor dies placed on top of the carrier substrate.

[0115] The semiconductor structure built on top of the carrier substrate 802 may be formed based on the same or similar processes used to form the semiconductor structure built on top of the carrier substrate 702. For example, contact pads (not shown), passivation layer 808, first dielectric layer 812, mold protection layer 814, redistribution layer 816, second dielectric layer 818, UBM 820, and solder balls 822 may be formed in the same or similar manner as explained in the previous embodiments.

[0116] In other embodiments, the process of forming the contact pad 706, the passivation layer 708, the first dielectric layer 712, the mold protection layer 714, the redistribution layer 716, the second dielectric layer 718, the UBM 720, the solder balls 722, etc. on the semiconductor die 704 can be in a single unified process for multiple semiconductor dies mounted on a carrier substrate. For example, the aforementioned elements and layers can be formed in a single process for each of the multiple semiconductor dies mounted on the carrier substrate. Thus, the same elements and layers formed on the semiconductor die 704 will be formed on the adjacent semiconductor die 804 and on any other multiple semiconductor dies mounted on the carrier substrates 702, 802. For example, the passivation layer 708 in the first semiconductor die 704 can be formed in the same process as the passivation layer 808 in the second semiconductor die 804. The passivation layers for all other semiconductor dies (not shown) on the carrier substrates 702, 802 can also be formed in the same single process.

[0117] An exemplary method of forming an extended redistribution layer on a semiconductor die is to form a redistribution layer on each of a plurality of semiconductor dies on a reconstructed wafer. In the reconstructed wafer, a plurality of semiconductor dies are mounted on the reconstructed wafer and are spaced apart from each of the plurality of semiconductor dies. The process of forming various layers on top of the plurality of semiconductor dies involved is as explained in conjunction with the previous embodiments. After forming the various layers (e.g., contact pads, passivation layer, first dielectric layer, mold protection layer, redistribution layer, second dielectric layer, UBM, solder balls, etc.), the semiconductor die with the redistribution layer and the adjacent semiconductor die with the redistribution layer are picked up and unloaded from a carrier substrate (not shown).

[0118] In other embodiments, the semiconductor die may have lip portions 705, 805, and the lip portion 705 of one semiconductor die 704 may be connected to the lip portion 805 of an adjacent semiconductor die 804, such as Figure 7 As shown. For these semiconductor dies, another exemplary method of forming an extended redistribution layer on a semiconductor die can be used. The exemplary method includes: forming a redistribution layer on each of a plurality of semiconductor dies on a half-cut wafer, and scribing a lip portion of each of adjacent semiconductor dies.

[0119] For example, in Figure 7 , the first semiconductor die 704 is connected to the second semiconductor die 804 through their respective lip portions 705, 805. The process of forming various layers on the first semiconductor die 704 and the second semiconductor die 804 includes the same similar process as that explained in conjunction with the relevant previous embodiments. After forming various layers (e.g., contact pads, passivation layers, first dielectric layers, mold protection layers, redistribution layers, second dielectric layers, UBMs, solder balls, etc.), the first semiconductor die 704 and the adjacent second semiconductor die 804 are cut along the scribe line 710. The cut line 710 cuts between the lip portion 705 of the first semiconductor die 704 and the lip portion 805 of the second semiconductor die 804. After cutting on the half-cut wafer along the scribe line 710, the first semiconductor die 704 and the adjacent second semiconductor die 804 are separated. Other multiple semiconductor dies mounted on the carrier substrate are cut in a similar manner. After singulating each of the plurality of semiconductor dies into individual semiconductor dies, the individual dies are detached from the carrier substrate 702, 802. Each semiconductor die includes an extended redistribution layer that allows for a large contact area at the chip sidewalls.

[0120] The various embodiments described above may be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are incorporated herein by reference in their entirety. If it is necessary to adopt the concepts of various patents, applications, and publications to provide other embodiments, various aspects of the embodiments may be modified.

[0121] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and equivalents to the full scope of the rights of the claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A device comprising: a semiconductor die including a first surface and a second surface lateral to the first surface, and including a third surface opposite to the first surface, the second surface being between the first surface and the third surface; a contact pad on the first surface of the semiconductor die; a passivation layer on the first surface of the semiconductor die; a redistribution layer, the redistribution layer being on the first surface of the semiconductor die and the contact pad, the redistribution layer having an extension portion, the extension portion extending from the contact pad to the second surface of the semiconductor die, the extension portion including a first electrical contact region on the second surface of the semiconductor die, the first electrical contact region being transverse to the first surface, the first electrical contact region being exposed from the passivation layer, the extension portion extending along the second surface toward the third surface, the extension portion and the first electrical contact region having ends terminating on the second surface of the semiconductor die; as well as A conductive structure is spaced apart from the contact pad on the redistribution layer, the conductive structure comprising a second electrical contact region on the first surface of the semiconductor die. 2 . The device of claim 1 , wherein the second electrical contact region comprises an under bump metallurgy structure, a solder ball, or a solder bump. 3 . The device according to claim 1 , wherein the first electrical contact region and the second electrical contact region provide electrical signals different from each other. 4 . The device of claim 1 , wherein the extension portion and the first electrical contact region extend beyond the first surface to the third surface of the semiconductor die, the end portion terminating at the third surface of the semiconductor die. 5 . The device of claim 1 , wherein the extension portion covers the second surface from the first surface to the third surface of the semiconductor die.

6. The device according to claim 1, wherein The passivation layer is between the redistribution layer and the semiconductor die, and the passivation layer overlaps a first portion of the contact pad.

7. The device according to claim 6, further comprising: A first dielectric layer, the first dielectric layer is between the redistribution layer and the passivation layer, the first dielectric layer overlaps with a second portion of the contact pad, the second portion is between the first portion of the contact pad and a third portion of the contact pad, the third portion of the contact pad contacts the redistribution layer.

8. The device according to claim 7, further comprising: a second dielectric layer, the second dielectric layer being on the redistribution layer; as well as The conductive structure comprises: A metallization layer is spaced apart from the contact pad on the redistribution layer.

9. The device according to claim 1, further comprising: A mold protection layer is between the second surface of the semiconductor die and the extending portion of the redistribution layer.

10. A device comprising: a first semiconductor die comprising a first surface, a second surface, and a third surface, the second surface being lateral to the first surface and the third surface; a first redistribution layer, the first redistribution layer being on the first surface of the first semiconductor die, the first redistribution layer having a first portion and a first extension portion, the first portion extending along the first surface toward the second surface, the first extension portion being on the second surface transversely to the first portion; A second semiconductor die, comprising a fourth surface, a fifth surface and a sixth surface, wherein the fifth surface is transverse to the fourth surface and the sixth surface, and the fourth surface faces the third surface; A second redistribution layer is on the sixth surface of the second semiconductor die, the second redistribution layer has a second portion and a second extending portion, the second portion extends along the sixth surface toward the fifth surface, and the second extending portion is spaced apart from the first extending portion.

11. The device according to claim 10, further comprising: A conductive connection electrically connects the first extension portion and the second extension portion.

12. The device of claim 11, wherein the conductive connection comprises a solder bump, a solder joint, a solder ball, or a wire bond. 13 . The device of claim 10 , wherein the first extension portion includes a first bonding surface on the second surface; and the second extension portion includes a second bonding surface on the fifth surface.

14. A method comprising: forming a contact pad on a first surface of the first semiconductor die; Forming a first redistribution layer on the first surface of the first semiconductor die and the contact pad, wherein forming the first redistribution layer comprises: forming an extension portion of the first redistribution layer, the extension portion of the first redistribution layer extending from the contact pad to the second surface of the first semiconductor die, extending along the second surface toward a third surface of the first semiconductor die opposite to the first surface, the extension portion having an end terminating on the second surface of the first semiconductor die and having a bonding surface exposed at the second surface, the bonding surface and the second surface being lateral to the first surface, the second surface being between the first surface and the third surface; as well as A conductive structure is formed on the first redistribution layer and is spaced apart from the contact pad.

15. The method according to claim 14, further comprising: forming a second redistribution layer on a fourth surface of the second semiconductor die, comprising: forming an extension portion of the second redistribution layer, the extension portion of the second redistribution layer extending from the fourth surface to a fifth surface of the second semiconductor die, An adhesive layer is formed between the first semiconductor die and the second semiconductor die.

16. The method according to claim 15, further comprising: The extending portion of the second redistribution layer is formed on the fifth surface of the second semiconductor die, the extending portion of the first redistribution layer being aligned with the extending portion of the second redistribution layer.

Images