Organic light emitting diode display device

Abstract

An organic light emitting diode display device includes a substrate, a buffer layer, a first circuit structure, a sub-pixel structure, and a first signal line. The substrate includes a display area and a peripheral area surrounding the display area, and the display area includes a plurality of sub-pixel areas. The buffer layer is disposed on the substrate in the display area and the peripheral area. The first circuit structure is disposed on the buffer layer in the peripheral area. The sub-pixel structure is disposed in each of the sub-pixel areas and on the first circuit structure. The first signal line is disposed between the substrate and the buffer layer in the peripheral area, and the first signal line overlaps with the first circuit structure when viewed from a plan view in the thickness direction of the substrate.

Description

Technical Field

[0001] The exemplary embodiments generally relate to an organic light emitting diode display device and more particularly to an organic light emitting diode display device including a signal line. Background Art

[0002] Flat panel display ("FPD") devices are widely used as display devices for electronic devices because they are lightweight and thin compared to cathode ray tube ("CRT") display devices. FPD devices include liquid crystal display ("LCD") devices and organic light emitting diode ("OLED") display devices.

[0003] An OLED display device may have a display area in which an image is displayed and a peripheral area in which a gate driver, a data driver, a plurality of signal lines, etc. are disposed. In such an OLED display device, the peripheral area may substantially surround the display area. A plurality of transistors may be disposed in the gate driver, and a signal line (e.g., a data signal line) may be disposed adjacent to the gate driver. Summary of the invention

[0004] As the size and resolution of an organic light emitting diode ("OLED") display device increases, the number of transistors and data signal lines included in a gate driver disposed in a peripheral region (eg, a dead region) may increase relatively. In this case, the area of ​​the peripheral region may increase.

[0005] An exemplary embodiment provides an OLED display device including a signal line.

[0006] According to an exemplary embodiment, an OLED display device includes a substrate, a buffer layer, a first circuit structure, a sub-pixel structure, and a first signal line. In such an embodiment, the substrate has a display area including a plurality of sub-pixel areas and a peripheral area surrounding the display area. In such an embodiment, the buffer layer is disposed on the substrate in the display area and the peripheral area. In such an embodiment, the first circuit structure is disposed on the buffer layer in the peripheral area. In such an embodiment, the sub-pixel structure is disposed in each of the sub-pixel areas and on the first circuit structure. In such an embodiment, the first signal line is disposed between the substrate and the buffer layer in the peripheral area, and the first signal line overlaps with the first circuit structure when viewed from a plan view in the thickness direction of the substrate.

[0007] In an exemplary embodiment, the OLED display device may further include a switching transistor disposed on the buffer layer in the sub-pixel region and a driving transistor spaced apart from the switching transistor.

[0008] In an exemplary embodiment, the switching transistor may include a first active layer disposed on the substrate in the sub-pixel region, a first gate electrode disposed on the first active layer, and a first source electrode and a first drain electrode disposed on the first gate electrode.

[0009] In an exemplary embodiment, the driving transistor may include a second active layer spaced apart from the first active layer, a second gate electrode disposed on the second active layer, and a second source electrode and a second drain electrode disposed on the second gate electrode.

[0010] In an exemplary embodiment, the first circuit structure may include: a gate driver including a first transistor.

[0011] In exemplary embodiments, the gate driver may provide a gate signal to a first gate electrode of the switching transistor.

[0012] In an exemplary embodiment, the OLED display device may further include a second circuit structure spaced apart from the first circuit structure on the substrate in the peripheral region.

[0013] In an exemplary embodiment, the second circuit structure may include a light emitting driver including a second transistor spaced apart from the first circuit structure.

[0014] In an exemplary embodiment, the OLED display device may further include a second signal line spaced apart from the first signal line between the substrate and the buffer layer in the peripheral region. In such an embodiment, when viewed from a plan view in the thickness direction of the substrate, the second signal line may overlap with the second circuit structure.

[0015] In an exemplary embodiment, the first signal line may include a clock signal line to which a clock signal is applied, and the clock signal may be provided to the first circuit structure and the second circuit structure. In such an embodiment, the second signal line may include a driving power supply line to which a driving power supply is applied, and the driving power supply may be provided to the first circuit structure and the second circuit structure.

[0016] In an exemplary embodiment, the OLED display device may further include a power supply line spaced apart from the first circuit structure on the buffer layer in the peripheral region, and a connection pattern disposed on the power supply line.

[0017] In exemplary embodiments, the power supply line may be electrically connected to the sub-pixel structure through a connection pattern.

[0018] In an exemplary embodiment, the OLED display device may further include a blocking structure disposed on the outermost middle substrate in the peripheral region.

[0019] In an exemplary embodiment, the prevention structure may include a first prevention pattern disposed on the connection pattern and a second prevention pattern spaced apart from the first prevention pattern. In such an embodiment, the second prevention pattern may surround the first prevention pattern.

[0020] In an exemplary embodiment, the sub-pixel structure may include a lower electrode disposed on a substrate, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer. In such an embodiment, the upper electrode may be electrically connected to the connection pattern.

[0021] In exemplary embodiments, the substrate may include a first organic layer, a first barrier layer disposed on the first organic layer, a second organic layer disposed on the first barrier layer, and a second barrier layer disposed on the second organic layer.

[0022] In an exemplary embodiment, the OLED display device may further include a thin film encapsulation structure disposed on the sub-pixel structure, and the thin film encapsulation structure may include a first thin film encapsulation layer, a second thin film encapsulation layer, and a third thin film encapsulation layer. In such an embodiment, the first thin film encapsulation layer may include an inorganic material having flexibility. In such an embodiment, the second thin film encapsulation layer may be disposed on the first thin film encapsulation layer and may include an organic material having flexibility. In such an embodiment, the third thin film encapsulation layer may be disposed on the second thin film encapsulation layer and may include an inorganic material having flexibility.

[0023] According to an exemplary embodiment, an OLED display device includes a substrate, a sub-pixel structure, a first circuit structure, and a signal line. In such an embodiment, the substrate has a display area including a plurality of sub-pixel areas and a peripheral area surrounding the display area. In such an embodiment, the sub-pixel structure is disposed on each of the sub-pixel areas on the substrate. In such an embodiment, the first circuit structure is disposed on the substrate in the peripheral area. In such an embodiment, the signal line is disposed in the substrate in the peripheral area, and the signal line overlaps with the first circuit structure when viewed from a plan view in the thickness direction of the substrate.

[0024] In exemplary embodiments, the substrate may include a plurality of layers, and the first signal line may be interposed between the plurality of layers.

[0025] In an exemplary embodiment, the OLED display device may further include a switching transistor disposed on the substrate in the sub-pixel region and a driving transistor spaced apart from the switching transistor. In such an embodiment, the first circuit structure may include: a gate driver including the first transistor, and the gate driver may provide a gate signal to a gate electrode of the switching transistor.

[0026] In such an embodiment, the OLED display device includes a first signal line and a second signal line that are arranged to overlap with the first circuit structure and the second circuit structure respectively, so that the OLED display device can relatively reduce the width of the border corresponding to the non-display area, or can relatively increase the area of ​​the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present invention will become more apparent through the following description of detailed embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1A is a plan view showing an organic light emitting diode ("OLED") display device according to an exemplary embodiment;

[0029] Figure 1B is with Figure 1A An enlarged plan view of a portion corresponding to a region “A” of an OLED display device;

[0030] Figure 2 is shown electrically connected to Figure 1A A block diagram of external devices of an OLED display device;

[0031] Figure 3A It is shown Figure 1A a circuit diagram of a gate level included in the first circuit structure;

[0032] Figure 3B It is shown Figure 1A A circuit diagram of a light emitting stage included in a second circuit structure;

[0033] Figure 3C It shows that the setting Figure 1A A circuit diagram of a sub-pixel circuit and an OLED in a sub-pixel region;

[0034] Figure 4 is along Figure 1A A cross-sectional view taken along line II';

[0035] Figure 5A It is shown Figure 4 A cross-sectional view of a connection between a first transistor and a first signal line included in an OLED display device;

[0036] Figure 5B It is shown Figure 4 A cross-sectional view of a connection between a second transistor and a second signal line included in an OLED display device;

[0037] Figures 6 to 11 is a cross-sectional view illustrating a method of manufacturing an OLED display device according to an exemplary embodiment; and

[0038] Fig.12is a cross-sectional view showing an OLED display device according to an alternative exemplary embodiment. DETAILED DESCRIPTION

[0039] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various exemplary embodiments are shown. However, the present invention may be embodied in a variety of different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the disclosure comprehensive and complete and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0040] It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0041] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited to these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be named as the second element, component, region, layer or part without departing from the teachings of this article.

[0042] The purpose of the terms used herein is to describe only specific embodiments and is not intended to be limiting. As used herein, the singular forms "one" and "said" are intended to include plural forms, including "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". "At least one of A and B" means "A and / or B". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It is further understood that the terms "include" and / or "comprising" when used in this specification indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their combinations.

[0043] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in one of the drawings is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawings, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in one of the drawings is turned over, the element described as being "below" or "below" the other elements will be oriented "above" the other elements. Therefore, the exemplary term "below" or "below" can include both upper and lower orientations.

[0044] As used herein, "about" or "approximately" includes the stated value and the average within an acceptable deviation from the particular value as determined by one of ordinary skill in the art, taking into account relevant measurements and errors associated with measurement of a particular quantity.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with that in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense, unless such a definition is explicitly made herein.

[0046] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, changes in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be interpreted as limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp angles shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, nor are they intended to limit the scope of the claims.

[0047] Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0048] Figure 1A is a plan view showing an organic light emitting diode ("OLED") display device according to an exemplary embodiment, and Figure 1B is with Figure 1A FIG. 1 is an enlarged plan view of a portion corresponding to a region “A” of an OLED display device. Figure 2 is shown electrically connected to Figure 1AA block diagram of the external devices of an OLED display device.

[0049] refer to Figure 1A , Figure 1B and Figure 2 , an exemplary embodiment of the OLED display device 100 may include a display area 10 and a peripheral area 20 surrounding the display area 10. In such an embodiment, the display area 10 may include a plurality of sub-pixel areas 30. The sub-pixel areas 30 may be arranged in a matrix form throughout the display area 10.

[0050] The first circuit structure 800 and the second circuit structure 600 may be disposed in a side portion of the peripheral region 20 (eg, a left side of the display region 10), and the first circuit structure 800 may be disposed closer to the display region 10 than the second circuit structure 600. The first circuit structure 800 may include a plurality of gates (eg, Figure 3A The gate stage GST), and the second circuit structure 600 may include a plurality of light emitting stages (eg, Figure 3B In an exemplary embodiment, Figure 1B As shown in FIG. , first signal lines 710, 711, and 712 (eg, Figure 4 The first signal line 710 of the embodiment may be disposed under the first circuit structure 800, and the second signal lines 510, 511, and 512 (eg, Figure 4 The second signal line 510 of the embodiment may be disposed under the second circuit structure 600. In such an embodiment, the first signal lines 710, 711, and 712 may include clock signal lines, and the second signal lines 510, 511, and 512 may include high power lines. In such an embodiment, a clock signal may be applied to the first signal lines 710, 711, and 712, and a high power may be applied to the second signal lines 510, 511, and 512. In such an embodiment, the first signal lines 710, 711, and 712 may electrically connect the first circuit structure 800 and the second circuit structure 600 to each other, and the second signal lines 510, 511, and 512 may electrically connect the first circuit structure 800 and the second circuit structure 600 to each other. In such an embodiment, the first signal lines 710, 711, and 712 may provide a clock signal to the first circuit structure 800 and the second circuit structure 600, and the second signal lines 510, 511, and 512 may provide a high power to the first circuit structure 800 and the second circuit structure 600.

[0051] In an exemplary embodiment, if Figure 1A and Figure 1B As shown in , each of the first signal line and the second signal line includes three lines, but is not limited thereto. In an exemplary embodiment, each of the first signal line and the second signal line may include at least one line, for example, one, two or four lines.

[0052] The plurality of pad electrodes 470 may be disposed in another side portion of the peripheral region 20 (e.g., the bottom or lower portion of the display region 10). Alternatively, the first circuit structure 800 and the second circuit structure 600 may be disposed in the peripheral region 20 on the right side or top of the display region 10. In an exemplary embodiment, the OLED display device 100 may further include a data driver, a timing controller, etc., and the data driver, the timing controller, etc. may be disposed in the peripheral region 20.

[0053] Sub-pixel circuits (e.g., Figure 3C SUB-PIXEL CIRCUIT) may be provided in each of the sub-pixel regions 30 of the display region 10, and an OLED (eg, Figure 3C An OLED) may be disposed on the sub-pixel circuit. An image (or a display image) may be displayed in the display area 10 through the sub-pixel circuit and the OLED.

[0054] The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit may be disposed in the sub-pixel region 30. In an exemplary embodiment, for example, the first sub-pixel circuit may be coupled to (or connected to) a first OLED capable of emitting red light, and the second sub-pixel circuit may be coupled to a second OLED capable of emitting green light. The third sub-pixel circuit may be coupled to a third OLED capable of emitting blue light.

[0055] In an exemplary embodiment, the first OLED may be arranged to overlap with the first sub-pixel circuit, and the second OLED may be arranged to overlap with the second sub-pixel circuit. The third OLED may be arranged to overlap with the third sub-pixel circuit. Alternatively, the first OLED may be arranged to overlap with a portion of the first sub-pixel circuit and a portion of a sub-pixel circuit different from the first sub-pixel circuit, and the second OLED may be arranged to overlap with a portion of the second sub-pixel circuit and a portion of a sub-pixel circuit different from the second sub-pixel circuit. The third OLED may be arranged to overlap with a portion of the third sub-pixel circuit and a portion of a sub-pixel circuit different from the third sub-pixel circuit.

[0056] In an exemplary embodiment, for example, the first OLED, the second OLED and the third OLED may be arranged based on an RGB stripe method in which quadrilaterals of the same size are sequentially arranged, an S stripe method including a blue OLED having a relatively large area, a WRGB method further including a white OLED, a honeycomb method repeatedly arranged in an RG-GB pattern, and the like.

[0057] In an exemplary embodiment, at least one driving transistor, at least one switching transistor, and at least one capacitor may be provided in each of the sub-pixel regions 30. In an exemplary embodiment, for example, a single driving transistor (eg, Figure 3C The first transistor TR1), six switch transistors (eg, Figure 3C The second to seventh transistors TR2, TR3, TR4, TR5, TR6 and TR7) and a single storage capacitor (eg, Figure 3C A storage capacitor CST) may be provided in each of the sub-pixel regions 30.

[0058] In an exemplary embodiment, when viewed from a plan view in the thickness direction of the OLED display device 100, the shape of each of the display area 10, the peripheral area 20, and the sub-pixel area 30 has a quadrangular planar shape, but is not limited thereto. In an exemplary embodiment, for example, the shape of each of the display area 10, the peripheral area 20, and the sub-pixel area 30 may have a triangular planar shape, a rhombus planar shape, a polygonal planar shape, a circular planar shape, a racetrack planar shape, an elliptical planar shape, etc.

[0059] The external device 101 may be electrically connected to the OLED display device 100 via a flexible printed circuit board ("FPCB"). In an exemplary embodiment, for example, one side of the FPCB may be in direct contact with the pad electrode 470, and the other side of the FPCB may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emitting signal, a gate initialization signal, an initialization voltage, a power supply, etc. to the OLED display device 100. In an exemplary embodiment, a driver integrated circuit may be mounted (or arranged) in the FPCB. In an exemplary embodiment, the driver integrated circuit may be mounted in the OLED display device 100 and positioned adjacent to the pad electrode 470. Alternatively, the OLED display device 100 includes a bending area, and the pad electrode 470 and the external device 101 may be electrically connected via the FPCB.

[0060] The first circuit structure 800 may include a gate driver, and the gate driver may include a plurality of gate stages (eg, Figure 3A Each gate includes at least one transistor (eg, Figure 4 The first circuit structure 800 may receive a gate signal from the external device 101, and the gate signal may be provided to the sub-pixel circuit through a gate level of a gate driver.

[0061] The second circuit structure 600 may include a light emitting driver, and the light emitting driver may include a plurality of light emitting stages (eg, Figure 3Blight-emitting stages EST), each of which includes at least one transistor (e.g., Figure 4 The second circuit structure 600 may receive a light emission signal from the external device 101, and the light emission signal may be provided to the sub-pixel circuit through the light emission stage of the light emission driver.

[0062] Figure 3A It is shown Figure 1A A circuit diagram of a gate stage included in the first circuit structure.

[0063] refer to Figure 3A , an exemplary embodiment of the gate stage GST may include a first driver 1210 , a second driver 1220 , and an output circuit 1230 .

[0064] The output circuit 1230 may include a fifth transistor M5 and a sixth transistor M6. The output circuit 1230 may control the voltage supplied to the output terminal 1004 based on the first node N1 and the second node N2. The fifth transistor M5 may be coupled between the first driving power supply VDD line (e.g., a high power supply line) and the output terminal 1004, and the gate electrode of the fifth transistor M5 may be coupled to the first node N1. The fifth transistor M5 may control the connection between the first driving power supply VDD line and the output terminal 1004 based on the voltage applied to the first node N1. The sixth transistor M6 may be coupled between the output terminal 1004 and the third input terminal 1003, and the gate electrode of the sixth transistor M6 may be coupled to the second node N2. The sixth transistor M6 may control the connection between the output terminal 1004 and the third input terminal 1003 based on the voltage applied to the second node N2. The output circuit 1230 may operate as a buffer. Alternatively, the fifth transistor M5 and / or the sixth transistor M6 may have a configuration in which a plurality of transistors are coupled in parallel to each other.

[0065] The first driver 1210 may include a second transistor M2, a third transistor M3, and a fourth transistor M4. The first driver 1210 may control the voltage of the third node N3 based on the clock signal supplied to the first input terminal 1001, the second input terminal 1002, and the third input terminal 1003. The second transistor M2 may be coupled between the first input terminal 1001 and the third node N3, and the gate electrode of the second transistor M2 may be coupled to the second input terminal 1002. The second transistor M2 may control the connection between the first input terminal 1001 and the third node N3 based on the clock signal supplied to the second input terminal 1002. The third transistor M3 and the fourth transistor M4 may be coupled in series between the third node N3 and the first driving power supply VDD line. The third transistor M3 may be coupled between the fourth transistor M4 and the third node N3, and the gate electrode of the third transistor M3 may be coupled to the third input terminal 1003. The third transistor M3 may control the connection between the fourth transistor M4 and the third node N3 based on the clock signal supplied to the third input terminal 1003. The fourth transistor M4 may be coupled between the third transistor M3 and the first driving power supply VDD line, and a gate electrode of the fourth transistor M4 may be coupled to the first node N1. The fourth transistor M4 may control the connection of the third transistor M3 and the first driving power supply VDD line based on the voltage of the first node N1.

[0066] The second driver 1220 may include a first transistor M1, a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2. The second driver 1220 may control the voltage of the first node N1 based on the voltage of the second input terminal 1002 and the third node N3. The first capacitor C1 may be coupled between the second node N2 and the output terminal 1004. The first capacitor C1 may charge the voltage based on the conduction and cutoff of the sixth transistor M6. The second capacitor C2 may be coupled between the first node N1 and the first driving power supply VDD line. The second capacitor C2 may charge the voltage applied to the first node N1. The seventh transistor M7 may be coupled between the first node N1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 may be coupled to the third node N3. The seventh transistor M7 may control the connection of the first node N1 and the second input terminal 1002 based on the voltage of the third node N3. The eighth transistor M8 may be coupled between the first node N1 and a second driving power supply VSS line (e.g., a low power supply line), and a gate electrode of the eighth transistor M8 may be coupled to the second input terminal 1002. The eighth transistor M8 may control the connection of the first node N1 and the second driving power supply VSS line based on the clock signal of the second input terminal 1002.

[0067] The first transistor M1 may be coupled between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 may be coupled to the second driving power supply VSS line. When the first transistor M1 remains in the on state, the electrical connection between the third node N3 and the second node N2 may be maintained. Alternatively, the first transistor M1 may limit the degree of reduction of the voltage of the third node N3 based on the voltage of the second node N2. In such an embodiment, even when the voltage of the second node N2 is reduced to a voltage lower than the voltage of the second driving power supply VSS, the voltage of the third node N3 may not drop below the threshold voltage of the second driving power supply VSS minus the first transistor M1.

[0068] Therefore, the first input terminal 1001, the second input terminal 1002, and the third input terminal 1003 can be electrically connected to the first signal lines 710, 711, and 712, and the first driving power supply VDD line can be electrically connected to the second signal lines 510, 511, and 512. In such an embodiment, when the clock signal applied to the first signal lines 710, 711, and 712 is provided to the first input terminal 1001, the second input terminal 1002, and the third input terminal 1003, the gate signal (for example, Figure 3C The gate signal GW) can be output to the output terminal 1004.

[0069] Figure 3B It is shown Figure 1A A circuit diagram of a light emitting stage included in the second circuit structure.

[0070] refer to Figure 3B , an exemplary embodiment of the light emitting stage EST may include a first signal processor 2100 , a second signal processor 2200 , a third signal processor 2300 , and an output circuit 2400 .

[0071] The first signal processor 2100 may include a first transistor M11, a second transistor M12, and a third transistor M13. The first signal processor 2100 may control the voltages of the first node N21 and the second node N22 based on the clock signal supplied to the first input terminal 2001 and the second input terminal 2002. The first transistor M11 may be coupled between the first input terminal 2001 and the first node N21, and the gate electrode of the first transistor M11 may be coupled to the second input terminal 2002. When the clock signal is supplied to the second input terminal 2002, the first transistor M11 may be turned on. The second transistor M12 may be coupled between the second input terminal 2002 and the second node N22, and the gate electrode of the second transistor M12 may be coupled to the first node N21. The second transistor M12 may be turned on or off based on the voltage of the first node N21. The third transistor M13 may be coupled between the second driving power supply VSS line and the second node N22, and the gate electrode of the third transistor M13 may be coupled to the second input terminal 2002. When the clock signal is supplied to the second input terminal 2002 , the third transistor M13 may be turned on.

[0072] The second signal processor 2200 may include a fourth transistor M14, a fifth transistor M15, a sixth transistor M16, a seventh transistor M17, a first capacitor C11, and a second capacitor C12. The second signal processor 2200 may control the voltages of the first node N21 and the third node N23 based on the clock signal supplied to the third input terminal 2003 and the voltage of the second node N22. The fourth transistor M14 may be coupled between the fifth transistor M15 and the first node N21, and the gate electrode of the fourth transistor M14 may be coupled to the third input terminal 2003. When the clock signal is supplied to the third input terminal 2003, the fourth transistor M14 may be turned on. The fifth transistor M15 may be coupled between the first driving power supply VDD line and the fourth transistor M14, and the gate electrode of the fifth transistor M15 may be coupled to the second node N22. The fifth transistor M15 may be turned on or off based on the voltage of the second node N22. The sixth transistor M16 may be coupled between the first electrode of the seventh transistor M17 and the third input terminal 2003, and the gate electrode of the sixth transistor M16 may be coupled to the second node N22. The sixth transistor M16 may be turned on or off based on the voltage of the second node N22. The seventh transistor M17 may be coupled between the first electrode of the sixth transistor M16 and the third node N23, and the gate electrode of the seventh transistor M17 may be coupled to the third input terminal 2003. When the clock signal is supplied to the third input terminal 2003, the seventh transistor M17 may be turned on. The first capacitor C11 may be coupled between the first node N21 and the third input terminal 2003. The second capacitor C12 may be coupled between the second node N22 and the first electrode of the seventh transistor M17.

[0073] The third signal processor 2300 may include an eighth transistor M18 and a third capacitor C13. The third signal processor 2300 may control the voltage of the third node N23 based on the voltage of the first node N21. The eighth transistor M18 may be coupled between the first driving power supply VDD line and the third node N23, and the gate electrode of the eighth transistor M18 may be coupled to the first node N21. The eighth transistor M18 may be turned on or off based on the voltage of the first node N21. The third capacitor C13 may be coupled between the first driving power supply VDD line and the third node N23.

[0074] The output circuit 2400 may include a ninth transistor M19 and a tenth transistor M20. The output circuit 2400 may control the voltage supplied to the output terminal 2004 based on the voltage of the first node N21 and the third node N23. The ninth transistor M19 may be coupled between the first drive power supply VDD line and the output terminal 2004, and the gate electrode of the ninth transistor M19 may be coupled to the third node N23. The ninth transistor M19 may be turned on or off based on the voltage of the third node N23. The tenth transistor M20 may be coupled between the output terminal 2004 and the second drive power supply VSS line, and the gate electrode of the tenth transistor M20 may be coupled to the first node N21. The tenth transistor M20 may be turned on or off based on the voltage of the first node N21. The output circuit 2400 may operate as a buffer. Alternatively, the ninth transistor M19 and / or the tenth transistor M20 may have a configuration in which a plurality of transistors are coupled in parallel to each other.

[0075] Therefore, the first input terminal 2001, the second input terminal 2002, and the third input terminal 2003 can be electrically connected to the first signal lines 710, 711, and 712, and the first driving power supply VDD line can be electrically connected to the second signal lines 510, 511, and 512. In such an embodiment, when the clock signal applied to the first signal lines 710, 711, and 712 is provided to the first input terminal 2001, the second input terminal 2002, and the third input terminal 2003, the light emitting signal (for example, Figure 3C The luminous signal EM) can be output to the output terminal 2004.

[0076] Figure 3C It shows that the setting Figure 1A A circuit diagram of a sub-pixel circuit and an OLED in a sub-pixel area.

[0077] refer to Figure 3C , sub-pixel circuit ("SPC") and OLED (eg, corresponding to Figure 4 The sub-pixel structure 200 of the OLED display device 100 may be disposed in each of the sub-pixel regions 30 of the OLED display device 100, and the OLED may be disposed on the SPC. The SPC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, and a seventh transistor TR7, a storage capacitor CST, a high power supply voltage ELVDD line, a low power supply voltage ELVSS line, an initialization voltage VINT line, a data signal DATA line, a gate signal GW line, a gate initialization signal GI line, a light emitting signal EM line, a diode initialization signal GB line, and the like.

[0078] The OLED may emit light based on a driving current ID. The OLED may include a first terminal and a second terminal. In an exemplary embodiment, the second terminal of the OLED receives a low power supply voltage ELVSS. In an exemplary embodiment, for example, the first terminal of the OLED is an anode terminal, and the second terminal of the OLED is a cathode terminal. Alternatively, the first terminal of the OLED may be a cathode terminal, and the second terminal of the OLED may be an anode terminal. In an exemplary embodiment, the anode terminal of the OLED may correspond to Figure 4 The lower electrode 290 of the OLED may correspond to the cathode terminal of the OLED. Figure 4 The upper electrode 340 is provided.

[0079] The first transistor TR1 (eg, Figure 4 The driving transistor 253) may include a gate terminal, a first terminal, and a second terminal. In an exemplary embodiment, the first terminal of the first transistor TR1 is a source terminal, and the second terminal of the first transistor TR1 is a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0080] The driving current ID may be generated by the first transistor TR1. In an exemplary embodiment, the first transistor TR1 operates in a saturation region. In such an embodiment, the first transistor TR1 may generate the driving current ID based on the voltage difference between the gate terminal and the source terminal, and the grayscale (e.g., the brightness of the light corresponding to the grayscale level of the image to be displayed by the sub-pixel) may be implemented based on the amount of the driving current ID generated by the first transistor TR1. Alternatively, the first transistor TR1 operates in a linear region. In such an embodiment, the grayscale may be implemented based on the amount of time that the first transistor TR1 provides the driving current ID to the OLED within a frame.

[0081] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. A gate signal GW may be applied to the gate terminal of the second transistor TR2. The first terminal of the second transistor TR2 may receive the data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. In an exemplary embodiment, for example, the gate signal GW may be provided from a first terminal included in the Figure 1A The gate level GST in the first circuit structure 800 is generated and can be applied to the gate terminal of the second transistor TR2 through the gate signal GW line. In an exemplary embodiment, the first terminal of the second transistor TR2 is a source terminal, and the second terminal of the second transistor TR2 is a drain terminal. Alternatively, the first terminal of the second transistor TR2 can be a drain terminal, and the second terminal of the second transistor TR2 can be a source terminal.

[0082] In an exemplary embodiment, the second transistor TR2 may provide the data signal DATA to the first terminal of the first transistor TR1 when the gate signal GW is activated (or turned on). In such an embodiment, the second transistor TR2 operates in a linear region.

[0083] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may receive a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. In an exemplary embodiment, for example, the gate signal GW may be received from Figure 1A The first circuit structure 800 is generated, and the gate signal GW can be applied to the gate terminal of the third transistor TR3 through the gate signal GW line. In an exemplary embodiment, the first terminal of the third transistor TR3 is a source terminal, and the second terminal of the third transistor TR3 is a drain terminal. Alternatively, the first terminal of the third transistor TR3 can be a drain terminal, and the second terminal of the third transistor TR3 can be a source terminal.

[0084] In an exemplary embodiment, the third transistor TR3 can connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 when the gate signal GW is activated. In such an embodiment, the third transistor TR3 operates in a linear region. In such an embodiment, the third transistor TR3 can form a diode connection of the first transistor TR1 when the gate signal GW is activated. Due to the diode connection of the first transistor TR1, a voltage difference corresponding to the threshold voltage of the first transistor TR1 may occur between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1. As a result, when the gate signal GW is activated, the sum voltage of the data signal DATA provided to the first terminal of the first transistor TR1 and the voltage difference (i.e., the threshold voltage) can be applied to the gate terminal of the first transistor TR1. Therefore, the data signal DATA can be compensated for as much as the threshold voltage of the first transistor TR1. The compensated data signal DATA can be applied to the gate terminal of the first transistor TR1. The uniformity of the drive current ID can be improved by effectively preventing or fully reducing the influence of the threshold voltage of the first transistor TR1.

[0085] An input terminal of an initialization voltage VINT line to which the initialization voltage VINT is applied is connected to first terminals of the fourth transistor TR4 and the seventh transistor TR7 , and an output terminal of the initialization voltage VINT line is connected to a second terminal of the fourth transistor TR4 and a first terminal of the storage capacitor CST.

[0086] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may receive a gate initialization signal GI. An initialization voltage VINT may be applied to the first terminal of the fourth transistor TR4. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an exemplary embodiment, the first terminal of the fourth transistor TR4 is a source terminal, and the second terminal of the fourth transistor TR4 is a drain terminal. Alternatively, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0087] When the gate initialization signal GI is activated, the fourth transistor TR4 may apply the initialization voltage VINT to the gate terminal of the first transistor TR1. In such an embodiment, the fourth transistor TR4 may operate in a linear region. Therefore, when the gate initialization signal GI is activated, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT. In an exemplary embodiment, the voltage level of the initialization voltage VINT is sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame. In such an embodiment, the initialization voltage VINT may be applied to the gate terminal of the first transistor TR1 which is a P-channel metal oxide semiconductor ("PMOS") type transistor. In an alternative exemplary embodiment, the voltage level of the initialization voltage VINT is sufficiently higher than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame. In such an embodiment, the initialization voltage VINT may be applied to the gate terminal of the first transistor TR1 which is an N-channel metal oxide semiconductor ("NMOS") type transistor.

[0088] In an exemplary embodiment, the gate initialization signal GI is the same as the gate signal GW advanced or phase-shifted by one horizontal time period. In an exemplary embodiment, for example, the gate initialization signal GI applied to the SPC located in the nth row (where n is an integer of 2 or greater) among the multiple SPCs included in the OLED display device 100 may be substantially the same as the gate signal GW applied to the SPC located in the n-1th row among the multiple SPCs. In such an embodiment, the activated gate initialization signal GI may be applied to the SPC located in the nth row among the SPCs by applying the activated gate signal GW to the SPC located in the n-1th row among the SPCs. As a result, when the data signal DATA is applied to the SPC located in the n-1th row among the SPCs, the gate terminal of the first transistor TR1 included in the SPC located in the nth row among the SPCs may be initialized to the initialization voltage VINT.

[0089] The fifth transistor TR5 (eg, corresponding to Figure 4The switching transistor 250 may include a gate terminal, a first terminal, and a second terminal. The light emitting signal EM may be applied to the gate terminal of the fifth transistor TR5. The high power supply voltage ELVDD may be applied to the first terminal of the fifth transistor TR5. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1. In an exemplary embodiment, for example, the light emitting signal EM may be applied from the gate terminal of the fifth transistor TR5. Figure 1A The light emission level EST is generated in the second circuit structure 600 and can be applied to the gate terminal of the fifth transistor TR5 through the light emission signal EM line. In an exemplary embodiment, the first terminal of the fifth transistor TR5 is a source terminal, and the second terminal of the fifth transistor TR5 is a drain terminal. In an alternative exemplary embodiment, the first terminal of the fifth transistor TR5 can be a drain terminal, and the second terminal of the fifth transistor TR5 can be a source terminal.

[0090] When the light emitting signal EM is activated, the fifth transistor TR5 may apply the high power supply voltage ELVDD to the first terminal of the first transistor TR1, and when the light emitting signal EM is deactivated, the fifth transistor TR5 may not apply the high power supply voltage ELVDD. In such an embodiment, the fifth transistor TR5 may operate in a linear region. When the light emitting signal EM is activated, the fifth transistor TR5 may apply the high power supply voltage ELVDD to the first terminal of the first transistor TR1, so that the first transistor TR1 generates a driving current ID. In such an embodiment, when the light emitting signal EM is deactivated, the fifth transistor TR5 may not apply the high power supply voltage ELVDD, so that the data signal DATA applied to the first terminal of the first transistor TR1 is applied to the gate terminal of the first transistor TR1.

[0091] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The light emitting signal EM may be applied to the gate terminal of the sixth transistor TR6. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the OLED. In an exemplary embodiment, for example, the light emitting signal EM may be applied to the gate terminal of the sixth transistor TR6. Figure 1A The second circuit structure 600 is generated and can be applied to the gate terminal of the sixth transistor TR6 through the luminous signal EM line. In an exemplary embodiment, the first terminal of the sixth transistor TR6 is a source terminal, and the second terminal of the sixth transistor TR6 is a drain terminal. In an alternative exemplary embodiment, the first terminal of the sixth transistor TR6 can be a drain terminal, and the second terminal of the sixth transistor TR6 can be a source terminal.

[0092] When the light emitting signal EM is activated, the sixth transistor TR6 may provide the driving current ID generated by the first transistor TR1 to the OLED. In such an embodiment, the sixth transistor TR6 may operate in a linear region. In such an embodiment, when the light emitting signal EM is activated, the sixth transistor TR6 may provide the driving current ID generated by the first transistor TR1 to the OLED, so that the OLED emits light. In such an embodiment, when the light emitting signal EM is deactivated, the sixth transistor TR6 may electrically disconnect the first transistor TR1 from the OLED, so that the compensated data signal DATA applied to the second terminal of the first transistor TR1 is applied to the gate terminal of the first transistor TR1.

[0093] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. A diode initialization signal GB may be applied to the gate terminal of the seventh transistor TR7. An initialization voltage VINT may be applied to the first terminal of the seventh transistor TR7. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the OLED. In an exemplary embodiment, the first terminal of the seventh transistor TR7 is a source terminal, and the second terminal of the seventh transistor TR7 is a drain terminal. In an alternative exemplary embodiment, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0094] When the diode initialization signal GB is activated, the seventh transistor TR7 can apply the initialization voltage VINT to the first terminal of the OLED. In such an embodiment, the seventh transistor TR7 can operate in a linear region. In such an embodiment, when the diode initialization signal GB is activated, the seventh transistor TR7 can initialize the first terminal of the OLED to the initialization voltage VINT.

[0095] Alternatively, the gate initialization signal GI and the diode initialization signal GB are signals substantially identical to each other. The initialization operation of the gate terminal of the first transistor TR1 may not affect the initialization operation of the first terminal of the OLED. In such an embodiment, the initialization operation of the gate terminal of the first transistor TR1 and the initialization operation of the first terminal of the OLED may be independent of each other. Therefore, the gate initialization signal GI is used as the diode initialization signal GB, thereby improving manufacturing efficiency.

[0096] The storage capacitor CST may include a first terminal and a second terminal, and may be connected between the high power supply voltage ELVDD line and the gate terminal of the first transistor TR1. In an exemplary embodiment, for example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply voltage ELVDD line. When the gate signal GW is deactivated, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1. When the gate signal GW is deactivated, the light emitting signal EM may be activated (for example, the portion where the gate signal GW is deactivated may include the portion where the light emitting signal EM is activated). When the light emitting signal EM is activated, the driving current ID generated by the first transistor TR1 may be provided to the OLED. Therefore, the driving current ID generated by the first transistor TR1 based on the voltage level maintained by the storage capacitor CST may be provided to the OLED.

[0097] In an exemplary embodiment, the SPC includes seven transistors and a single capacitor, but is not limited thereto. In one exemplary embodiment, for example, the SPC may have a configuration including at least one transistor and at least one capacitor.

[0098] Figure 4 is along Figure 1A A cross-sectional view taken along line II' of Figure 5A It is shown Figure 4 A cross-sectional view of a connection between a first transistor and a first signal line included in an OLED display device. Figure 5B It is shown Figure 4 A cross-sectional view of a connection between a second transistor and a second signal line included in an OLED display device.

[0099] refer to Figure 1A and Figure 4, an exemplary embodiment of the OLED display device 100 may include a substrate 110, a buffer layer 115, a first signal line 710, a second signal line 510, a first circuit structure 800, a second circuit structure 600, a gate insulating layer 150, an insulating interlayer 190, a power line 380, a switching transistor 250, a driving transistor 253, a planarization layer 270, a blocking structure 400, a sub-pixel structure 200, a connection pattern 295, a pixel defining layer 310, a thin film encapsulation ("TFE") structure 450, etc. Here, the substrate 110 may include a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114. In an exemplary embodiment, the OLED display device 100 includes a sub-pixel area 30 and a peripheral area 20, and the substrate 110 may be divided into the sub-pixel area 30 and the peripheral area 20. The first circuit structure 800 (e.g., gate driver) may include a first transistor 850, and the first transistor 850 may include a first active pattern 730, a first gate electrode pattern 770, a first source electrode pattern 810, and a first drain electrode pattern 830. The second circuit structure 600 (e.g., light emitting driver) may include a second transistor 650, and the second transistor 650 may include a second active pattern 530, a second gate electrode pattern 570, a second source electrode pattern 610, and a second drain electrode pattern 630. In such an embodiment, the switching transistor 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the driving transistor 253 may include a second active layer 133, a second gate electrode 173, a second source electrode 213, and a second drain electrode 233. The blocking structure 400 may include a first blocking pattern 345 and a second blocking pattern 350, and the second blocking pattern 350 may include a first sub-blocking pattern 360 and a second sub-blocking pattern 370. In such an embodiment, the sub-pixel structure 200 may include a lower electrode 290 , a light emitting layer 330 , and an upper electrode 340 , and the TFE structure 450 may include a first TFE layer 451 , a second TFE layer 452 , and a third TFE layer 453 .

[0100] In an exemplary embodiment, as described above, the OLED display device 100 may include a display area 10 and a peripheral area 20 surrounding the display area 10, and the display area 10 includes a plurality of sub-pixel areas 30. In an exemplary embodiment, for example, Figure 4 The sub-pixel region 30 in the embodiment may correspond to a sub-pixel region 30 located adjacent to the peripheral region 20 among the plurality of sub-pixel regions 30. Figure 4 In the embodiment, the sub-pixel area 30 may be located at the outermost portion of the display area 10 .

[0101] An image may be displayed in the sub-pixel region 30 through the sub-pixel structure 200, and the blocking structure 400, the power line 380 (e.g., the low power line), the first transistor 850, the second transistor 650, the first signal line 710, the second signal line 510, etc. may be disposed in the peripheral region 20. Here, the peripheral region 20 may be a non-display region. A plurality of transistors, a plurality of capacitors, a plurality of lines (e.g., a gate signal line, a data signal line, a high power line, a light emitting signal line, an initialization signal line, etc.) may be additionally disposed in the display region 10, for example. In an exemplary embodiment, the OLED display device 100 includes a flexible substrate 110 and a TFE structure 450, and the OLED display device 100 may be used as a flexible OLED display device.

[0102] The first organic layer 111 may define the lowermost portion of the OLED display device 100. The first organic layer 111 may include an organic material having flexibility. In an exemplary embodiment, the first organic layer 111 may include, for example, polyimide.

[0103] The first barrier layer 112 may be disposed on the entire first organic layer 111. The first barrier layer 112 may block moisture or water that may penetrate the first organic layer 111. The first barrier layer 112 may include an inorganic material having flexibility. In an exemplary embodiment, the first barrier layer 112 may include, for example, silicon oxide or silicon nitride.

[0104] The second organic layer 113 may be disposed on the first barrier layer 112. The second organic layer 113 may be disposed on the entire first barrier layer 112. The second organic layer 113 may include an organic material having flexibility. In an exemplary embodiment, the second organic layer 113 may include, for example, polyimide.

[0105] The second barrier layer 114 may be disposed on the entire second organic layer 113. The second barrier layer 114 may block moisture or water that may penetrate the second organic layer 113. The second barrier layer 114 may include an inorganic material having flexibility. In an exemplary embodiment, the second barrier layer 114 may include, for example, silicon oxide or silicon nitride.

[0106] Thus, the substrate 110 including the first organic layer 111 , the first barrier layer 112 , the second organic layer 113 , and the second barrier layer 114 may be provided.

[0107] In an exemplary embodiment, the substrate 110 includes four layers, but is not limited thereto. In one exemplary embodiment, for example, the substrate 110 may include a single layer or at least two layers, for example, three layers or five layers.

[0108] In an exemplary embodiment, the first signal line 710 may be disposed on the substrate 110 (e.g., the second barrier layer 114) in the peripheral region 20. In such an embodiment, the first signal line 710 may be disposed between the substrate 110 and the buffer layer 115 in the peripheral region 20, and may partially overlap with the first transistor 850. The first signal line 710 may be disposed adjacent to a boundary between the peripheral region 20 and the sub-pixel region 30. Here, the first signal line 710 may be Figure 1B In an exemplary embodiment, the first signal line 710 may be a clock signal line and may receive a clock signal generated from the external device 101. The first signal line 710 may extend in a first direction D1 parallel to the upper surface of the substrate 110. In such an embodiment, as shown in FIG. Figure 5A As shown in FIG. 1 , when viewed from different cross-sectional views of the OLED display device 100, the first signal line 710 may be electrically connected to the first transistor 850. In one exemplary embodiment, for example, the first signal line 710 may provide a clock signal to the first source electrode pattern 810 of the first transistor 850, or may provide a clock signal to the first gate electrode pattern 770 of the first transistor 850 through the first source electrode pattern 811. Here, the first transistor 850 may be Figure 3A one of the first to eighth transistors M1, M2, M3, M4, M5, M6, M7 and M8.

[0109] In such an embodiment, in another different cross-sectional view of the OLED display device 100, the first signal line 710 may be electrically connected to the second transistor 650. In one exemplary embodiment, for example, the first signal line 710 may provide a clock signal to the second transistor 650.

[0110] The first signal line 710 may include, for example, at least one selected from a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, and a transparent conductive material. In an exemplary embodiment, for example, the first signal line 710 may include, for example, at least one selected from gold (Au), silver (Ag), aluminum (Al), tungsten (W), copper (Cu), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum alloy, aluminum nitride (AlN), silver alloy, tungsten nitride (WN), copper alloy, molybdenum alloy, titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (“ITO”), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), and indium zinc oxide (“IZO”). These materials may be used alone or in appropriate combination thereof. Alternatively, the first signal line 710 may have a multilayer structure including a plurality of layers. In an alternative exemplary embodiment, the first signal line 710 may be substantially composed of, for example, super aluminum metal.

[0111] The second signal line 510 may be disposed on the substrate 110 in the peripheral region 20 and may be spaced apart from the first signal line 710. In such an embodiment, the second signal line 510 may be spaced apart from the first signal line 710 in the third direction D3 between the substrate 110 and the buffer layer 115 in the peripheral region 20 and may partially overlap the second transistor 650. In an exemplary embodiment, for example, the third direction D3 may be perpendicular to the first direction D1, and the third direction D3 may be opposite to the second direction D2. Here, the second signal line 510 may be Figure 1B In an exemplary embodiment, the second signal line 510 may be a first driving power VDD line and may receive the first driving power VDD generated from the external device 101. The second signal line 510 may extend in the first direction D1.

[0112] like Figure 5B As shown in FIG. 1 , in different cross-sectional views of the OLED display device 100, the second signal line 510 may be electrically connected to the second transistor 650. In one exemplary embodiment, for example, the second signal line 510 may provide the first driving power source VDD to the second source electrode pattern 610 of the second transistor 650. Here, the second transistor 650 may be Figure 3B one of the first to tenth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19 and M20.

[0113] In another different cross-sectional view of the OLED display device 100, the second signal line 510 may be electrically connected to the first transistor 850. In one exemplary embodiment, for example, the second signal line 510 may provide the first driving power source VDD to the first transistor 850.

[0114] The second signal line 510 may include, for example, at least one selected from a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the second signal line 510 may have a multilayer structure including a plurality of layers. In an alternative exemplary embodiment, the second signal line 510 may be substantially composed of super aluminum metal.

[0115] In an exemplary embodiment, each of the first signal line 710 and the second signal line 510 includes or is defined by a single line, but is not limited thereto. In one exemplary embodiment, for example, each of the first signal line 710 and the second signal line 510 may include at least two lines.

[0116] In a conventional OLED display device, the first signal line 710 (i.e., the clock signal line) and the first transistor 850 (i.e., the gate driver) may be disposed or located in the same layer as each other, and may be spaced apart from each other. In such a conventional OLED display device, the second signal line 510 (i.e., the first driving power line) and the second transistor 650 (i.e., the light emitting driver) may be located in the same layer as each other, and may be spaced apart from each other. In such a conventional OLED display device, the light emitting driver, the first driving power line, the gate driver, and the clock signal line may be spaced apart from each other on the substrate 110 in the peripheral area 20, so that the area of ​​the peripheral area 20 may be relatively large. Therefore, a conventional OLED display device may include a dead zone having a relatively large area.

[0117] In an exemplary embodiment of the present invention, the OLED display device 100 includes a first signal line 710 disposed under the first circuit structure 800 and a second signal line 510 disposed under the second circuit structure 600, and the area of ​​the peripheral region 20 of the substrate 110 can be relatively reduced. In such an embodiment, the OLED display device 100 can include a dead zone having a relatively small area.

[0118] The buffer layer 115 may be disposed on the substrate 110, the first signal line 710, and the second signal line 510. The buffer layer 115 may cover the first signal line 710 and the second signal line 510 on the substrate 110 in the peripheral region 20, and may extend in the first direction D1. In such an embodiment, the buffer layer 115 may be disposed on the entire substrate 110 or be disposed to cover the entire upper surface of the substrate 110. In an exemplary embodiment, for example, the buffer layer 115 may fully cover the first signal line 710 and the second signal line 510, and may have a substantially flat upper surface without steps around the first signal line 710 and the second signal line 510. Alternatively, the buffer layer 115 may cover the first signal line 710 and the second signal line 510 on the substrate 110, and may be disposed to a substantially uniform thickness along the contours of the first signal line 710 and the second signal line 510.

[0119] The buffer layer 115 can effectively prevent metal atoms and / or impurities from diffusing from the substrate 110 into the first transistor 850, the second transistor 650, the switch transistor 250, and the driving transistor 253. In such an embodiment, the buffer layer 115 can control the rate of heat transfer in the crystallization process for forming the first active pattern 730, the second active pattern 530, the first active layer 130, and the second active layer 133, thereby obtaining substantially uniform first active patterns 730 and second active patterns 530 and first active layers 130 and second active layers 133. In addition, when the surface of the substrate 110 is relatively uneven, the buffer layer 115 can improve the surface flatness of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be provided on the substrate 110, or the buffer layer 115 may not be formed. In an exemplary embodiment, the buffer layer 115 may include an organic material or an inorganic material. In an exemplary embodiment, for example, the buffer layer 115 may include an inorganic material.

[0120] The first active pattern 730 and the second active pattern 530 may be disposed on the buffer layer 115 in the peripheral region 20 and may be spaced apart from each other. The first active layer 130 and the second active layer 133 may be disposed on the buffer layer 115 in the sub-pixel region 30 and may be spaced apart from each other. In an exemplary embodiment, the first active pattern 730 may partially overlap the first signal line 710, and the second active pattern 530 may partially overlap the second signal line 510. Each of the first active pattern 730, the second active pattern 530, the first active layer 130, and the second active layer 133 may include at least one selected from a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, and the like.

[0121] The gate insulating layer 150 may be disposed on the buffer layer 115, the first and second active patterns 730 and 530, and the first and second active layers 130 and 133. The gate insulating layer 150 may cover the first and second active patterns 730 and 530 in the peripheral region 20 and the first and second active layers 130 and 133 in the sub-pixel region 30 on the buffer layer 115, and may extend in the first direction D1. In such an embodiment, the gate insulating layer 150 may be disposed on the entire buffer layer 115. In an exemplary embodiment, for example, the gate insulating layer 150 may fully cover the first and second active patterns 730 and 530 and the first and second active layers 130 and 133 on the buffer layer 115, and may have a substantially flat upper surface without steps around the first and second active patterns 730 and 730 and the first and second active layers 130 and 133. Alternatively, the gate insulating layer 150 may cover the first active pattern 730 and the second active pattern 530 and the first active layer 130 and the second active layer 133 on the buffer layer 115, and may be set to a substantially uniform thickness along the contours of the first active pattern 730 and the second active pattern 530 and the first active layer 130 and the second active layer 133. The gate insulating layer 150 may include, for example, a silicon compound or a metal oxide. In an exemplary embodiment, for example, the gate insulating layer 150 may include, for example, at least one selected from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), and titanium oxide (TiO).

[0122] The first gate electrode pattern 770 and the second gate electrode pattern 570 may be disposed on the gate insulating layer 150 in the peripheral region 20 and may be spaced apart from each other. The first gate electrode 170 and the second gate electrode 173 may be disposed on the gate insulating layer 150 in the sub-pixel region 30 and may be spaced apart from each other. In one exemplary embodiment, for example, the first gate electrode pattern 770 may be disposed on the gate insulating layer 150 under which the first active pattern 730 is located, and the second gate electrode pattern 570 may be disposed on the gate insulating layer 150 under which the second active pattern 530 is located. The first gate electrode 170 may be disposed on the gate insulating layer 150 under which the first active layer 130 is located, and the second gate electrode 173 may be disposed on the gate insulating layer 150 under which the second active layer 133 is located. Each of the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 may include, for example, at least one selected from metal, alloy of metal, metal nitride, conductive metal oxide, and transparent conductive material. These materials may be used alone or in appropriate combination thereof. Alternatively, each of the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173 may have a multi-layered structure including a plurality of layers.

[0123] The insulating interlayer 190 may be disposed on the gate insulating layer 150, the first and second gate electrode patterns 770 and 570, and the first and second gate electrodes 170 and 173. The insulating interlayer 190 may cover the first and second gate electrode patterns 770 and 570 in the peripheral region 20 and the first and second gate electrodes 170 and 173 in the sub-pixel region 30 on the gate insulating layer 150, and may extend in the first direction D1. In such an embodiment, the insulating interlayer 190 may be disposed on the entire gate insulating layer 150. In an exemplary embodiment, for example, the insulating interlayer 190 may fully cover the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173 on the gate insulating layer 150, and may have a substantially flat upper surface without steps around the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173. Alternatively, the insulating interlayer 190 may cover the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173 on the gate insulating layer 150, and may be provided to a substantially uniform thickness along contours of the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173. The insulating interlayer 190 may include, for example, a silicon compound or a metal oxide.

[0124] The first source electrode pattern 810, the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630 may be disposed on the insulating interlayer 190 in the peripheral region 20 and may be spaced apart from each other. The first source electrode 210, the first drain electrode 230, the second source electrode 213 and the second drain electrode 233 may be disposed on the insulating interlayer 190 in the sub-pixel region 30 and may be spaced apart from each other.

[0125] The first source electrode pattern 810 can contact the source region of the first active pattern 730 via a contact hole defined by passing through the gate insulation layer 150 and the insulating interlayer 190, for example, formed by removing a first portion of the gate insulation layer 150 and the insulating interlayer 190, and the first drain electrode pattern 830 can contact the drain region of the first active pattern 730 via a contact hole defined by passing through the gate insulation layer 150 and the insulating interlayer 190, for example, formed by removing a second portion of the gate insulation layer 150 and the insulating interlayer 190.

[0126] The second source electrode pattern 610 can contact the source region of the second active pattern 530 via a contact hole defined by passing through the gate insulation layer 150 and the insulating interlayer 190, for example, formed by removing a third portion of the gate insulation layer 150 and the insulating interlayer 190, and the second drain electrode pattern 630 can contact the drain region of the second active pattern 530 via a contact hole defined by passing through the gate insulation layer 150 and the insulating interlayer 190, for example, formed by removing a fourth portion of the gate insulation layer 150 and the insulating interlayer 190.

[0127] The first source electrode 210 can contact the source region of the first active layer 130 via a contact hole defined by passing through the gate insulating layer 150 and the insulating interlayer 190, for example, formed by removing the fifth portion of the gate insulating layer 150 and the insulating interlayer 190, and the first drain electrode 230 can contact the drain region of the first active layer 130 via a contact hole defined by passing through the gate insulating layer 150 and the insulating interlayer 190, for example, formed by removing the sixth portion of the gate insulating layer 150 and the insulating interlayer 190.

[0128] The second source electrode 213 can contact the source region of the second active layer 133 via a contact hole defined by passing through the gate insulating layer 150 and the insulating interlayer 190, for example, formed by removing the seventh portion of the gate insulating layer 150 and the insulating interlayer 190, and the second drain electrode 233 can contact the drain region of the second active layer 133 via a contact hole defined by passing through the gate insulating layer 150 and the insulating interlayer 190, for example, formed by removing the eighth portion of the gate insulating layer 150 and the insulating interlayer 190.

[0129] Each of the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, and the second source electrode 213 and the second drain electrode 233 may include, for example, at least one selected from a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, and the second source electrode 213 and the second drain electrode 233 may have a multilayer structure including a plurality of layers.

[0130] Therefore, a first transistor 850 including a first active pattern 730, a first gate electrode pattern 770, a first source electrode pattern 810, and a first drain electrode pattern 830 may be disposed on the buffer layer 115, and a second transistor 650 including a second active pattern 530, a second gate electrode pattern 570, a second source electrode pattern 610, and a second drain electrode pattern 630 may be disposed on the buffer layer 115. In such an embodiment, the second transistor 650 may be spaced apart from the first transistor 850 in the third direction D3. In such an embodiment, a switching transistor 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 may be disposed on the buffer layer 115, and a driving transistor 253 including a second active layer 133, a second gate electrode 173, a second source electrode 213, and a second drain electrode 233 may be disposed on the buffer layer 115. In such an embodiment, the driving transistor 253 may be spaced apart from the switching transistor 250 in the second direction D2.

[0131] In such an embodiment, as described above, the switch transistor 250 may be coupled to Figure 3C The fifth transistor TR5 corresponds to the driving transistor 253. Figure 3C In such an embodiment, the second transistor TR2, the third transistor TR3 and the fourth transistor TR4, the sixth transistor TR6 and the seventh transistor TR7, and the storage capacitor CST, etc. may be disposed in different parts of the OLED display device 100.

[0132] In an exemplary embodiment, if Figure 4As shown in , each of the first transistor 850, the second transistor 650, the switch transistor 250 and the drive transistor 253 has a top gate structure, but is not limited thereto. In an alternative exemplary embodiment, for example, each of the first transistor 850, the second transistor 650, the switch transistor 250 and the drive transistor 253 may have a bottom gate structure and / or a double gate structure.

[0133] The power line 380 may be disposed on the insulating interlayer 190 in the peripheral region 20. In an exemplary embodiment, the power line 380 may be spaced apart from the first source electrode pattern 810 and the first drain electrode pattern 830 and the second source electrode pattern 610 and the second drain electrode pattern 630. In an exemplary embodiment, as described above, the low power supply voltage ELVSS may be provided to the power line 380 (refer to Figure 3C ). In such an embodiment, the low power supply voltage ELVSS may be applied to the upper electrode 340. In an exemplary embodiment, for example, the power supply line 380 may include at least one selected from, for example, a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the power supply line 380 may have a multilayer structure including a plurality of layers.

[0134] In an exemplary embodiment, the OLED display device 100 may further include a plurality of other lines in the peripheral area 20 or the sub-pixel area 30 .

[0135] The planarization layer 270 may be disposed on the insulating interlayer 190, the power line 380, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, and the second source electrode 213 and the second drain electrode 233, and may expose the power line 380. The planarization layer 270 may be disposed to have a large thickness to fully cover the power line 380, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, and the second source electrode 213 and the second drain electrode 233 on the insulating interlayer 190. In such an embodiment, the planarization layer 270 may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may include an organic material. In an exemplary embodiment, for example, the planarization layer 270 may include at least one selected from photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, and epoxy resin.

[0136] The first sub-blocking pattern 360 may be disposed on the insulating interlayer 190 in the peripheral region 20. The first sub-blocking pattern 360 may overlap a portion of the power line 380. In such an embodiment, the first sub-blocking pattern 360 may block leakage of the second TFE layer 452 and may be located in the same layer as the planarization layer 270. The first sub-blocking pattern 360 may include an organic material or an inorganic material. In an exemplary embodiment, the first sub-blocking pattern 360 may include an organic material.

[0137] The lower electrode 290 may be disposed on the planarization layer 270 in the sub-pixel region 30. In an exemplary embodiment, for example, the lower electrode 290 may include at least one selected from, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0138] The connection pattern 295 may be disposed on a portion of the planarization layer 270, the power line 380, and a portion of the upper surface of the first sub-blocking pattern 360 in the peripheral region 20. In such an embodiment, the connection pattern 295 may be spaced apart from the lower electrode 290 on the planarization layer 270 and may extend in the third direction D3. In such an embodiment, the connection pattern 295 may be disposed along the contours of the planarization layer 270, the power line 380, and the first sub-blocking pattern 360. The connection pattern 295 may be interposed between the first blocking pattern 345 and the power line 380 in the peripheral region 20, and a portion of the connection pattern 295 may be interposed between the first sub-blocking pattern 360 and the second sub-blocking pattern 370. Alternatively, the connection pattern 295 may not be disposed on the upper surface of the first sub-blocking pattern 360. The connection pattern 295 may electrically connect the power line 380 and the upper electrode 340, and may receive the low power supply voltage ELVSS from the power line 380. The low power supply voltage ELVSS may be applied to the upper electrode 340 through the connection pattern 295. The connection pattern 295 may include, for example, at least one selected from a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the connection pattern 295 may have a multilayer structure including a plurality of layers.

[0139] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290, a portion of the connection pattern 295, and the planarization layer 270. The pixel defining layer 310 may cover a side portion of the lower electrode 290, and an opening exposing a portion of an upper surface of the lower electrode 290 is defined through the pixel defining layer 310. The pixel defining layer 310 may include an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 310 may include an organic material.

[0140] The light emitting layer 330 may be disposed on the lower electrode 290 exposed by the opening of the pixel defining layer 310. The light emitting layer 330 may include at least one of the light emitting materials capable of generating light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel or be formed using the same. Alternatively, the light emitting layer 330 may generally generate white light by stacking a plurality of light emitting materials capable of generating light of different colors (such as red light, green light, blue light, etc.). In an exemplary embodiment, a color filter may be disposed on the light emitting layer 330 (e.g., on the upper surface of the TFE structure 450 to overlap with the light emitting layer 330). The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include at least one selected from a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include, for example, at least one selected from a photosensitive resin and a color photoresist.

[0141] The first preventing pattern 345 may be disposed on the connection pattern 295 in the peripheral region 20. In such an embodiment, the first preventing pattern 345 may be disposed on the connection pattern 295 under which the power line 380 is located. In one exemplary embodiment, for example, the first preventing pattern 345 may surround the display region 10 (or the sub-pixel region 30). In an exemplary embodiment, the first preventing pattern 345 may prevent leakage of the second TFE layer 452. The first preventing pattern 345 may include an organic material or an inorganic material. In an exemplary embodiment, the first preventing pattern 345 may include an organic material.

[0142] The second sub-preventing pattern 370 may be disposed on the first sub-preventing pattern 360 and a portion of the connection pattern 295. In an exemplary embodiment, the second sub-preventing pattern 370 together with the first sub-preventing pattern 360 may prevent leakage of the second TFE layer 452. In an exemplary embodiment, the second sub-preventing pattern 370 may include an organic material.

[0143] Thus, a second preventing pattern 350 including a first sub-preventing pattern 360 and a second sub-preventing pattern 370 may be provided. In one exemplary embodiment, for example, the second preventing pattern 350 may be spaced apart from the first preventing pattern 345 and may surround the first preventing pattern 345. The height of the second preventing pattern 350 may be greater than the height of the first preventing pattern 345. In an exemplary embodiment, the first preventing pattern 345 and the second preventing pattern 350 may jointly define a preventing structure 400. In an exemplary embodiment, the preventing structure 400 may be provided on the substrate 110 at the outermost portion of the peripheral region 20.

[0144] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be disposed on the entire substrate 110. In an exemplary embodiment, the upper electrode 340 may cover the light emitting layer 330 and extend in the third direction D3, and may be electrically connected to the connection pattern 295. The upper electrode 340 may include, for example, at least one selected from a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Therefore, the sub-pixel structure 200 including the lower electrode 290, the light emitting layer 330, and the upper electrode 340 may be disposed on the planarization layer 270.

[0145] The first TFE layer 451 may be disposed on the upper electrode 340, the connection pattern 295, the blocking structure 400, and the insulating interlayer 190. The first TFE layer 451 may cover the upper electrode 340, the connection pattern 295, and the blocking structure 400, and may be disposed to a substantially uniform thickness along the contours of the upper electrode 340, the connection pattern 295, and the blocking structure 400. The first TFE layer 451 may prevent the sub-pixel structure 200 from being degraded by the penetration of moisture, water, oxygen, etc. In such an embodiment, the first TFE layer 451 may protect the sub-pixel structure 200 from external influences. The first TFE layer 451 may include an inorganic material having flexibility.

[0146] The second TFE layer 452 may be disposed on the first TFE layer 451. The second TFE layer 452 may improve the flatness of the OLED display device 100 and may protect the sub-pixel structure 200. The second TFE layer 452 may include an organic material having flexibility.

[0147] The third TFE layer 453 may be disposed on the second TFE layer 452. The third TFE layer 453 may cover the second TFE layer 452 and may be disposed to a substantially uniform thickness along the contour of the second TFE layer 452. The third TFE layer 453, together with the first TFE layer 451 and the second TFE layer 452, may prevent the sub-pixel structure 200 from being degraded by the penetration of moisture, water, oxygen, etc. In such an embodiment, the third TFE layer 453, together with the first TFE layer 451 and the second TFE layer 452, may protect the sub-pixel structure 200 from external influences. The third TFE layer 453 may include an inorganic material having flexibility. Therefore, a TFE structure 450 including the first TFE layer 451, the second TFE layer 452 and the third TFE layer 453 may be provided.

[0148] Alternatively, the TFE structure 450 may have a five-layer structure in which the first to fifth TFE layers are stacked one on top of another, or a seven-layer structure in which the first to seventh TFE layers are stacked one on top of another.

[0149] In an exemplary embodiment, the OLED display device 100 includes a first signal line 710 and a second signal line 510 that are arranged to overlap with the first circuit structure 800 and the second circuit structure 600, so that the OLED display device 100 can relatively reduce the width of the border corresponding to the non-display area, or can relatively increase the area of ​​the display area 10.

[0150] Alternatively, a gate signal line, an initialization voltage line, an initialization signal line, etc. may be further disposed between the substrate 110 and the buffer layer 115 .

[0151] Figures 6 to 11 is a cross-sectional view illustrating a method of manufacturing an OLED display device according to an exemplary embodiment.

[0152] refer to Figure 6 , a rigid glass substrate 105 may be provided. A first organic layer 111 may be provided or formed on the rigid glass substrate 105. The first organic layer 111 may be provided or formed on the entire rigid glass substrate 105, and may be formed using an organic material having flexibility such as polyimide.

[0153] The first barrier layer 112 may be provided or formed on the entire first organic layer 111. The first barrier layer 112 may block moisture or water from penetrating through the first organic layer 111. The first barrier layer 112 may be formed using an inorganic material having flexibility such as silicon oxide, silicon nitride, or the like.

[0154] The second organic layer 113 may be provided or formed on the first barrier layer 112. The second organic layer 113 may be provided or formed on the entire first barrier layer 112, and may be formed using, for example, an organic material having flexibility such as polyimide.

[0155] The second barrier layer 114 may be provided or formed on the entire second organic layer 113. The second barrier layer 114 may block moisture or water from penetrating through the second organic layer 113. The second barrier layer 114 may be formed using an inorganic material having flexibility such as silicon oxide, silicon nitride, or the like.

[0156] Since the substrate 110 is relatively thin and soft, the substrate 110 may be provided or formed on the rigid glass substrate 105 to help support the formation of the above structure (e.g., the first signal line, the second signal line, the transistor, the sub-pixel structure, etc.). In an exemplary embodiment, for example, after the above structure is provided or formed on the substrate 110, the rigid glass substrate 105 may be removed. In such an embodiment, since the first organic layer 111 and the second organic layer 113 and the first barrier layer 112 and the second barrier layer 114 are relatively thin and soft, it may be difficult to directly form the above structure on the first organic layer 111 and the second organic layer 113 and the first barrier layer 112 and the second barrier layer 114. Therefore, the above structure is provided or formed on the substrate 110 and the rigid glass substrate 105, and then after the rigid glass substrate 105 is removed, the first organic layer 111 and the second organic layer 113 and the first barrier layer 112 and the second barrier layer 114 can be used as the substrate 110.

[0157] In an exemplary embodiment, the substrate 110 includes four layers, but is not limited thereto. In one exemplary embodiment, for example, the substrate 110 may include a single layer or at least two layers.

[0158] The first signal line 710 may be provided or formed on the substrate 110 (e.g., the second barrier layer 114) in the peripheral region 20. The first signal line 710 may be provided or formed adjacent to a boundary of the peripheral region 20 and the sub-pixel region 30. The second signal line 510 may be provided or formed on the substrate 110 in the peripheral region 20, and may be spaced apart from the first signal line 710.

[0159] For example, each of the first signal line 710 and the second signal line 510 may be formed using at least one selected from, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. In an exemplary embodiment, for example, each of the first signal line 710 and the second signal line 510 may include at least one selected from Au, Ag, Al, W, Cu, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, Mo, Sc, Nd, Ir, an alloy of aluminum, AlN, an alloy of silver, WN, an alloy of copper, an alloy of molybdenum, TiN, CrN, TaN, SrRuO, ZnO, ITO, SnO, InO, GaO, IZO, etc. These materials may be used alone or in appropriate combinations thereof. Alternatively, each of the first signal line 710 and the second signal line 510 may have a multilayer structure including a plurality of layers. In an exemplary embodiment, each of the first signal line 710 and the second signal line 510 may be substantially composed of super aluminum metal. In an exemplary embodiment, the first signal line 710 and the second signal line 510 can be formed simultaneously (or concurrently) using the same material as each other. In an exemplary embodiment, for example, after the preliminary signal line layer is provided or formed on the entire second barrier layer 114, the first signal line 710 and the second signal line 510 can be formed by selectively etching the preliminary signal line layer.

[0160] refer to Figure 7 , a buffer layer 115 may be provided or formed on the substrate 110, the first signal line 710, and the second signal line 510. The buffer layer 115 may cover the first signal line 710 and the second signal line 510 on the substrate 110 in the peripheral area 20, and may extend in the first direction D1. In such an embodiment, the buffer layer 115 may be provided or formed on the entire substrate 110. In an exemplary embodiment, for example, the buffer layer 115 may fully cover the first signal line 710 and the second signal line 510, and may have a substantially flat upper surface without steps around the first signal line 710 and the second signal line 510. Alternatively, the buffer layer 115 may cover the first signal line 710 and the second signal line 510 on the substrate 110, and may be formed to a substantially uniform thickness along the contours of the first signal line 710 and the second signal line 510.

[0161] At least two buffer layers 115 may be provided on the substrate 110 or the buffer layer 115 may be omitted depending on the type of the substrate 110. In one exemplary embodiment, for example, the buffer layer 115 may include an organic material or an inorganic material. In an exemplary embodiment, the buffer layer 115 may be formed using an inorganic material.

[0162] The first active pattern 730 and the second active pattern 530 may be provided or formed on the buffer layer 115 in the peripheral region 20 and may be spaced apart from each other. The first active layer 130 and the second active layer 133 may be provided or formed on the buffer layer 115 in the sub-pixel region 30 and may be spaced apart from each other. In an exemplary embodiment, the first active pattern 730 may be formed to partially overlap the first signal line 710, and the second active pattern 530 may be formed to partially overlap the second signal line 510. Each of the first active pattern 730, the second active pattern 530, the first active layer 130, and the second active layer 133 may be formed using at least one selected from a metal oxide semiconductor, an inorganic semiconductor, an organic semiconductor, and the like. In an exemplary embodiment, the first active pattern 730, the second active pattern 530, the first active layer 130, and the second active layer 133 may be simultaneously formed using the same material as each other. In one exemplary embodiment, for example, after a preliminary active layer is provided or formed on the entire buffer layer 115 , the first active pattern 730 , the second active pattern 530 , the first active layer 130 , and the second active layer 133 may be formed by selectively etching the preliminary active layer.

[0163] The gate insulating layer 150 may be provided or formed on the buffer layer 115, the first and second active patterns 730 and 530, and the first and second active layers 130 and 133. The gate insulating layer 150 may cover the first and second active patterns 730 and 530 in the peripheral region 20 and the first and second active layers 130 and 133 in the sub-pixel region 30 on the buffer layer 115, and may extend in the first direction D1. That is, the gate insulating layer 150 may be provided or formed on the entire buffer layer 115. In an exemplary embodiment, for example, the gate insulating layer 150 may fully cover the first and second active patterns 730 and 530 and the first and second active layers 130 and 133 on the buffer layer 115, and may have a substantially flat upper surface without steps around the first and second active patterns 730 and 530 and the first and second active layers 130 and 133. Alternatively, the gate insulating layer 150 may cover the first active pattern 730 and the second active pattern 530 and the first active layer 130 and the second active layer 133 on the buffer layer 115, and may be formed to a substantially uniform thickness along the contours of the first active pattern 730 and the second active pattern 530 and the first active layer 130 and the second active layer 133. The gate insulating layer 150 may be formed using, for example, a silicon compound or a metal oxide. In an exemplary embodiment, for example, the gate insulating layer 150 may include at least one selected from SiO, SiN, SiON, SiOC, SiCN, AlO, AlN, TaO, HfO, ZrO, TiO, etc.

[0164] The first gate electrode pattern 770 and the second gate electrode pattern 570 may be provided or formed on the gate insulating layer 150 in the peripheral region 20 and may be spaced apart from each other. The first gate electrode 170 and the second gate electrode 173 may be provided or formed on the gate insulating layer 150 in the sub-pixel region 30 and may be spaced apart from each other. In one exemplary embodiment, for example, the first gate electrode pattern 770 may be provided or formed on the gate insulating layer 150 under which the first active pattern 730 is located, and the second gate electrode pattern 570 may be provided or formed on the gate insulating layer 150 under which the second active pattern 530 is located. The first gate electrode 170 may be provided or formed on the gate insulating layer 150 under which the first active layer 130 is located, and the second gate electrode 173 may be provided or formed on the gate insulating layer 150 under which the second active layer 133 is located. Each of the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 can be formed using, for example, at least one selected from a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials can be used alone or in appropriate combinations thereof. Alternatively, each of the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 can have a multilayer structure including a plurality of layers. In an exemplary embodiment, the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 can be formed simultaneously using the same material as each other. In an exemplary embodiment, for example, after the preliminary first electrode layer is provided or formed on the entire gate insulating layer 150, the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 can be formed by selectively etching the preliminary first electrode layer.

[0165] refer to Figure 8, the insulating interlayer 190 may be provided or formed on the gate insulating layer 150, the first gate electrode pattern 770, the second gate electrode pattern 570, and the first gate electrode 170 and the second gate electrode 173. The insulating interlayer 190 may cover the first gate electrode pattern 770 and the second gate electrode pattern 570 in the peripheral region 20 and the first gate electrode 170 and the second gate electrode 173 in the sub-pixel region 30 on the gate insulating layer 150, and may extend in the first direction D1. That is, the insulating interlayer 190 may be provided or formed on the entire gate insulating layer 150. In an exemplary embodiment, for example, the insulating interlayer 190 may fully cover the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173 on the gate insulating layer 150, and may have a substantially flat upper surface without steps around the first gate electrode pattern 770 and the second gate electrode pattern 570 and the first gate electrode 170 and the second gate electrode 173. Alternatively, the insulating interlayer 190 may cover the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173 on the gate insulating layer 150, and may be formed to a substantially uniform thickness along contours of the first and second gate electrode patterns 770 and 570 and the first and second gate electrodes 170 and 173. The insulating interlayer 190 may be formed using, for example, a silicon compound or a metal oxide.

[0166] The first source electrode pattern 810, the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630 may be provided or formed on the insulating interlayer 190 in the peripheral region 20 and may be spaced apart from each other. The first source electrode 210, the first drain electrode 230, the second source electrode 213 and the second drain electrode 233 may be provided or formed on the insulating interlayer 190 in the sub-pixel region 30 and may be spaced apart from each other.

[0167] The first source electrode pattern 810 may contact the source region of the first active pattern 730 via a contact hole formed by removing a first portion of the gate insulating layer 150 and the insulating interlayer 190, and the first drain electrode pattern 830 may contact the drain region of the first active pattern 730 via a contact hole formed by removing a second portion of the gate insulating layer 150 and the insulating interlayer 190. The second source electrode pattern 610 may contact the source region of the second active pattern 530 via a contact hole formed by removing a third portion of the gate insulating layer 150 and the insulating interlayer 190, and the second drain electrode pattern 630 may contact the drain region of the second active pattern 530 via a contact hole formed by removing a fourth portion of the gate insulating layer 150 and the insulating interlayer 190.

[0168] The first source electrode 210 may contact the source region of the first active layer 130 via a contact hole formed by removing the fifth portion of the gate insulating layer 150 and the insulating interlayer 190, and the first drain electrode 230 may contact the drain region of the first active layer 130 via a contact hole formed by removing the sixth portion of the gate insulating layer 150 and the insulating interlayer 190. The second source electrode 213 may contact the source region of the second active layer 133 via a contact hole formed by removing the seventh portion of the gate insulating layer 150 and the insulating interlayer 190, and the second drain electrode 233 may contact the drain region of the second active layer 133 via a contact hole formed by removing the eighth portion of the gate insulating layer 150 and the insulating interlayer 190.

[0169] Therefore, a first transistor 850 including a first active pattern 730, a first gate electrode pattern 770, a first source electrode pattern 810, and a first drain electrode pattern 830 may be formed, and a second transistor 650 including a second active pattern 530, a second gate electrode pattern 570, a second source electrode pattern 610, and a second drain electrode pattern 630 may be provided or formed on the buffer layer 115. Here, the second transistor 650 may be spaced apart from the first transistor 850 in the third direction D3. In addition, a switching transistor 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 may be formed, and a driving transistor 253 including a second active layer 133, a second gate electrode 173, a second source electrode 213, and a second drain electrode 233 may be provided or formed on the buffer layer 115. Here, the driving transistor 253 may be spaced apart from the switching transistor 250 in the second direction D2.

[0170] The power supply line 380 may be provided or formed on the insulating interlayer 190 in the peripheral region 20. In an exemplary embodiment, the power supply line 380 may be spaced apart from the first source and drain electrode patterns 810 and 830 and the second source and drain electrode patterns 610 and 630.

[0171] Each of the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, the second source electrode 213 and the second drain electrode 233, and the power line 380 can be formed using, for example, at least one selected from metals, metal alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used alone or in appropriate combinations thereof. Alternatively, each of the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, the second source electrode 213 and the second drain electrode 233, and the power line 380 can have a multilayer structure including a plurality of layers. In an exemplary embodiment, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, the second source electrode 213 and the second drain electrode 233, and the power supply line 380 may be simultaneously formed using the same material as each other. In one exemplary embodiment, for example, after the preliminary second electrode layer is provided or formed on the entire insulating interlayer 190, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, the second source electrode 213 and the second drain electrode 233, and the power supply line 380 may be formed by selectively etching the preliminary second electrode layer.

[0172] refer to Fig. 9 , a planarization layer 270 may be provided or formed on the insulating interlayer 190, the power line 380, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, the second source electrode 213 and the second drain electrode 233. The planarization layer 270 may be formed to a high thickness to fully cover the power line 380, the first source electrode pattern 810 and the first drain electrode pattern 830, the second source electrode pattern 610 and the second drain electrode pattern 630, the first source electrode 210 and the first drain electrode 230, and the second source electrode 213 and the second drain electrode 233 on the insulating interlayer 190. In such an embodiment, the planarization layer 270 may have a substantially flat upper surface, and a planarization process may be further performed on the planarization layer 270 to achieve a flat upper surface of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may be formed using, for example, an organic material such as a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin.

[0173] The first sub-blocking pattern 360 may be provided or formed on the insulating interlayer 190 in the peripheral region 20. The first sub-blocking pattern 360 may overlap a portion of the power supply line 380. In such an embodiment, the first sub-blocking pattern 360 may be located in the same layer as the planarization layer 270. In one exemplary embodiment, for example, after a preliminary first organic insulating layer is provided or formed on the entire insulating interlayer 190, the first sub-blocking pattern 360 and the planarization layer 270 may be formed by partially etching the preliminary first organic insulating layer.

[0174] The lower electrode 290 may be provided or formed on the planarization layer 270 in the sub-pixel region 30. In an exemplary embodiment, for example, the lower electrode 290 may be formed using at least one selected from, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0175] The connection pattern 295 may be provided or formed on a portion of the planarization layer 270, the power supply line 380, and a portion of the upper surface of the first sub-blocking pattern 360. In such an embodiment, the connection pattern 295 may be spaced apart from the lower electrode 290 on the planarization layer 270 and may extend in the third direction D3. In such an embodiment, the connection pattern 295 may be formed along the contours of the planarization layer 270, the power supply line 380, and the first sub-blocking pattern 360. The connection pattern 295 and the lower electrode 290 may be formed simultaneously using the same material as each other. In an exemplary embodiment, for example, after the preliminary third electrode layer is entirely provided or formed on the insulating interlayer 190, the first sub-blocking pattern 360, the power supply line 380, and the planarization layer 270, the connection pattern 295 and the lower electrode 290 may be formed by partially etching the preliminary third electrode layer. Alternatively, the connection pattern 295 may have a multilayer structure including a plurality of layers.

[0176] refer to Fig.10 , a pixel defining layer 310 may be provided or formed on a portion of the lower electrode 290, a portion of the connection pattern 295, and the planarization layer 270. The pixel defining layer 310 may cover both side portions of the lower electrode 290, and may have an opening exposing a portion of the upper surface of the lower electrode 290. The pixel defining layer 310 may be formed using an organic material.

[0177] The first preventing pattern 345 may be provided or formed on the connection pattern 295 in the peripheral region 20. In such an embodiment, the first preventing pattern 345 may be provided or formed on the connection pattern 295 under which the power line 380 is located. In one exemplary embodiment, for example, the first preventing pattern 345 may surround the display region 10. The first preventing pattern 345 may be formed using an organic material.

[0178] The second sub-preventing pattern 370 may be provided or formed on a portion of the first sub-preventing pattern 360 and the connecting pattern 295. In such an embodiment, the second sub-preventing pattern 370 may be formed using an organic material. In an exemplary embodiment, the pixel defining layer 310, the first preventing pattern 345, and the second sub-preventing pattern 370 may be simultaneously formed using the same material as each other. In an exemplary embodiment, for example, after the preliminary second organic layer is entirely formed on the insulating interlayer 190, the first sub-preventing pattern 360, the connecting pattern 295, the planarization layer 270, and the lower electrode 290, the pixel defining layer 310, the first preventing pattern 345, and the second sub-preventing pattern 370 may be formed by partially etching (e.g., an etching process using a halftone mask or a slit mask) the preliminary second organic layer.

[0179] Thus, a second preventing pattern 350 including a first sub-preventing pattern 360 and a second sub-preventing pattern 370 may be formed. In one exemplary embodiment, for example, the second preventing pattern 350 may be spaced apart from the first preventing pattern 345 and may surround the first preventing pattern 345. The height of the second preventing pattern 350 may be greater than the height of the first preventing pattern 345. In such an embodiment, the first preventing pattern 345 and the second preventing pattern 350 may collectively define a preventing structure 400.

[0180] refer to Fig.11 , the light-emitting layer 330 may be provided or formed on the lower electrode 290 exposed by the opening of the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials capable of producing light of different colors (e.g., red light, blue light, green light, etc.) according to the sub-pixel. Alternatively, the light-emitting layer 330 may generally produce white light by stacking a plurality of light-emitting materials capable of producing light of different colors (such as red light, green light, blue light, etc.). In this case, a color filter may be provided or formed on the light-emitting layer 330. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include at least one selected from a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using, for example, at least one selected from a photosensitive resin and a color photoresist.

[0181] The upper electrode 340 may be provided or formed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be provided or formed on the entire substrate 110. In an exemplary embodiment, the upper electrode 340 may cover the light emitting layer 330 and extend in the third direction D3, and may be electrically connected to the connection pattern 295. The upper electrode 340 may be formed using at least one selected from, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, and a transparent conductive material. These materials may be used alone or in appropriate combinations thereof. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Therefore, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be formed.

[0182] The first TFE layer 451 may be provided or formed on the upper electrode 340, the connection pattern 295, the blocking structure 400, and the insulating interlayer 190. The first TFE layer 451 may cover the upper electrode 340, the connection pattern 295, and the blocking structure 400, and may be formed to a substantially uniform thickness along the contours of the upper electrode 340, the connection pattern 295, and the blocking structure 400. The first TFE layer 451 may prevent the sub-pixel structure 200 from being degraded by the penetration of moisture, water, oxygen, etc. In such an embodiment, the first TFE layer 451 may protect the sub-pixel structure 200 from external influences. The first TFE layer 451 may be formed using an inorganic material having flexibility.

[0183] The second TFE layer 452 may be provided or formed on the first TFE layer 451. The second TFE layer 452 may improve the flatness of the OLED display device 100 and may protect the sub-pixel structure 200. The second TFE layer 452 may be formed using an organic material having flexibility.

[0184] The third TFE layer 453 may be provided or formed on the second TFE layer 452. The third TFE layer 453 may cover the second TFE layer 452 and may be formed to a substantially uniform thickness along the contour of the second TFE layer 452. The third TFE layer 453 together with the first TFE layer 451 and the second TFE layer 452 may prevent the sub-pixel structure 200 from being degraded by the penetration of moisture, water, oxygen, etc. In such an embodiment, the third TFE layer 453 together with the first TFE layer 451 and the second TFE layer 452 may protect the sub-pixel structure 200 from external influences. The third TFE layer 453 may be formed using an inorganic material having flexibility. Therefore, a TFE structure 450 including the first TFE layer 451, the second TFE layer 452 and the third TFE layer 453 may be formed. Alternatively, the TFE structure 450 may have a five-layer structure in which the first to fifth TFE layers are stacked one on top of another, or a seven-layer structure in which the first to seventh TFE layers are stacked one on top of another. After the TFE structure 450 is formed, the rigid glass substrate 105 may be removed from the substrate 110 .

[0185] Therefore, it is possible to produce Figure 4 The OLED display device 100 shown in FIG.

[0186] Fig.12 1 is a cross-sectional view showing an OLED display device according to an alternative exemplary embodiment. In addition to the respective positions of the first signal line 710 and the second signal line 510, Fig.12 The OLED display device 1000 shown in FIG. 1 may have the same Figures 1A to 4 The configuration of the OLED display device 100 described above is substantially the same or similar to the configuration. Fig.12 In, with reference Figures 1A to 4 Any repeated detailed description of elements that are substantially the same or similar will be omitted or simplified.

[0187] refer to Fig.12 , an exemplary embodiment of an OLED display device 1000 may include a substrate 110, a buffer layer 115, a first signal line 710, a second signal line 510, a first circuit structure 800, a second circuit structure 600, a gate insulating layer 150, an insulating interlayer 190, a power line 380, a switching transistor 250, a driving transistor 253, a planarization layer 270, a blocking structure 400, a sub-pixel structure 200, a connection pattern 295, a pixel defining layer 310, a thin film encapsulation ("TFE") structure 450, etc. Here, the substrate 110 may include a first organic layer 111, a first barrier layer 112, a second organic layer 113, and a second barrier layer 114.

[0188] In such an embodiment, the first signal line 710 may be disposed on the first barrier layer 112 in the peripheral region 20. In such an embodiment, the first signal line 710 may be disposed between the first barrier layer 112 and the second organic layer 113 in the peripheral region 20, and may partially overlap with the first transistor 850. The first signal line 710 may be disposed adjacent to a boundary of the peripheral region 20 and the sub-pixel region 30. In an exemplary embodiment, the first signal line 710 may be a clock signal line, and may receive a clock signal generated from the external device 101.

[0189] In such an embodiment, the second signal line 510 may be disposed on the first barrier layer 112 in the peripheral region 20 and may be spaced apart from the first signal line 710. In such an embodiment, the second signal line 510 may be spaced apart from the first signal line 710 in the third direction D3 between the first barrier layer 112 and the second organic layer 113 in the peripheral region 20 and may partially overlap with the second transistor 650. In an exemplary embodiment, the second signal line 510 may be a first driving power source VDD line and may receive the first driving power source VDD generated from the external device 101.

[0190] In an exemplary embodiment, the first signal line 710 and the second signal line 510 may be disposed within the substrate 110. In other words, the substrate 110 may include a plurality of layers, and the first signal line 710 and the second signal line 510 may be interposed between the layers.

[0191] In an exemplary embodiment, the OLED display device 1000 includes the first and second signal lines 710 and 510 disposed within the substrate 110 and under the first and second circuit structures 800 and 600 , so that the area of ​​the peripheral region 20 of the OLED display device 1000 may be relatively reduced.

[0192] Exemplary embodiments of the present invention may be applied to various display devices including OLED display devices, such as vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, and the like.

[0193] The foregoing is an illustration of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although several exemplary embodiments have been described, it is readily understood by those skilled in the art that various modifications may be made to the exemplary embodiments without substantially exceeding the novel teachings and advantages of the present invention. Therefore, it is intended that all such modifications be included within the scope of the present invention as defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as being limited to the specific exemplary embodiments disclosed, and it is intended that modifications to the disclosed exemplary embodiments and other exemplary embodiments be included within the scope of the appended claims.

Claims

1. An organic light emitting diode display device, comprising: A substrate, comprising: a display area including a plurality of sub-pixel areas; and a peripheral area surrounding the display area; a buffer layer on the substrate in the display area and the peripheral area; a first circuit structure on the buffer layer in the peripheral region, wherein the first circuit structure comprises a gate driver, the gate driver comprising a first transistor; a sub-pixel structure on the first circuit structure in each of the plurality of sub-pixel regions; and A first signal line between the substrate and the buffer layer in the peripheral region, wherein the first signal line overlaps the first transistor when viewed from a plan view in a thickness direction of the substrate.

2. The organic light emitting diode display device according to claim 1, further comprising: a switch transistor disposed on the buffer layer in each of the plurality of sub-pixel regions; as well as A driving transistor is spaced apart from the switching transistor.

3. The organic light emitting diode display device according to claim 2, wherein the switching transistor comprises: a first active layer disposed on the substrate in each of the plurality of sub-pixel regions; a first gate electrode disposed on the first active layer; and a first source electrode and a first drain electrode disposed on the first gate electrode, and The driving transistor includes: a second active layer spaced apart from the first active layer; a second gate electrode disposed on the second active layer; and a second source electrode and a second drain electrode disposed on the second gate electrode.

4. The organic light emitting diode display device according to claim 3, wherein: The gate driver provides a gate signal to the first gate electrode of the switching transistor.

5. The organic light emitting diode display device according to claim 4, further comprising: a second circuit structure spaced apart from the first circuit structure on the substrate in the peripheral region, The second circuit structure includes a light emitting driver, and the light emitting driver includes a second transistor separated from the first circuit structure.

6. The organic light emitting diode display device according to claim 5, further comprising: a second signal line spaced apart from the first signal line between the substrate and the buffer layer in the peripheral region, Wherein, when viewed from the plan view in the thickness direction of the substrate, the second signal line and the second circuit structure overlap.

7. The organic light emitting diode display device according to claim 6, wherein: The first signal line includes a clock signal line to which a clock signal is applied, The first signal line provides the clock signal to the first circuit structure and the second circuit structure, The second signal line includes a driving power line to which a driving power is applied, and The second signal line provides the driving power to the first circuit structure and the second circuit structure.

8. The organic light emitting diode display device according to claim 1, further comprising: a power line spaced apart from the first circuit structure on the buffer layer in the peripheral region; as well as A connection pattern is provided on the power line, Wherein, the power line is electrically connected to the sub-pixel structure through the connection pattern.

9. The organic light emitting diode display device according to claim 8, further comprising: a blocking structure disposed on the substrate in the outermost portion of the peripheral region, The blocking structure includes: a first blocking pattern disposed on the connection pattern; and a second blocking pattern spaced apart from the first blocking pattern, and The second prevention pattern surrounds the first prevention pattern.

10. The organic light emitting diode display device according to claim 1, wherein the substrate comprises: A first organic layer; a first barrier layer disposed on the first organic layer; a second organic layer disposed on the first barrier layer; as well as A second barrier layer is disposed on the second organic layer.

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