Fingerprint sensor, display device including fingerprint sensor, and fingerprint detection method

Abstract

Disclosed are a fingerprint sensor, a display device including the fingerprint sensor, and a fingerprint detection method. The fingerprint sensor may include: a light-transmitting hole array layer including a plurality of light-blocking patterns having a plurality of light-transmitting holes to form a light transmission path for light; a sensor layer including a plurality of light sensors configured to sense light that passes through the light-transmitting holes and is incident on the sensor layer; and a metal pattern configured to apply an electrical signal to pixels or the light-blocking pattern. Gaps between the light-blocking patterns may overlap with at least some of the metal patterns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0001364, filed on January 4, 2019, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0004] Recently, as mobile display devices such as smartphones and tablets are becoming increasingly common and used in various ways, and are becoming increasingly vulnerable to misplacement or loss, effective authentication methods are needed to protect data stored in mobile devices, including personal information. Biometric authentication methods such as fingerprint recognition are gaining popularity. To provide fingerprint sensing functionality, a fingerprint sensor may be provided in the display device, such that the fingerprint sensor is mounted or assembled to the display device.

[0005] For example, a fingerprint sensor can be configured as a light-sensing type sensor. A light-sensing fingerprint sensor may include a light source, a lens, and an optical sensor array. When fingerprint sensing is performed in some parts of a display device, the accuracy of fingerprint sensing increases as the intensity of light emitted from the light source increases. However, in this case, the image quality may degrade due to changes in the brightness of the image displayed on the display panel. Summary of the Invention

[0006] Exemplary embodiments of the present inventive concept relate to a fingerprint sensor capable of improving the accuracy of fingerprint sensing without degrading image quality, and a display device including the fingerprint sensor.

[0007] Exemplary embodiments of the present inventive concept relate to a fingerprint sensor and a display device including the fingerprint sensor, which can increase the amount of light emitted from a light-emitting element according to a change in a bias voltage applied to a pinhole array layer using characteristics of a transistor in a pixel and can sense a user's fingerprint using reflected light obtained from the light emitted from the self-light-emitting element.

[0008] Exemplary embodiments of the present inventive concept relate to a fingerprint sensor and a display device including the fingerprint sensor, which uses a pinhole array layer including a plurality of light-blocking patterns so that a bias voltage applying operation and a fingerprint sensing operation can be performed only on specific light-blocking patterns located in the display device.

[0009] Exemplary embodiments of the present inventive concept relate to a fingerprint sensor in which a light-blocking metal pattern is disposed over a gap between divided light-blocking patterns of a pinhole array layer, thereby providing an effective light-blocking function, and a display device including the fingerprint sensor.

[0010] Exemplary embodiments of the present inventive concept can provide a fingerprint sensor comprising: a light-transmitting hole array layer including a plurality of light-blocking patterns having a plurality of light-transmitting holes to form a light-transmitting path for light; a sensor layer including a plurality of light sensors configured to sense light that passes through the light-transmitting holes and is incident on the sensor layer; and a metal pattern configured to apply an electrical signal to pixels or the light-blocking patterns. Gaps between the light-blocking patterns may overlap with at least some of the metal patterns.

[0011] In an exemplary embodiment, the fingerprint sensor may further include a circuit element layer in which at least one circuit element forming each of the pixels is formed. The metal pattern may include a line formed in the circuit element layer.

[0012] In an exemplary embodiment, the metal pattern may include at least one of a scan line configured to supply a scan signal to a pixel, a data line configured to supply a data signal to the pixel, an emission control line configured to supply an emission control signal to the pixel, and a power line configured to apply driving power to the pixel.

[0013] In an exemplary embodiment, the fingerprint sensor may further include a contact layer configured to apply power to the light blocking pattern. The metal pattern may include a line formed in the contact layer.

[0014] In example embodiments, the contact layer may be electrically coupled to the light-blocking patterns through one or more contact holes and selectively apply a bias voltage to at least one of the light-blocking patterns.

[0015] In example embodiments, each of the pixels may include at least one transistor, and when a bias voltage is selectively applied to at least one of the light-blocking patterns, a threshold voltage of the at least one transistor may be changed.

[0016] In an exemplary embodiment, each of the pixels may include a light emitting element. When a bias voltage is selectively applied to at least one of the light blocking patterns, current passing through the light emitting element may be controlled.

[0017] In an exemplary embodiment, the bias voltage may be a positive voltage.

[0018] In example embodiments, the light transmission hole array layer may include a plurality of light blocking patterns extending in a first direction and arranged in a second direction perpendicular to the first direction.

[0019] In example embodiments, the light transmission hole array layer may include a plurality of light blocking patterns arranged in a first direction and a second direction perpendicular to the first direction.

[0020] In an exemplary embodiment, the fingerprint sensor may further include a circuit element layer and a contact layer, wherein the circuit element layer is provided with at least one circuit element forming each pixel, and the contact layer is configured to apply power to the light-blocking pattern. The metal pattern may include a first metal pattern and a second metal pattern, wherein the first metal pattern includes lines formed in the circuit element layer, and the second metal pattern includes lines formed in the contact layer.

[0021] In example embodiments, first gaps extending in the first direction among the gaps between the light blocking patterns may overlap the first metal pattern, and second gaps extending in the second direction among the gaps may overlap the second metal pattern.

[0022] In example embodiments, the metal pattern may block light incident into gaps between the light blocking patterns.

[0023] Exemplary embodiments of the present inventive concept may provide a display device including: a display panel including pixels and a light-transmitting hole array layer, the light-transmitting hole array layer including a plurality of light-blocking patterns having a plurality of light-transmitting holes; a sensor layer formed on one surface of the display panel and including a plurality of light sensors configured to sense light incident through the display panel; and a metal pattern configured to apply an electrical signal to the pixels or the light-blocking patterns. Gaps between the light-blocking patterns may overlap with at least some of the metal patterns.

[0024] In an exemplary embodiment, the display panel may include a circuit element layer in which at least one circuit element forming each of the pixels is formed. The metal pattern may include a line formed in the circuit element layer.

[0025] In an exemplary embodiment, the metal pattern may include at least one of a scan line configured to supply a scan signal to a pixel, a data line configured to supply a data signal to the pixel, an emission control line configured to supply an emission control signal to the pixel, and a power line configured to apply driving power to the pixel.

[0026] In an exemplary embodiment, the display panel may include a contact layer configured to apply power to the light blocking pattern. The metal pattern may include a line formed in the contact layer.

[0027] In example embodiments, the contact layer may be electrically coupled to the light-blocking patterns through one or more contact holes and selectively apply a bias voltage to at least one of the light-blocking patterns.

[0028] In example embodiments, the light transmission hole array layer may include a plurality of light blocking patterns extending in a first direction and arranged in a second direction perpendicular to the first direction.

[0029] In example embodiments, the light transmission hole array layer may include a plurality of light blocking patterns arranged in a first direction and a second direction perpendicular to the first direction.

[0030] In an exemplary embodiment, a display panel may include a circuit element layer in which at least one circuit element forming each pixel is disposed, and a contact layer configured to apply power to the light blocking pattern. The metal pattern may include a first metal pattern and a second metal pattern, wherein the first metal pattern includes a line formed in the circuit element layer, and the second metal pattern includes a line formed in the contact layer.

[0031] In example embodiments, a first direction gap among the gaps between the light blocking patterns may overlap with the first metal pattern, and a second direction gap among the gaps may overlap with the second metal pattern.

[0032] In example embodiments, the metal pattern may block light incident into gaps between the light blocking patterns.

[0033] According to an exemplary embodiment of the present inventive concept, a display device includes: pixels coupled to scan lines and data lines; first to nth scan drivers configured to supply scan signals to the pixels through the scan lines; data drivers configured to supply data signals and bias signals to the pixels through the data lines; and a timing controller configured to supply image data and bias data to the data drivers and sequentially supply first to nth start signals to the first to nth scan drivers, respectively. The data signal is supplied to the pixel when the scan signal is supplied to the pixel during a display period, and the bias signal is supplied to the pixel when the scan signal is supplied to the pixel during a bias period between display periods, where n is a natural number greater than 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features of the present inventive concept will be more clearly understood by describing in detail exemplary embodiments of the present inventive concept with reference to the attached drawings.

[0035] Figure 1 and Figure 2 is a plan view schematically illustrating a display device according to an exemplary embodiment of the inventive concept.

[0036] Figures 3A to 3E is a plan view illustrating an arrangement structure of pixels and light sensors according to an embodiment of the inventive concept.

[0037] Figure 4 It shows Figures 1 to 3E A circuit diagram of an example of a pixel is shown in FIG.

[0038] Figure 5 It shows Figures 1 to 3E An example circuit diagram of a light sensor is shown in .

[0039] Figure 6 is a cross-sectional view of a display device according to an exemplary embodiment of the inventive concept.

[0040] Figure 7A and Figure 7B It shows Figure 6 A plan view of an exemplary embodiment of a pinhole array layer.

[0041] Figure 8 is used to describe the Figure 6 A graph showing changes in the characteristics of transistors in the circuit element layer caused by the bias voltage of the pinhole array layer.

[0042] Figure 9 yes Figure 6 An enlarged plan view of the area of ​​the display device shown in FIG.

[0043] Figure 10 It is along Figure 9 A cross-sectional view taken along line II′.

[0044] Figure 11 yes Figure 6 An enlarged plan view of the area of ​​the display device shown in FIG.

[0045] Figure 12 It is along Figure 11 A cross-sectional view taken along line II-II′.

[0046] Figure 13 is a cross-sectional view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0047] Figure 14 It shows Figure 13 A plan view of an exemplary embodiment of a pinhole array layer.

[0048] Figure 15 yes Figure 13 An enlarged plan view of the area of ​​the display device shown in FIG.

[0049] Figure 16 It is along Figure 15 A cross-sectional view taken along line III-III′.

[0050] Figure 17 is an enlarged plan view of a region of a display device according to an exemplary embodiment of the inventive concept.

[0051] Figure 18 It is along Figure 17 A cross-sectional view taken along line IV-IV′. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the inventive concept provide a display device for initializing a threshold voltage characteristic of a driving transistor by applying a start-up bias voltage to the driving transistor during a vertical blanking period, and a driving method of the display device.

[0053] Throughout the specification, when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element, or indirectly connected or coupled to the other element with one or more intervening elements interposed therebetween. It should also be understood that when an element is referred to as being between two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0054] Exemplary embodiments of the present inventive concept will be described in more detail below with reference to the accompanying drawings.Throughout this application, like reference numerals may denote like elements.

[0055] Figure 1 and Figure 2 Schematically illustrates a display device 10 according to an exemplary embodiment of the present invention. Figure 1 and Figure 2 1 is a diagram schematically illustrating a display panel 110 provided in a display device 10 and a driving circuit 200 for driving the display panel 110 according to an exemplary embodiment of the present inventive concept. Figure 1 and Figure 2 The display panel 110 and the driving circuit 200 are shown to be separately provided, but the present inventive concept is not limited thereto. For example, all or part of the driving circuit 200 may be integrally formed on the display panel 110 .

[0056] refer to Figure 1 and Figure 2 , the display device 10 may include a display panel 110 and a driving circuit 200 configured to drive the display panel 110 .

[0057] The display panel 110 includes a display area AA and a non-display area NA. The display area AA is a region in which a plurality of pixels PXL are disposed and may be referred to as an active area. In an exemplary embodiment, each of the pixels PXL may include at least one light-emitting element. The display device 10 may drive the pixels PXL in response to image data input from an external device, thereby displaying an image in the display area AA.

[0058] In an exemplary embodiment of the present inventive concept, the display area AA may include the sensing area SA. The sensing area SA may include at least some of the pixels PXL disposed in the display area AA.

[0059] In an exemplary embodiment, Figure 1 As shown in FIG, at least a portion of the display area AA may be configured as a sensing area SA. Figure 2 As shown in , the entire display area AA may be set as the sensing area SA.

[0060] Although Figure 1 Although an example is shown in which only one sensing area SA is formed in the display area AA, the technical spirit of the present inventive concept is not limited thereto. In other words, in exemplary embodiments, a plurality of sensing areas SA arranged in a regular or irregular pattern may be formed in the display area AA. In these exemplary embodiments, the plurality of sensing areas SA may have the same or different surface areas and shapes.

[0061] Although Figure 1 An example is shown in which the sensing area SA is formed in at least a portion of the display area AA, but the technical spirit of the inventive concept is not limited thereto. In other words, in an exemplary embodiment, the display area AA and the sensing area SA may be disposed to overlap each other only in some areas.

[0062] The non-display area NA is an area disposed around the display area AA and may be referred to as a non-active area. In an exemplary embodiment, the non-display area NA may refer to other areas of the display panel 110 excluding the display area AA. In an exemplary embodiment, the non-display area NA may include, for example, a line area, a pad area, and various dummy areas.

[0063] In an exemplary embodiment of the present inventive concept, the display device 10 may further include a plurality of light sensors PHS disposed in the sensing area SA. In an exemplary embodiment, the light sensor PHS may sense light reflected by a user's finger after being emitted from a light source, and analyze the reflected light to sense the user's fingerprint. Although the light sensor PHS will be described below as being used for fingerprint sensing by way of example, the light sensor PHS may be used for a variety of purposes and to perform various functions, for example, as a touch sensor and a scanner.

[0064] In an exemplary embodiment of the present inventive concept, the light sensor PHS may be disposed in the sensing area SA. Here, the light sensor PHS may overlap with at least some or all of the pixels PXL disposed in the sensing area SA, or may be disposed to surround the pixels PXL. For example, at least some or all of the light sensors PHS may be disposed between the pixels PXL. Figures 3A to 3EAn exemplary embodiment of the arrangement relationship between the photosensor PHS and the pixels PXL is described in more detail.

[0065] In an exemplary embodiment in which the light sensor PHS is positioned adjacent to the pixels PXL, the light sensor PHS may utilize a light-emitting element disposed in at least one pixel PXL disposed in or surrounding the sensing area SA as a light source. In this exemplary embodiment, the light sensor PHS, together with the pixels PXL of the sensing area SA and the light-emitting elements disposed in the pixels PXL, may form a light-sensing fingerprint sensor. In this manner, when a fingerprint sensor-embedded display device is configured to utilize the pixels PXL as a light source rather than a separate external light source, the thickness of the light-sensing fingerprint sensor and the display device's module including the fingerprint sensor may be reduced, and production costs may also be reduced.

[0066] In an exemplary embodiment, the light sensor PHS may be provided on both an image display surface (eg, front surface) and another surface (eg, rear surface) opposite to the front surface of the display panel 110. However, the present inventive concept is not limited thereto.

[0067] In exemplary embodiments of the present invention, the display device 10 may further include an optical system for configuring the optical sensor PHS and the optical sensing type fingerprint sensor. In these exemplary embodiments, at least a portion of the optical system may be integrally formed with the display panel 110. For example, the display panel 110 may include a pinhole array layer (e.g., see FIG. Figure 7A and Figure 7B An optical system-integrated display panel (“PHL” in FIG).

[0068] The driving circuit 200 may drive the display panel 110. For example, the driving circuit 200 may output a data signal corresponding to image data to the display panel 110, or may output a driving signal for the optical sensor PHS and receive a sensing signal from the optical sensor PHS. The driving circuit 200, having received the sensing signal, may detect the shape of the user's fingerprint using the sensing signal.

[0069] In an exemplary embodiment of the present inventive concept, the driving circuit 200 may include a panel driving unit 210 and a fingerprint detection unit 220. In some examples, the fingerprint detection unit 220 may detect a fingerprint, which may then be analyzed based on features known as minutiae points (i.e., fingerprint features including points where fingerprint ridges connect, branch, or terminate). For example, the processor of the display device 10 may measure the distances and angles between the minutiae points and then convert information about the minutiae points and their relationships into a unique code corresponding to a specific fingerprint. This code may then be used to identify or authenticate the user.

[0070] According to an embodiment of the present invention, a method for fingerprint detection may include: identifying the position of a finger placed in or near the display area AA; selecting a portion of the display area AA corresponding to the position of the finger (which may be a portion of the sensing area SA); and applying a bias voltage to the pixel PXL (or one or more patterns of the pinhole array layer) of the display device 10 corresponding to the selected portion of the display area AA.

[0071] In some examples, the method may include: increasing the brightness of a portion of the display area AA where the finger is located (i.e., based on applying a bias voltage); blocking a first portion of light reflected from the finger, wherein the light reflected from the finger is at least partially based on the increased brightness, wherein the first portion of light is blocked using a light blocking pattern that is aligned with one or more gaps in one or more patterns of the pinhole array layer; and utilizing a sensor layer of the display device 10 (see Figure 6 '120' in the figure) sensing a second portion of the light reflected from the finger, wherein the second portion of the light passes through the pinholes in the one or more patterns of the pinhole array layer; and detecting the fingerprint based on the second portion of the light.

[0072] In other words, the pinhole array layer can be divided into regions so that when a finger is placed near display device 10, only those regions near the finger have increased brightness. This can improve the accuracy of fingerprint detection without affecting the display quality of the rest of the display area. If the finger is placed in another position, a different region can be selected for increased brightness.

[0073] Because the pinhole array layer is segmented into different parts (i.e., to have bias voltages selectively applied to subsets of regions based on finger position), gaps may exist between different regions (i.e., between different patterns in the pinhole array layer). Therefore, according to various embodiments of the present disclosure, metal patterns in layers other than the pinhole array layer may be aligned with the gaps. For example, the metal patterns may include power lines for pixels, emission control lines, scan lines (such as Figure 9 and Figure 10 In), data line (such as Figures 11 to 12 ), contact layer pattern (such as Figures 15 and 16 or other metal patterns (such as Figures 17 and 18 middle).

[0074] Although Figure 1 and Figure 2 The panel driving unit 210 and the fingerprint detecting unit 220 are shown as being separately provided, but the technical spirit of the present inventive concept is not limited thereto. For example, at least a portion of the fingerprint detecting unit 220 may be integrated with the panel driving unit 210 or interlocked with the panel driving unit 210 .

[0075] The panel driving unit 210 may sequentially scan the pixels PXL of the display area AA and supply data signals corresponding to image data to the pixels PXL, thereby allowing the display panel 110 to display an image corresponding to the image data.

[0076] In an exemplary embodiment, the panel drive unit 210 may supply a drive signal for fingerprint sensing to the pixel PXL. The drive signal may be configured to cause the pixel PXL to emit light and operate as a light source for the light sensor PHS. In this exemplary embodiment, the drive signal for fingerprint sensing may be provided to the pixels PXL disposed in a specific area of ​​the display panel 110, for example, to the pixels PXL disposed in the sensing area SA. In an exemplary embodiment, the drive signal for fingerprint sensing may be provided by the fingerprint detection unit 220.

[0077] The fingerprint detection unit 220 may transmit a driving signal for driving the light sensor PHS to the light sensor PHS and detect a fingerprint of the user based on a sensing signal received from the light sensor PHS.

[0078] The embodiments of the present disclosure describe how the fingerprint detection unit 220 can perform accurate fingerprint sensing without degrading the quality of the image in the display area AA.

[0079] Figures 3A to 3E is a plan view illustrating an exemplary embodiment of an arrangement structure of a pixel PXL and a photo sensor PHS according to an embodiment of the inventive concept. Figures 3A to 3E Various exemplary embodiments are shown regarding relative sizes, resolutions, and arrangement relationships between one or more pixels PXL and the photosensor PHS provided in the sensing area SA.

[0080] refer to Figure 3A , the light sensors PHS may be provided in the sensing area SA with the same resolution (or the same density) as that of the pixels PXL. In other words, the number of light sensors PHS provided in the sensing area SA may be the same as the number of pixels PXL. In this exemplary embodiment, the pixels PXL and the light sensors PHS may be provided in pairs one to one with each other. Figure 3A In the exemplary embodiment, the pixel PXL and the light sensor PHS have been shown to overlap with each other. However, in the exemplary embodiment, the pixel PXL and the light sensor PHS may not overlap with each other, or may overlap with each other only in some areas. Figure 3AIn the exemplary embodiment, each light sensor PHS is shown to have a size smaller than that of each pixel PXL, but the technical spirit of the present inventive concept is not limited thereto. For example, in the exemplary embodiment, each light sensor PHS may have a size equal to or larger than that of each pixel PXL. Figure 3C and Figure 3D This exemplary embodiment is shown in FIG.

[0081] refer to Figures 3B to 3E , the light sensors PHS may be provided in the sensing area SA with a resolution lower than that of the pixels PXL. In other words, the number of light sensors PHS provided in the sensing area SA may be less than the number of pixels PXL. Figures 3B to 3E An example is shown in which one light sensor PHS is provided every four pixels PXL, but the inventive concept is not limited thereto.

[0082] In this exemplary embodiment, Figure 3B and Figure 3E As shown in , each photosensor PHS may have a size smaller than that of each pixel PXL, or as Figure 3C and Figure 3D As shown in , each light sensor PHS may have a size larger than that of each pixel PXL. In the case where the light sensors PHS are provided with a resolution smaller than that of the pixels PXL, some or all of the light sensors PHS may be provided to overlap with the pixels PXL. In other words, Figure 3B and Figure 3C As shown in , the photosensor PHS may partially overlap with some of the pixels PXL.

[0083] Alternatively, as Figure 3D As shown in FIG, the light sensor PHS may be disposed between the pixels PXL and partially overlap with the pixels PXL. In this exemplary embodiment, as shown in FIG. Figure 3D As shown in , each light sensor PHS may have a size larger than that of each pixel PXL. For example, each light sensor PHS may have a size suitable for covering at least one pixel PXL.

[0084] Alternatively, as Figure 3E As shown in , the photosensor PHS may not overlap with the pixel PXL.

[0085] In an embodiment of the present invention, the arrangement structure between the pixels PXL and the light sensors PHS is not limited to the above arrangement structure. In other words, within the scope of the technical spirit of the present invention, the shape, arrangement, relative size, number, resolution, etc. of the pixels PXL and the light sensors PHS in the sensing area SA can be modified in various ways. In addition, in an exemplary embodiment, the pixels PXL and the light sensors PHS can be arranged in a manner that is consistent with the present invention. Figures 3A to 3E In the exemplary embodiment, two or more combinations are provided.

[0086] In addition, although Figures 3A to 3E The light sensors PHS have been shown to be regularly arranged in the sensing area SA, but the technical spirit of the inventive concept is not limited thereto. In an exemplary embodiment, the light sensors PHS may be irregularly arranged in the sensing area SA. In some embodiments, the number or density of the light sensors PHS may be greater than the number or density of the pixels PXL. Although Figures 3A to 3E The pixel PXL and the light sensor PHS are shown to be arranged horizontally, but as shown below Figure 6 As shown, the pixels PXL and the photosensors PHS may be vertically separated (ie, located in separate horizontal layers). Figure 4 It shows Figures 1 to 3E For the purpose of description, Figure 4 1 and 2. The pixel PXL is shown as being disposed on both the i-th scan line Si (i is a natural number) and the j-th data line Dj (j is a natural number), wherein the i-th scan line Si is disposed on the i-th horizontal pixel line and the j-th data line Dj is disposed on the j-th vertical pixel line. However, the structure of the pixel PXL according to the present invention is not limited to Figure 4 The structure shown in .

[0087] refer to Figure 4 According to an exemplary embodiment of the present inventive concept, the pixel PXL may include a light emitting element LD, first to seventh transistors T1 to T7, and a storage capacitor Cst. In an exemplary embodiment, the light emitting element LD may be an organic light emitting diode (OLED), but the present inventive concept is not limited thereto.

[0088] The anode electrode of the light-emitting element LD may be coupled to the first transistor T1 via the sixth transistor T6, and the cathode electrode of the light-emitting element LD may be coupled to the second power supply ELVSS. The light-emitting element LD may emit light having a predetermined brightness corresponding to the current supplied from the first transistor T1. The voltage of the first power supply ELVDD may be set to a value higher than the voltage of the second power supply ELVSS to allow current to flow to the light-emitting element LD.

[0089] The seventh transistor T7 may be coupled between an initialization power supply Vint and a first electrode (e.g., an anode electrode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 may be coupled to the (i+1)th scan line Si+1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on, so that the voltage of the initialization power supply Vint can be supplied to the anode electrode of the light-emitting element LD. The voltage of the initialization power supply Vint may be set to a voltage lower than that of the data signal. In other words, the voltage of the initialization power supply Vint may be set to the lowest voltage of the data signal or lower.

[0090] Although the exemplary embodiment describes the case where the anode initialization control line coupled to the gate electrode of the seventh transistor T7 is the (i+1)th scan line Si+1, the present invention is not limited thereto. For example, in an exemplary embodiment of the present invention, the gate electrode of the seventh transistor T7 may be coupled to the i-th scan line Si. In this case, when a gate-on scan signal is supplied to the i-th scan line Si, the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light-emitting element LD via the seventh transistor T7.

[0091] The sixth transistor T6 is coupled between the first transistor T1 and the light emitting element LD. A gate electrode of the sixth transistor T6 may be coupled to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage (e.g., a high-level voltage) is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0092] The fifth transistor T5 may be coupled between the first power source ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be coupled to the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0093] A first electrode of the first transistor T1 (driving transistor) may be coupled to the first power supply ELVDD via the fifth transistor T5, and a second electrode thereof may be coupled to the anode electrode of the light-emitting element LD via the sixth transistor T6. A gate electrode of the first transistor T1 may be coupled to a first node N1. The first transistor T1 may control a current flowing from the first power supply ELVDD to the second power supply ELVSS via the light-emitting element LD in response to a voltage at the first node N1.

[0094] The third transistor T3 may be coupled between the first node N1 and the second electrode of the first transistor T1. A gate electrode of the third transistor T3 may be coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the third transistor T3 may be turned on to electrically connect the second electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0095] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to the (i-1)th scan line Si-1. When a scan signal is supplied to the (i-1)th scan line Si-1, the fourth transistor T4 is turned on, so that the voltage of the initialization power supply Vint can be supplied to the first node N1. In this exemplary embodiment, the (i-1)th scan line Si-1 may be used as an initialization control line to initialize the gate node of the first transistor T1, that is, the first node N1. However, the present inventive concept is not limited thereto. For example, in an exemplary embodiment, another control line (e.g., the (i-2)th scan line Si-2) may be used as an initialization control line to initialize the gate node of the first transistor T1.

[0096] The second transistor T2 may be coupled between the j-th data line Dj and the first electrode of the first transistor T1. A gate electrode of the second transistor T2 may be coupled to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the second transistor T2 may be turned on, so that the first electrode of the first transistor T1 may be electrically coupled to the j-th data line Dj.

[0097] The storage capacitor Cst may be coupled between the first power source ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0098] The structure of the pixel PXL is not limited to Figure 4 For example, various pixel circuits having known structures may be applied to the pixel PXL.

[0099] Figure 5 It shows Figures 1 to 3E For the purpose of description, Figure 5 Only the light sensor PHS coupled to the mth horizontal sensing line Txm (m is a natural number) and the nth vertical sensing line Rxn (n is a natural number) is shown. In an exemplary embodiment, the horizontal sensing lines and the vertical sensing lines may be arranged in the same manner as Figure 5 In these exemplary embodiments, the elements constituting the light sensor PHS may also be oriented in corresponding directions.

[0100] refer to Figure 5 , the light sensor PHS according to an exemplary embodiment of the inventive concept may include a photodiode PD and a transistor M.

[0101] The photodiode PD may be configured to convert light energy into electric energy by generating a photoelectromotive force that changes current according to the intensity of incident light.

[0102] A transistor M is coupled between the nth vertical sensing line Rxn and the photodiode PD. A gate electrode of the transistor M is coupled to the mth horizontal sensing line Txm. When a driving signal having a gate-on voltage (e.g., a low voltage) is supplied to the mth horizontal sensing line Txm, the transistor M is turned on. When the transistor M is turned on, current flowing through the photodiode PD may flow to the nth vertical sensing line Rxn.

[0103] The display apparatus 10 may apply a driving signal to the horizontal sensing line coupled to the light sensor PHS and sense the fingerprint of the user based on a current supplied to the vertical sensing line (hereinafter, referred to as a sensing signal).

[0104] Figure 6 is a cross-sectional view of a display apparatus 10 according to an exemplary embodiment of the inventive concept. Figure 7A and Figure 7B It shows Figure 6 FIG. 1 is a plan view of an exemplary embodiment of a pinhole array layer PHL. Figure 8 is used to describe the Figure 6 A graph showing changes in characteristics of transistors in the circuit element layer BPL caused by the bias voltage of the pinhole array layer PHL.

[0105] refer to Figure 6 , a display device 10 according to an exemplary embodiment of the present inventive concept may include a display panel 110, a sensor layer 120, and a window 130, wherein the display panel 110 includes a plurality of pixels PXL, the sensor layer 120 is provided on one surface of the display panel 110, and the window 130 is provided on the other surface of the display panel 110. Specifically, Figure 6 A cross section of the display device 10 is shown on which a finger has been pressed to perform a fingerprint detection operation. A finger may include ridges and valleys in a unique pattern that enables the fingerprint to be recognized by the display device 10.

[0106] The display panel 110 may include a first substrate SUB1, and a circuit element layer BPL, a light emitting element layer LDL, a first protection layer PTL1, and a first adhesive layer ADL1 sequentially disposed on a first surface (eg, an upper surface) of the first substrate SUB1.

[0107] The first substrate SUB1 may be a base substrate of the display panel 110 and may be formed of a substantially transparent light-transmitting substrate. In an exemplary embodiment, the first substrate SUB1 may be a thin film substrate formed of polyimide (PI). In an exemplary embodiment, the first substrate SUB1 may be formed of a rigid substrate including glass or tempered glass or a flexible substrate made of plastic. However, the material of the first substrate SUB1 is not limited thereto, and the first substrate SUB1 may be formed of various materials. In an exemplary embodiment of the present inventive concept, as Figure 1 and Figure 2 As shown in FIG, the first substrate SUB1 may include a display area AA and a non-display area NA.

[0108] The circuit element layer BPL may be disposed on the first surface of the first substrate SUB1 and may include at least one conductive layer. For example, the circuit element layer BPL may include a plurality of circuit elements constituting the pixel circuit of each pixel PXL, as well as lines configured to supply power and signals for driving the pixel PXL, such as scan lines, data lines, emission control lines, and power lines. In this exemplary embodiment, the circuit element layer BPL may include circuit elements such as transistors and capacitors, and a plurality of conductive layers configured to form lines connected to the circuit elements.

[0109] The light emitting element layer LDL may be disposed on the circuit element layer BPL. In an exemplary embodiment, the light emitting element layer LDL may include a plurality of light emitting elements LD, which are coupled to circuit elements and / or lines of the circuit element layer BPL through contact holes, etc. Such light emitting elements LD may form each pixel PXL.

[0110] In these exemplary embodiments, each of the pixels PXL may be formed of a circuit element provided in the circuit element layer BPL and a light emitting element LD provided in the light emitting element layer LDL.

[0111] The first protective layer PTL1 may be provided on the light emitting element layer LDL to cover all or part of the display panel 110, for example, to cover the display area AA. In an exemplary embodiment, the first protective layer PTL1 may include a thin film encapsulation (TFE) layer or a sealing member such as an encapsulation substrate. The first protective layer PTL1 may also include a protective film, etc.

[0112] The first adhesive layer ADL1 may be disposed between the first protective layer PTL1 and the window 130 and couple the first protective layer PTL1 with the window 130. In an exemplary embodiment, the first adhesive layer ADL1 may include a transparent adhesive such as an optically clear adhesive (OCA), but the adhesive material is not limited thereto.

[0113] In an exemplary embodiment, the display panel 110 may further include a second protection layer PTL2 and a second adhesive layer ADL2 sequentially disposed on a second surface (eg, a lower surface) of the first substrate SUB1.

[0114] The second protection layer PTL2 may be disposed on the second surface of the first substrate SUB1 and include at least one film layer such as a protection film layer.

[0115] The second adhesive layer ADL2 may be disposed between the second protection layer PTL2 and the sensor layer 120 and couple the second protection layer PTL2 with the sensor layer 120. Although the second adhesive layer ADL2 may include a transparent adhesive such as OCA, the adhesive material is not limited thereto.

[0116] In an exemplary embodiment of the present inventive concept, the display panel 110 may further include a pinhole array layer PHL (i.e., a light-transmitting hole array layer). In an exemplary embodiment, the pinhole array layer PHL may be disposed to overlap with one or more sensing areas SA. In other words, the sensing area SA of the display device 10 may be defined to correspond to the arrangement of the pinhole array layer PHL.

[0117] However, the technical spirit of the present inventive concept is not limited thereto. In other words, the pin hole array layer PHL may be provided in the entire display area AA of the display panel 110 .

[0118] The pinhole array layer PHL is disposed between the light-emitting element layer LDL and the sensor layer 120 and is configured to selectively transmit incident light therethrough. By allowing light to pass through the pinhole array layer PHL before reaching the sensor layer 120, the display device 10 can improve the accuracy of fingerprint detection. Each pinhole PIH in the pinhole array layer PHL can transmit light from a specific field of view (FOV) to the sensor layer 120, which can be controlled by modifying the design of the pinhole array layer PHL. In addition, a bias voltage can be selectively applied to portions of the pinhole array layer PHL, causing the pixels PXL corresponding to these portions to have increased brightness. This can further improve the accuracy of fingerprint detection without affecting the display quality of the entire display area AA.

[0119] Specifically, if Figure 7A and Figure 7B As shown in , the pinhole array layer PHL may be formed of a light blocking mask LBM having a plurality of pinholes PIH. In some examples, each pinhole PIH may be configured to project a sub-image corresponding to specific portions of the display area AA onto the photosensor PHS.

[0120] The light blocking mask LBM may be formed of an opaque metal layer partially open in the portion where the pinholes PIH are formed. However, the material of the light blocking mask LBM is not limited to metal, and the light blocking mask LBM may be formed of various materials capable of blocking the transmission of light. For example, the light blocking mask LBM may be formed of a black matrix material. In an exemplary embodiment, the light blocking mask LBM may be rigid or flexible.

[0121] The pinholes PIH may form openings distributed in the light blocking mask LBM. In other words, the pinhole array layer PHL may include a plurality of pinholes PIH having the same or different sizes and being regularly or irregularly arranged in the light blocking mask LBM at positions spaced apart from each other at the same or different intervals.

[0122] The pinholes (PIH) can be appropriately sized and spaced to prevent diffraction of incident light and more clearly sense the user's fingerprint shape. For example, the width of each pinhole (PIH) can be set to a value that is ten times or more the wavelength of the incident light to prevent light diffraction. For example, the width of the pinholes (PIH) can range from 2 μm to 15 μm.

[0123] Furthermore, the spacing between the pinholes PIH can be determined based on the distance between the pinhole array layer PHL and the sensor layer 120, the wavelength of the incident light, and the field of view (FOV) required for each pinhole PIH. In an exemplary embodiment, the angle of the field of view (FOV) of the pinhole PIH may be approximately in the range of 30° to 60°, for example, 45°, but is not limited thereto. In an exemplary embodiment, when the angle of the field of view (FOV) is approximately 45°, the spacing between the pinholes PIH may be set to a value that is twice or more of the distance between the pinhole array layer PHL and the sensor layer 120, or may be set to or greater than a value obtained by adding a predetermined error range to the distance. For example, each pinhole PIH may have a width in the range of approximately 5 μm to approximately 15 μm (or a diameter in the range of approximately 5 μm to approximately 15 μm in the case of a circular shape) along a first direction DR1 (e.g., a vertical direction) and / or a second direction DR2 (e.g., a horizontal direction) perpendicular to the first direction DR1.

[0124] However, the technical spirit of the present invention is not limited thereto, and the size, shape, number, resolution, and arrangement of the pinholes PIH may be modified in various ways. For example, in an exemplary embodiment of the present invention, the pinholes PIH may be arranged in an irregular pattern in the light blocking mask LBM. In addition, the size of each pinhole PIH may be changed according to various factors such as the wavelength bandwidth of light to be used for sensing fingerprints and the thickness of each of the layers constituting the display device 10. In an exemplary embodiment of the present invention, as Figure 7A and Figure 7B As shown in , the pinhole array layer PHL may be formed of a plurality of light-blocking patterns A (which may be referred to as “light-blocking regions”).

[0125] In an exemplary embodiment, Figure 7A As shown in , the pinhole array layer PHL may be formed of a plurality of light blocking patterns A arranged in the first direction DR1. For example, the light blocking patterns A of the pinhole array layer PHL may be disposed to correspond to at least some of a plurality of pixel rows disposed in the display panel 110, respectively.

[0126] In an exemplary embodiment, Figure 7B As shown in , the pinhole array layer PHL may be formed of a plurality of light-blocking patterns A arranged in the second direction DR2. For example, the light-blocking patterns A of the pinhole array layer PHL may be arranged to correspond to at least some of the plurality of pixel columns provided in the display panel 110. In the exemplary embodiment described above, a light-blocking metal pattern capable of blocking light transmission may be formed above the gaps G defined between the light-blocking patterns A. The metal pattern may include lines for supplying drive signals or power (drive power, initialization power, etc.) to the pixels PXL, for example, scan lines for supplying scan signals to the pixels PXL, emission control lines for supplying emission control signals to the pixels PXL, data lines for supplying data signals to the pixels PXL, and power lines for applying drive power to the pixels PXL.

[0127] Will refer to it later Figure 10 and Figure 12 An exemplary embodiment in which the metal pattern is disposed over the gap G between the light blocking patterns A of the pinhole array layer PHL is described in more detail.

[0128] Although Figure 7A and Figure 7B Although an example is shown in which each light-blocking pattern A of the pinhole array layer PHL includes one pinhole row or one pinhole column, the technical spirit of the present inventive concept is not limited thereto. In an exemplary embodiment of the present inventive concept, two or more pinhole rows and / or two or more pinhole columns may be formed in each light-blocking pattern A of the pinhole array layer PHL.

[0129] In addition, although Figure 7A and Figure 7B In the example shown, pinholes PIH having the same size and shape are regularly arranged in each light-blocking pattern A of the pinhole array layer PHL, but the technical spirit of the present inventive concept is not limited thereto. In exemplary embodiments, a plurality of pinholes PIH may be regularly or irregularly arranged in each light-blocking pattern A of the pinhole array layer PHL. In these exemplary embodiments, the plurality of pinholes PIH may have the same or different surface areas and / or shapes.

[0130] Due to the pinhole array layer PHL having the above-described structure, some of the light incident on the pinhole array layer PHL may be blocked by the light blocking mask LBM, and other light may pass through the pinholes PIH and reach the sensor layer 120 provided below the pinhole array layer PHL. In an exemplary embodiment of the present invention, the light incident on the pinhole array layer PHL may be light reflected by an object (e.g., a finger) placed on the display device 10 (hereinafter, referred to as "reflected light"). In other words, reflected light emitted from the pixel PXL (in more detail, the light emitting element LD of the pixel PXL) and reflected by the user's finger may be incident on the pinhole array layer PHL. Among the incident reflected light, some reflected light that has reached the light blocking mask LBM may be blocked by the light blocking mask LBM, and only some reflected light that has been incident on the pinholes PIH may pass through the pinholes PIH and reach the sensor layer 120. Although not shown in these drawings, in an exemplary embodiment of the present invention, an insulating layer may be further provided on each of the opposite surfaces of the pinhole array layer PHL (see Figure 10 、 Figure 12 、 Figure 16 and Figure 18 INS1 and INS2 in FIG. 1 ). The insulating layer may be provided to prevent impurities from diffusing on the pinhole array layer PHL, and may have a single-layer structure or a multi-layer structure. In the case where the insulating layer has a multi-layer structure, the multiple layers of the insulating layer may be formed of the same or different materials.

[0131] In an exemplary embodiment of the present inventive concept, the pinhole array layer PHL may receive a bias voltage through a power line (not shown). If the bias voltage is applied to the pinhole array layer PHL, electrical characteristics of at least one circuit element (e.g., a transistor) provided in the circuit element layer BPL may change.

[0132] refer to Figure 8 (and a pixel circuit Figure 4 ), the graph shows a vertical axis representing the current (Ids) flowing through the light-emitting element LD, and a horizontal axis representing the bias voltage (Vg) at the pinhole array layer PHL. When a negative bias voltage is applied to the pinhole array layer PHL, the threshold voltage of the first transistor T1 provided on the circuit element layer BPL can be increased due to the field effect of the pinhole array layer PHL. As a result, the current (Ids) flowing through the light-emitting element LD can be reduced (within a certain range of bias voltages). Conversely, when a positive bias voltage is applied to the pinhole array layer PHL, the threshold voltage of the first transistor T1 can be reduced. As a result, the current (Ids) flowing through the light-emitting element LD can be increased.

[0133] If the current flowing to the light-emitting element LD increases, the amount of light emitted from the light-emitting element LD can increase. If the amount of light emitted from the light-emitting element LD increases, the intensity of the reflected light incident on the pinhole array layer PHL can increase. Therefore, the intensity of light that passes through the pinholes PIH and reaches the sensor layer 120 can also increase. Therefore, the amount of light having the characteristics (based on which the photosensor PHS provided on the sensor layer 120 outputs the sensing signal) can increase. The accuracy of fingerprint sensing based on the sensing signal can be improved.

[0134] However, a change in the amount of light in each pixel PXL may degrade the quality of an image displayed on the display panel 110. Therefore, in an exemplary embodiment of the present inventive concept, in the case where the pinhole array layer PHL is formed of a plurality of light-blocking patterns A, a bias voltage may be applied only to some of the light-blocking patterns A that will be substantially involved in fingerprint sensing.

[0135] As described above, in the case where the pinhole array layer PHL is integrally provided in the display panel 110, the thickness of the module of the display device 10 can be reduced. However, in some exemplary embodiments, the pinhole array layer PHL may be separately provided under the display panel 110, rather than being integrally provided with the display panel 110. In these exemplary embodiments, the pinhole array layer PHL may be attached to the lower surface of the display panel 110 by an adhesive or the like.

[0136] In another exemplary embodiment of the present inventive concept, the display panel 110 may be transparent in a region where the pinholes PIH are provided so as to allow reflected light to pass through the corresponding pinholes PIH. Specifically, the display panel 110 may be transparent at positions corresponding to the pinholes PIH and the surrounding regions of the pinholes PIH so as to satisfy the field of view (FOV) required for each pinhole PIH.

[0137] The sensor layer 120 may be disposed on one surface of the display panel 110 such that the sensor layer 120 overlaps at least a portion of the display panel 110. For example, the sensor layer 120 may be disposed to overlap the sensing area SA of the display panel 110.

[0138] like Figure 6 As shown in , the sensor layer 120 may be provided on the lower surface (e.g., the surface opposite to the surface on which an image is displayed) of the display panel 110. For example, the sensor layer 120 may be implemented as a sensor integrated circuit (IC) attached to the lower surface of the display panel 110. In an exemplary embodiment in which the sensor layer 120 is provided on the lower surface of the display panel 110, degradation of the image quality of the display device 10 due to the sensor layer 120 may be prevented.

[0139] The sensor layer 120 may include a plurality of light sensors PHS arranged at a predetermined resolution (density, pitch). Figures 3A to 3E As described, the light sensors PHS may have various sizes, numbers, resolutions, and arrangements with respect to the pixels PXL in the display panel 110 .

[0140] The light sensor PHS can output an electrical signal corresponding to the reflected light received after passing through the pinhole PIH as a sensing signal. The reflected light received by the light sensor PHS can have different optical characteristics (e.g., frequency, wavelength, and intensity) depending on whether the reflected light is formed by the valleys or ridges of the user's fingerprint. Therefore, the light sensor PHS can output a sensing signal having different electrical characteristics corresponding to the optical characteristics of the reflected light. The sensing signal output from the light sensor PHS can be converted into image data and used to identify the user's fingerprint (i.e., detect the fingerprint minutiae feature points and the relationship between them).

[0141] The window 130 may be a protective member disposed on the uppermost surface of the display device 10 including the display panel 110 and may be a substantially transparent light-transmitting substrate. The window 130 may include a rigid or flexible substrate, and its constituent material is not limited to a specific material.

[0142] In addition, although not shown, in an exemplary embodiment, the display device 10 may further include, for example, a polarizing plate and / or a touch sensor layer (touch electrode layer). The polarizing plate and / or the touch sensor layer may be provided between the first protective layer PTL1 and the window 130, but is not limited thereto.

[0143] Figure 9 It shows Figure 6 1 is an enlarged plan view of the area of ​​the display device 10 shown in FIG. Figure 10 It is along Figure 9 A cross-sectional view taken along line II′. Figure 9 and Figure 10 Shown in the Figure 6 A relative arrangement relationship between the scan lines Si-2 to Si+5 on the circuit element layer BPL and the plurality of light-blocking patterns A included in the pinhole array layer PHL.

[0144] refer to Figure 9 and Figure 10 Together Figures 1 to 8 The display device 10 may include pixels PXL of the display area AA and a line unit configured to supply driving signals and / or power to the pixels PXL. In an exemplary embodiment, the line unit may include scan lines, data lines, emission control lines, and power lines.

[0145] In an exemplary embodiment of the present inventive concept, the line unit may be made of a metal material such as titanium (Ti), copper (Cu), molybdenum (Mo), aluminum (Al), gold (Au), chromium (Cr), titanium nitride (TiN), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), tin (Sn), cobalt (Co), rhenium (Rh), iridium (Ir), iron (Fe), ruthenium (Ru), osmium (Os), manganese (Mn), tungsten (W), niobium (Nb), tantalum (Ta), bismuth (Bi), antimony (Sb), lead (Pb), etc. In addition, various other metals may be used.

[0146] Alternatively, the wire unit may be made of an alloy, such as a molybdenum-titanium alloy (MoTi) or an aluminum-nickel-lanthanum (La) alloy (AlNiLa). In an exemplary embodiment, the wire unit may have a multilayer structure. In this exemplary embodiment, the wire unit may be formed of a conductive material having a multilayer structure, such as Ti / Cu, Ti / Au, Mo / Al / Mo, indium tin oxide (ITO) / Ag / ITO, TiN / Ti / Al / Ti, or TiN / Ti / Cu / Ti.

[0147] However, the materials forming the line unit are not limited to those described above. In other words, the constituent materials of the line unit are not limited to metals. Any material can be used as long as it can provide conductivity sufficient to smoothly drive the pixel PXL. For example, the line unit can be formed of a conductive polymer or a conductive metal oxide. Examples of conductive polymers may include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polytolyl compounds, and mixtures thereof. For example, among the polythiophene compounds, poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT / PSS) compounds can be used. Examples of conductive metal oxides may include ITO, indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), tin dioxide (SnO2), etc.

[0148] For the purpose of explanation, Figure 9 and Figure 10 Only scan lines Si-2 to Si+5 are shown. Scan lines Si-2 to Si+5 may be disposed in the circuit element layer BPL and extend in the second direction DR2 in the display area AA. In an exemplary embodiment, the scan lines Si-2 to Si+5 may include an i-2th scan line Si-2 to an i+5th scan line Si+5 sequentially arranged in a first direction DR1 intersecting the second direction DR2. Scan lines Si-2 to Si+5 may receive scan signals. For example, the i-1th scan line Si-1 may receive the i-1th scan signal, the i-th scan line Si may receive the i-th scan signal, and the i+1th scan line Si+1 may receive the i+1th scan signal.

[0149] Each pixel PXL may be formed of a plurality of circuit elements provided in the circuit element layer BPL and a light emitting element LD provided in the light emitting element layer LDL. The pixel PXL may be supplied with scan signals, data signals, emission control signals, and driving voltages through a line unit provided in the circuit element layer BPL.

[0150] The pinhole array layer PHL may be disposed below the circuit element layer BPL. In an exemplary embodiment of the present inventive concept, the pinhole array layer PHL may be formed of a plurality of light blocking patterns A arranged in the first direction DR1. Each light blocking pattern A may have at least one pinhole PIH. Figure 9 As shown in , the pinholes PIH may have the same size and may be regularly arranged to form at least one pinhole row. However, the technical spirit of the present inventive concept is not limited thereto, and the pinholes PIH may be irregularly arranged in each light-blocking pattern A and may have the same or different sizes and / or shapes.

[0151] Here, each light blocking pattern A may overlap at least one of the scan lines Si-1, Si-2, Si+1, Si+2, Si+4, and Si+5. Figure 9 It is shown that one light-blocking pattern A overlaps two scan lines, but the technical spirit of the present inventive concept is not limited thereto. The number of scan lines overlapping each light-blocking pattern A may be reduced or increased.

[0152] In an exemplary embodiment of the present inventive concept, each light-blocking pattern A may not overlap with the scan lines Si-2 to Si+5. Whether each light-blocking pattern A overlaps with the scan lines Si-2 to Si+5 may be determined based on an arrangement relationship between the pixel PXL and the photosensor PHS, an arrangement relationship between the pixel PXL and the pinhole PIH, an arrangement relationship between the photosensor PHS and the pinhole PIH, a field of view FOV of the pinhole PIH, and relative sizes between the photosensor PHS and / or the pixel PXL.

[0153] When performing a fingerprint sensing operation, a bias voltage may be selectively applied to at least one of the multiple light-blocking patterns A. In an exemplary embodiment, a bias voltage may be selectively applied to at least one of the multiple light-blocking patterns A positioned at a location where a user's touch is to be sensed. The user's touch location may be sensed, for example, through changes in electromagnetic fields, pressure, brightness or intensity of ambient light, and the like. However, the technical spirit of the present inventive concept is not limited to the aforementioned description. In an exemplary embodiment, a bias voltage may be selectively applied to certain of the multiple light-blocking patterns A based on specific areas preset based on a usage mode or application.

[0154] In an exemplary embodiment, the bias voltage may have a positive value. The photosensor PHS disposed at a position corresponding to at least one light blocking pattern A to which the bias voltage is applied may sense reflected light received through the pinhole PIH of the corresponding light blocking pattern A and output a sensing signal corresponding thereto.

[0155] exist Figure 9 In the exemplary embodiment shown in , scan lines Si and Si+3 may be disposed above gaps G between the light-blocking patterns A. In other words, the light-blocking patterns A may be arranged so that each of the gaps G between the light-blocking patterns A overlaps with any one of scan lines Si-2 to Si+5. Scan lines Si and Si+3 disposed above the gaps G may block reflected light instead of the light-blocking mask LBM of the pinhole array layer PHL. Therefore, reflected light incident on the pinhole array layer PHL may be prevented from passing through the gaps G and reaching the sensor layer 120.

[0156] In this exemplary embodiment, the distance between the light blocking patterns A (the width of each gap G) may correspond to the width of the corresponding scan line Si or Si+3. The width of each gap G may be generally equal to or smaller than the width of the corresponding scan line Si or Si+3 disposed above the gap G. The width of each of the scan lines Si and Si+3 may be greater than the width of the corresponding gap G.

[0157] Although Figure 9 and Figure 10 An example is shown in which the i-th scan line Si is disposed above the gap G between the light-blocking patterns A included in the pinhole array layer PHL, but the technical spirit of the present inventive concept is not limited thereto. In an exemplary embodiment, lines (e.g., emission control lines and power lines) extending in the circuit element layer BPL in the second direction DR2 may be disposed above the gap G.

[0158] Figure 11 It shows Figure 6 1 is an enlarged plan view of the area of ​​the display device 10 shown in FIG. Figure 12 It is along Figure 11 A cross-sectional view taken along line II′. Figure 11 and Figure 12 Shown in the Figure 6 The relative arrangement relationship between the data lines Dj-2 to Dj+5 in the circuit element layer BPL and the plurality of light-blocking patterns A included in the pinhole array layer PHL.

[0159] refer to Figure 11 and Figure 12 Together Figures 1 to 8The display device 10 may include pixels PXL of the display area AA and a line unit configured to supply driving signals and / or power to the pixels PXL. In an exemplary embodiment, the line unit may include scan lines, data lines, emission control lines, and power lines.

[0160] For the purpose of explanation, Figure 11 and Figure 12 Only data lines Dj-2 to Dj+5 are shown. The data lines Dj-2 to Dj+5 may be disposed in the circuit element layer BPL and extend in the first direction DR1 in the display area AA. In an exemplary embodiment, the data lines Dj-2 to Dj+5 may include a j-2th data line Dj-2 to a j+5th data line Dj+5 sequentially arranged in a second direction DR2 intersecting the first direction DR1. The data lines Dj-2 to Dj+5 may receive data signals. For example, the j-1th data line Dj-1 may receive the j-1th data signal, the jth data line Dj may receive the jth data signal, and the j+1th data line Dj+1 may receive the j+1th data signal.

[0161] The pinhole array layer PHL may be disposed below the circuit element layer BPL. In an exemplary embodiment of the present inventive concept, the pinhole array layer PHL may be formed of a plurality of light blocking patterns A arranged in the second direction DR2. Each light blocking pattern A may have at least one pinhole PIH. Figure 12 As shown in , the pinholes PIH may have the same size and be regularly arranged to form at least one pinhole column. However, the technical spirit of the present inventive concept is not limited thereto, and the pinholes PIH may be irregularly arranged in each light-blocking pattern A and may have the same or different sizes and / or shapes.

[0162] Here, each light-blocking pattern A may overlap at least one of the data lines Dj-1, Dj-2, Dj+1, Dj+2, Dj+4, and Dj+5. Figure 11 It is shown that one light-blocking pattern A overlaps two data lines, but the technical spirit of the present inventive concept is not limited thereto. The number of data lines overlapping each light-blocking pattern A may be reduced or increased.

[0163] In an exemplary embodiment of the present inventive concept, each light-blocking pattern A may not overlap with the data lines Dj-2 to Dj+5. Whether each light-blocking pattern A overlaps with the data lines Dj-2 to Dj+5 may be determined based on an arrangement relationship between the pixel PXL and the light sensor PHS, an arrangement relationship between the pixel PXL and the pinhole PIH, an arrangement relationship between the light sensor PHS and the pinhole PIH, a field of view FOV of the pinhole PIH, and relative sizes between the light sensor PHS and / or the pixel PXL.

[0164] When performing a fingerprint sensing operation, a bias voltage may be selectively applied to at least one of the multiple light-blocking patterns A. In an exemplary embodiment, a bias voltage may be selectively applied to at least one of the multiple light-blocking patterns A positioned at a location where a user's touch is to be sensed. The user's touch location may be sensed, for example, through changes in electromagnetic fields, pressure, brightness or intensity of ambient light, and the like. However, the technical spirit of the present inventive concept is not limited to the aforementioned description. In an exemplary embodiment, a bias voltage may be selectively applied to certain of the multiple light-blocking patterns A based on specific areas preset based on a usage mode or application.

[0165] In an exemplary embodiment, the bias voltage may have a positive value. The photosensor PHS disposed at a position corresponding to at least one light blocking pattern A to which the bias voltage is applied may sense reflected light received through the pinhole PIH of the corresponding light blocking pattern A and output a sensing signal corresponding thereto.

[0166] exist Figure 11 In the exemplary embodiment shown in , the data lines Dj and Dj+3 may be disposed above the gaps G between the light-blocking patterns A. In other words, the light-blocking patterns A may be arranged so that each of the gaps G between the light-blocking patterns A overlaps with any one of the data lines Dj-2 to Dj+5. The data lines Dj and Dj+3 disposed above the gaps G may block reflected light instead of the light-blocking mask LBM of the pinhole array layer PHL. Therefore, the reflected light may be prevented from reaching the sensor layer 120 through the gaps G.

[0167] In this exemplary embodiment, the distance between the light-blocking patterns A (the width of each gap G) may correspond to the width of the corresponding data line Dj or Dj+3. The width of each gap G may be generally equal to or smaller than the width of the corresponding data line Dj or Dj+3 disposed above the gap G. The width of each of the data lines Dj and Dj+3 may be greater than the width of the corresponding gap G.

[0168] Although Figure 11 and Figure 12 An example is shown in which the j-th data line Dj is disposed above the gap G between the light blocking patterns A included in the pinhole array layer PHL, but the technical spirit of the present inventive concept is not limited thereto. In an exemplary embodiment, a line (e.g., a power line) extending in the circuit element layer BPL in the second direction DR2 may be disposed above the gap G.

[0169] Figure 13 is a cross-sectional view of a display apparatus 10 ′ according to an exemplary embodiment of the inventive concept. Figure 14 It shows Figure 13 FIG. 1 is a plan view of an exemplary embodiment of a pinhole array layer PHL.

[0170] and Figure 6 Compared with the display device 10, the display device 10′ includes a contact layer CTL. Figure 6 Therefore, the same reference numerals will now be used to designate the display device 10 of FIG. Figure 6 The components of the display device 10 are the same components, and a detailed explanation thereof will be omitted.

[0171] refer to Figure 13 According to an exemplary embodiment of the present inventive concept, the display device 10 ′ may further include a contact layer CTL. In an exemplary embodiment, the contact layer CTL may be disposed to overlap with the sensing area SA. However, the technical spirit of the present inventive concept is not limited thereto. In other words, the contact layer CTL may be disposed in the entire display area AA of the display panel 110 .

[0172] The contact layer CTL may be disposed below the pinhole array layer PHL and may be made of a conductive material such as Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, or Pb. Alternatively, the contact layer CTL may be formed of an alloy such as MoTi or AlNiLa. In this exemplary embodiment, the contact layer CTL may have a multilayer structure. For example, the contact layer CTL may be made of a conductive material having a multilayer structure such as Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, or TiN / Ti / Cu / Ti.

[0173] However, the materials forming the contact layer CTL are not limited to those described above. In other words, the constituent materials of the contact layer CTL are not limited to metals. Any material can be used as long as it provides sufficient conductivity to smoothly drive the pinhole array layer PHL. For example, the contact layer CTL can be formed of a conductive polymer or a conductive metal oxide. Examples of conductive polymers include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polytolyl compounds, and mixtures thereof. For example, a PEDOT / PSS compound of a polythiophene compound can be used. Examples of conductive metal oxides include ITO, IZO, AZO, ITZO, ZnO, SnO2, and the like.

[0174] The contact layer CTL may be formed at least partially through a contact hole CT (see Figure 15 ) and the like are electrically coupled to the light blocking pattern A of the pin hole array layer PHL. Therefore, a voltage supplied to the contact layer CTL may be applied to the pin hole array layer PHL as a bias voltage.

[0175] In an exemplary embodiment, Figure 14 As shown in , the pinhole array layer PHL may be formed of a plurality of light-blocking patterns A arranged in a first direction DR1 and a second direction DR2. For example, the light-blocking patterns A of the pinhole array layer PHL may be arranged to correspond to at least some of the plurality of pixel rows and at least some of the plurality of pixel columns on the display panel 110, respectively. The contact layer CTL may be configured such that a bias voltage is applied only to some of the light-blocking patterns A that will be substantially involved in fingerprint sensing.

[0176] In the exemplary embodiment described above, a light-blocking metal pattern capable of blocking light transmission may be formed above the gaps G defined between the light-blocking patterns A. The metal pattern may be at least a portion of the contact layer CTL. Alternatively, the metal pattern may be a line, such as a power line configured to supply power (driving power or initialization power) to the pixel PXL.

[0177] Will refer to it later Figure 15 and Figure 16 Exemplary embodiments in which the metal pattern is disposed above the gap G1 and / or below the gap G2 between the light-blocking patterns A of the pinhole array layer PHL are described in more detail.

[0178] Although Figure 14 An example is shown in which each light-blocking pattern A of the pinhole array layer PHL includes only one pinhole PIH, but the technical spirit of the present inventive concept is not limited thereto. For example, each light-blocking pattern A may include a plurality of pinholes.

[0179] A second substrate SUB2 may be further provided between the contact layer CTL and the pinhole array layer PHL. The second substrate SUB2 may be a substantially transparent light-transmitting substrate, for example, a thin film substrate made of polyimide (PI). In an exemplary embodiment, the second substrate SUB2 may be formed of a rigid substrate including glass or tempered glass, or a flexible substrate made of plastic. However, the material of the second substrate SUB2 is not limited thereto, and the second substrate SUB2 may be formed of various materials.

[0180] Figure 15 It shows Figure 13 FIG. 1 is an enlarged plan view of the area of ​​the display device 10 ′ shown in FIG. Figure 16 It is along Figure 15 A cross-sectional view taken along line III-III′. Figure 15 and Figure 16 Shown in the Figure 13A relative arrangement relationship among the scan lines Si-2 to Si+5 in the circuit element layer BPL, the multiple patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5 and CTL_P6 included in the contact layer CTL, and the multiple light-blocking patterns A included in the pinhole array layer PHL.

[0181] refer to Figure 15 and Figure 16 Together Figures 1 to 5 、 Figure 13 and Figure 14 , the display device 10 ′ may include pixels PXL of the display area AA and a line unit configured to supply driving signals and / or power to the pixels PXL. In an exemplary embodiment, the line unit may include scan lines, data lines, emission control lines, and power lines. For the purpose of explanation, Figure 15 and Figure 16 Only scan lines Si-2 to Si+5 are shown.

[0182] The pinhole array layer PHL may be disposed below the circuit element layer BPL. In an exemplary embodiment of the present inventive concept, the pinhole array layer PHL may be formed of a plurality of light-blocking patterns A arranged in the first direction DR1 and the second direction DR2. The light-blocking patterns A may be arranged in an M×N matrix (M and N are natural numbers of 2 or greater).

[0183] Each of the light-blocking patterns A may have at least one pinhole PIH. Figure 15 An example is shown in which each light-blocking pattern A includes one pinhole PIH having the same size and shape. However, the technical spirit of the present inventive concept is not limited thereto, and a plurality of pinholes PIH may be regularly or irregularly arranged in each light-blocking pattern A and may have the same or different sizes and / or shapes.

[0184] Here, each light blocking pattern A may overlap at least one of the scan lines Si-1, Si-2, Si+1, Si+2, Si+4, and Si+5. Figure 14 It is shown that one light-blocking pattern A overlaps two scan lines, but the technical spirit of the present inventive concept is not limited thereto. The number of scan lines overlapping each light-blocking pattern A may be reduced or increased.

[0185] The contact layer CTL is disposed below the pinhole array layer PHL. In an exemplary embodiment of the present inventive concept, the contact layer CTL may be formed of a plurality of patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5, and CTL_P6. The patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5, and CTL_P6 may be respectively coupled to the plurality of light-blocking patterns A included in the pinhole array layer PHL through contact holes CT or the like.

[0186] The contact layer CTL may receive a voltage from an external device and transmit the voltage as a bias voltage to the light-blocking patterns A of the pinhole array layer PHL. If a voltage is applied to any one of the patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5, and CTL_P6 of the contact layer CTL, the bias voltage may be selectively applied to the corresponding light-blocking pattern A among the plurality of light-blocking patterns A included in the pinhole array layer PHL.

[0187] In an exemplary embodiment, the bias voltage may have a positive value. The photosensor PHS disposed at a position corresponding to at least one light blocking pattern A to which the bias voltage is applied may sense reflected light received through the pinhole PIH of the corresponding light blocking pattern A and output a sensing signal corresponding thereto.

[0188] exist Figure 15 In the exemplary embodiment shown in , the pinhole array layer PHL may include first gaps G1 defined between the light-blocking patterns A arranged in the first direction DR1 and second gaps G2 defined between the light-blocking patterns A arranged in the second direction DR2. In this exemplary embodiment, the scan lines Si and Si+3 may be disposed above the first gaps G1. In other words, each of the gaps G may be arranged to overlap any one of the scan lines Si-2 to Si+5.

[0189] In addition, Figure 15 In the exemplary embodiment shown in , the second gap G2 may be arranged to overlap with at least some of the patterns CTL_P1 and CTL_P4 of the contact layer CTL. In this exemplary embodiment, the width of each second gap G2 may correspond to the width of each of the patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5, and CTL_P6 of the contact layer CTL. In other words, the width of each second gap G2 may be equal to or smaller than the width of each of the patterns CTL_P1 and CTL_P4 of the contact layer CTL disposed above the second gap G2.

[0190] Instead of the light blocking mask LBM of the pinhole array layer PHL, the scan lines Si and Si+3 and the patterns CTL_P1 and CTL_P4 of the contact layer CTL disposed above the first and second gaps G1 and G2 can block reflected light. Therefore, reflected light incident on the pinhole array layer PHL can be prevented from passing through the gaps G1 and G2 and reaching the sensor layer 120.

[0191] Although Figure 15 and Figure 16 An example is shown in which the first gap G1 and the second gap G2 of the light-blocking pattern A included in the pinhole array layer PHL overlap with the i-th scan line Si and the patterns CTL_P1 and CTL_P4 of the contact layer CTL, but the technical spirit of the present inventive concept is not limited thereto. In exemplary embodiments, the first gap G1 may overlap with the emission control line or the power line, and / or the second gap G2 may overlap with the data line or the power line.

[0192] Although Figure 15 and Figure 16 Each of the second gaps G2 of the light-blocking pattern A is shown to overlap with any one of the patterns CTL_P1, CTL_P2, CTL_P3, CTL_P4, CTL_P5, and CTL_P6 of the contact layer CTL configured to apply a bias voltage to the light-blocking pattern A, but the technical spirit of the present inventive concept is not limited thereto. For example, in an exemplary embodiment of the present inventive concept, the second gap G2 may overlap with some dummy patterns (e.g., metal patterns) additionally provided in the contact layer CTL.

[0193] Figure 17 is an enlarged plan view illustrating a region of a display device according to an exemplary embodiment of the inventive concept. Figure 18 It is along Figure 17 A cross-sectional view taken along line IV-IV′.

[0194] Different from Figures 9 to 16 In the display device according to the exemplary embodiment, the lines and / or metal patterns Pi and Pi+3 respectively provided from the contact layer CTL are disposed over the gaps G of the plurality of light blocking patterns A included in the pinhole array layer PHL.

[0195] Each of the metal patterns Pi-2 to Pi+5 may have a shape and size corresponding to the shape and size of each of the gaps G of the plurality of light blocking patterns A included in the pinhole array layer PHL. Figure 17The plurality of light-blocking patterns A are shown to have a rectangular shape and the gap G thus has a straight line shape, but in an exemplary embodiment, the plurality of light-blocking patterns A may have various shapes, such as a circular, elliptical, and polygonal shape, and the gap G may have various shapes corresponding to the shapes of the light-blocking patterns A. In this exemplary embodiment, each of the metal patterns Pi-2 to Pi+5 may have a shape and size corresponding to the shape and size of the gap G.

[0196] The metal patterns Pi-2 to Pi+5 may be made of a conductive material, such as Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, or Pb. Alternatively, the metal patterns Pi-2 to Pi+5 may be formed of an alloy such as MoTi or AlNiLa. In this exemplary embodiment, each of the metal patterns Pi-2 to Pi+5 may have a multilayer structure. For example, each of the metal patterns Pi-2 to Pi+5 may be made of a conductive material having a multilayer structure, such as Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, or TiN / Ti / Cu / Ti.

[0197] The constituent materials of the metal patterns Pi-2 to Pi+5 are not limited to the above materials. For example, each of the metal patterns Pi-2 to Pi+5 may be formed of a conductive polymer or a conductive metal oxide. Examples of conductive polymers may include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polytolyl compounds, and mixtures thereof. For example, a PEDOT / PSS compound of a polythiophene compound may be used. Examples of conductive metal oxides may include ITO, IZO, AZO, ITZO, ZnO, SnO2, and the like.

[0198] Although Figure 18 The metal patterns Pi-2 to Pi+5 are shown as being disposed in the circuit element layer BPL, but the technical spirit of the present inventive concept is not limited thereto. In exemplary embodiments of the present inventive concept, the metal patterns Pi-2 to Pi+5 may be disposed in any layer disposed above or below the pinhole array layer PHL or as a separate layer.

[0199] The metal patterns Pi and Pi+3 may block the reflected light instead of the light blocking mask LBM of the pinhole array layer PHL, thereby preventing the reflected light incident on the pinhole array layer PHL from reaching the sensor layer 120 through the gap G.

[0200] As described above, in the fingerprint sensor and the display device including the fingerprint sensor according to exemplary embodiments of the present inventive concept, light emitting elements provided in pixels are used as light sources, and the amount of light sources can be increased so that the accuracy of fingerprint sensing can be improved.

[0201] In addition, in a fingerprint sensor and a display device including a fingerprint sensor according to an exemplary embodiment of the present invention, a pinhole array layer is formed of a plurality of light-blocking patterns, and a fingerprint sensing operation using the pinhole array layer can be performed only on a specific light-blocking pattern, so that the quality of the image on the entire display panel can be prevented from being degraded and the sensing processing time can be reduced.

[0202] While the present inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will readily understand that changes may be made therein in form and details without materially departing from the spirit and scope of the present inventive concept as set forth in the following claims.

Claims

1. Fingerprint sensor, including: a light-transmitting hole array layer, comprising a plurality of light-blocking patterns, wherein the plurality of light-blocking patterns have a plurality of light-transmitting holes to form a light-transmitting path; a sensor layer comprising a plurality of light sensors configured to sense light that passes through the light-transmitting holes and is incident on the sensor layer; a contact layer configured to apply power to the light-blocking patterns, wherein the contact layer is electrically coupled to the light-blocking patterns through one or more contact holes and selectively applies a bias voltage to at least one of the light-blocking patterns; and a metal pattern configured to apply an electrical signal to a pixel or the light-blocking pattern, wherein the metal pattern includes a line formed in the contact layer, The gaps between the light-blocking patterns overlap with at least some of the metal patterns.

2. The fingerprint sensor according to claim 1, further comprising: A circuit element layer is formed in which at least one circuit element forming each of the pixels is formed, wherein the metal pattern includes a line formed in the circuit element layer.

3. The fingerprint sensor according to claim 2, wherein: The metal pattern includes at least one of a scan line configured to supply a scan signal to the pixel, a data line configured to supply a data signal to the pixel, an emission control line configured to supply an emission control signal to the pixel, and a power line configured to apply driving power to the pixel.

4. The fingerprint sensor according to claim 1, in, Each of the pixels includes at least one transistor, and When the bias voltage is selectively applied to the at least one of the light-blocking patterns, a threshold voltage of the at least one transistor changes.

5. The fingerprint sensor according to claim 1, in, Each of the pixels includes a light emitting element, and When the bias voltage is selectively applied to the at least one of the light-blocking patterns, a current passing through the light-emitting element is controlled.

6. The fingerprint sensor according to claim 1, wherein: The bias voltage is a positive voltage.

7. The fingerprint sensor according to claim 1, wherein: The plurality of light-blocking patterns included in the light-transmitting hole array layer extend in a first direction and are arranged in a second direction perpendicular to the first direction.

8. The fingerprint sensor according to claim 1, wherein: The plurality of light-blocking patterns included in the light-transmitting hole array layer are arranged in a first direction and a second direction perpendicular to the first direction.

9. The fingerprint sensor according to claim 8, further comprising: a circuit element layer in which at least one circuit element forming each of the pixels is provided, Wherein, the metal pattern includes: a first metal pattern including lines formed in the circuit element layer; and A second metal pattern includes lines formed in the contact layer.

10. The fingerprint sensor according to claim 9, wherein: A first gap extending in the first direction among the gaps between the light-blocking patterns overlaps the first metal pattern, and a second gap extending in the second direction among the gaps overlaps the second metal pattern.

11. The fingerprint sensor according to claim 1, wherein: The metal pattern blocks light incident on the gaps between the light blocking patterns.

12. Display devices, including: A display panel comprising pixels and a light-transmitting hole array layer, the light-transmitting hole array layer comprising a plurality of light-blocking patterns having a plurality of light-transmitting holes, wherein the display panel further comprises a contact layer configured to apply power to the light-blocking patterns, wherein the contact layer is electrically coupled to the light-blocking patterns through one or more contact holes and selectively applies a bias voltage to at least one of the light-blocking patterns; a sensor layer formed on one surface of the display panel and including a plurality of light sensors configured to sense light incident through the display panel; and a metal pattern configured to apply an electrical signal to the pixel or the light-blocking pattern, wherein the metal pattern includes a line formed in the contact layer, The gaps between the light-blocking patterns overlap with at least some of the metal patterns.

13. The display device according to claim 12, in, The display panel includes a circuit element layer in which at least one circuit element forming each of the pixels is formed, and The metal pattern includes lines formed in the circuit element layer.

14. The display device according to claim 13, wherein The metal pattern includes at least one of a scan line configured to supply a scan signal to the pixel, a data line configured to supply a data signal to the pixel, an emission control line configured to supply an emission control signal to the pixel, and a power line configured to apply driving power to the pixel.

15. The display device according to claim 12, wherein The plurality of light-blocking patterns included in the light-transmitting hole array layer extend in a first direction and are arranged in a second direction perpendicular to the first direction.

16. The display device according to claim 12, wherein The plurality of light-blocking patterns included in the light-transmitting hole array layer are arranged in a first direction and a second direction perpendicular to the first direction.

17. The display device according to claim 16, wherein The display panel includes: a circuit element layer in which at least one circuit element forming each of the pixels is provided; and Wherein, the metal pattern includes: a first metal pattern including lines formed in the circuit element layer; and A second metal pattern includes lines formed in the contact layer.

18. The display device according to claim 17, wherein A first gap extending in the first direction among the gaps between the light-blocking patterns overlaps the first metal pattern, and a second gap extending in the second direction among the gaps overlaps the second metal pattern.

19. The display device according to claim 12, wherein The metal pattern blocks light incident on the gaps between the light blocking patterns.

20. A fingerprint detection method comprising: identifying a location of a finger placed on or near a display area of ​​a display device; selecting a portion of the display area corresponding to the position of the finger; applying a bias voltage to one or more patterns of pixels or a pinhole array layer of the display device corresponding to the selected portion of the display area; increasing the brightness of the selected portion of the display area based on applying the bias voltage; blocking a first portion of light reflected from the finger, wherein the reflected light is based at least in part on the increased brightness, and wherein the first portion of the reflected light is blocked using a light blocking pattern aligned with one or more gaps in the one or more patterns of the pinhole array layer; sensing a second portion of the light reflected from the finger with a sensor layer of the display device, wherein the second portion of the reflected light passes through pinholes in the one or more patterns of the pinhole array layer; as well as A fingerprint is detected based on the second portion of the reflected light.

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