Display Devices

Abstract

A display device includes: a pixel connected to a scan line and a data line crossing the scan line. The pixel includes a light emitting element and a driving transistor, the driving transistor controls a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first active layer, the first active layer includes an oxide semiconductor doped with a metal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0006406, filed on January 17, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device. Background Art

[0004] As the information society develops, the demand for display devices for displaying images in various forms is growing. Therefore, various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and light-emitting displays are being utilized. Light-emitting displays include organic light-emitting displays using organic light-emitting diodes as light-emitting elements and light-emitting diode displays using micro light-emitting diodes as light-emitting elements.

[0005] Such a flat panel display device includes a display panel, a gate driver circuit, a data driver circuit, and a timing controller. The display panel includes a data line, a gate line, and pixels formed at the intersection of the data line and the gate line. Each pixel in the pixel uses a thin film transistor as a switching element and receives a data voltage from the data line when a gate signal is supplied to the gate line. Each pixel in the pixel emits light of a predetermined brightness according to the data voltage.

[0006] Recently, flat panel display devices capable of displaying images with ultra high definition (UHD) have been released, and flat panel display devices capable of displaying images with a high resolution of 8K UHD are being developed. UHD represents a resolution of 3840×2160, and 8K UHD represents a resolution of 7680×4320.

[0007] In the case of a high-resolution flat panel display device, as the number of pixels increases, the driving current of each of the pixels may decrease, thereby reducing the driving voltage range of the driving transistor of each of the pixels.

[0008] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0009] Exemplary embodiments of the present invention provide a display device capable of increasing a driving voltage range of a driving transistor of each pixel.

[0010] Exemplary embodiments of the present invention also provide a method of manufacturing a display device capable of increasing a driving voltage range of a driving transistor of each pixel.

[0011] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0012] An exemplary embodiment of the present invention provides a display device, comprising: a pixel connected to a scan line and a data line crossing the scan line. The pixel includes a light emitting element and a driving transistor, the driving transistor controlling a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first active layer having an oxide semiconductor doped with a metal.

[0013] The proportion of the metal in the first active layer may be about 10 atomic % or less.

[0014] The metal may be copper (Cu), arsenic (As), antimony (Sb), lanthanum (La), a mixture of silver (Ag) and nitrogen (N), a mixture of boron (B) and nitrogen (N), or a mixture of gallium (Ga) and nitrogen (N).

[0015] The metal may be copper (Cu), and the oxide semiconductor may include tin (Sn).

[0016] The first active layer may include indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO).

[0017] Metal may be doped into the upper surface of the first active layer.

[0018] The metal may be doped into at least one side surface of the first active layer.

[0019] The first active layer may include a first conductive region, a second conductive region, and a channel region disposed between the first conductive region and the second conductive region.

[0020] The driving transistor may further include: a first light shielding layer arranged under the first active layer; a first gate electrode arranged on the first active layer; a first source electrode connected to the first conductive region via a first contact hole passing through an interlayer insulating film arranged on the first gate electrode; and a first drain electrode connected to the second conductive region via a second contact hole passing through the interlayer insulating film.

[0021] The first source electrode may contact the first light shielding layer through a third contact hole penetrating the interlayer insulating film and the insulating layer disposed between the first active layer and the first light shielding layer.

[0022] The pixel may further include a scan transistor for applying a data voltage of the data line to a gate electrode of the driving transistor according to a scan signal transmitted to the scan line. The scan transistor may include a second active layer including an oxide semiconductor.

[0023] The second active layer may not be doped with metal.

[0024] The scan transistor may further include: a second light shielding layer disposed under the second active layer, and a second gate electrode disposed on the second active layer.

[0025] The second gate electrode may contact the second light shielding layer through a sixth contact hole passing through the gate insulating layer disposed between the second active layer and the second gate electrode and the insulating layer disposed between the second active layer and the second light shielding layer.

[0026] The display device may further include a scan driver circuit that outputs a scan signal to the scan line. The scan driver circuit may include a pull-up transistor that outputs a gate-on voltage when the pull-up transistor is charged with a gate-on voltage. The pull-up transistor may include a third active layer having polysilicon.

[0027] The third active layer may not be doped with metal.

[0028] The pull-up transistor may further include a third light shielding layer disposed under the third active layer and a third gate electrode disposed on the third active layer.

[0029] The third gate electrode may contact the third light shielding layer through a ninth contact hole passing through the gate insulating layer disposed between the third active layer and the third gate electrode and the insulating layer disposed between the third active layer and the third light shielding layer.

[0030] The display device may further include a data voltage distribution circuit including a first distribution transistor connected between the path selection line and the data line and a second distribution transistor connected between the path selection line and another data line adjacent to the data line. Each of the first distribution transistor and the second distribution transistor may include a fourth active layer including polysilicon.

[0031] Another exemplary embodiment of the present invention provides a method for manufacturing a display device, the method comprising: forming a first light-shielding layer on a first substrate, and forming a buffer layer on the first light-shielding layer; forming an active layer on the entire surface of the buffer layer; patterning a photoresist on the active layer; forming a metal film on the photoresist and the active layer not covered by the photoresist, and then etching the metal film to dope the exposed active layer with a metal; forming a first active layer by removing the photoresist and patterning the active layer; forming a first gate insulating layer on the first active layer, and forming a first gate electrode on the first gate insulating layer; and forming a first interlayer insulating film on the first gate electrode, and forming a first source electrode and a first drain electrode on the first interlayer insulating film.

[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. They illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0034] Figure 1 is a perspective view of a display apparatus according to an exemplary embodiment.

[0035] Figure 2 is a plan view of an example of a display apparatus according to an exemplary embodiment.

[0036] Figure 3 yes Figure 2 A circuit diagram of an example of a pixel is shown in FIG.

[0037] Figure 4 yes Figure 2 A circuit diagram of an example of a scan driver circuit is shown in FIG.

[0038] Figure 5 yes Figure 2 A circuit diagram of an example of a data voltage distribution circuit is shown in FIG.

[0039] Figure 6 yes Figure 3 0 is a plan view of an example of a driving transistor of a pixel shown in FIG.

[0040] Figure 7 is along Figure 6 An example cross-sectional view taken along line I-I'.

[0041] Figure 8 yes Figure 3 0047 is a plan view of an example of a switching transistor of a pixel shown in FIG.

[0042] Fig. 9 is along Figure 8 An example cross-sectional view taken along line II-II'.

[0043] Fig.10 is a graph illustrating a driving current according to a gate voltage of a driving transistor when the driving transistor includes an active layer doped with a metal and when the driving transistor does not include an active layer doped with a metal.

[0044] Fig.11 yes Figure 3 0047 is a plan view of an example of a switching transistor of a pixel shown in FIG.

[0045] Fig.12 is along Fig.11 An example cross-sectional view taken along line III-III'.

[0046] Fig.13 yes Figure 4 0 is a plan view of an example of a pull-up transistor of a scan driver circuit shown in FIG.

[0047] Fig.14 is along Fig.13 Example cross-sectional view taken along line IV-IV'.

[0048] Fig.15 yes Figure 4 0 is a plan view of an example of a pull-up transistor of a scan driver circuit shown in FIG.

[0049] Fig.16 is along Fig.15 Example cross-sectional view taken along line V-V'.

[0050] Fig.17 is a flowchart illustrating a method of manufacturing a display apparatus according to an exemplary embodiment.

[0051] Fig.18A , Fig.18B , Fig.18C , Fig.18D , Fig.18E , Fig.18F and Figure 18G is a cross-sectional view for explaining a method of manufacturing a display apparatus according to an exemplary embodiment.

[0052] Fig.19 is a flowchart illustrating a method of manufacturing a display apparatus according to an exemplary embodiment.

[0053] Fig. 20A , Fig. 20B and Fig. 20C is a cross-sectional view for explaining a method of manufacturing a display apparatus according to an exemplary embodiment.

[0054] Fig.21is a flowchart illustrating a method of manufacturing a display apparatus according to an exemplary embodiment.

[0055] Fig.22A , Fig. 22B and Fig. 22C is a cross-sectional view for explaining a method of manufacturing a display apparatus according to an exemplary embodiment. DETAILED DESCRIPTION

[0056] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words for non-limiting examples of one or more devices or methods using the inventive concept disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment.

[0057] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter referred to as "elements" respectively or collectively) of the various embodiments can be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0058] The use of cross hatching and / or shadows in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shadows does not convey or indicate any preference or demand for a specific material, material properties, size, ratio, commonality between the illustrated elements and / or any other features, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiment can be implemented in different ways, the specific process can be performed differently from the described order. For example, the processes of two consecutive descriptions can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals refer to the same elements.

[0059] When an element such as a layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element may be directly located on, directly connected to or coupled to, another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as, the x-axis, the y-axis and the z-axis), but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0061] For descriptive purposes, spatially relative terms such as "below," "under," "below," "down," "above," "on," "above," "above," "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figure is flipped, an element described as "under" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "under" can cover both above and below orientations. In addition, the device can be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0062] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "the (described)" as used herein are also intended to include plural forms. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than as terms of degree, and are therefore used to include the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0063] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Therefore, changes in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the exemplary embodiments disclosed herein should not be interpreted as being limited to the shapes of the specifically illustrated areas, but include deviations in shape due to, for example, manufacturing. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and therefore need not be intended to be limiting.

[0064] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0065] Figure 1 is a perspective view of a display apparatus 10 according to an exemplary embodiment. Figure 2 is a plan view of an example of the display device 10 according to this exemplary embodiment.

[0066] In this specification, the terms "above", "top" and "upper surface" indicate a direction upward from the display panel 100, that is, the Z-axis direction, and the terms "below", "bottom" and "lower surface" indicate a direction downward from the display panel 100, that is, a direction opposite to the Z-axis direction. In addition, "left", "right", "upper" and "lower surface" indicate directions when the display panel 100 is viewed in a plane. For example, "left" indicates a direction opposite to the X-axis direction, "right" indicates the X-axis direction, "upper" indicates the Y-axis direction, and "lower" indicates a direction opposite to the Y-axis direction.

[0067] refer to Figure 1 and Figure 2 , the display device 10 is a device for displaying a moving image or a still image. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as display screens in various products such as televisions, notebook computers, monitors, billboards, and the Internet of Things. The display device 10 can be any one of an organic light-emitting display, a liquid crystal display, a plasma display, a field emission display, an electrophoretic display, an electrowetting display, a quantum dot light-emitting display, and a micro-light-emitting diode (LED) display. An organic light-emitting display will be described below as an example of the display device 10, but the inventive concept is not limited to an organic light-emitting display.

[0068] The display apparatus 10 according to an exemplary embodiment includes a display panel 100 , a display driver circuit 200 , and a circuit board 300 .

[0069] The display panel 100 may be formed as a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). Each corner where the short side extending in the first direction (X-axis direction) intersects the long side extending in the second direction (Y-axis direction) may be a rounded corner with a predetermined curvature, or may be a right angle. The planar shape of the display panel 100 is not limited to a rectangular shape, but may also be other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat. However, the display panel 100 is not limited to this example, and may also include a curved portion formed at the left and right ends of the display panel 100 and having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed to be flexible so that it can be bent, folded, folded, or curled.

[0070] The display panel 100 may include a display area DA in which a plurality of pixels P are formed to display an image, and a non-display area NDA arranged around the display area DA. When the display panel 100 includes a curved portion, the display area DA may be arranged in the curved portion. In this case, an image may also be displayed on the curved portion of the display panel 100.

[0071] In the display area DA, not only pixels P but also scan lines SL, data lines DL, and power lines connected to the pixels P may be arranged. The scan lines SL may be formed to be parallel to each other in a first direction (X-axis direction), and the data lines DL may be formed to be parallel to each other in a second direction (Y-axis direction) crossing the first direction (X-axis direction). Each of the pixels P may be connected to at least any one of the scan lines SL and any one of the data lines DL.

[0072] Each of the pixels P may include a driving transistor DT, at least one switching transistor ST, a light emitting element EL, and a capacitor Cst (see Figure 3 ). Since the switching transistor ST is turned on by the scan signal received from the scan line SL, the data voltage of the data line DL may be applied to the gate electrode of the driving transistor DT. The driving transistor DT may supply a driving current to the light emitting element EL according to the data voltage applied to the gate electrode. The light emitting element EL may emit light according to the driving current. The driving transistor DT and at least one switching transistor ST may be thin film transistors. The light emitting element EL may emit light according to the driving current of the driving transistor DT. The light emitting element EL may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The capacitor Cst may maintain the data voltage applied to the gate electrode of the driving transistor DT constant.

[0073] The non-display area NDA may be defined as an area extending from the outside of the display area DA to the edge of the display panel 100. In the non-display area NDA, a scan driver circuit SDC for transmitting a scan signal to the scan line SL and a data voltage distribution circuit DMUX connected between the data line DL and the path selection line RL may be arranged. In addition, a pad DP electrically connected to the display driver circuit 200 and the circuit board 300 may be arranged in the non-display area NDA. In this case, the display driver circuit 200 and the pad DP may be arranged on the edge of the display panel 100.

[0074] The scan driver circuit SDC may be connected to the display driver circuit 200 through at least one scan control line SCL. The scan driver circuit SDC may receive a scan control signal from the display driver circuit 200 through at least one scan control line SCL. The scan driver circuit SDC may generate a scan signal according to the scan control signal and sequentially output the scan signal to the scan lines SL. Figure 2 In the embodiment, the scan driver circuit SDC is formed in the non-display area NDA on one side (e.g., the left side) of the display area DA, but the inventive concept is not limited to this case. For example, the scan driver circuit SDC may also be formed in the non-display area NDA on both sides (e.g., the left and right sides) of the display area DA.

[0075] The data voltage distribution circuit DMUX may be connected between the path selection line RL and the data line DL. The ratio of the number of the path selection lines RL connected to the data voltage distribution circuit DMUX to the number of the data lines DL connected to the data voltage distribution circuit DMUX may be 1:q, where q is an integer equal to or greater than 2. The data voltage distribution circuit DMUX may distribute a data voltage applied to one path selection line RL to a plurality of data lines DL.

[0076] The display driver circuit 200 is connected to the pad DP and receives digital video data and a timing signal. The display driver circuit 200 converts the digital video data into an analog positive / negative polarity data voltage, and supplies the analog positive / negative polarity data voltage to the data line DL through the path selection line RL and the data voltage distribution circuit DMUX. In addition, the display driver circuit 200 generates a scan control signal for controlling the scan driver circuit SDC, and supplies the scan control signal to the scan driver circuit SDC through the scan control line SCL. The pixel P to be supplied with the data voltage is selected by the scan signal of the scan driver circuit SDC, and the data voltage is supplied to the selected pixel P. In addition, the display driver circuit 200 can supply the power supply voltage to the power supply line.

[0077] The display driver circuit 200 may be formed as an integrated circuit (IC) and may be mounted on a pad region of the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method. However, the inventive concept is not limited to this case, and the display driver circuit 200 may also be mounted on the circuit board 300.

[0078] The pad DP may be electrically connected to the display driver circuit 200. The circuit board 300 may be attached to the pad DP using an anisotropic conductive film. Thus, the leads of the circuit board 300 may be electrically connected to the pad DP. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0079] Figure 3 yes Figure 2 A circuit diagram of an example of a pixel P is shown in FIG.

[0080] refer to Figure 3 , the pixel P may include a driving transistor DT, at least one switching transistor ST, a light emitting element EL and a capacitor Cst.

[0081] The switching transistor ST is turned on by a scan signal received from a k-th scan line SLk (where k is a positive integer). Therefore, a data voltage of a j-th data line DLj (where j is a positive integer) may be applied to a gate electrode of the driving transistor DT. The switching transistor ST may have a gate electrode connected to the k-th scan line SLk, a source electrode connected to the gate electrode of the driving transistor DT, and a drain electrode connected to the j-th data line DLj.

[0082] The driving transistor DT may supply a driving current to the light emitting element EL according to a data voltage applied to a gate electrode. The light emitting element EL may emit light according to the driving current. The driving transistor DT may have a gate electrode connected to a source electrode of the switching transistor ST, a source electrode connected to a first electrode of the light emitting element EL, and a drain electrode connected to a first power line VDDL to which a first power voltage is applied.

[0083] The driving transistor DT and at least one switching transistor ST may be thin film transistors. Figure 3 In the embodiment, the driving transistor DT and the at least one switching transistor ST are formed as N-type semiconductor transistors having N-type semiconductor characteristics, but the present invention is not limited to this case. That is, the driving transistor DT and the at least one switching transistor ST may also be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0084] The light emitting element EL may emit light according to the driving current of the driving transistor DT. The light emitting element EL may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The first electrode of the light emitting element EL may be connected to the source electrode of the driving transistor DT, and the second electrode may be connected to a second power line VSSL to which a second power voltage lower than the first power voltage is applied.

[0085] The capacitor Cst may be connected between the gate electrode and the drain electrode of the driving transistor DT. Therefore, the capacitor Cst may maintain the data voltage applied to the gate electrode of the driving transistor DT constant.

[0086] Figure 4 yes Figure 2 A circuit diagram of an example of a scan driver circuit SDC is shown in FIG.

[0087] The scan driver circuit SDC may include stages connected in a dependent manner. Each stage may sequentially output a scan signal to the scan line SL. Figure 4 The level STA is shown in .

[0088] like Figure 4As shown in , each of the levels STA includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU, a pull-down transistor TD and a node controller NC, the pull-up transistor TU is turned on when the pull-up node NQ has a gate-on voltage, the pull-down transistor TD is turned on when the pull-down node NQB has a gate-on voltage, and the node controller NC is used to control the charging and discharging of the pull-up node NQ and the pull-down node NQB.

[0089] The node controller NC may be connected to a start terminal ST to which a start signal or an output signal of a previous stage is input, a reset terminal RT to which an output signal of a next stage is input, a gate-on voltage terminal VGHT to which a gate-on voltage is applied, and a gate-off voltage terminal VGLT to which a gate-off voltage is applied. The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB according to the start signal input to the start terminal ST or the output signal of the previous stage. In order to stably control the output of the stage STA, the node controller NC controls the pull-down node NQB to have a gate-off voltage when the pull-up node NQ has a gate-on voltage, and controls the pull-up node NQ to have a gate-off voltage when the pull-down node NQB has a gate-on voltage. To this end, the node controller NC may include a plurality of transistors.

[0090] When the stage STA is pulled up (i.e., when the pull-up node NQ has a gate-on voltage), the pull-up transistor TU is turned on and outputs the clock signal input to the clock terminal CT to the output terminal OT. When the stage STA is pulled down (e.g., when the pull-down node NQB has a gate-on voltage), the pull-down transistor TD is turned on and outputs the gate-off voltage of the gate-off voltage terminal VGLT to the output terminal OT.

[0091] The pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC may be formed as a thin film transistor. Figure 4 In the embodiment, the pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC are formed as N-type semiconductor transistors having N-type semiconductor characteristics, but the inventive concept is not limited to this case. That is, the pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC may also be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0092] Figure 5 yes Figure 2 A circuit diagram of an example of a data voltage distribution circuit DMUX is shown in FIG.

[0093] refer to Figure 5, the data voltage distribution circuit DMUX can time-divide the data voltage supplied to the path selection lines RL1 to RLp (where p is an integer equal to or greater than 2) and distribute the data voltage to a plurality of data lines DL1 to DLm (where m is an integer satisfying m=2p) by using distribution transistors MT1 and MT2, wherein the distribution transistors MT1 and MT2 are sequentially turned on by distribution control signals transmitted to the distribution control lines DM1 and DM2. Figure 5 In the embodiment, the data voltage distribution circuit DMUX time-divides the data voltage supplied to one path selection line and distributes the data voltage to two data lines. However, the embodiment is not limited to this case.

[0094] The data voltage distribution circuit DMUX may include a first distribution transistor MT1 and a second distribution transistor MT2. Respective gate electrodes of the first distribution transistor MT1 may be connected to a first distribution control line DM1, and respective gate electrodes of the second distribution transistor MT2 may be connected to a second distribution control line DM2.

[0095] The first distribution transistor MT1 and the second distribution transistor MT2 connected to one path selection line may be connected to different data lines. For example, the first distribution transistor MT1 connected to the first path selection line RL1 may be connected to the first data line DL1, and the second distribution transistor MT2 connected to the first path selection line RL1 may be connected to the second data line DL2. The first distribution transistor MT1 connected to the p-th path selection line RLp may be connected to the m-1-th data line DLm-1, and the second distribution transistor MT2 connected to the p-th path selection line RLp may be connected to the m-th data line DLm.

[0096] When the first distribution control signal of the gate-on voltage is transmitted to the first distribution control line DM1, the first distribution transistor MT1 can be turned on. Therefore, the path selection lines RL1 to RLp can be connected to the odd data lines DL1, DL3, DL5, ..., DLm-1. When the second distribution control signal of the gate-on voltage is transmitted to the second distribution control line DM2, the second distribution transistor MT2 can be turned on. Therefore, the path selection lines RL1 to RLp can be connected to the even data lines DL2, DL4, DL6, ..., DLm. Therefore, the data voltage distribution circuit DMUX can time-divide the data voltage supplied to the path selection lines RL1 to RLp (where p is an integer equal to or greater than 2), and distribute the data voltage to the data lines DL1 to DLm (where m is an integer satisfying m=2p).

[0097] The first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be formed as thin film transistors. Figure 5In the embodiment, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are formed as N-type semiconductor transistors having N-type semiconductor characteristics, but the present invention is not limited to this case. That is, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX can also be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0098] Figure 6 yes Figure 3 0 is a plan view of an example of a driving transistor DT of a pixel P shown in FIG. Figure 7 is along Figure 6 An example cross-sectional view taken along line I-I'. Figure 8 yes Figure 3 0 is a plan view of an example of a switching transistor ST of a pixel P shown in FIG. Fig. 9 is along Figure 8 An example cross-sectional view taken along line II-II'. Fig.10 is a graph illustrating a driving current according to a gate voltage of the driving transistor DT when the driving transistor DT includes an active layer doped with a metal and when the driving transistor DT does not include an active layer doped with a metal.

[0099] exist Figures 6 to 9 In the embodiment of the present invention, the driving transistor DT and the switching transistor ST of the pixel P are formed in a coplanar structure. The coplanar structure has a top gate structure in which a gate electrode is formed on an active layer.

[0100] refer to Figures 6 to 9 The driving transistor DT of the pixel P includes a first gate electrode 111, a first active layer 131, a first source electrode 141, a first drain electrode 151 and a first light shielding layer 161. The switching transistor ST of the pixel P includes a second gate electrode 112, a second active layer 132, a second source electrode 142 and a second drain electrode 152.

[0101] The driving transistor DT and the switching transistor ST are formed on the first substrate 101. The first substrate 101 may be made of plastic or glass.

[0102] The first light shielding layer 161 may be formed on the first substrate 101. The first light shielding layer 161 is a layer for blocking light from the first substrate 101 from entering the first active layer 131. The first light shielding layer 161 is designed to prevent leakage current of the first active layer 131 when light from the first substrate 101 is incident on the first active layer 131. The length of the first light shielding layer 161 in the fourth direction DR4 and the fifth direction DR5 may be greater than the length of the first active layer 131 in the fourth direction DR4 and the fifth direction DR5. The first light shielding layer 161 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. Meanwhile, the sixth direction DR6 may be the thickness direction of the substrate 101.

[0103] The buffer layer 102 may be formed on the first light shielding layer 161. The buffer layer 102 is a layer for protecting the driving transistor DT and the switching transistor ST of the pixel P from moisture introduced through the first substrate 101. The buffer layer 102 may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer 102 may be a layer in which silicon oxide (SiO x ) layer, silicon nitride (SiN x A multilayer in which one or more inorganic layers selected from ) layers and SiON layers are alternately stacked.

[0104] The first active layer 131 and the second active layer 132 may be formed on the buffer layer 102. The first active layer 131 and the second active layer 132 may include first conductive regions 131a and 132a, second conductive regions 131b and 132b, and channel regions 131c and 132c, respectively. The channel regions 131c and 132c may be disposed between the first conductive regions 131a and 132a and the second conductive regions 131b and 132b.

[0105] The first active layer 131 and the second active layer 132 may be oxide semiconductors. The first active layer 131 may be an oxide semiconductor doped with a metal, and the second active layer 132 may be an oxide semiconductor not doped with a metal. The metal doped into the first active layer 131 may be a mixture of copper (Cu), arsenic (As), antimony (Sb), lanthanum (La), silver (Ag) and nitrogen (N), a mixture of boron (B) and nitrogen (N), or a mixture of gallium (Ga) and nitrogen (N).

[0106] According to the manufacturing process, the metal doped into the first active layer 131 may be formed only on the upper surface of the first active layer 131, or may be formed on the upper surface and the side surface of the first active layer 131. In addition, in order to prevent the first conductive region 131a and the second conductive region 131b from being short-circuited due to the metal, the proportion of the metal doped into the first active layer 131 in the first active layer 131 may be about 10 atomic % or less.

[0107] In order to prevent the first active layer 131 from being damaged in the metal doping process, the first active layer 131 and the second active layer 132 may be oxide semiconductors containing tin (Sn). In this case, the first active layer 131 and the second active layer 132 may be made of indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO). For example, if the first active layer 131 is an oxide semiconductor containing tin (Sn) and the metal to be doped into the first active layer 131 is copper (Cu), a copper metal film may be formed on the first active layer 131, and then copper (Cu) may be doped into the first active layer 131 using an etchant that reacts with copper (Cu) but not with the first active layer 131. In this case, the etchant that reacts with copper (Cu) but not with the first active layer 131 may be a non-hydrogen peroxide solution including citric acid or ammonium persulfate.

[0108] The metal doped into the first active layer 131 may capture electrons moving through the channel region 131c of the first active layer 131. In this case, due to the metal doped into the first active layer 131, the slope of the driving current (drain-source current Ids) curve according to the gate voltage Vg of the driving transistor DT may be reduced, as shown in FIG. Fig.10 As shown in Fig.10 In FIG. 1 , the Ids1 curve represents a driving current curve when the first active layer 131 is not doped with metal, and the Ids2 curve represents a driving current curve when the first active layer 131 is doped with metal. Fig.10 As shown in FIG. 1 , when the first active layer 131 is doped with metal, within the range IR of the driving current, the range VR2 of the gate voltage Vg of the driving transistor DT may be wider than the range VR1 of the gate voltage Vg of the driving transistor DT when the first active layer 131 is not doped with metal. Therefore, even in a high-resolution flat panel display device, the driving current of each pixel decreases as the number of pixels increases, and the reduction in the driving voltage range of the driving transistor DT can be prevented or reduced.

[0109] The first gate insulating layer 120 is formed on the first active layer 131 and the second active layer 132. The first gate insulating layer 120 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiNx ) layer or multiple layers composed of these layers.

[0110] The first gate electrode 111 and the second gate electrode 112 are formed on the first gate insulating layer 120. The first gate electrode 111 may overlap the first active layer 131 with the first gate insulating layer 120 interposed therebetween, and the second gate electrode 112 may overlap the second active layer 132 with the first gate insulating layer 120 interposed therebetween. Specifically, the first gate electrode 111 may overlap the channel region 131c of the first active layer 131, and the second gate electrode 112 may overlap the channel region 132c of the second active layer 132. Each of the first gate electrode 111 and the second gate electrode 112 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0111] Despite Figure 7 and Fig. 9 In the embodiment, the first gate insulating layer 120 is disposed only between the first gate electrode 111 and the first active layer 131 and between the second gate electrode 112 and the second active layer 132, but the inventive concept is not limited to this case. That is, the first gate insulating layer 120 may be formed on the upper surface and the side surface of the first active layer 131 and the second active layer 132.

[0112] The first interlayer insulating film 160 is formed on the first gate electrode 111 and the second gate electrode 112. The first interlayer insulating film 160 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or multiple layers composed of these layers.

[0113] A first contact hole CT1 passing through the first interlayer insulating film 160 to expose a portion of the upper surface of the first active layer 131 and a second contact hole CT2 passing through the first interlayer insulating film 160 to expose another portion of the upper surface of the first active layer 131 may be formed in the first interlayer insulating film 160. That is, the first contact hole CT1 may expose the first conductive region 131a of the first active layer 131, and the second contact hole CT2 may expose the second conductive region 131b of the first active layer 131. In addition, a third contact hole CT3 passing through the first interlayer insulating film 160 and the buffer layer 102 to expose the first light shielding layer 161 may be formed in the first interlayer insulating film 160 and the buffer layer 102.

[0114] In addition, a fourth contact hole CT4 passing through the first interlayer insulating film 160 to expose a portion of the upper surface of the second active layer 132 and a fifth contact hole CT5 passing through the first interlayer insulating film 160 to expose another portion of the upper surface of the second active layer 132 may be formed in the first interlayer insulating film 160. That is, the fourth contact hole CT4 may expose the first conductive region 132a of the second active layer 132, and the fifth contact hole CT5 may expose the second conductive region 132b of the second active layer 132.

[0115] The first source electrode 141 and the first drain electrode 151 of the driving transistor DT and the second source electrode 142 and the second drain electrode 152 of the switching transistor ST are formed on the first interlayer insulating film 160 .

[0116] The first source electrode 141 contacts the first conductive region 131a formed at one side of the first active layer 131 through the first contact hole CT1. The first drain electrode 151 contacts the second conductive region 131b formed at the other side of the first active layer 131 through the second contact hole CT2.

[0117] In addition, the first source electrode 141 may contact the first light shielding layer 161 through the third contact hole CT3. In this case, the first light shielding layer 161 disposed below the first active layer 131 has the same voltage as the first source electrode 141. When the first light shielding layer 161 has the same potential as the first source electrode 141, the first active layer 131 adjacent to the first light shielding layer 161 may not be activated compared to the first active layer 131 adjacent to the first gate electrode 111. That is, since the electron mobility in the channel region 131c of the first active layer 131 can be reduced, the slope of the driving current (drain-source current Ids) curve according to the gate voltage Vg of the driving transistor DT can be reduced, as shown in FIG. Fig.10 Therefore, Fig.10 As shown in FIG. 1 , when the first active layer 131 is doped with metal, within the range IR of the driving current, the range VR2 of the gate voltage Vg of the driving transistor DT may be wider than the range VR1 of the gate voltage Vg of the driving transistor DT when the first active layer 131 is not doped with metal. Therefore, even in a high-resolution flat panel display device, the driving current of each pixel decreases as the number of pixels increases, and the reduction in the driving voltage range of the driving transistor DT can be prevented or reduced.

[0118] The second source electrode 142 contacts the first conductive region 132a formed at one side of the second active layer 132 through the fourth contact hole CT4. The second drain electrode 152 contacts the second conductive region 132b formed at the other side of the second active layer 132 through the fifth contact hole CT5.

[0119] The first protective layer 170 is formed on the first source electrode 141, the second source electrode 142, the first drain electrode 151 and the second drain electrode 152. The first protective layer 170 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or multiple layers composed of these layers.

[0120] The first planarization layer 180 may be formed on the first protection layer 170 to flatten steps caused by thin film transistors such as the driving transistor DT and the switching transistor ST. The first planarization layer 180 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0121] The light emitting element EL including the first electrode 191, the organic light emitting layer 192 and the second electrode 193 and the pixel defining layer 195 may be formed on the first planarization layer 180, as shown in FIG. Figure 7 as shown in .

[0122] The first electrode 191 may be formed on the first planarization layer 180. The first electrode 191 may be connected to the first source electrode 141 of the driving transistor DT through a contact hole CNT passing through the first protection layer 170 and the first planarization layer 180.

[0123] The pixel defining layer 195 may be formed on the first planarization layer 180 and may cover the edge of the first electrode 191 to define the pixel. That is, the pixel defining layer 195 serves as a pixel defining layer for defining the pixel. Here, each pixel in the pixel is a region where the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are sequentially stacked so that holes from the first electrode 191 and electrons from the second electrode 193 are combined in the organic light emitting layer 192 to emit light.

[0124] The organic light emitting layer 192 may be disposed on the first electrode 191 and the pixel defining layer 195. The organic light emitting layer 192 may include a hole transport layer, a light emitting layer, and an electron transport layer. In addition, the organic light emitting layer 192 may be formed in a series structure of two or more stacks, in which case a charge generation layer may be formed between the stacks.

[0125] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer shared by all pixels.

[0126] The light emitting element EL may be a top emission type that emits light in a direction opposite to the first substrate 101 (i.e., in an upward direction). In this case, the first electrode 191 may be made of a metal material with high reflectivity, such as a stack of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stack of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, or a stack of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu). In addition, the second electrode 193 may be made of a transparent conductive material (TCO) (such as ITO or indium zinc oxide (IZO)) that can transmit light, or may be made of a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 193 is made of a semi-transmissive conductive material, the luminous efficiency may be improved by a microcavity.

[0127] The encapsulation layer 196 may be formed on the second electrode 193 to prevent the introduction of oxygen or moisture. The encapsulation layer 196 may include at least one inorganic layer. The inorganic layer may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In addition, the encapsulation layer 196 may include at least one organic layer to prevent particles from penetrating the encapsulation layer 196 and entering the organic light-emitting layer 192 and the second electrode 193. The organic layer may be made of epoxy resin, acrylate, or polyurethane acrylate.

[0128] The pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may each include a third gate electrode, a third active layer, a third source electrode, and a third drain electrode. Each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may be connected to Figure 8 and Fig. 9 The switching transistor ST shown in FIG. 1 is formed substantially the same. In this case, the third gate electrode, the third active layer, the third source electrode and the third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC and the transistor of the node controller NC are the same as those in the above reference. Figure 8 and Fig. 9 The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the described switching transistor ST are substantially the same, and thus a detailed description thereof is omitted.

[0129] In addition, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may each include a fourth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. Each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be connected to Figure 8 and Fig. 9 The switching transistor ST shown in FIG. 1 is formed substantially the same. In this case, the fourth gate electrode, the fourth active layer, the fourth source electrode and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are the same as those of the above reference. Figure 8 and Fig. 9 The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the described switching transistor ST are substantially the same, and thus a detailed description thereof is omitted.

[0130] Fig.11 yes Figure 3 0 is a plan view of an example of a switching transistor ST of a pixel P shown in FIG. Fig.12 is along Fig.11 An example cross-sectional view taken along line III-III'.

[0131] Fig.11 and Fig.12 An exemplary embodiment of Figure 8 and Fig. 9 The exemplary embodiment of FIG. 1 is different in that the second gate electrode 112 of the switch transistor ST is connected to the second light shielding layer 162. Fig.11 and Fig.12 In the Figure 8 and Fig. 9 The redundant description of the elements and features of the embodiments of the present invention is omitted, and the description will mainly focus on the elements and features of the embodiments of the present invention. Figure 8 and Fig. 9 The differences between the exemplary embodiments are shown in FIG.

[0132] refer to Fig.11 and Fig.12 In addition to the second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 , the switching transistor ST may further include a second light shielding layer 162 .

[0133] In order to block external light from entering the second active layer 132 through the first substrate 101, a second light shielding layer 162 may be formed on the first substrate 101. The length of the second light shielding layer 162 in the fourth direction DR4 and the fifth direction DR5 may be greater than the length of the second active layer 132 in the fourth direction DR4 and the fifth direction DR5. The second light shielding layer 162 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The buffer layer 102 may be formed on the second light shielding layer 162.

[0134] The second gate electrode 112 may contact the second light shielding layer 162 through the sixth contact hole CT6. The sixth contact hole CT6 may pass through the first gate insulating layer 120 and the buffer layer 102 to expose the second light shielding layer 162. In this case, the second light shielding layer 162 disposed below the second active layer 132 has the same voltage as the second gate electrode 112. That is, the second gate electrode 112 may be used as a top gate electrode, and the second light shielding layer 162 may be used as a bottom gate electrode. Therefore, since the switching transistor ST may be driven in a dual-gate manner, it is possible to prevent or reduce leakage current from flowing through the channel region 132c of the second active layer 132 when the switching transistor ST is turned off.

[0135] Each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may be connected to Fig.11 and Fig.12 The switching transistor ST shown in FIG. 1 is formed substantially the same. In this case, the third gate electrode, the third active layer, the third source electrode and the third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC and the transistor of the node controller NC are the same as those in the above reference. Fig.11 and Fig.12 The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the described switching transistor ST are substantially the same, and thus a detailed description thereof is omitted.

[0136] In addition, each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX can be connected to Fig.11 and Fig.12 The switching transistor ST shown in FIG. 1 is formed substantially the same. In this case, the fourth gate electrode, the fourth active layer, the fourth source electrode and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are the same as those of the above reference. Fig.11 and Fig.12The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the described switching transistor ST are substantially the same, and thus a detailed description thereof is omitted.

[0137] Fig.13 yes Figure 4 0 is a plan view of an example of a pull-up transistor TU of a scan driver circuit SDC shown in FIG. Fig.14 is along Fig.13 Example cross-sectional view taken along line IV-IV'.

[0138] Fig.13 and Fig.14 An exemplary embodiment of Figures 6 to 9 The exemplary embodiment of is different in that the third active layer 233 of the pull-up transistor TU of the scan driver circuit SDC includes polysilicon, and therefore, the driving transistor DT and the switching transistor ST of the pixel P are formed on a higher layer than the pull-up transistor TU of the scan driver circuit SDC. Fig.13 and Fig.14 In the Figures 6 to 9 The redundant description of the elements and features of the embodiments of the present invention is omitted, and the description will mainly focus on the elements and features of the embodiments of the present invention. Figures 6 to 9 The differences between the embodiments.

[0139] refer to Fig.13 and Fig.14 , the pull-up transistor TU of the scan driver circuit SDC includes a third gate electrode 213 , a third active layer 233 , a third source electrode 243 and a third drain electrode 253 .

[0140] The third active layer 233 including polysilicon may be formed on the buffer layer 102. The third active layer 233 may include a first heavily doped region 233a, a second heavily doped region 233b, a channel region 233c, a first lightly doped region 233d, and a second lightly doped region 233e. The channel region 233c may be made of polysilicon not doped with impurities, the first heavily doped region 233a and the second heavily doped region 233b may be made of polysilicon heavily doped with impurities, and the first lightly doped region 233d and the second lightly doped region 233e may be made of polysilicon lightly doped with impurities.

[0141] The second gate insulating layer 220 is formed on the third active layer 233. The second gate insulating layer 220 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or multiple layers composed of these layers.

[0142] The third gate electrode 213 is formed on the second gate insulating layer 220. The third gate electrode 213 may overlap the third active layer 233, wherein the second gate insulating layer 220 is interposed between the third gate electrode 213 and the third active layer 233. Specifically, the third gate electrode 213 may overlap the channel region 233c of the third active layer 233. The third gate electrode 213 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials.

[0143] Despite Fig.14 In the embodiment, the second gate insulating layer 220 is disposed between the third gate electrode 213 and the third active layer 233 , but the embodiment is not limited to this case. That is, the second gate insulating layer 220 may also be formed on the upper surface and the side surface of the third active layer 233 .

[0144] The second interlayer insulating film 260 is formed on the third gate electrode 213. The second interlayer insulating film 260 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or multiple layers composed of these layers.

[0145] A seventh contact hole CT7 passing through the second interlayer insulating film 260 to expose a portion of the upper surface of the third active layer 233 and an eighth contact hole CT8 passing through the second interlayer insulating film 260 to expose another portion of the upper surface of the third active layer 233 may be formed in the second interlayer insulating film 260. That is, the seventh contact hole CT7 may expose the first heavily doped region 233a of the third active layer 233, and the eighth contact hole CT8 may expose the second heavily doped region 233b of the third active layer 233.

[0146] The third source electrode 243 and the third drain electrode 253 of the pull-up transistor TU are formed on the second interlayer insulating film 260. The third source electrode 243 contacts the first heavily doped region 233a formed on one side of the third active layer 233 through the seventh contact hole CT7. The third drain electrode 253 contacts the second heavily doped region 233b formed on the other side of the third active layer 233 through the eighth contact hole CT8.

[0147] The second protective layer 270 is formed on the third source electrode 243 and the third drain electrode 253. The second protective layer 270 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or multiple layers composed of these layers.

[0148] The second planarization layer 280 may be formed on the second protection layer 270 to flatten a step due to a thin film transistor such as the pull-up transistor TU. The second planarization layer 280 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0149] Each of the pull-down transistor TD of the scan driver circuit SDC and the transistor of the node controller NC may be connected to Fig.13 and Fig.14 The pull-up transistors TU shown in are formed substantially identically.

[0150] In addition, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may each include a fourth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. Each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be connected to Fig.13 and Fig.14 The pull-up transistor TU of the scan driver circuit SDC shown in FIG. 1 is formed substantially the same. In this case, the fourth gate electrode, the fourth active layer, the fourth source electrode and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are the same as those of the above reference. Fig.13 and Fig.14 The third gate electrode 213 , the third active layer 233 , the third source electrode 243 , and the third drain electrode 253 of the described pull-up transistor TU are substantially the same, and thus a detailed description thereof is omitted.

[0151] Replacement reference Figures 6 to 9 The buffer layer 102 and the insulating layer 103 described above may be formed on the second planarization layer 280. Figures 6 to 9 The first interlayer insulating film 160, the first protective layer 170, and the first planarizing layer 180 described above may be formed on the insulating layer 103. Fig.13 and Fig.14 In the exemplary embodiment of the present invention, the first thin film transistor layer TFTL1 (see Fig.22A ) may be formed on the first substrate 101, the first thin film transistor layer TFTL1 includes a pull-up transistor TU, a pull-down transistor TD of the scan driver circuit SDC, and a transistor of the node controller NC, and a first distribution transistor MT1 and a second distribution transistor MT2 of the data voltage distribution circuit DMUX. The second thin film transistor layer TFTL2 (see Fig. 22B) may be formed on the first thin film transistor layer TFTL1, and the second thin film transistor layer TFTL2 includes a driving transistor DT and a switching transistor ST of each pixel P. Then, light emitting elements EL each including a first electrode 191, an organic light emitting layer 192, and a second electrode 193 may be formed on the second thin film transistor layer TFTL2.

[0152] Fig.15 yes Figure 4 0 is a plan view of an example of a pull-up transistor TU of a scan driver circuit SDC shown in FIG. Fig.16 is along Fig.15 Example cross-sectional view taken along line V-V'.

[0153] Fig.15 and Fig.16 An exemplary embodiment of Fig.13 and Fig.14 The exemplary embodiment of FIG. 1 is different in that the third gate electrode 213 of the pull-up transistor TU is connected to the third light shielding layer 263. Fig.15 and Fig.16 In the Fig.13 and Fig.14 The redundant description of the elements and features of the exemplary embodiments of the present invention is omitted, and the description will mainly focus on the elements and features of the exemplary embodiments of the present invention. Fig.13 and Fig.14 The differences between the embodiments.

[0154] refer to Fig.15 and Fig.16 In addition to the third gate electrode 213 , the third active layer 233 , the third source electrode 243 , and the third drain electrode 253 , the pull-up transistor TU of the scan driver circuit SDC further includes a third light shielding layer 263 .

[0155] In order to block external light from entering the third active layer 233 through the first substrate 101, a third light shielding layer 263 may be formed on the first substrate 101. The length of the third light shielding layer 263 in the fourth direction DR4 and the fifth direction DR5 may be greater than the length of the third active layer 233 in the fourth direction DR4 and the fifth direction DR5. The third light shielding layer 263 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The buffer layer 102 may be formed on the third light shielding layer 263.

[0156] The third gate electrode 213 may contact the third light shielding layer 263 through the ninth contact hole CT9. The ninth contact hole CT9 may pass through the second gate insulating layer 220 and the buffer layer 102 to expose the third light shielding layer 263. In this case, the third light shielding layer 263 arranged below the third active layer 233 has the same voltage as the third gate electrode 213. That is, the third gate electrode 213 may be used as a top gate electrode, and the third light shielding layer 263 may be used as a bottom gate electrode. Therefore, since the pull-up transistor TU can be driven in a dual-gate manner, it is possible to prevent or reduce leakage current from flowing through the channel region 233c of the third active layer 233 of the pull-up transistor TU when the pull-up transistor TU is turned off.

[0157] Each of the pull-down transistor TD of the scan driver circuit SDC and the transistor of the node controller NC may be connected to Fig.15 and Fig.16 The pull-up transistors TU shown in are formed substantially identically.

[0158] In addition, the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may each include a fourth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. Each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be connected to Fig.15 and Fig.16 The pull-up transistor TU of the scan driver circuit SDC shown in FIG. 1 is formed substantially the same. In this case, the fourth gate electrode, the fourth active layer, the fourth source electrode and the fourth drain electrode of each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX are the same as those of the above reference. Fig.15 and Fig.16 The third gate electrode 213 , the third active layer 233 , the third source electrode 243 , and the third drain electrode 253 of the described pull-up transistor TU are substantially the same, and thus a detailed description thereof is omitted.

[0159] Fig.17 is a flowchart illustrating a method of manufacturing a display apparatus according to an exemplary embodiment. FIG. 18A to FIG. 18G is a cross-sectional view for explaining a method of manufacturing a display apparatus according to an exemplary embodiment.

[0160] Now refer to Fig.17 as well as FIG. 18A to FIG. 18G A method of manufacturing a display device according to an embodiment is described in detail. FIG. 18A to FIG. 18G Each of the Figure 6 The cross section taken along I-I' and Fig.11 The cross section is taken from III-III'.

[0161] First, reference Fig.18A, a first light shielding layer 161 and a second light shielding layer 162 are formed on the first substrate 101, and a buffer layer 102 is formed on the first light shielding layer 161 and the second light shielding layer 162 ( Fig.17 Operation S101 in .

[0162] The first light shielding layer 161 is a layer for preventing light from the first substrate 101 from entering the first active layer 131, and the second light shielding layer 162 is a layer for preventing light from the first substrate 101 from entering the second active layer 132. Each of the first light shielding layer 161 and the second light shielding layer 162 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first light shielding layer 161 and the second light shielding layer 162 may be formed by patterning a light shielding metal layer formed on the entire surface of the first substrate 101 by sputtering in an etching process using a photoresist pattern.

[0163] The buffer layer 102 is formed on the first light shielding layer 161 and the second light shielding layer 162. The buffer layer 102 is a layer for protecting the driving transistor DT and the switching transistor ST of each pixel P from moisture introduced through the first substrate 101. The buffer layer 102 may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer 102 may be a layer in which silicon oxide (SiO x ) layer, silicon nitride (SiN x The buffer layer 102 may be formed by chemical vapor deposition.

[0164] Second, reference Fig.18B , the active layer 130 is formed on the entire surface of the buffer layer 102 ( Fig.17 Operation S102 in FIG.

[0165] The active layer 130 may be an oxide semiconductor. For example, the active layer 130 may be an oxide semiconductor including tin (Sn). In this case, the active layer 130 may be indium gallium tin oxide (IGTO) or indium gallium zinc tin oxide (IGZTO). The active layer 130 may be formed by sputtering.

[0166] Third, reference Fig.18C , patterning the photoresist PR on the active layer 130 ( Fig.17 Operation S103 in .

[0167] The photoresist PR may be formed on the active layer 130 except for a region where the first active layer 131 is to be formed. Alternatively, the photoresist PR may be formed on a region of the active layer 130 where the second active layer 132 is to be formed.

[0168] Fourth, reference Fig.18C , a metal film MF is formed on the photoresist PR and the exposed active layer 130. Then, referring to Fig.18D , the metal film MF is etched to dope the exposed active layer 130 ( Fig.17 Operation S104 in .

[0169] The metal film MF may be a mixture of copper (Cu), arsenic (As), antimony (Sb), lanthanum (La), silver (Ag), and nitrogen (N), a mixture of boron (B) and nitrogen (N), or a mixture of gallium (Ga) and nitrogen (N). The metal film MF may be formed by sputtering.

[0170] In order to prevent the active layer 130 from being damaged by the etchant used to etch the metal film MF, the etchant used to etch the metal film MF may be a solution that reacts only with the metal film MF but not with the active layer 130. For example, if the metal film MF is copper (Cu) and the active layer 130 is an oxide semiconductor including tin (Sn), the etchant may be a non-hydrogen peroxide solution including citric acid or ammonium persulfate to react with copper (Cu) but not with the active layer 130. The metal film MF may be etched by wet etching.

[0171] Fifth, reference Fig.18E , the first active layer 131 and the second active layer 132 are formed by removing the photoresist PR and patterning the active layer 130 ( Fig.17 Operation S105 in .

[0172] The photoresist PR may be removed by a stripping process. The first active layer 131 and the second active layer 132 may be formed by patterning the active layer 130 in an etching process using a photoresist pattern different from the photoresist PR. The active layer 130 may be patterned by wet etching or dry etching.

[0173] The metal doped into the first active layer 131 may be formed only on an upper surface of the first active layer 131. In addition, the metal doped into the first active layer 131 may have a ratio of about 10 atomic % or less in the first active layer 131.

[0174] Sixth, reference Fig.18F , a first gate insulating layer 120 is formed on the first active layer 131 and the second active layer 132, and a first gate electrode 111 and a second gate electrode 112 are formed on the first gate insulating layer 120 ( Fig.17 Operation S106 in .

[0175] The first gate insulating layer 120 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiNx ) layer or a multilayer composed of these layers. The first gate insulating layer 120 may be formed by chemical vapor deposition.

[0176] Each of the first gate electrode 111 and the second gate electrode 112 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first gate electrode 111 and the second gate electrode 112 may be formed by patterning a gate metal layer formed on the entire surface of the first gate insulating layer 120 by sputtering in an etching process using a photoresist pattern.

[0177] The first gate insulating layer 120 may be etched and patterned by using the first gate electrode 111 and the second gate electrode 112 as masks, such as Fig.18F By etching the first gate electrode 111, the second gate electrode 112, and the first gate insulating layer 120 in batches, the upper surface of the first active layer 131 and the upper surface of the second active layer 132 not covered by the first gate insulating layer 120 can be made conductive.

[0178] Seventh, reference Figure 18G , a first interlayer insulating film 160 is formed on the first gate electrode 111 and the second gate electrode 112, and a first source electrode 141, a second source electrode 142, a first drain electrode 151 and a second drain electrode 152 are formed on the first interlayer insulating film 160 ( Fig.17 Operation S107 in .

[0179] The first interlayer insulating film 160 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers. The first interlayer insulating film 160 may be formed by chemical vapor deposition.

[0180] A first contact hole CT1 passing through the first interlayer insulating film 160 to expose a portion of the upper surface of the first active layer 131 and a second contact hole CT2 passing through the first interlayer insulating film 160 to expose another portion of the upper surface of the first active layer 131 may be formed in the first interlayer insulating film 160. A third contact hole CT3 passing through the first interlayer insulating film 160 and the buffer layer 102 to expose the first light shielding layer 161 may be formed in the first interlayer insulating film 160 and the buffer layer 102.

[0181] In addition, a fourth contact hole CT4 passing through the first interlayer insulating film 160 to expose a portion of the upper surface of the second active layer 132 and a fifth contact hole CT5 passing through the first interlayer insulating film 160 to expose another portion of the upper surface of the second active layer 132 may be formed in the first interlayer insulating film 160. A sixth contact hole CT6 passing through the first interlayer insulating film 160 and the buffer layer 102 to expose the second light shielding layer 162 may be formed in the first interlayer insulating film 160 and the buffer layer 102.

[0182] Each of the first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be formed by patterning a source-drain metal layer formed on the entire surface of the first interlayer insulating film 160 by sputtering in an etching process using a photoresist pattern.

[0183] The first source electrode 141 may be formed to contact the first conductive region 131a formed on one side of the first active layer 131 through the first contact hole CT1. The first drain electrode 151 may be formed to contact the second conductive region 131b formed on the other side of the first active layer 131 through the second contact hole CT2. In addition, the first source electrode 141 may be formed to contact the first light shielding layer 161 through the third contact hole CT3.

[0184] The second source electrode 142 may be formed to contact the first conductive region 132a formed on one side of the second active layer 132 through the fourth contact hole CT4. The second drain electrode 152 may be formed to contact the second conductive region 132b formed on the other side of the second active layer 132 through the fifth contact hole CT5. In addition, the second gate electrode 112 may be formed to contact the second light shielding layer 162 through the sixth contact hole CT6.

[0185] The first protective layer 170 is formed on the first source electrode 141, the second source electrode 142, the first drain electrode 151 and the second drain electrode 152. The first protective layer 170 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a plurality of layers consisting of these layers. The first protective layer 170 may be formed by chemical vapor deposition.

[0186] The first planarization layer 180 may be formed on the first protection layer 170 to flatten steps caused by thin film transistors such as the driving transistor DT and the switching transistor ST. The first planarization layer 180 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0187] The third gate electrode, the third active layer, the third source electrode, and the third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the plurality of transistors of the node controller NC may be the same as those described above with reference to FIG. Fig.17 , FIG. 18A to FIG. 18G The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the described switching transistor ST are substantially identically formed, and thus a detailed description thereof is omitted.

[0188] In addition, each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX can be the same as that in the above reference. Fig.17 as well as FIG. 18A to FIG. 18G The described switching transistor ST is formed substantially identically, and thus a detailed description thereof is omitted.

[0189] Fig.19 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. FIG. 20A to FIG. 20C is a cross-sectional view for explaining a method of manufacturing the display device according to this exemplary embodiment.

[0190] FIG. 20A to FIG. 20C Each of the Figure 6 The cross section taken along I-I' and Fig.11 The cross section is taken from III-III'. Fig.19 as well as FIG. 20A to FIG. 20C An exemplary embodiment of Fig.17 as well as FIG. 18A to FIG. 18G The difference of the exemplary embodiment of is operations S203 to S205. Fig.19 as well as FIG. 20A to FIG. 20C In the Fig.17 as well as FIG. 18A to FIG. 18G The redundant description of the elements and features of the exemplary embodiments of the present invention is omitted, and the description will mainly focus on the elements and features of the exemplary embodiments of the present invention. Fig.17 as well as FIG. 18A to FIG. 18G The differences between the exemplary embodiments are shown in FIG.

[0191] Fig.19 Operations S201, S202, S206 and S207 are Fig.17 Operations S101, S102, S106, and S107 are substantially the same, and thus a detailed description thereof will be omitted.

[0192] refer to Fig. 20A , the first active layer 131 and the second active layer 132 are formed by patterning the active layer 130, and a photoresist PR is formed on the second active layer 132 ( Fig.19 Operation S203 in .

[0193] The first active layer 131 and the second active layer 132 may be formed by patterning the active layer 130 in an etching process using a photoresist pattern. The photoresist PR may be formed on the second active layer 132 or may be formed in a region other than a region where the first active layer 131 is to be formed.

[0194] Then, refer to Fig. 20B , the metal film MF is formed on the photoresist PR and the first active layer 131 not covered by the photoresist PR ( Fig.19 Operation S204 in .

[0195] The metal film MF may be a mixture of copper (Cu), arsenic (As), antimony (Sb), lanthanum (La), silver (Ag), and nitrogen (N), a mixture of boron (B) and nitrogen (N), or a mixture of gallium (Ga) and nitrogen (N). The metal film MF may be formed by sputtering.

[0196] Next, refer to Fig. 20C , the metal film MF is etched to dope the first active layer 131 with a metal, and the photoresist PR is removed ( Fig.19 Operation S205 in .

[0197] In order to prevent the active layer 130 from being damaged by the etchant used to etch the metal film MF, the etchant used to etch the metal film MF may be a solution that reacts only with the metal film MF but not with the active layer 130. For example, if the metal film MF is copper (Cu) and the active layer 130 is an oxide semiconductor including tin (Sn), the etchant may be a non-hydrogen peroxide solution including citric acid or ammonium persulfate to react with copper (Cu) but not with the active layer 130. The metal film MF may be etched by wet etching.

[0198] The metal doped into the first active layer 131 may be formed on the upper surface and the side surface of the first active layer 131. In addition, the metal doped into the first active layer 131 may have a ratio of about 10 atomic % or less in the first active layer 131.

[0199] The photoresist PR may be removed through a stripping process.

[0200] Fig.21 is a flowchart illustrating a method of manufacturing a display apparatus according to an exemplary embodiment. FIG. 22A to FIG. 22Cis a cross-sectional view for explaining a method of manufacturing a display apparatus according to an exemplary embodiment.

[0201] FIG. 22A to FIG. 22C Each of the Figure 6 The cross section taken along I-I' and Fig.15 The cross section is taken along line V-V'.

[0202] First, a first thin film transistor layer TFTL1 is formed on a first substrate 101, and the first thin film transistor layer TFTL1 includes a pull-up transistor TU, a pull-down transistor TD of a scan driver circuit SDC, and a transistor of a node controller NC, and a first distribution transistor MT1 and a second distribution transistor MT2 of a data voltage distribution circuit DMUX. Each transistor formed in the first thin film transistor layer TFTL1 may include polysilicon ( Fig.21 Operation S301 in .

[0203] refer to Fig.22A The pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may each include a third gate electrode 213, a third active layer 233, a third source electrode 243, a third drain electrode 253, and a third light shielding layer 263. Fig.22A In the figure, for the convenience of description, only the pull-up transistor TU of the scan driver circuit SDC is illustrated.

[0204] The third light shielding layer 263 is formed on the first substrate 101, and the buffer layer 102 is formed on the third light shielding layer 263. The third light shielding layer 263 is a layer for blocking light from the first substrate 101 from entering the third active layer 233. The third light shielding layer 263 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The third light shielding layer 263 may be formed by patterning a light shielding metal layer formed on the entire surface of the first substrate 101 by sputtering in an etching process using a photoresist pattern.

[0205] The buffer layer 102 is formed on the third light shielding layer 263. The buffer layer 102 is a layer for protecting the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC from the influence of moisture introduced through the first substrate 101. The buffer layer 102 may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer 102 may be a layer in which silicon oxide (SiO x ) layer, silicon nitride (SiN x The buffer layer 102 may be formed by chemical vapor deposition.

[0206] The third active layer 233 is formed on the buffer layer 102. The third active layer 233 may be formed by patterning an active layer formed on the entire surface of the buffer layer 102 in an etching process using a photoresist pattern. The third active layer 233 may include polysilicon.

[0207] The second gate insulating layer 220 is formed on the third active layer 233 , and the third gate electrode 213 is formed on the second gate insulating layer 220 .

[0208] The second gate insulating layer 220 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers. The second gate insulating layer 220 may be formed by chemical vapor deposition. A ninth contact hole CT9 passing through the second gate insulating layer 220 and the buffer layer 102 to expose a portion of the third light shielding layer 263 may be formed in the second gate insulating layer 220 and the buffer layer 102.

[0209] The third gate electrode 213 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The third gate electrode 213 may be formed by patterning a gate metal layer formed on the entire surface of the second gate insulating layer 220 by sputtering in an etching process using a photoresist pattern. The third gate electrode 213 may contact the third light shielding layer 263 through a ninth contact hole CT9 passing through the second gate insulating layer 220 and the buffer layer 102.

[0210] Here, before removing the photoresist pattern formed on the third gate electrode 213 , heavy impurity doping may be performed to form a heavily doped region in the third active layer 223 .

[0211] The second gate insulating layer 220 may be etched and patterned by using the third gate electrode 213 as a mask. Then, light impurity doping may be performed to form a lightly doped region in the third active layer 233.

[0212] A second interlayer insulating film 260 may be formed on the third gate electrode 213 , and a third source electrode 243 and a third drain electrode 253 may be formed on the second interlayer insulating film 260 .

[0213] The second interlayer insulating film 260 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers. The second interlayer insulating film 260 may be formed by chemical vapor deposition.

[0214] A seventh contact hole CT7 passing through the second interlayer insulating film 260 to expose a portion of the upper surface of the second active layer 233 and an eighth contact hole CT8 passing through the second interlayer insulating film 260 to expose another portion of the upper surface of the third active layer 233 may be formed in the second interlayer insulating film 260 .

[0215] Each of the third source electrode 243 and the third drain electrode 253 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The third source electrode 243 and the third drain electrode 253 may be formed by patterning a source-drain metal layer formed on the entire surface of the second interlayer insulating film 260 by sputtering in an etching process using a photoresist pattern.

[0216] The third source electrode 243 may be formed to contact the first heavily doped region 233a formed at one side of the third active layer 233 through the seventh contact hole CT7. The third drain electrode 253 may be formed to contact the second heavily doped region 233b formed at the other side of the third active layer 233 through the eighth contact hole CT8.

[0217] The second protective layer 270 is formed on the third source electrode 243 and the third drain electrode 253. The second protective layer 270 may be an inorganic layer, for example, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a plurality of layers consisting of these layers. The second protective layer 270 may be formed by chemical vapor deposition.

[0218] The second planarization layer 280 may be formed on the second protection layer 270 to flatten the steps caused by thin film transistors such as the pull-up transistor TU of the scan driver circuit SDC, the pull-down transistor TD, and the transistor of the node controller NC. The second planarization layer 280 may be made of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0219] Each of the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX can be connected to the above Fig.21 The pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC described in operation S301 are substantially identically formed, and thus a detailed description thereof will be omitted.

[0220] Second, a second thin film transistor layer TFTL2 is formed on the first thin film transistor layer TFTL1, and the second thin film transistor layer TFTL2 includes a driving transistor DT and a switching transistor ST of each pixel P. Fig. 22B In the figure, for the convenience of description, only the driving transistor DT of each pixel P is illustrated. Each transistor formed in the second thin film transistor layer TFTL2 may include an oxide semiconductor ( Fig.21 Operation S302 in .

[0221] Process and reference for forming the second thin film transistor layer TFTL2 Fig.17 as well as FIG. 18A to FIG. 18G Described exemplary embodiments or references Fig.19 as well as FIG. 20A to FIG. 20C The processes of the described exemplary embodiments are substantially the same except that the first light shielding layer 161 and the second light shielding layer 162 are not formed on the first substrate 101 but are formed on the second planarization layer 280 , and thus a detailed description thereof is omitted.

[0222] Third, the light emitting elements EL each including the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are formed on the second thin film transistor layer TFTL2 ( Fig.21 Operation S303 in .

[0223] The first electrode 191 may be formed on the first planarization layer 180 . The first electrode 191 may contact the source electrode 141 of the driving transistor DT through a contact hole CNT passing through the first protection layer 170 and the first planarization layer 180 .

[0224] The pixel defining layer 195 may be formed on the first planarization layer 180 and may cover the edge of the first electrode 191 to define the pixel. That is, the pixel defining layer 195 serves as a pixel defining layer for defining the pixel. Here, each pixel in the pixel is a region where the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are sequentially stacked so that holes from the first electrode 191 and electrons from the second electrode 193 are combined in the organic light emitting layer 192 to emit light.

[0225] The organic light emitting layer 192 may be disposed on the first electrode 191 and the pixel defining layer 195. The organic light emitting layer 192 may include a hole transport layer, a light emitting layer, and an electron transport layer. In addition, the organic light emitting layer 192 may be formed in a series structure of two or more stacks, in which case a charge generation layer may be formed between the stacks.

[0226] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer shared by all pixels.

[0227] The light emitting element EL may be a top emission type that emits light in the direction opposite to the first substrate 101 (i.e., in the upward direction). In this case, the first electrode 191 may be made of a metal material with high reflectivity, such as a stack of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stack of aluminum (Al) and ITO (ITO / Al / ITO), an APC alloy, or a stack of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu). In addition, the second electrode 193 may be made of a transparent conductive material (TCO) (such as ITO or IZO) that can transmit light, or may be made of a semi-transmissive conductive material such as an alloy of magnesium (Mg), silver (Ag) or magnesium (Mg) and silver (Ag). When the second electrode 193 is made of a semi-transmissive conductive material, the luminous efficiency may be improved by a microcavity.

[0228] The encapsulation layer 196 may be formed on the second electrode 193 to prevent the introduction of oxygen or moisture. The encapsulation layer 196 may include at least one inorganic layer. The inorganic layer may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In addition, the encapsulation layer 196 may include at least one organic layer to prevent particles from penetrating the encapsulation layer 196 and entering the organic light-emitting layer 192 and the second electrode 193. The organic layer may be made of epoxy resin, acrylate, or polyurethane acrylate.

[0229] according to Fig.21 as well as FIG. 22A to FIG. 22C In an exemplary embodiment, the pull-up transistor TU, the pull-down transistor TD, and the transistor of the node controller NC of the scan driver circuit SDC and the first distribution transistor MT1 and the second distribution transistor MT2 of the data voltage distribution circuit DMUX may be thin film transistors including a polysilicon active layer, and the driving transistor DT and the switching transistor ST of each pixel P may be transistors including an active layer of an oxide semiconductor.

[0230] According to the inventive concept, in a display device including a thin film transistor and a method for manufacturing a display device according to an exemplary embodiment, the first active layer is doped with a metal. Therefore, it is possible to capture electrons moving through the channel region of the first active layer. In this case, due to the metal doped into the first active layer, the slope of the drive current (drain-source current) curve according to the gate voltage of the drive transistor can be reduced. Therefore, even in a high-resolution flat-panel display device, the drive current of each pixel decreases as the number of pixels increases, and the reduction in the drive voltage range of the drive transistor can be prevented or reduced.

[0231] According to the inventive concept, in a display device including a thin film transistor and a method for manufacturing a display device according to an exemplary embodiment, the transistors of a scan driver circuit and the transistors of a data voltage distribution circuit may be thin film transistors including an active layer of polysilicon, and the driving transistor and the switching transistor of each pixel may be thin film transistors including an active layer of an oxide semiconductor.

[0232] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements, as will be apparent to one of ordinary skill in the art.

Claims

1. A display device, comprising: pixels connected to scan lines and data lines crossing the scan lines, in, The pixels include: a light emitting element and a driving transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line; and a scanning transistor for applying the data voltage of the data line to the gate electrode of the driving transistor according to a scanning signal transmitted to the scanning line, The driving transistor includes a first active layer including an oxide semiconductor doped with a metal, The scanning transistor includes a second active layer including the oxide semiconductor, and The second active layer is not doped with the metal.

2. The display device according to claim 1, wherein: The ratio of the metal in the first active layer is 10 atomic % or less.

3. The display device according to claim 1, wherein: The metal is copper, arsenic, antimony, lanthanum, a mixture of silver and nitrogen, a mixture of boron and nitrogen, or a mixture of gallium and nitrogen.

4. The display device according to claim 1, wherein: The metal is copper, and the oxide semiconductor includes tin.

5. The display device according to claim 4, wherein: The first active layer includes indium gallium tin oxide or indium gallium zinc tin oxide.

6. The display device according to claim 1, wherein: The metal is doped into an upper surface of the first active layer.

7. The display device according to claim 6, wherein: The metal is doped into at least one side surface of the first active layer.

8. The display device according to claim 1, wherein: The first active layer includes a first conductive region, a second conductive region, and a channel region disposed between the first conductive region and the second conductive region.

9. The display device according to claim 8, wherein the driving transistor further comprises: a first light shielding layer disposed below the first active layer; a first gate electrode disposed on the first active layer; a first source electrode connected to the first conductive region through a first contact hole penetrating the interlayer insulating film arranged on the first gate electrode; as well as a first drain electrode connected to the second conductive region through a second contact hole penetrating the interlayer insulating film, The first source electrode contacts the first light shielding layer through a third contact hole that passes through the interlayer insulating film and an insulating layer arranged between the first active layer and the first light shielding layer.

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