Display device and electronic device

Abstract

The present invention provides a display device capable of improving image quality. A pixel includes a plurality of capacitors, a plurality of transistors, and a display element. The plurality of capacitors are connected in series through wirings, and one, the other, and the wiring of the plurality of capacitors connected in series are electrically connected to one of the plurality of transistors respectively. The display element can be operated according to the sum of a plurality of input data, and image correction such as up-conversion of an image, HDR display, or improvement of brightness can be performed.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Thus, more specifically, as an example of the technical field of one aspect of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a imaging device, a driving method of these devices, or a manufacturing method of these devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. In addition, a storage device, a display device, a imaging device, and an electronic device sometimes include a semiconductor device. Background Art

[0004] As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known. As other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0005] Through research on IGZO, in oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been discovered (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Documents 4 and 5 disclose that even in an oxide semiconductor with lower crystallinity than the CAAC structure and the nc structure, there are also minute crystals.

[0006] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, Patent Document 1 discloses a storage device having a structure in which a transistor with an extremely low off-state current is used for a storage cell.

[0008] [Prior Art Documents]

[0009] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119674

[0011] [Non-Patent Documents]

[0012] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p. 183-186

[0013] [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10

[0014] [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p. 151-154

[0015] [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022

[0016] [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164

[0017] [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7

[0018] [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217

[0019] [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626-629 Summary of the Invention

[0020] Technical Problem to be Solved by the Invention

[0021] The resolution of display devices has been continuously improved, and hardware capable of displaying images with a resolution of 8K4K (number of pixels: 7680×4320) or higher has been developed. In addition, the introduction of HDR (High Dynamic Range) display technology for improving image quality by adjusting brightness has been promoted.

[0022] In order to properly display by a display device, it is necessary to make the image data correspond to the resolution of the display device. For example, when the resolution of the display device is 8K4K and the image data is data for 4K2K (number of pixels: 3840×2160), full-screen display cannot be performed unless the amount of data is converted to 4 times. On the contrary, when the resolution of the display device is 4K2K and the image data is data for 8K4K, the amount of data needs to be converted to 1 / 4.

[0023] In addition, there is a problem that dedicated circuits are required for the generation of image data and the conversion of the amount of data in HDR processing, resulting in increased power consumption. It is preferable to input the original image data into the pixels of the display device without at least converting it.

[0024] Therefore, one of the objects of one aspect of the present invention is to provide a display device capable of improving image quality. Another object of one aspect of the present invention is to provide a display device capable of properly displaying without converting image data. Another object of one aspect of the present invention is to provide a display device capable of performing HDR display. Another object of one aspect of the present invention is to provide a display device capable of performing up-conversion operation. Another object of one aspect of the present invention is to provide a display device capable of increasing the brightness of a displayed image. Another object of one aspect of the present invention is to provide a display device capable of overlappingly displaying two or more images. Another object of one aspect of the present invention is to provide a display device capable of applying a voltage higher than the output voltage of a driving circuit to a pixel circuit.

[0025] In addition, one of the objects of one embodiment of the present invention is to provide a display device with low power consumption. Further, one of the objects of one embodiment of the present invention is to provide a display device with high reliability. In addition, one of the objects of one embodiment of the present invention is to provide a novel display device and the like. In addition, one of the objects of one embodiment of the present invention is to provide a driving method for the above-described display device. In addition, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device and the like.

[0026] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of the above objects. In addition, objects other than the above are obvious from the description in the specification, drawings, claims, etc., and objects other than the above can be extracted from the description in the specification, drawings, claims, etc.

[0027] Means for Solving the Technical Problem

[0028] One embodiment of the present invention relates to a display device capable of improving image quality. In addition, one embodiment of the present invention relates to a display device capable of performing image processing.

[0029] One embodiment of the present invention is a display device including: a plurality of capacitors; a plurality of transistors; and a display element, wherein the plurality of capacitors are connected in series through wirings, one electrode of the plurality of capacitors connected in series is electrically connected to one of the transistors, the other electrode of the plurality of capacitors connected in series is electrically connected to one of the transistors, the other electrode of the plurality of capacitors connected in series is electrically connected to the display element, and the wiring is electrically connected to one of the above-described transistors.

[0030] Another embodiment of the present invention is a display device including: a first transistor; a second transistor; a third transistor; a first capacitor; a second capacitor; and a circuit block, wherein one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor, one electrode of the first capacitor is electrically connected to the circuit block, the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the second transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and drain of the third transistor, and the circuit block includes a display element.

[0031] The above-described display device may further include a first wiring, wherein the other of the source and drain of the first transistor is electrically connected to the first wiring, and the other of the source and drain of the third transistor is electrically connected to the first wiring.

[0032] The above display device may further include a fourth transistor, a fifth transistor, a second wiring, and a third wiring, wherein one of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor, one of the source and the drain of the fifth transistor is electrically connected to the other electrode of the second capacitor, the other of the source and the drain of the second transistor is electrically connected to the first wiring, the gate of the first transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gate of the second transistor is electrically connected to the third wiring, and the gate of the fifth transistor is electrically connected to the third wiring.

[0033] Another aspect of the present invention is a display device, including: a first circuit; a second circuit; a second transistor; a third transistor; and a second capacitor, wherein the first circuit and the second circuit each include a first transistor, a first capacitor, and a circuit block, one of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, one electrode of the first capacitor is electrically connected to the circuit block, the other electrode of the first capacitor is electrically connected to one of the source and the drain of the second transistor, one of the source and the drain of the second transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and the drain of the third transistor, and the circuit block includes a display element.

[0034] The above display device may further include a first wiring, wherein the other of the source and the drain of the first transistor included in the first circuit is electrically connected to the first wiring, and the other of the source and the drain of the third transistor is electrically connected to the first wiring.

[0035] The above display device may further include a fourth transistor, a fifth transistor, a second wiring, and a third wiring, wherein one of the source and the drain of the fourth transistor is electrically connected to one electrode of the second capacitor, one of the source and the drain of the fifth transistor is electrically connected to the other electrode of the second capacitor, the other of the source and the drain of the second transistor is electrically connected to the first wiring, the gate of the first transistor included in the first circuit is electrically connected to the second wiring, the gate of the first transistor included in the second circuit is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gate of the second transistor is electrically connected to the third wiring, and the gate of the fifth transistor is electrically connected to the third wiring.

[0036] The circuit block may also include a sixth transistor, a seventh transistor, a third capacitor, and an EL element serving as a display element. One electrode of the EL element is electrically connected to one of the source and drain of the seventh transistor, the other of the source and drain of the seventh transistor is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to one of the source and drain of the sixth transistor, the gate of the sixth transistor is electrically connected to the other electrode of the third capacitor, and the other electrode of the third capacitor is electrically connected to one electrode of the first capacitor.

[0037] The circuit block may also include a fourth capacitor and a liquid crystal element serving as a display element. One electrode of the liquid crystal element is electrically connected to one electrode of the fourth capacitor, and one electrode of the fourth capacitor is electrically connected to one electrode of the first capacitor.

[0038] The above display device may further include an eighth transistor, wherein one electrode of the fourth capacitor is electrically connected to one of the source and drain of the eighth transistor, and the other of the source and drain of the eighth transistor is electrically connected to one electrode of the first capacitor.

[0039] The first transistor preferably includes a metal oxide in the channel formation region, and the metal oxide includes In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0040] Advantages of the Invention

[0041] By using one aspect of the present invention, a display device capable of improving image quality can be provided. By using one aspect of the present invention, a display device capable of performing appropriate display without converting image data can be provided. By using one aspect of the present invention, a display device capable of performing HDR display can be provided. By using one aspect of the present invention, a display device capable of performing up-conversion operation can be provided. By using one aspect of the present invention, a display device capable of increasing the brightness of a displayed image can be provided. By using one aspect of the present invention, a display device capable of overlappingly displaying two or more images can be provided. By using one aspect of the present invention, a display device capable of applying a voltage higher than the output voltage of the driving circuit to the pixel circuit can be provided.

[0042] In addition, a display device with low power consumption can be provided. Furthermore, a display device with high reliability can be provided. Additionally, a novel display device, etc. can be provided. Additionally, a driving method for the above display device can be provided. Additionally, a novel semiconductor device, etc. can be provided. Brief Description of the Drawings

[0043] Figure 1 ​A diagram illustrating a pixel circuit.

[0044] [Figure 2] A timing diagram illustrating the operation of a pixel circuit.

[0045] [Figure 3] A timing diagram illustrating the operation of a pixel circuit.

[0046] [Figure 4] A diagram illustrating a pixel circuit and a timing diagram illustrating the operation of the pixel circuit.

[0047] [Figure 5] A diagram illustrating a pixel circuit and a timing diagram illustrating the operation of the pixel circuit.

[0048] Figure 6 A diagram illustrating a pixel circuit.

[0049] [Figure 7] A diagram illustrating a circuit block.

[0050] [Figure 8] A diagram illustrating a circuit block.

[0051] [Figure 9] A diagram illustrating a pixel circuit.

[0052] [Figure 10] A diagram illustrating the correction of image data and the synthesis of images.

[0053] Figure 11 A diagram illustrating a pixel matrix.

[0054] Figure 12 A diagram illustrating a pixel matrix.

[0055] Figure 13 A diagram illustrating a pixel matrix.

[0056] [Figure 14] A block diagram illustrating a display device.

[0057] [Figure 15] A diagram illustrating an example of the structure of a neural network.

[0058] Figure 16 A diagram illustrating a pixel circuit for simulation.

[0059] [Figure 17] A diagram illustrating simulation results.

[0060] [Figure 18] A diagram illustrating a display device.

[0061] [Figure 19] A diagram illustrating a touch screen.

[0062] [Figure 20] A diagram illustrating a display device.

[0063] Figure 21 A diagram illustrating a display device.

[0064] [Figure 22] A diagram illustrating a transistor.

[0065] [Figure 23] A diagram illustrating a transistor.​​​​​​

[0066] [Figure 24] Diagram of a transistor.

[0067] [Figure 25] Diagram of a transistor.

[0068] [Figure 26] Diagram of an electronic device. Detailed implementation mode

[0069] The implementation mode will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those of ordinary skill in the art can easily understand the fact that its mode and details can be changed into various forms without departing from the gist and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following implementation modes. Note that in the structure of the invention described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. Note that sometimes the shading of the same constituent elements is appropriately omitted or changed in different drawings.

[0070] (Embodiment 1)

[0071] In the present embodiment, a display device according to one mode of the present invention will be described with reference to the accompanying drawings.

[0072] One mode of the present invention is a display device having a function of correcting image data in pixels. A plurality of storage nodes are serially provided in each pixel, and a display element can be operated according to the sum of a plurality of input data.

[0073] Therefore, in this display device, for example, image correction such as up-conversion of an image, HDR display for correcting a part or the whole of an image in a display area, or increasing the brightness of a displayed image can be performed. In addition, overlapping display of a plurality of images and supplying a voltage higher than the output voltage of a driving circuit to a pixel circuit can also be performed.

[0074] By using one mode of the present invention, appropriate display can be performed without up-converting or down-converting image data with different resolutions. As an example, in the case of adopting a pixel structure for three levels of high, medium, and low resolutions, when displaying at a high resolution, different data are supplied to each pixel through a first transistor included in each pixel. When displaying at a medium resolution, the same data are supplied to a plurality of pixels electrically connected to a second transistor in a first group through the second transistor. When displaying at a low resolution, the same data are supplied to a plurality of pixels electrically connected to a third transistor in a second group through the third transistor.

[0075] Here, high-resolution image data, for example, corresponds to data including information amount corresponding to 8K4K (number of pixels: 7,680 × 4,320). In addition, medium-resolution image data, for example, corresponds to data including information amount corresponding to 4K2K (number of pixels: 3,840 × 2,160). In addition, low-resolution image data, for example, corresponds to data including information amount corresponding to FullHD (number of pixels: 1,920 × 1,080).

[0076] That is, it is described on the premise that the ratio of the effective data amount (corresponding to the effective number of pixels) of the high-resolution image data to the medium-resolution image data and the ratio of the effective data amount of the medium-resolution image data to the low-resolution image data are 4:1. The ratio of the effective data amount of the high-resolution image data to the low-resolution image data is 16:1. Note that as long as the data amount is in the above ratio, the number of pixels is not limited to the above examples, and other specifications can also be adopted.

[0077] Figure 1 FIG. is a diagram showing pixel 10 of a display device that can be used in one embodiment of the present invention. Pixel 10 includes two capacitors and can perform display according to the sum of up to three data through capacitive coupling.

[0078] Pixel 10 includes transistor 101, transistor 102, transistor 103, capacitor 104, capacitor 105, and circuit block 110. Circuit block 110 may include transistors, capacitors, display elements, etc., and its detailed content will be described later.

[0079] One of the source and drain of transistor 101 is electrically connected to one electrode of capacitor 104. One electrode of capacitor 104 is electrically connected to circuit block 110. The other electrode of capacitor 104 is electrically connected to one of the source and drain of transistor 102. One of the source and drain of transistor 102 is electrically connected to one electrode of capacitor 105. The other electrode of capacitor 105 is electrically connected to one of the source and drain of transistor 103.

[0080] Here, the wiring connected to one of the source and drain of transistor 101, one electrode of capacitor 104, and circuit block 110 is referred to as node NM. In addition, the component of circuit block 110 connected to node NM can make node NM in a floating state. In addition, the wiring connected to the other electrode of capacitor 104, one of the source and drain of transistor 102, and one electrode of capacitor 105 is referred to as node NB. In addition, the wiring connected to one of the source and drain of transistor 103 and the other electrode of capacitor 105 is referred to as node NA.

[0081] The gate of transistor 101 is electrically connected to wiring 121. The gate of transistor 102 is electrically connected to wiring 122. The gate of transistor 103 is electrically connected to wiring 123. The other one of the source and drain of transistor 101 is electrically connected to wiring 124. The other one of the source and drain of transistor 102 is electrically connected to wiring 125. The other one of the source and drain of transistor 103 is electrically connected to wiring 126.

[0082] Wirings 121, 122, and 123 may function as signal lines for controlling the operation of the transistors. Wiring 124 may function as a signal line for supplying first data. Wiring 125 may function as a signal line for supplying second data. Wiring 126 may function as a signal line for supplying third data.

[0083] Nodes NM, NB, and NA may be used as storage nodes. By turning on transistor 101, the first data supplied to wiring 124 can be written into node NM. By turning off transistor 101, the data can be held in node NM. In addition, by turning on transistor 102, the second data supplied to wiring 125 can be written into node NB. By turning off transistor 102, the data can be held in node NB. In addition, by turning on transistor 103, the third data supplied to wiring 126 can be written into node NA. By turning off transistor 103, the data can be held in node NA.

[0084] By using transistors with an extremely low off-state current as transistors 101, 102, and 103, the potentials of nodes NM and NB can be held for a long time. As such a transistor, for example, a transistor using a metal oxide for the channel formation region (hereinafter referred to as an OS transistor) can be used.

[0085] OS transistors can be used for other transistors included in the pixel. The transistors included in the pixel may also use transistors with Si in the channel formation region (hereinafter referred to as Si transistors), or both OS transistors and Si transistors may be used. As the above Si transistors, transistors containing amorphous silicon, transistors containing crystalline silicon (typically low-temperature polycrystalline silicon, single-crystalline silicon), etc. can be cited.

[0086] As a semiconductor material for the OS transistor, a metal oxide with a bandgap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an indium-containing oxide semiconductor, etc. can be used. For example, CAAC-OS or CAC-OS mentioned later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. CAC-OS exhibits high mobility characteristics and is suitable for transistors for high-speed driving.

[0087] The OS transistor has a large energy gap and exhibits extremely low off-state current characteristics. Different from Si transistors, the OS transistor does not suffer from impact ionization, avalanche breakdown, short-channel effect, etc., and thus can form a highly reliable circuit.

[0088] As the semiconductor layer in the OS transistor, for example, a film represented by "In-M-Zn-based oxide" containing indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be used.

[0089] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn-based oxide, it is preferable that the atomic number ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. The atomic number ratio of the metal elements in such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic number ratio of the formed semiconductor layer may vary within the range of ±40% of the atomic number ratio of the metal elements in the above sputtering target.

[0090] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, as the semiconductor layer, an oxide semiconductor with a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, further preferably 1×10 11 / cm 3 or less, even more preferably less than 1×10 10 / cm 3 ,1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The defect energy level density of this oxide semiconductor is low, so it can be said that it is an oxide semiconductor with stable characteristics.

[0091] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistors. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic number ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the required semiconductor characteristics of the transistor.

[0092] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen defects increase, and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Hereinafter, it is preferably 2×10 17 atoms / cm 3 Hereinafter.

[0093] In addition, sometimes when alkali metals and alkaline earth metals bond with the oxide semiconductor, carriers are generated, increasing the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Hereinafter, it is preferably 2×10 16 atoms / cm 3 Hereinafter.

[0094] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons serving as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor having an oxide semiconductor containing nitrogen easily becomes a normally-on characteristic. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 Hereinafter.

[0095] In addition, the semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals with c-axis orientation, polycrystalline structure, microcrystalline structure, or amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest defect state density, while CAAC-OS has the lowest defect state density.

[0096] The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not have a crystalline component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and does not have a crystalline part.

[0097] In addition, the semiconductor layer may also be a hybrid film of two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region of CAAC-OS, and a region having a single crystal structure. The hybrid film sometimes has, for example, a single-layer structure or a stacked structure including two or more of the above regions.

[0098] Hereinafter, the structure of CAC (Cloud-Aligned Composite)-OS in one mode of the non-single crystal semiconductor layer will be described.

[0099] CAC-OS refers to, for example, a structure in which elements contained in an oxide semiconductor are unevenly distributed, and the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size is also referred to as a mosaic or patch state.

[0100] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to this, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.

[0101] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, in particular, In-Ga-Zn oxide may be referred to as CAC-IGZO) refers to a state in which the material is divided into indium oxide (hereinafter, referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter, referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter, referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0)) etc. to become a mosaic state, and the mosaic-like InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film (hereinafter, also referred to as a cloud state).

[0102] In other words, CAC-OS has a structure with GaO X3The region with [main component] and In X2 Zn Y2 O Z2 or InO X1 The composite oxide semiconductor is composed of regions mixed together. In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region.

[0103] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO 3 (ZnO) m1 (where m1 is a natural number) or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≤ x0 ≤ 1, and m0 is an arbitrary number) represents a crystalline compound.

[0104] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the a-b plane.

[0105] On the other hand, CAC-OS is related to the material composition of the oxide semiconductor. CAC-OS refers to the following composition: in a material composition containing In, Ga, Zn, and O, nanoparticle-like regions with Ga as the main component are observed in some parts and nanoparticle-like regions with In as the main component are observed in some parts, and they are dispersed irregularly in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0106] CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure composed of two layers of a film with In as the main component and a film with Ga as the main component.

[0107] Note that sometimes no clear boundary can be observed between the region with [main component] and the region with In X3 Zn X2 O Y2 O Z2 or InO X1 as the main component.

[0108] When one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are included in CAC-OS to replace gallium, CAC-OS refers to the following structure: nanoparticle-like regions mainly composed of the metal element are observed in a part, and nanoparticle-like regions mainly composed of In are observed in a part, and they are randomly dispersed in a mosaic pattern.

[0109] CAC-OS can be formed, for example, by sputtering under the condition of not intentionally heating the substrate. When forming CAC-OS by sputtering, as the film-forming gas, one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used. In addition, the lower the flow ratio of oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow ratio of oxygen gas is set to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0110] CAC-OS has the following characteristics: when measured by θ / 2θ scanning using the out-of-plane method, one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods, no distinct peak is observed. That is, according to X-ray diffraction, it can be known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0111] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nano-beam), a bright annular region and multiple bright spots within the annular region are observed. Thus, according to the electron diffraction pattern, it can be known that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-section direction.

[0112] In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis image (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that: there are regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 which are unevenly distributed and mixed.

[0113] The structure of CAC-OS is different from that of the IGZO compound in which the metal elements are evenly distributed, and it has properties different from those of the IGZO compound. In other words, CAC-OS has GaO X3Regions mainly composed of etc. and In X2 Zn Y2 O Z2 or InO X1 The regions mainly composed of are separated from each other, and the regions mainly composed of each element are in a mosaic structure.

[0114] Here, for In X2 Zn Y2 O Z2 or InO X1 The conductivity of the region mainly composed of is higher than that of the region mainly composed of GaO X3 etc. In other words, when carriers flow through the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 it exhibits the conductivity of an oxide semiconductor. Therefore, when the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is distributed in the oxide semiconductor in a cloud-like manner, a high field-effect mobility (μ) can be achieved.

[0115] On the other hand, the insulation of the region mainly composed of GaO X3 etc. is higher than that of the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 In other words, when the region mainly composed of GaO X3 etc. is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0116] Therefore, when CAC-OS is used for semiconductor elements, through the complementary action due to the insulation of GaO X3 etc. and the conductivity of In X2 Zn Y2 O Z2 or InO X1 a high on-state current (I on ) and a high field-effect mobility (μ) can be achieved.

[0117] In addition, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0118] Refer to Figure 2A , Figure 2B and Figure 2CThe timing chart shown illustrates an example of the operation of pixel 10 that adds the second data and the third data to the first data. Note that in the following description, a high potential is represented by "H" and a low potential is represented by "L". In addition, the first data is "V data1 ", the second data is "V data2 ", and the third data is "V data3 ". In addition, one of the reference potentials (e.g., 0V, GND potential, or a specific potential) is "V ref ". Additionally, the first to third data can also be negative values, which also correspond to subtraction of data.

[0119] First, refer to Figure 2A to illustrate the operation of writing the first data "V data1 " to node NM. Note that the ideal operation is described here, without considering detailed variations in the circuit structure, operating timing, etc. due to potential distribution, coupling, or loss. The potential change caused by capacitive coupling depends on the capacitance ratio between the supply side and the supplied side. However, for ease of explanation, it is assumed that the capacitance values of nodes NB and NM are sufficiently small.

[0120] At time T1, make the potential of wiring 121 "H", make the potential of wiring 122 "H", make the potential of wiring 124 "V data1 ", and make the potential of wiring 125 "V ref ", whereby transistor 102 is turned on and the potential of node NB becomes "V ref ". This operation is a reset operation for subsequent capacitive coupling operations.

[0121] Transistor 101 is turned on, and the potential of wiring 124 (the first data "V data1 ") is written to node NM.

[0122] At time T2, make the potential of wiring 121 "L" and make the potential of wiring 122 "L", whereby transistors 101 and 102 are turned off, and the first data "V data1 " is held in node NM. In addition, "V data1 - V ref " is held in capacitor 104.

[0123] Up to here is the writing operation of the first data "V data1 ". In addition, when the first data is not reflected in the display, a potential identical to "V data1 " can be supplied as the first data "V ref ".

[0124] Next, refer to Figure 2B to illustrate the operation of writing the second data "V data2 " to node NB.

[0125] At time T11, set the potential of wiring 122 to "H", set the potential of wiring 123 to "H", and set the potential of wiring 125 to "V data2 ", and set the potential of wiring 126 to "V ref ", whereby transistor 103 is turned on and the potential of node NA becomes "V ref ". This operation is a reset operation for subsequent capacitive coupling operations.

[0126] In addition, transistor 102 is turned on, and the potential of wiring 125 (second data "V data2 ") is written to node NB.

[0127] At this time, the potential of node NB is added to the potential of node NM by the capacitive coupling of capacitor 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 ", and when "V ref " = 0, the potential of node NM is "V data1 +V data2 ".

[0128] At time T12, set the potential of wiring 122 to "L" and the potential of wiring 123 to "L", whereby transistor 102 is turned off, and the second data "V data2 " is held in node NB. In addition, the sum of the first data and the second data, "V data1 +V data2 ", is held in node NM. Also, "V data2 -V ref " is held in capacitor 105.

[0129] Up to here is the writing operation of the second data "V data2 ". In addition, when the second data is not reflected in the display, a potential the same as "V data2 " can be supplied as the second data "V ref ".

[0130] Next, refer to Figure 2C to describe the operation of writing the third data "V data3 ".

[0131] At time T21, set the potential of wiring 123 to "H" and the potential of wiring 126 to "V data3 ", transistor 103 is turned on, and the potential of node NA becomes "V data3 ".

[0132] At this time, the potential of node NA is added to the potential of node NB by the capacitive coupling of capacitor 105. Therefore, the potential of node NB is "Vdata2 -V ref +V data3 ”, at “V ref ” = 0, the potential of node NB is “V data2 +V data3 ”.

[0133] In addition, the potential of node NB is added to the potential of node NM by the capacitive coupling of capacitor 104. Therefore, the potential of node NM is “V data1 +V data2 +V data3 ”.

[0134] At time T22, the potential of wiring 123 is made “L”, whereby transistor 103 is turned off and the potential of node NM is maintained at “V data1 +V data2 +V data3 ”.

[0135] As described above, the writing operation of the first data “V data1 ” to the third data “V data3 ” is completed. In addition, when the third data is not reflected in the display, the same potential as “V data3 ” can be supplied as the third data “V ref ”. Alternatively, the writing operation of the third data can be omitted.

[0136] Then, in the display element included in circuit block 110, a display operation corresponding to the potential of node NM is performed. In addition, depending on the structure of the circuit block, the display operation may be performed from time T1 or time T11.

[0137] As Figure 3A , Figure 3B , Figure 3C shown, it is also possible to interchange Figure 2A the operations shown and Figure 2B the operation order shown.

[0138] Refer to Figure 3A to describe the operation of writing the first data “V data2 ” to node NB.

[0139] At time T1, the potential of wiring 122 is made “H”, the potential of wiring 123 is made “H”, the potential of wiring 125 is made “V data2 ”, the potential of wiring 126 is made “V ref ”, whereby transistor 103 is turned on and the potential of node NA becomes “V ref ”. In addition, transistor 102 is turned on and the potential of wiring 125 (the second data “V data2 ”) is written to node NB.

[0140] At time T2, the potential of wiring 122 is set to "L", the potential of wiring 123 is set to "L", transistors 102 and 103 are turned off, and the second data "V" is held at node NB. data2 In addition, "V" is held in capacitor 105. data2 -V ref ".

[0141] Next, refer to Figure 3B the operation of writing the first data "V" to node NM. data1 ".

[0142] At time T11, the potential of wiring 121 is set to "H", the potential of wiring 122 is set to "H", the potential of wiring 124 is set to "V", data1 ", the potential of wiring 125 is set to "V", ref ", whereby transistor 102 is turned on and the potential of node NB becomes "V". ref ". In addition, transistor 101 is turned on, and the potential of wiring 124 (the first data "V") is written to node MN. data1 ".

[0143] At time T12, the potential of wiring 121 is set to "L", the potential of wiring 122 is set to "L", whereby transistor 102 is turned off and "V" is held at node NB. ref ". In addition, the first data "V" is held at node NM. Also, since "V" is held in capacitor 105, data1 ", when "V" = 0, the potential of node NA is "-V". data2 -V ref ", so when "V" ref " = 0, the potential of node NA is "-V". data1 ".

[0144] Next, refer to Figure 3C the operation of writing the third data "V". data3 ".

[0145] At time T21, the potential of wiring 123 is set to "H", the potential of wiring 126 is set to "V", data3 ", transistor 103 is turned on, and the potential of node NA becomes "V". data3 ".

[0146] At this time, due to the capacitive coupling of capacitor 105, the potential of node NA is added to the potential of node NB. Therefore, the potential of node NB is "V", data3 -(-V data2 ) + V ref ", and when "V" ref " = 0, the potential of node NB is "V". data2 +V data3”。

[0147] In addition, the potential of node NB is added to the potential of node NM by the capacitive coupling of capacitor 104. Therefore, the potential of node NM is "V data1 +V data2 +V data3 ”。

[0148] At time T22, the potential of wiring 123 is made "L", whereby transistor 103 is turned off, and the potential of node NM is maintained at "V data1 +V data2 +V data3 ”。

[0149] As described above, the writing operations of the first data "V data1 " to the third data "V data3 " are completed.

[0150] Figure 2A 、 Figure 2B 、 Figure 2C 's operations can be continuously performed within one horizontal period. Alternatively, the operation of Figure 2A can be performed in the k-th frame (k is a natural number), and the operations of Figure 2B 、 Figure 2C can be performed in the (k + 1)-th frame. Alternatively, the operations of Figure 2A 、 Figure 2B can be performed in the k-th frame, and the operation of Figure 2C can be performed in the (k + 1)-th frame. Alternatively, the operations of Figure 2A 、 Figure 2B 、 Figure 2C can be performed in consecutive different frames respectively. Alternatively, the operation of Figure 2A can be performed in the k-th frame, and the operations of Figure 2B 、 Figure 2C can be repeatedly performed after the (k + 1)-th frame. Alternatively, the operations of Figure 2A 、 Figure 2B can be performed in the k-th frame, and the operation of Figure 2C can be repeatedly performed after the (k + 1)-th frame. In addition, regarding Figure 3A 、 Figure 3B 、 Figure 3C 's operations can also be performed in the same way. In addition, the above operations can be applied to pixels of other structures in this embodiment.

[0151] Pixels that can be used in a display device according to one aspect of the present invention may also have the structure of pixel 11 shown in Figure 4A . In pixel 11, the other of the source and drain of transistor 103 is electrically connected to wiring 124. Therefore, wiring 126 can be omitted. Other structures are the same as those of pixel 10.

[0152] Reference Figure 4B , Figure 4C , Figure 4D The timing chart shown in FIG. 6 illustrates an example of the operation of pixel 11 that adds the second data and the third data to the first data. Since Figure 4B the method of writing the first data shown in FIG. 7 is substantially the same as that of pixel 10, its description is omitted here.

[0153] Reference Figure 4C to illustrate the operation of writing the second data "V data2 " to node NB.

[0154] At time T11, the potential of wiring 122 is set to "H", the potential of wiring 123 is set to "H", the potential of wiring 124 is set to "V ref ", and the potential of wiring 125 is set to "V data2 ". As a result, transistor 103 is turned on, and the potential of node NA becomes "V ref ". This operation is a reset operation for performing subsequent capacitive coupling operations.

[0155] In addition, transistor 102 is turned on, and the potential of wiring 125 (the second data "V data2 ") is written to node NB.

[0156] At this time, the potential of node NB is added to the potential of node NM by capacitive coupling of capacitor 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 ", and when "V ref " = 0, the potential of node NM is "V data1 +V data2 ".

[0157] At time T12, the potential of wiring 122 is set to "L", and the potential of wiring 123 is set to "L". As a result, transistor 102 is turned off, and the second data "V data2 " is held in node NB. In addition, the sum of the first data and the second data, "V data1 +V data2 ", is held in node NM. Also, "V data2 -V ref " is held in capacitor 105.

[0158] This concludes the operation of writing the second data "V data2 ". In addition, when the second data is not reflected in the display, a potential identical to "V data2 " may be supplied as the second data "V ref ".

[0159] Next, reference Figure 4DDescribe the operation of writing the third data "V data3 ".

[0160] At time T21, set the potential of wiring 123 to "H" and the potential of wiring 124 to "V data3 ". As a result, transistor 103 turns on and the potential of node NA becomes "V data3 ".

[0161] At this time, due to the capacitive coupling of capacitor 105, the potential of the other electrode of capacitor 105 is added to the potential of node NB. Therefore, the potential of node NB is "V data2 -V ref +V data3 ". When "V ref " = 0, the potential of node NB is "V data2 +V data3 ".

[0162] In addition, due to the capacitive coupling of capacitor 104, the potential of node NB is added to the potential of node NM. Therefore, the potential of node NM is "V data1 +V data2 +V data3 ".

[0163] At time T22, set the potential of wiring 123 to "L". As a result, transistor 103 turns off and the potential of node NM remains "V data1 +V data2 +V data3 ".

[0164] As described above, the writing operations of the first data "V data1 " to the third data "V data3 " are completed. In addition, when not reflecting the third data on the display, supply the same potential as "V data3 " for the third data "V ref ". Alternatively, the writing operation of the third data can be omitted.

[0165] Then, in the display element included in circuit block 110, perform the display operation corresponding to the potential of node NM. In addition, depending on the structure of the circuit block, the display operation may start from time T1 or time T11.

[0166] As described above, since the first data and the third data can be supplied from wiring 124, the number of wirings can be reduced. In addition, although not described here, the equivalent operation can also be performed in pixel 11. Figures 3A to 3C operation.

[0167] The pixel of the display device that can be used in one embodiment of the present invention may also have Figure 5AThe structure of pixel 12 shown. Pixel 12 has a structure with transistors 106 and 107 added to the structure of pixel 10. In addition, wirings 125 and 126 required for pixel 10 can be omitted. Other structures are the same as those of pixel 10.

[0168] In pixel 12, the other one of the source and drain of transistor 102 is electrically connected to wiring 124. In addition, the other one of the source and drain of transistor 103 is electrically connected to wiring 124.

[0169] The other electrode of capacitor 104 is electrically connected to one of the source and drain of transistor 106. The other electrode of capacitor 105 is electrically connected to one of the source and drain of transistor 107. The gate of transistor 106 is electrically connected to wiring 121. The gate of transistor 107 is electrically connected to wiring 122.

[0170] The other one of the source and drain of transistor 106 is electrically connected to a wiring capable of supplying the reference potential "V ref ". The other one of the source and drain of transistor 107 is electrically connected to a wiring capable of supplying the reference potential "V ref ". As the wiring capable of supplying "V ref ", for example, a power supply line or the like electrically connected to the components of circuit block 110 can be used.

[0171] In order to perform capacitive coupling operation efficiently, for example, it is preferable that the potential of the electrode opposite to the electrode on the data side of the writing capacitor is "V ref ", much smaller than this data.

[0172] In pixel 10, data and "V ref " are supplied from the same wiring, while in pixel 12, "V ref " is supplied from a power supply line or the like, so the first data to the third data can be supplied from one wiring (wiring 124). Therefore, the number of wirings can be further reduced, and thus wirings 125 and 126 can be omitted.

[0173] Refer to Figure 5B 、 Figure 5C 、 Figure 5D The timing chart shown illustrates an example of the operation of pixel 12 to which the second data and the third data are added to the first data.

[0174] First, refer to Figure 5B to explain the operation of writing the first data "V data1 " to node NM.

[0175] At time T1, the potential of wiring 121 is made "H", and the potential of wiring 124 is made "V data1", thereby turning on transistor 106, and the potential of node NB becomes "V ref ". This operation is a reset operation for subsequent capacitive coupling operations.

[0176] Transistor 101 is turned on, and the potential of write line 124 to node NM (first data "V data1 ") is written.

[0177] At time T2, the potential of line 121 is made "L", thereby turning off transistor 101 and transistor 106, and the first data "V data1 " is held in node NM. In addition, "V data1 -V ref " is held in capacitor 104.

[0178] Up to here is the write operation of the first data "V data1 ". In addition, when the first data is not reflected in the display, a potential the same as "V data1 " is supplied as the first data "V ref ".

[0179] Next, refer to Figure 5C to describe the operation of writing the second data "V data2 " to node NB.

[0180] At time T11, the potential of line 122 is made "H", the potential of line 123 is made "H", the potential of line 125 is made "V data2 ", and the potential of line 126 is made "V ref ", thereby turning on transistor 103, and the potential of node NA becomes "V ref ". This operation is a reset operation for subsequent capacitive coupling operations.

[0181] In addition, transistor 102 is turned on, and the potential of write line 125 to node NB (second data "V data2 ") is written.

[0182] At this time, the potential of node NB is added to the potential of node NM by capacitive coupling of capacitor 104. Therefore, the potential of node NM is "V data1 -V ref +V data2 ", and when "V ref " = 0, the potential of node NM is "V data1 +V data2 ".

[0183] At time T12, the potential of line 122 is made "L", the potential of line 123 is made "L", thereby turning off transistor 102, and the second data "V data2”. In addition, “V” that holds the sum of the first data and the second data is maintained in the node NM data1 +V data2 ”. Additionally, “V” is maintained in the capacitor 105 data2 -V ref ”.

[0184] Up to here is the writing operation of the second data “V data2 ”. In addition, when the second data is not reflected in the display, the same potential as “V data2 ” can be supplied as the second data “V ref ”.

[0185] Next, refer to Figure 5D to illustrate the operation of writing the third data “V data3 ”.

[0186] At time T21, the potential of the wiring 123 is set to “H”, the potential of the wiring 126 is set to “V data3 ”, the transistor 103 is turned on, and the potential of the node NA becomes “V data3 ”.

[0187] At this time, due to the capacitive coupling of the capacitor 105, the potential of the other electrode of the capacitor 105 is added to the potential of the node NB. Therefore, the potential of the node NB is “V data2 -V ref +V data3 ”, and when “V ref ” = 0, the potential of the node NB is “V data2 +V data3 ”.

[0188] In addition, due to the capacitive coupling of the capacitor 104, the potential of the node NB is added to the potential of the node NM. Therefore, the potential of the node NM is “V data1 +V data2 +V data3 ”.

[0189] At time T22, the potential of the wiring 123 is set to “L”, whereby the transistor 103 is turned off, and the potential of the node NM is maintained at “V data1 +V data2 +V data3 ”.

[0190] As described above, the writing operations of the first data “V data1 ” to the third data “V data3 ” are completed. In addition, when the third data is not reflected in the display, the same potential as “V data3 ” can be supplied as the third data “V ref ”. Alternatively, the writing operation of the third data can be omitted.

[0191] Then, among the display elements included in the circuit block 110, display work corresponding to the potential of the node NM is performed. In addition, depending on the structure of the circuit block, the display work may sometimes be performed starting from time T1 or time T11. In addition, although not described here, equivalent work may also be performed in the pixel 13. Figures 3A to 3C work.

[0192] In pixels 10, 11, and 12, an example of a structure in which two capacitors are connected in series is shown. As Figure 6 shown, more capacitors C 1 to C n connected in series may also be used. At this time, while adding one capacitor, one transistor is also added. One of the source and drain of this transistor is electrically connected to the wiring connecting one capacitor to another capacitor. That is, a node such as node NB is added.

[0193] The number n of capacitors connected in series is preferably 2 to 8, more preferably 2 to 6, and further preferably 2 to 4. The more the number of capacitors, the higher the effect of one aspect of the present invention. Note that since adding transistors and signal lines is required as the number of capacitors increases, problems such as a decrease in the aperture ratio and resolution of the pixel and an inability to ensure the signal input time may sometimes occur. Therefore, it is preferable to set the number n of capacitors connected in series within the above range according to the application.

[0194] Figures 7A to 7C is an example of a structure that can be applied to the circuit block 110 and includes an EL element as a display element.

[0195] Figure 7A The structure shown includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain of the transistor 111 is electrically connected to one electrode of the EL element 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to the node NM.

[0196] The other of the source and drain of the transistor 111 is electrically connected to the wiring 128. The other electrode of the EL element 114 is electrically connected to the wiring 129. The wirings 128 and 129 have the function of supplying power. For example, the wiring 128 can supply a high-potential power supply. In addition, the wiring 129 can supply a low-potential power supply.

[0197] In Figure 7A the structure shown, when the potential of the node NM becomes equal to or higher than the threshold voltage of the transistor 111, current flows through the EL element 114. As a result, sometimes in Figure 2A , Figure 3A , Figure 4A orFigure 5B The light emission of the EL element 114 starts at the stage of the time T1 in the shown timing chart, so the use of this structure may be limited.

[0198] Figure 7B is the structure in which a transistor 112 is added to the Figure 4A structure. One of the source and drain of the transistor 112 is electrically connected to one of the source and drain of the transistor 111. The other of the source and drain of the transistor 112 is electrically connected to the EL element 114. The gate of the transistor 112 is electrically connected to the wiring 127. The wiring 127 can function as a signal line for controlling the conduction of the transistor 112.

[0199] In this structure, when the potential at the node NM is above the threshold voltage of the transistor 111 and the transistor 112 is conducting, current flows through the EL element 114. Therefore, it is possible to Figure 2C , Figure 3C , Figure 4D or Figure 5D start the light emission of the EL element 114 after the time T22 in the shown timing chart, so this structure is suitable for the operation accompanied by correction.

[0200] Figure 7C is the structure in which a transistor 115 is added to the Figure 7B structure. One of the source and drain of the transistor 115 is electrically connected to one of the source and drain of the transistor 111. The other of the source and drain of the transistor 115 is electrically connected to the wiring 130. The gate of the transistor 115 is electrically connected to the wiring 131. The wiring 131 can function as a signal line for controlling the conduction of the transistor 115. In addition, the gate of the transistor 115 can also be electrically connected to the wiring 123.

[0201] The wiring 130 can be electrically connected to a supply source of a specific potential such as a reference potential. By supplying a specific potential to one of the source and drain of the transistor 111 from the wiring 130, it is also possible to stabilize the writing of image data.

[0202] In addition, the wiring 130 can be connected to the circuit 120 and can function as a monitoring line. The circuit 120 can have one or more of the functions of supplying the above-mentioned specific potential, obtaining the electrical characteristics of the transistor 111, and generating correction data.

[0203] When the wiring 130 is used as a monitoring line, for example, the circuit 120 generates a potential for correcting the threshold voltage of the transistor 111 as the first data written to the node NM.

[0204] Here, Figure 5A the transistors 106 and 107 shown for supplying "V ref " are as Figure 7DAs shown, it can be electrically connected to the wiring 128. Since "V ref " is preferably 0V, GND, or a low potential, the wiring 128 also has the function of supplying at least any one of these potentials. For the wiring 128, "V ref " is supplied at the timing of writing data to the node NM or the node NB, and a high-potential power supply is supplied at the timing of causing the EL element 114 to emit light.

[0205] Figures 8A to 8C is an example of a structure that can be applied to the circuit block 110 and includes a liquid crystal element as a display element.

[0206] Figure 8A The structure shown includes a capacitor 116 and a liquid crystal element 117. One electrode of the liquid crystal element 117 is electrically connected to one electrode of the capacitor 116. One electrode of the capacitor 116 is electrically connected to the node NM.

[0207] The other electrode of the capacitor 116 is electrically connected to the wiring 132. The other electrode of the liquid crystal element 117 is electrically connected to the wiring 133. The wirings 132 and 133 have the function of supplying power. For example, the wirings 132 and 133 can supply a reference potential such as GND and 0V or an arbitrary potential.

[0208] In this structure, the operation of the liquid crystal element 117 starts when the potential of the node NM becomes equal to or higher than the operating threshold of the liquid crystal element 117. Thus, sometimes Figure 2A , Figure 3A , Figure 4B or Figure 5B The display operation starts at the stage of the moment T1 in the timing chart shown, so the use of this structure may be limited. Note that in the case of a transmissive liquid crystal display device, by also performing operations such as turning off the backlight until Figure 2C , Figure 3C , Figure 4D or Figure 5D The moment T22 shown, the unwanted display operation can be suppressed from being seen.

[0209] Figure 8B is a structure in which a transistor 118 is added to the Figure 8A structure. One of the source and drain of the transistor 118 is electrically connected to one electrode of the capacitor 116. The other of the source and drain of the transistor 118 is electrically connected to the node NM. The gate of the transistor 118 is electrically connected to the wiring 127. The wiring 127 can have the function of a signal line for controlling the conduction of the transistor 118.

[0210] In this structure, the potential of the node NM is applied to the liquid crystal element 117 while the transistor 118 is conducting. Thus, it is possible to Figure 2C , Figure 3C ,Figure 4D or Figure 5D Start the operation of the liquid crystal element after the time T22 in the timing chart shown, so that this structure is suitable for the operation accompanied by correction.

[0211] In addition, since the potentials supplied to the capacitor 116 and the liquid crystal element 117 are continuously maintained while the transistor 118 is in the non-conductive state, it is preferable to reset the potentials supplied to the capacitor 116 and the liquid crystal element 117 before rewriting the image data. In this reset, for example, a reset potential is supplied to the wiring 123, and at the same time, the transistors 102 and 118 are turned on.

[0212] Figure 8C is a structure in which a transistor 119 is added to the Figure 8B structure. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and drain of the transistor 119 is electrically connected to the wiring 130. The gate of the transistor 115 is electrically connected to the wiring 131. The wiring 131 can function as a signal line for controlling the conduction of the transistor 119. In addition, the gate of the transistor 119 can also be electrically connected to the wiring 123.

[0213] The circuit 120 electrically connected to the wiring 130, similar to the description in the above Figure 7C , can also have the function of resetting the potentials supplied to the capacitor 116 and the liquid crystal element 117.

[0214] Here, Figure 5A The transistors 106 and 107 shown for supplying "V ref " can be electrically connected to the wiring 132 as Figure 8D shown.

[0215] In addition, although Figure 7D , Figure 8D shows an example of supplying "V ref " from the power supply line, it can also be supplied from the scan line "V ref ". For example, as Figure 9A shown, it can also be supplied from the wiring 121 or the wiring 123, etc. "V ref ". For example, as Figure 2A shown, since when writing data to the node NM (when the transistor 101 is turned on), the wiring 123 is supplied with a potential equivalent to "L", this potential can be used as "V ref ". For example, as Figure 2B shown, since when writing data to the node NB (when the transistor 102 is turned on), the wiring 121 is supplied with a potential equivalent to "L", this potential can be used as "V ref ".

[0216] In addition, as Figure 9B , Figure 9C shown, the transistors 101, 102, and 103 may also adopt a structure provided with a back gate. Figure 9B A structure showing the back gate electrically connected to the front gate is shown, and this structure has the effect of increasing the on-state current. Figure 9C A structure showing the back gate electrically connected to the wiring 134 capable of supplying a constant potential is shown, and this structure can control the threshold voltage of the transistor. In addition, the structures shown in Figure 9B and Figure 9C can be appropriately combined. In addition, a back gate can also be provided for the transistors included in the circuit block 110 shown in Figures 7A to 7C and Figures 8A to 8C .

[0217] Next, with reference to Figure 10A the correction operation of the image data will be described.

[0218] Figure 10A An example of the data potentials input to four pixels (P1 to P4) in the horizontal and vertical directions is shown, which are the first data (+A1, +A2, -A1, A0), the second data (+B1, B0, B0, -B1), the third data (+C3, C2, C2, +C1), and the generated image data. In the display element, display can be performed according to the sum of the first to third data, and the original image can be corrected.

[0219] For example, the first data and the second data can be data for correction. In addition, the third data can be the original image data.

[0220] Such a combination of correction data and image data can perform any one of upconversion, HDR display, correction of display unevenness inherent in the display device, and correction of the threshold voltage of the transistors included in the pixels. Or, these can be combined to perform.

[0221] In the upconversion operation, for example, the same image data is supplied to all four pixels. Through correction, each pixel can display a different image. For example, image data applicable to a specific one pixel of a display device having a pixel count of 4K×2K can be input to specific four pixels of a display device having a pixel count of 8K×4K, thereby performing a display with increased resolution.

[0222] By using the same image data as the first to third data, the brightness of the displayed image can be greatly increased. In this operation, since a voltage above the maximum output value of the column driver can be supplied to the pixel circuit, not only the image quality is improved, but also product costs such as power consumption can be reduced or a cheap driving IC chip can be used.

[0223] In a broad sense, it is the correction of image data, and different images can be overlapped for display. Figure 10B Shows an image of the entire display unit, showing a first image composed of first data, a second image composed of second data, a third image composed of third data, and an image synthesized from the first image, second image, and third image.

[0224] The combination of such different image data can be applied to, for example, text insertion or AR (Augmented Reality) display.

[0225] Among the pixels 10, 11, and 12 described above, they can be arranged in a matrix with the structures described for each as the constituent elements of one pixel to form a pixel matrix. In addition, as another method, sharing a part of the transistors between pixels can endow other functions. By sharing transistors, the number of wirings can be reduced, the aperture ratio of the pixels can be increased, the resolution can be improved, and the power consumption can be reduced due to the efficiency improvement of the charging and discharging of the signal lines or the driving operation.

[0226] Figure 11 FIG. shows a part (16 pixels) of a pixel matrix including pixel 13 having the basic structure of pixel 10. Transistor 101, capacitor 104, and circuit block 110 are provided in pixel 13. Note that n and m in the parentheses attached to the symbols represent specific rows, and i, j, and k represent specific columns (n, m, i, j, and k are natural numbers).

[0227] Transistor 102 connected to four pixels 13 is provided in the pixel matrix. In addition, capacitor 105 connected to four pixels 13 is provided. In addition, transistor 103 connected to four capacitors 105 is provided.

[0228] In addition, when assuming the basic structure of pixel 10, transistor 102 and capacitor 105 are the constituent elements of each pixel 13, and it can also be said that transistor 102 and capacitor 105 are shared among four pixels. In addition, transistor 103 is the constituent element of each pixel 13, and it can also be said that transistor 103 is shared among sixteen pixels.

[0229] In this pixel matrix, several identical operations can be performed using a structure with fewer wiring numbers and transistor numbers than the structure in which pixel 10 is simply arranged in a matrix.

[0230] In the case where the resolution of the display device and the image data is different, appropriate display can also be performed without up-conversion or down-conversion by switching the input paths of the image data and the correction data. In addition, it can operate basically according to Figures 2A to 2C or Figures 3A to 3C the timing chart shown.

[0231] An example of displaying image data with different resolutions when the number of pixels in the pixel matrix corresponds to 8K×4K is described below. Note that the display operations for other pixel matrices described later can be performed in the same manner.

[0232] First, the case of displaying using image data with 8K×4K resolution is described. When displaying using image data with 8K×4K resolution, the image data can be written as first data to the node NM of each pixel through the transistor 101. At this time, by supplying second data through the transistor 102, the second data can be applied to the node NM of four pixels that commonly use the transistor 102. In addition, by supplying third data through the transistor 103, the third data can be applied to the node NM of sixteen pixels that commonly use the transistor 103. That is, the second data and the third data can be used for image correction or overlay.

[0233] Next, the case of displaying image data with 4K×2K resolution is described. When displaying using 4K×2K image data, the image data can be written as second data to the node NB of each pixel. Since the second data is supplied to four pixels, it is possible to perform display without generating new image data even when using a pixel matrix with 8K×4K resolution.

[0234] At this time, by supplying first data to the node NM of each pixel through the transistor 101, different displays can be performed in each pixel. In this operation, for example, upscaling from 4K×2K resolution to 8K×4K resolution can be performed. In addition, by supplying third data through the transistor 103, the third data can be applied to the node NM of sixteen pixels that commonly use the transistor 103. That is, the first data and the third data can be used for image correction or overlay.

[0235] Next, the case of displaying using image data with FullHD resolution is described. When displaying using FullHD image data, the image data can be written as third data to each pixel through the transistor 103. Since the third data is supplied to sixteen pixels, it is possible to perform display without generating new image data even when using a pixel matrix with 8K×4K resolution.

[0236] At this time, by supplying first data to the node NM of each pixel through the transistor 101, different displays can be performed in each pixel. In this operation, upscaling from FullHD resolution to 8K×4K resolution can be performed. In addition, by supplying second data through the transistor 102, the second data can be applied to the node NM of four pixels that commonly use the transistor 102. That is, the first data and the second data can be used for image correction or overlay.

[0237] Figure 12 It is a diagram showing a part (sixteen pixels) of a pixel matrix of pixel 14 showing the basic structure including applicable pixel 11. Figure 12 The shown pixel matrix is different from Figure 10A and Figure 10B in that wiring 126 is omitted as a constituent element, and the other of the source and drain of transistor 103 is connected to wiring 124. In addition, an example where the other of the source and drain of transistor 103 is connected to wiring 124[i] is shown, and it may also be connected to wiring 124[i + 1]. Figure 12 The shown pixel matrix can operate according to Figures 4B to 4D the shown timing diagram.

[0238] Figure 13 It is a diagram showing a part (sixteen pixels) of a pixel matrix of pixel 15 showing the basic structure including applicable pixel 12. In pixel 15, transistor 101, capacitor 104, and circuit block 110 are provided in the same way as in pixel 13 and pixel 14. In addition, an example where the other of the source and drain of transistor 103 is connected to wiring 124[i] is shown, and it may also be connected to wiring 124[i + 1]. Figure 13 The shown pixel matrix can operate according to Figures 5B to 5D the shown timing diagram.

[0239] In the pixel matrix, transistor 102 connected to four pixels 15 is provided. In addition, transistor 106 connected to four pixels 15 is provided. In addition, capacitor 105 connected to four pixels 15 is provided. In addition, transistor 107 connected to four capacitors 105 is provided. In addition, transistor 103 connected to four capacitors 105 is provided. Note that the electrical connection state is as described above, and the operation of transistor 106 is based on the operation of two pixels 15 sharing the gate line.

[0240] Note that when assuming the basic structure of pixel 12, transistor 102 and capacitor 105 are constituent elements of each pixel 15, and it can also be said that transistor 102 and capacitor 105 are shared among four pixels. Transistor 106 is a constituent element of each pixel 15, and it can also be said that transistor 106 is shared among two pixels. Transistor 107 is a constituent element of each pixel 15, and it can also be said that transistor 107 is shared among eight pixels. In addition, transistor 103 is a constituent element of each pixel 15, and it can also be said that transistor 103 is shared among sixteen pixels.

[0241] Figure 14A Is applicable Figure 11An example of a block diagram of a display device with a pixel matrix as shown. The display device includes a pixel matrix 19 in which pixels 13 are arranged in a matrix, a row driver 31, a column driver 32, a circuit 33, and a selection circuit 34. In Figure 14A a pixel 13 represents a component that can input data separately through a transistor 101, a pixel block 17 represents a group of four pixels that can input the same data through a transistor 102, and a pixel block 18 represents a group of sixteen pixels that can input the same data through a transistor 103.

[0242] Note that the number of wirings connecting each driver to the pixels is different from the above, and it can also be used in the display device Figure 12 or Figure 13 the pixel matrix as shown.

[0243] The row driver 31 can have a structure combining a shift register 20 and a buffer circuit 21, for example. By controlling the conduction of the buffer circuit 21, data can be output to the wiring 121 or the wiring 122.

[0244] The column driver 32 can have a structure combining a shift register 22 and a buffer circuit 23, for example. By controlling the conduction of the buffer circuit 23, data can be output to the wiring 123. In addition, it can also have a structure combining a selection circuit.

[0245] The circuit 33 has a function of generating correction data. In addition, the circuit 33 can also be said to be an external device for generating correction data. Here, the correction data is data generated based on the main image data and corresponds to any one of the above first to third data.

[0246] The row driver 31 can control the conduction of the transistor 101 and the transistors 102, 103. The column driver 32 can supply the first to third data to the wirings 124, 125, 126.

[0247] The first to third data can be input to the circuit 33. The circuit 33 generates correction data for up-conversion or brightness correction based on the main image data and outputs it as any one of the first to third data.

[0248] In addition to the correction data generated by the circuit 33, the first to third data can also be input to the selection circuit 34, and any one of the first to third data can be output to the column driver 32.

[0249] In addition, the correction data can be generated not only in the circuit 33 but also in the above circuit 120 (refer to Figure 14B)。In addition, grayscale display can also be performed on the display unit, and correction data is generated based on the data read by a luminance meter according to the display brightness or the data of a photograph of the display. In addition, a sensor 24 for detecting the display brightness can be provided, and a circuit 25 capable of detecting deterioration of the display element to generate correction data can be provided (see Figure 14C ).

[0250] The circuit 33 and the circuit 25 may also include a neural network. For example, a deep neural network that has been trained with a large number of images as supervised data can be used to generate highly accurate correction data.

[0251] As Figure 15A shown, the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL all include one or more neurons (units). Note that the intermediate layer HL can be one layer or two or more layers. A neural network including two or more intermediate layers HL can be referred to as a DNN (deep neural network), and learning using a deep neural network can be referred to as deep learning.

[0252] Each neuron in the input layer IL is input with input data, each neuron in the intermediate layer HL is input with the output signals of the neurons in the previous layer or the next layer, and each neuron in the output layer OL is input with the output signals of the neurons in the previous layer. Note that each neuron can be connected (fully connected) to all neurons in the previous layer and the next layer, or can be connected to some neurons.

[0253] Figure 15B An example of the operation using neurons is shown. Here, a neuron N and two neurons in the previous layer that output signals to the neuron N are shown. The neuron N is input with the output x 1 of the neuron in the previous layer and the output x 2 of the neuron in the previous layer. In the neuron N, the multiplication result of the output x 1 and the weight w 1 (x 1 w 1 ) and the multiplication result of the output x 2 and the weight w 2 (x 2 w 2 ) are calculated, and the sum x 1 w 1 + x 2 w 2 is obtained. Then, a bias b is added as needed to obtain the value a = x 1 w 1 + x 2 w 2 + b. The value a is transformed by the activation function h, and the output signal y = h(a) is output from the neuron N.

[0254] Thus, the operation using neurons includes an operation of adding the product of the outputs of the neurons in the previous layer and the weights, that is, the product-sum operation (the above x 1 w 1 + x 2 w 2 ). This product-sum operation can be performed either by a program in software or by hardware. When performing the product-sum operation by hardware, a product-sum operation circuit can be used. As this product-sum operation circuit, either a digital circuit or an analog circuit can be used.

[0255] The product-sum operation circuit can be composed of Si transistors or OS transistors. In particular, since OS transistors have an extremely small off-state current, they are preferably used as the transistors for the analog memory that constitutes the product-sum operation circuit. Note that the product-sum operation circuit can also be composed of both Si transistors and OS transistors.

[0256] Next, the simulation results of applying the circuit block shown in Figure 8A to the structure of the pixel 10 shown in Figure 1 (refer to Figure 16 ) are described. The parameters are as follows. The transistor sizes are all L / W = 4 μm / 4 μm, the capacitance value of the capacitor 104 is 500 fF, the capacitance value of the capacitor 105 is 500 fF, the capacitance value of the capacitor 116 is 100 fF, and the capacitance value of the liquid crystal element 117 is 50 fF. The potentials of the wirings 132 and 133 are 0 V. Assuming that the source driver IC can perform a linear output from -5 V to +5 V, the potential of the node NM is estimated when the same voltage is written to the first data (D1) to the third data (D3). Note that SPICE is used as the circuit simulation software.

[0257] Figure 17A is a timing chart for simulation, corresponding to the operation described in Figures 3A to 3C . The writing order of the data is the second data (D2), the first data (D1), and the third data (D3), and the same value is written to each data.

[0258] Figure 17B are the simulation results. A comparison is made between the structure (Conventional) in which the transistors 102 and 103 and the capacitors 104 and 105 are omitted and only the first data (D1) is input, the structure (MEM_×1) in which the transistor 103 and the capacitor 105 are omitted and the first data (D1) and the second data (D2) can be input, and the structure (MEM_×2) of the present invention.

[0259] It can be confirmed from the simulation results that in the structure (MEM_×2) of the present invention, the potential applied to the pixel electrode can be made sufficiently large, i.e., above the output of the driver IC. In addition, it is confirmed that even if it is negative, the absolute value can be increased. This is useful for reverse driving and driving liquid crystal elements that require high voltage. Similarly, a high potential can be applied to the gate of the driving transistor in the EL element.

[0260] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0261] (Embodiment 2)

[0262] This embodiment describes an example of the structure of a display device using a liquid crystal element and an example of the structure of a display device using an EL element. Note that the constituent elements, operations, and functions of the display device described in Embodiment 1 are omitted in this embodiment.

[0263] Figures 18A to 18C The structure of a display device capable of using one mode of the present invention is shown.

[0264] In Figure 18A a sealant 4005 is provided so as to surround the display portion 215 provided on the first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006.

[0265] The display portion 215 is provided with a pixel array including any one of the pixels 10 to 15 shown in Embodiment 1. Note that the scan line driving circuit described below corresponds to a row driver, and the signal line driving circuit corresponds to a column driver.

[0266] In Figure 18A the scan line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a all include a plurality of integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuit 4042 is formed of single crystal semiconductor or polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a have the functions of the column driver shown in Embodiment 1. The scan line driving circuit 221a has the functions of the row driver shown in Embodiment 1. The common line driving circuit 241a has the function of supplying a prescribed potential to wirings 128, 129, 132, 133, etc. shown in Embodiment 1.

[0267] Various signals and potentials are supplied to the scan line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a through an FPC (Flexible Printed Circuit) 4018.

[0268] The integrated circuit 4042 included in the scan line driving circuit 221a and the common line driving circuit 241a has a function of supplying a selection signal to the display unit 215. The integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in an area different from the area surrounded by the sealant 4005 on the first substrate 4001.

[0269] Note that there is no particular limitation on the connection method of the integrated circuit 4042, and methods such as wire bonding method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, and COF (Chip On Film) method can be used.

[0270] Figure 18B An example of mounting the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a using the COG method is shown. In addition, by forming a part or the whole of the driving circuit on the substrate on which the display unit 215 is formed, a system-on-panel can be formed.

[0271] Figure 18B An example of forming the scan line driving circuit 221a and the common line driving circuit 241a on the substrate on which the display unit 215 is formed is shown. By simultaneously forming the driving circuit and the pixel circuit in the display unit 215, the number of components can be reduced. Thereby, the productivity can be improved.

[0272] In addition, in Figure 18B , the sealant 4005 is provided so as to surround the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a provided on the first substrate 4001. A second substrate 4006 is provided on the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a. Thus, the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a are hermetically sealed together with the display element through the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0273] Although Figure 18B shows an example of separately forming the signal line driving circuit 231a and the signal line driving circuit 232a and mounting them on the first substrate 4001, one aspect of the present invention is not limited to this structure, and a scan line driving circuit can also be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit can be separately formed and mounted. In addition, as Figure 18CAs shown, the signal line driving circuit 231a and the signal line driving circuit 232a may also be formed on the substrate on which the display unit 215 is formed.

[0274] In addition, a display device sometimes includes a panel in which display elements are in a sealed state and a module in which an IC including a controller is mounted in the panel.

[0275] The display unit and the scan line driving circuit provided on the first substrate include a plurality of transistors. As such transistors, the transistors shown in the above-described embodiments can be applied.

[0276] The structures of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may have the same structure or different structures. The transistors included in the peripheral driving circuit may all have the same structure, or two or more structures may be combined. Similarly, the transistors included in the pixel circuit may all have the same structure, or two or more structures may be combined.

[0277] In addition, the input device 4200 can be provided on the second substrate 4006. Figures 18A to 18C The structure in which the input device 4200 is provided for the display device shown can be used as a touch screen.

[0278] There is no particular limitation on the sensing element (also referred to as a sensing element) included in a touch screen according to one embodiment of the present invention. Various sensors that can detect the approach or contact of a detection object such as a finger or a stylus can also be used as the sensing element.

[0279] For example, as a sensor method, various methods such as a capacitive type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure sensitive type can be used.

[0280] In the present embodiment, a touch screen including a capacitive sensing element is described as an example.

[0281] As the capacitive type, there are a surface capacitive type, a projected capacitive type, etc. In addition, as the projected capacitive type, there are a self-capacitive type, a mutual-capacitive type, etc. The mutual-capacitive type is preferably used because multi-point sensing can be performed simultaneously.

[0282] A touch screen according to one embodiment of the present invention can adopt various structures such as a structure in which a separately manufactured display device and a sensing element are bonded, a structure in which electrodes constituting the sensing element are provided on one or both of a substrate supporting the display element and a counter substrate, and the like.

[0283] Figure 19A and Figure 19B Shows an example of a touch screen. Figure 19A Is a perspective view of the touch screen 4210. Figure 19BIt is a perspective view of the input device 4200. Note that, for clarity, only typical components are shown.

[0284] The touch screen 4210 has a structure in which a separately manufactured display device and a sensing element are bonded together.

[0285] The touch screen 4210 includes an input device 4200 and a display device that are overlapped and arranged.

[0286] The input device 4200 includes a substrate 4263, electrodes 4227, electrodes 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. In addition, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b can be electrically connected to the plurality of wirings 4237 and the plurality of wirings 4238 respectively. The FPC 4272b can be provided with an IC 4273b.

[0287] A touch sensor can be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, in addition to a capacitive touch sensor, an optical touch sensor using a photoelectric conversion element can also be used.

[0288] Figure 20A and Figure 20B is a cross-sectional view along Figure 18B the dotted line N1-N2 in Figure 20A and Figure 20B The display device shown in Figure 20A and Figure 20B includes an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 4018 through an anisotropic conductive layer 4019. In addition, in

[0289] the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0290] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source electrodes and drain electrodes of the transistors 4010 and 4011 are formed using the same conductive layer. Figure 20A and Figure 20B In addition, the display unit 215 and the scan line driver circuit 221a provided on the first substrate 4001 include a plurality of transistors. In Figure 20A and Figure 20BBottom-gate transistors are shown as transistors 4010 and 4011, but top-gate transistors may also be used.

[0291] In Figure 20A and Figure 20B an insulating layer 4112 is provided over transistors 4010 and 4011. Further, in Figure 20B a partition wall 4510 is formed over the insulating layer 4112.

[0292] Further, transistors 4010 and 4011 are provided over an insulating layer 4102. Further, transistors 4010 and 4011 include an electrode 4017 formed over an insulating layer 4111. The electrode 4017 can be used as a back gate electrode.

[0293] Further, Figure 20A and Figure 20B the display device shown includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps with each other with an insulating layer 4103 therebetween.

[0294] Generally, the capacitance of the capacitor provided in the pixel portion of the display device is set in consideration of the leakage current of the transistors disposed in the pixel portion or the like so that it can hold charges for a specified period. The capacitance of the capacitor may be set in consideration of the off-state current of the transistors or the like.

[0295] The transistor 4010 provided in the display portion 215 is electrically connected to the display element. Figure 20A is an example of a liquid crystal display device using a liquid crystal element as the display element. In Figure 20A the liquid crystal element 4013 as the display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033 used as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 overlaps with the second electrode layer 4031 with the liquid crystal layer 4008 therebetween.

[0296] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and it is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers may also be used.

[0297] In addition, optical components (optical substrates) such as a black matrix (light-shielding layer), a colored layer (color filter), a polarization member, a retardation member, and an antireflection member can be appropriately provided as needed. For example, circular polarization using a polarization substrate and a retardation substrate can also be used. In addition, as the light source, a backlight or a side light can also be used. As the above backlight or side light, Micro-LED or the like can also be used.

[0298] In Figure 20A In the display device shown, a light-shielding layer 4132, a colored layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.

[0299] Examples of materials that can be used for the light-shielding layer include carbon black, titanium black, metals, metal oxides, or composite oxides that are solid solutions containing multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film containing an inorganic material such as a metal. In addition, a laminated film of a film containing a material of the colored layer can also be used for the light-shielding layer. For example, a laminated structure of a film containing a material of a colored layer that transmits light of a certain color and a film containing a material of a colored layer that transmits light of other colors can be adopted. By making the materials of the colored layer and the light-shielding layer the same, not only can the same equipment be used, but also the process can be simplified, which is therefore preferable.

[0300] Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, etc. The light-shielding layer and the colored layer can be formed by, for example, an inkjet method.

[0301] In addition, Figure 20A and Figure 20B the display device shown includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer that does not easily allow impurity elements to pass through is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, the intrusion of impurities from the outside can be prevented.

[0302] In addition, as a display element included in the display device, a light-emitting element using electroluminescence (also referred to as an EL element) can be applied. The EL element has a layer containing a light-emitting compound (also referred to as an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, and thereby, the light-emitting compound contained in the EL layer emits light.

[0303] EL elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Usually, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0304] In an organic EL element, by applying a voltage, electrons are injected into the EL layer from one electrode, and holes are injected into the EL layer from the other electrode. Through the recombination of these carriers (electrons and holes), the light-emitting organic compound forms an excited state and emits light when returning from this excited state to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0305] The EL layer may also include, in addition to the light-emitting compound, a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property), etc.

[0306] The EL layer can be formed by methods such as vapor deposition method (including vacuum vapor deposition method), transfer method, printing method, inkjet method, coating method, etc.

[0307] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. The dispersed inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination type light emission using donor energy levels and acceptor energy levels. The thin-film inorganic EL element has a structure in which the light-emitting layer is sandwiched between dielectric layers, and the dielectric layer sandwiching the light-emitting layer is sandwiched between electrodes, and its light-emitting mechanism is local type light emission using the inner shell electron transition of metal ions. Note that here, an organic EL element is used for illustration as the light-emitting element.

[0308] In order to extract light emission, at least one of a pair of electrodes of the light-emitting element is made transparent. A transistor and a light-emitting element are formed on a substrate. As the light-emitting element, a top emission structure that emits light from the surface on the side opposite to the substrate; a bottom emission structure that emits light from the surface on the substrate side; and a double-sided emission structure that emits light from both surfaces can be adopted.

[0309] Figure 20B is an example of a light-emitting display device (also called an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513 used as the display element is electrically connected to the transistor 4010 provided in the display unit 215. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of extracting light from the light-emitting element 4513, etc.

[0310] The partition wall 4510 is formed of an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030, and to form the side surface of the opening into an inclined surface having a continuous curvature.

[0311] The light-emitting layer 4511 may be constituted by a single layer or a stack of multiple layers.

[0312] The emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, etc. depending on the material constituting the light-emitting layer 4511.

[0313] As a method for realizing color display, there are the following methods: a method of combining a light-emitting element 4513 having a white emission color and a coloring layer; and a method of providing light-emitting elements 4513 having different emission colors for each pixel. The productivity of the former method is higher than that of the latter method. On the other hand, in the latter method, it is necessary to form the light-emitting layer 4511 for each pixel, so its productivity is lower than that of the former method. However, in the latter method, an emission color with higher color purity than that of the former method can be obtained. By providing the light-emitting element 4513 with a microcavity structure in the latter method, the color purity can be further improved.

[0314] The light-emitting layer 4511 may also contain an inorganic compound such as a quantum dot. For example, by using a quantum dot for the light-emitting layer, it can also be used as a light-emitting material.

[0315] In order to prevent the intrusion of oxygen, hydrogen, moisture, carbon dioxide, etc. into the light-emitting element 4513, a protective layer may also be formed on the second electrode layer 4031 and the partition wall 4510. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), etc. can be formed. In addition, a filler 4514 is provided in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and is sealed. Thus, in order not to be exposed to external gases, it is preferable to use a protective film (adhesive film, ultraviolet curable resin film, etc.) and a covering material with high airtightness and less outgassing for encapsulation (enclosure).

[0316] As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can also be used. For example, PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene-vinyl acetate) can be used. The filler 4514 may also contain a desiccant.

[0317] As the sealant 4005, glass materials such as glass powder, or curable resins that cure at room temperature such as two-component mixed resins, photocurable resins, and thermosetting resins can be used. The sealant 4005 can also contain a desiccant.

[0318] In addition, as needed, optical films such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. can be appropriately provided on the light-emitting surface of the light-emitting element. In addition, an antireflection film can be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed, which is a treatment for reducing reflected glare by diffusing reflected light using irregularities on the surface.

[0319] By making the light-emitting element have a microcavity structure, light with high color purity can be extracted. In addition, by combining the microcavity structure and the color filter, reflected glare can be prevented, and the visibility of the image can be improved.

[0320] Regarding the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) that apply voltage to the display element, it is sufficient to select its light transmittance and reflectance according to the direction of light extraction, the place where the electrode layer is provided, and the pattern structure of the electrode layer.

[0321] As the first electrode layer 4030 and the second electrode layer 4031, light-transmissive conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0322] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or their alloys or nitrides.

[0323] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or their derivatives composed of two or more of aniline, pyrrole, and thiophene can be cited.

[0324] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably composed of a non-linear element.

[0325] Note that, as Figure 21 shown, a stacked structure in which a transistor and a capacitor include an overlapping region in the height direction can also be employed. For example, by arranging the transistors 4011 and 4022 that constitute the driving circuit so as to overlap, a display device with a narrow bezel can be realized. In addition, by arranging the transistors 4010, 4023, the capacitor 4020, etc. that constitute the pixel circuit so as to partially include an overlapping region, the aperture ratio and the resolution can be improved. In addition, in Figure 21 shows an example of applying the stacked structure to the Figure 20A liquid crystal display device shown, but it can also be applied to the Figure 20B EL display device shown.

[0326] In addition, in the pixel circuit, a transparent conductive film having high light transmittance to visible light is used as the electrode and the wiring, so that the light transmittance in the pixel can be increased, and thus the aperture ratio can be substantially increased. In addition, since the semiconductor layer also has light transmittance when using an OS transistor, the aperture ratio is further increased. This is also effective when a stacked structure is not adopted for the transistor or the like.

[0327] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0328] (Embodiment 3)

[0329] In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0330] The display device according to one aspect of the present invention can be manufactured using various types of transistors such as bottom-gate transistors or top-gate transistors. Therefore, it is possible to easily correspond to the existing production line by replacing the semiconductor layer material or the transistor structure used.

[0331] [Bottom-gate transistor]

[0332] Figure 22A1 A cross-sectional view in the channel length direction of a channel protection type transistor 810, which is one of the bottom-gate transistors, is shown. In Figure 22A1 , the transistor 810 is formed on the substrate 771. In addition, the transistor 810 includes an electrode 746 on the substrate 771 with an insulating layer 772 interposed therebetween. In addition, a semiconductor layer 742 is included on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0333] In addition, an insulating layer 741 is included over a channel formation region of the semiconductor layer 742. Further, electrodes 744a and 744b are included in contact with a part of the semiconductor layer 742 over the insulating layer 726. Electrode 744a can be used as one of a source electrode and a drain electrode. Electrode 744b can be used as the other of the source electrode and the drain electrode. A part of electrode 744a and a part of electrode 744b are formed over the insulating layer 741.

[0334] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 over the channel formation region, exposure of the semiconductor layer 742 can be prevented when forming the electrodes 744a and 744b. Thereby, etching of the channel formation region of the semiconductor layer 742 can be prevented when forming the electrodes 744a and 744b. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0335] In addition, the transistor 810 includes an insulating layer 728 over the electrodes 744a, the electrodes 744b, and the insulating layer 741, and an insulating layer 729 over the insulating layer 728.

[0336] When an oxide semiconductor is used for the semiconductor layer 742, a material capable of extracting oxygen from a part of the semiconductor layer 742 to generate oxygen defects is preferably used for at least a part of the electrodes 744a and 744b in contact with the semiconductor layer 742. The carrier concentration in the region where oxygen defects are generated in the semiconductor layer 742 increases, and this region is n-type doped to become an n-type region (n + layer). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, as an example of a material capable of extracting oxygen from the semiconductor layer 742 to generate oxygen defects, tungsten, titanium, etc. can be cited.

[0337] By forming a source region and a drain region in the semiconductor layer 742, the contact resistance between the electrodes 744a and 744b and the semiconductor layer 742 can be reduced. Therefore, electrical characteristics of the transistor such as field-effect mobility and threshold voltage can be made good.

[0338] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of the transistor.

[0339] The insulating layer 729 is preferably formed of a material having a function of preventing impurities from diffusing into the transistor from the outside or reducing the diffusion of impurities. Further, the insulating layer 729 can be omitted as needed.

[0340] Figure 22A2The transistor 811 shown in the figure is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0341] Generally speaking, the back gate electrode is formed using a conductive layer and is arranged in a manner that the channel forming region of the semiconductor layer is clamped by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0342] The electrode 746 and the electrode 723 can both be used as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can all be used as gate insulating layers. Alternatively, the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0343] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 is a top gate transistor. In addition, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0344] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween and setting the potentials of the electrode 746 and the electrode 723 to be the same, the region through which the carriers flow in the semiconductor layer 742 is further expanded in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-state current of the transistor 811 increases, and the field effect mobility also increases.

[0345] Therefore, transistor 811 is a transistor having a large on-state current relative to the occupied area. That is, the occupied area of ​​transistor 811 can be reduced relative to the required on-state current. According to one embodiment of the present invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0346] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, they have a function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0347] In addition, by forming a back gate electrode using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Thereby, light degradation of the semiconductor layer can be prevented, and degradation of electrical characteristics such as threshold voltage drift of the transistor can be prevented.

[0348] According to one aspect of the present invention, a transistor with good reliability can be realized. In addition, a semiconductor device with good reliability can be realized.

[0349] Figure 22B1 Shows Figure 22A1 A cross-sectional view in the channel length direction of a channel protection type transistor 820 having a structure different from that of the transistor 810. The transistor 820 has substantially the same structure as the transistor 810, except that an insulating layer 741 covers the end portion of the semiconductor layer 742. In an opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. In addition, in another opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0350] Figure 22B2 The transistor 821 shown is different from the transistor 820 in that it includes an electrode 723 on the insulating layer 729 that can be used as a back gate electrode.

[0351] By providing the insulating layer 741, exposure of the semiconductor layer 742 generated when forming the electrode 744a and the electrode 744b can be prevented. Therefore, thinning of the semiconductor layer 742 when forming the electrode 744a and the electrode 744b can be prevented.

[0352] In addition, compared with the transistor 810 and the transistor 811, the distances between the electrode 744a and the electrode 746 and between the electrode 744b and the electrode 746 of the transistor 820 and the transistor 821 are longer. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be provided.

[0353] Figure 22C1 A cross-sectional view in the channel length direction of a channel etching type transistor 825 which is one of the bottom gate type transistors is shown. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Therefore, a part of the semiconductor layer 742 exposed when forming the electrode 744a and the electrode 744b is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0354] Figure 22C2 The transistor 826 shown is different from the transistor 825 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729 .

[0355] Figure 23A1 , Figure 23A2 , Figure 23B1 , Figure 23B2 , Figure 23C1 and Figure 23C2 A cross-sectional view of transistors 810 , 811 , 820 , 821 , 825 , and 826 in the channel width direction is shown.

[0356] exist Figure 23B2 and Figure 23C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, so that the gate electrode and the back gate electrode have the same potential. In addition, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0357] The gate electrode and the back gate electrode are longer than the semiconductor layer 742 in the channel width direction, and the entire semiconductor layer 742 is covered by the gate electrode or the back gate electrode with the insulating layers 726 , 741 , 728 , and 729 interposed therebetween.

[0358] With this structure, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.

[0359] A device structure of a transistor such as the transistor 821 or the transistor 826 in which the semiconductor layer 742 forming a channel formation region is electrically surrounded by an electric field between a gate electrode and a back gate electrode can be referred to as a surrounded channel (S-channel) structure.

[0360] By adopting the S-channel structure, an electric field for causing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate electrode and the back gate electrode. As a result, the current driving capability of the transistor is improved, thereby obtaining a higher on-state current characteristic. In addition, since the on-state current can be increased, the transistor can be miniaturized. In addition, by adopting the S-channel structure, the mechanical strength of the transistor can be improved.

[0361] [Top-gate transistor]

[0362] Figure 24A1 The transistor 842 shown as an example is a top-gate transistor. The electrode 744 a and the electrode 744 b are electrically connected to the semiconductor layer 742 through openings formed in the insulating layer 728 and the insulating layer 729 .

[0363] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities 755 are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask. As a result, impurity regions can be formed in the semiconductor layer 742 in a self-alignment manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where impurities 755 are introduced through the insulating layer 726 is lower than that in the region where impurities 755 are not introduced through the insulating layer 726. Therefore, a lightly doped drain (LDD) region is formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0364] Figure 24A2 The transistor 843 shown is different from the transistor 842 in that it includes an electrode 723. The transistor 843 includes an electrode 723 formed on the substrate 771. A region where the electrode 723 overlaps with the semiconductor layer 742 with the insulating layer 772 therebetween. The electrode 723 can be used as a back gate electrode.

[0365] In addition, as Figure 24B1 shown in the transistor 844 and Figure 24B2 shown in the transistor 845, the insulating layer 726 in the region that does not overlap with the electrode 746 can also be completely removed. In addition, as Figure 24C1 shown in the transistor 846 and Figure 24C2 shown in the transistor 847, the insulating layer 726 may not be removed.

[0366] In the transistors 842 to 847, impurities 755 can also be introduced into the semiconductor layer 742 using the electrode 746 as a mask after forming the electrode 746, thereby forming impurity regions in the semiconductor layer 742 in a self-aligned manner. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized. In addition, according to one aspect of the present invention, a semiconductor device with high integration can be realized.

[0367] Figure 25A1 、 Figure 25A2 、 Figure 25B1 、 Figure 25B2 、 Figure 25C1 and Figure 25C2 show cross-sectional views of the transistors 842, 843, 844, 845, 846, and 847 in the channel width direction.

[0368] The transistors 843, 845, and 847 have the above-described S-channel structure. However, without being limited thereto, the transistors 843, 845, and 847 may not have the S-channel structure.

[0369] This embodiment can be implemented by appropriately combining with the structures described in other embodiments and the like.

[0370] (Embodiment 4)

[0371] Examples of electronic devices that can use one aspect of the present invention as a display device include display devices, personal computers, image storage devices and image reproduction devices having a recording medium, mobile phones, game machines including portable game machines, portable data terminals, e-book readers, photographing devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. Figures 26A to 26F Specific examples of these electronic devices are shown.

[0372] Figure 26A A digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom button 968, a lens 969, etc. By using a display device according to one aspect of the present invention for the display unit 965, various images can be displayed.

[0373] Figure 26B A digital sign, which includes a large display unit 922. For example, it can be installed on the side of a pillar 921. By using a display device according to one aspect of the present invention for the display unit 922, a high-quality display can be performed.

[0374] Figure 26C A mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations such as making a call or inputting text can be performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be used in a bent state as shown in the figure. By using a display device according to one aspect of the present invention for the display unit 952, various images can be displayed.

[0375] Figure 26D A portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Data can be input or output by using the touch screen function of the display unit 912. By using a display device according to one aspect of the present invention for the display unit 912, various images can be displayed.

[0376] Figure 26EIt is a television set, which includes a housing 971, a display unit 973, operation keys 974, speakers 975, communication connection terminals 976, a photoelectric sensor 977, etc. The display unit 973 is provided with a touch sensor and can perform input operations. By using the display device of one embodiment of the present invention for the display unit 973, various images can be displayed.

[0377] Figure 26F It is an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, a sensor 904, etc. The display unit 902 and the display unit 903 are composed of a single display panel and are flexible. In addition, the housing 901 is also flexible, so that the information processing terminal can be folded and used as shown in the attached drawings, and the information processing terminal can be made into a flat shape like a tablet terminal and used. The sensor 904 can detect the shape of the housing 901. For example, when the housing is bent, the display of the display unit 902 and the display unit 903 can be switched. By using the display device of one embodiment of the present invention for the display unit 902 and the display unit 903, various images can be displayed.

[0378] This embodiment can be implemented by appropriately combining with the structures described in other embodiments and the like.

[0379] [Reference Signs]

[0380] 10: Pixel, 11: Pixel, 12: Pixel, 13: Pixel, 14: Pixel, 15: Pixel, 17: Pixel block, 18: Pixel block, 19: Pixel matrix, 20: Shift register, 21: Buffer circuit, 22: Shift register, 23: Buffer circuit, 24: Sensor, 25: Circuit, 31: Row driver, 32: Column driver, 33: Circuit, 34: Selection circuit, 101: Transistor, 102: Transistor, 103: Transistor, 104: Capacitor, 105: Capacitor, 106: Transistor, 107: Transistor, 110: Circuit block, 111: Transistor, 112: Transistor, 113: Capacitor, 114: EL element, 115: Transistor, 116: Capacitor, 117: Liquid crystal element, 118: Transistor, 119: Transistor, 120: Circuit, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 215: Display unit, 221a: Scan line drive circuit, 231a: Signal line drive circuit, 232a: Signal line drive circuit, 241a: Common line drive circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Display unit, 903: Display unit, 904: Sensor, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Column, 922: Display unit, 951: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 966: Operation key, 967: Speaker, 968: Zoom button, 969: Lens, 971: Housing, 973: Display unit, 974: Operation key, 975: Speaker, 976: Communication connection terminal, 977: Light sensor, 4001: Substrate, 4005: Sealant, 4006: Substrate, 4008: Liquid crystal layer, 4010: Transistor, 4011: Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropic conductive layer, 4020: Capacitor4021: Electrode, 4022: Transistor, 4023: Transistor, 4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110: Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4131: Coloring layer, 4132: Light-shielding layer, 4133: Insulating layer, 4200: Input device, 4210: Touch screen, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4510: Partition wall, 4511: Light-emitting layer, 4513: Light-emitting element, 4514: Filling material.

Claims

1. A display device, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a first capacitor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a second capacitor; and a circuit block, wherein one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor, the one electrode of the first capacitor is electrically connected to the circuit block, the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor, the one of the source and drain of the second transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and drain of the third transistor, the circuit block includes a display element, the other of the source and drain of the first transistor is electrically connected to the first wiring, the other of the source and drain of the third transistor is electrically connected to the first wiring, one of the source and drain of the fourth transistor is electrically connected to the one electrode of the second capacitor, one of the source and drain of the fifth transistor is electrically connected to the other electrode of the second capacitor, the other of the source and drain of the second transistor is electrically connected to the first wiring, the other of the source and drain of the fourth transistor and the other of the source and drain of the fifth transistor are electrically connected to the fifth wiring, the gate of the first transistor is electrically connected to the second wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gate of the second transistor is electrically connected to the third wiring, the gate of the fifth transistor is electrically connected to the third wiring, and the gate of the third transistor is electrically connected to the fourth wiring.

2. The display device according to claim 1, wherein the circuit block includes a sixth transistor, a seventh transistor, a third capacitor, and an EL element as the display element, one electrode of the EL element is electrically connected to one of the source and drain of the seventh transistor, the other of the source and drain of the seventh transistor is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to one of the source and drain of the sixth transistor, the gate of the sixth transistor is electrically connected to the other electrode of the third capacitor, and the other electrode of the third capacitor is electrically connected to the one electrode of the first capacitor.

3. The display device according to claim 1, wherein the circuit block includes a fourth capacitor and a liquid crystal element as the display element, one electrode of the liquid crystal element is electrically connected to one electrode of the fourth capacitor, and the one electrode of the fourth capacitor is electrically connected to the one electrode of the first capacitor.

4. The display device according to claim 3, further comprising an eighth transistor, wherein the one electrode of the fourth capacitor is electrically connected to one of the source and drain of the eighth transistor, Further, the other of the source and drain of the eighth transistor is electrically connected to the one electrode of the first capacitor.

5. The display device according to claim 1, wherein the first transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M, where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

6. An electronic device, comprising: the display device according to claim 1; and a camera.

Images