Online self-test device for PET detector front-end circuit based on SiPM

Abstract

The present invention provides an online self-test device for the front-end circuit of a PET detector based on SiPM, which relates to the technical field of PET detectors, including a SiPM array, a front-end discrimination circuit, an analog shaping circuit, a self-test signal generating circuit, a multiplexer, a self-test control module, a time measurement circuit, an energy measurement circuit and an FPGA chip; the multiplexer is used to select the SiPM array output signal or the self-test signal, and then the time information is obtained through the front-end discrimination circuit and the time measurement circuit, and the energy information of the signal is obtained through the energy measurement circuit based on analog shaping and digital integration. The self-test control module can control the front-end self-test circuit to generate a self-test signal and complete a series of tasks. The self-test device of the present invention can generate a SiPM-like signal and complete a series of power-on state self-test, circuit parameter calibration and circuit problem detection functions, which is convenient for developers to debug the system in the early stage and detect the system in the later stage.

Description

Technical Field

[0001] The invention relates to an online self-test device for a front-end circuit of a PET detector based on SiPM, belonging to the technical field of PET detectors. Background Art

[0002] The principle of the positron emission tomography (PET) detector based on silicon photomultiplier (SiPM) devices is to convert the high-energy gamma photons captured by the crystal module into low-energy visible light signals through the photoelectric effect, and then use the SiPM to convert them into analog electrical signals, and use the front-end circuit to amplify and shape the analog electrical signals, and then use the energy measurement device and the time measurement device (Time-Digital Converter, TDC) to obtain the energy and arrival time information of the analog electrical signal, and upload the measured data to the back-end data acquisition system (Data Acquisition, DAQ) through optical fiber (or other media). DAQ performs online compliance and selection based on the data uploaded by the front-end module, and finally obtains the radiation source image through the image reconstruction algorithm. For a large number of front-end circuits, since there is no front-end circuit self-test circuit in the currently used PET detectors, developers generally use external arbitrary waveform signal generators or SiPM detectors to debug, so as to determine whether the system working status and performance are normal, which will undoubtedly increase the debugging cost and development cycle. In addition, when a problem occurs in the front-end circuit during the operation of the entire system, users or developers cannot quickly determine whether the problem occurs in the SiPM or the electronics, which increases maintenance costs.

[0003] Therefore, it is necessary to design an online self-test device to monitor the circuit status and complete basic functional measurements.

[0004] Secondly, the analog-digital converter (ADC) has a fixed measurement range and cannot be automatically adjusted to fully utilize its range. It is impossible to achieve online automatic threshold calibration and circuit gain monitoring functions;

[0005] Based on this, this application is made. Summary of the invention

[0006] In order to solve the above-mentioned defects existing in the prior art, the present invention provides an online self-test device for the front-end circuit of a PET detector based on SiPM, which can generate SiPM-like signals and complete a series of power-on status self-test, circuit parameter calibration, circuit problem detection and other functions, thereby facilitating developers' early system debugging and later system detection.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] An online self-test device for the front-end circuit of a PET detector based on SiPM, wherein the front-end circuit includes a SiPM array, a front-end discrimination circuit and an analog shaping circuit; the self-test device includes

[0009] A self-test signal generating circuit, used for generating a self-test signal having energy and being a SiPM-like signal;

[0010] A multiplexer, whose input end is connected to the output end of the self-test signal circuit and the output end of the SiPM array, and is used to select the SiPM array output signal or the self-test signal; the output end of the multiplexer is connected to the input end of the leading edge discrimination circuit and the analog shaping circuit;

[0011] A self-test control module, used to control the self-test signal generating circuit to generate a self-test signal;

[0012] A time measurement circuit, used for measuring the time of the signal from the leading edge discrimination circuit to obtain time information;

[0013] An energy measurement circuit, used for measuring the energy of the signal from the analog shaping circuit to obtain energy information;

[0014] The FPGA chip compares and analyzes the obtained time information and energy information with the self-test signal to determine whether an abnormality occurs.

[0015] The self-check control module, time measurement circuit and energy measurement circuit are all integrated in the FPGA chip.

[0016] The self-test control module controls the front-end self-test signal generation circuit to generate a series of self-test signals with specific energy and frequency, given a baseline and threshold.

[0017] The baseline measurement is achieved through the ADC chip, and then a large number of signals are measured and averaged to obtain the gain of the energy measurement circuit and save it. It is uploaded to the host computer and provided to the user for detection. If the gain is too large or too small compared to the given baseline, an alarm data packet is generated and uploaded to the user.

[0018] By comparing the given threshold, if the time measurement frequency is basically consistent with the self-test signal generation frequency set by the user, it proves that the time measurement circuit works basically normally, otherwise an alarm data packet is generated and uploaded to the user.

[0019] Furthermore, in order to make the baseline or threshold reasonable, the present invention adds baseline adjustment and threshold adjustment.

[0020] Principles and beneficial technical effects of the present invention:

[0021] (1) The present invention designs a self-test circuit that generates a SiPM-like signal online, which can control the generation of a self-test signal with specific energy and frequency, replace the SiPM signal to complete circuit detection and measurement, and reduce the R&D cycle and cost;

[0022] (2) The present invention utilizes a self-checking circuit to realize ADC baseline calibration, automatic calibration of time measurement threshold, energy measurement circuit gain monitoring, and TDC nonlinear correction;

[0023] (3) The present invention utilizes a self-checking circuit to facilitate developers or users to quickly locate the source of a problem online when a problem occurs in the detector.

[0024] It can be seen that the front-end circuit online self-test device used in PET of the present invention can generate SiPM-like signals and complete a series of power-on status self-test, circuit parameter calibration, circuit problem detection and other functions, which is convenient for developers to perform early system debugging and later system detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the overall structure of this embodiment;

[0026] Figure 2 Schematic diagram of the differential op amp driving the ADC input;

[0027] Figure 3 This is a flow chart of the system self-check in this embodiment. DETAILED DESCRIPTION

[0028] In order to make the technical means of the present invention and the technical effects that can be achieved by it more clearly and completely disclosed, the following embodiments are provided and described in detail as follows in conjunction with the accompanying drawings:

[0029] A front-end circuit online self-test device used in PET in this embodiment can generate SiPM-like signals and complete a series of boot-up state self-test, circuit parameter calibration, circuit problem detection and other functions. The overall structural schematic diagram of the system is shown in Figure 1, in which the digital processing part is completed by a field programmable gate array (FPGA). A multiplexer is used to select the SiPM array output signal or self-test signal, and then the time information is obtained through the leading edge discrimination circuit and the FPGA-based TDC (FPGA-TDC), and the energy information of the signal is obtained through the energy measurement circuit based on analog shaping and digital integration. The self-test control module can control the front-end self-test circuit to generate a self-test signal and complete a series of tasks. The energy information, time information and self-test results can be uploaded to the host computer through a high-speed interface (such as PCIE, etc.), and the host computer can send self-test tasks or parameters to the front-end FPGA chip. This embodiment specifically includes a SiPM array, a self-test signal generating circuit, an energy and time measurement circuit, a self-test control module, etc.

[0030] The specific implementation methods are as follows:

[0031] (4.1) The SiPM array is composed of 8X8 SiPM detection units, which completes the row and column current addition and reduces the number of system channels;

[0032] (4.2) The self-test signal generating circuit uses commercial switch chips and resistors and capacitors, controls the opening and closing of the switch through FPGA, and generates a SiPM-like signal with specific energy according to the principle of capacitor charging and discharging;

[0033] (4.3) The specific implementation process of the energy and time measurement circuit and logic is as follows:

[0034] (4.3.1) The analog shaping circuit shapes the signal into a quasi-Gaussian signal, and then uses the ADC to perform analog-to-digital conversion. The digitized information is sent to the FPGA for digital integration to obtain signal energy information;

[0035] (4.3.2) The time measurement circuit obtains the signal arrival time information based on leading edge timing and FPGA-TDC;

[0036] (4.4) The self-check module mainly completes a series of self-check tasks. The flow chart is shown in Figure 3. The specific implementation process is as follows:

[0037] (4.4.1) After the system is powered on or the user forces the self-test to start, the process control module configures Vref through the serial peripheral interface (SPI), and then the switch control module controls the front-end self-test circuit to generate a series of self-test signals with specific energy (Q) and frequency (f);

[0038] (4.4.2) According to the known self-test signal amplitude, adjust the time measurement circuit threshold Vth (time measurement threshold is automatically calibrated). According to the S-curve method, when the trigger rate is 50%, the time measurement circuit threshold is basically consistent with the self-test signal amplitude. Then, according to the self-test signal energy Q, the relative discrimination threshold of the time measurement circuit to be configured (for example, 0.1Q) is obtained; it should be noted that baseline calibration is conducive to improving energy measurement performance; since time measurement must have a reasonable threshold, threshold calibration is a necessary step for time measurement.

[0039] (4.4.3) Energy measurement uses the inherent delay of the ADC chip to perform baseline measurement and take the average. A reasonable baseline and amplitude should fully utilize the range of the ADC chip. Figure 2 The figure shows the circuit of driving the differential op amp at the ADC input. The ADC measurement baseline (positive and negative difference of the differential op amp output) can be adjusted by adjusting the Vset pin at the positive input of the differential op amp. If the ADC measurement baseline is unreasonable, or even causes a range overflow, the FPGA controls Vset to adjust until the baseline position and range are reasonable. By adjusting the ADC measurement baseline, the ADC measurement range can be fully utilized to improve measurement accuracy.

[0040] (4.4.4) According to step (4.4.3), by measuring a large number of signals and taking the average, the gain of the energy measurement circuit is obtained and stored in the internal memory of the FPGA, and then uploaded to the host computer for the user to detect. If the gain is too large or too small, an alarm data packet is generated and uploaded to the user;

[0041] (4.4.5) According to step (4.4.3), the time measurement result is obtained. If the time measurement frequency is basically consistent with the self-test signal generation frequency set by the user, it proves that the time measurement circuit is basically working normally, otherwise an alarm data packet is generated and uploaded to the user; it should be noted that the consistency between the frequency obtained by time measurement and the signal generation frequency controlled by the user is a basic test. If there is no circuit hardware failure, the self-test signal can be measured as long as the threshold setting is not too high or too low. However, in actual use, the threshold needs to be set at a better value to obtain better time resolution, so the above-mentioned time discrimination threshold adjustment is required.

[0042] (4.4.6) Using the signal generated by the self-test circuit, the code density method is used to complete the nonlinear correction of the FPGA-TDC, and the correction results are stored in the FPGA internal memory;

[0043] (4.4.7) After completing the self-test, control the multiplexer to select the SiPM array signal and enter the normal measurement mode.

[0044] The above content is a further detailed description of the technical solution provided in combination with the preferred implementation mode of the present invention. It cannot be determined that the specific implementation of the present invention is limited to the above descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. An online self-test device for the front-end circuit of a PET detector based on SiPM, wherein the front-end circuit comprises a SiPM array, a front-end discrimination circuit and an analog shaping circuit; characterized in that: The self-test device comprises A self-test signal generating circuit, used for generating a self-test signal having energy and being a SiPM-like signal; A multiplexer, whose input end is connected to the output end of the self-test signal circuit and the output end of the SiPM array, and is used to select the SiPM array output signal or the self-test signal; the output end of the multiplexer is connected to the input end of the leading edge discrimination circuit and the analog shaping circuit; A self-test control module, used to control the self-test signal generating circuit to generate a self-test signal; A time measurement circuit, used for measuring the time of the signal from the leading edge discrimination circuit to obtain time information; An energy measurement circuit, used for measuring the energy of the signal from the analog shaping circuit to obtain energy information; The FPGA chip compares and analyzes the obtained time information and energy information with the self-test signal to determine whether an abnormality occurs; The self-test control module, time measurement circuit and energy measurement circuit are all integrated in the FPGA chip; the self-test control module includes an SPI configuration module, a process control module, a switch control module and a signal generating module; the process control module configures the Vref pin through the SPI configuration module, and then the switch control module controls the front-end self-test signal generating circuit to generate a series of self-test signals with specific energy and frequency.

2. The SiPM-based PET detector front-end circuit online self-test device according to claim 1, characterized in that: The SPI configuration module adjusts the time measurement circuit threshold according to the known self-test signal amplitude, and then obtains the relative discrimination threshold of the time measurement circuit to be configured according to the self-test signal energy.

3. The SiPM-based PET detector front-end circuit online self-test device as claimed in claim 2, characterized in that: According to the S-curve method, when the trigger rate is 50%, the threshold of the time measurement circuit is basically consistent with the amplitude of the self-test signal.

4. The SiPM-based PET detector front-end circuit online self-test device according to claim 1, characterized in that: The analog shaping circuit is connected to the energy measurement circuit via an ADC chip, and the inherent delay of the ADC chip is used to perform baseline measurement and take an average.

5. The SiPM-based PET detector front-end circuit online self-test device as claimed in claim 4, characterized in that: The ADC chip input end is connected to a driving differential amplifier circuit, and the positive and negative differences of the differential amplifier output are used as the ADC measurement baseline. The ADC measurement baseline is adjusted through the Vset pin at the positive input end of the differential amplifier; the FPGA chip controls the Vset pin to adjust until the baseline position and the ADC chip range are reasonable.

6. The SiPM-based PET detector front-end circuit online self-test device as claimed in claim 4, characterized in that: By measuring a large number of signals and averaging them, the gain of the energy measurement circuit is obtained and saved, and then uploaded to the host computer for the user to detect. If the gain is too large or too small, an alarm data packet is generated and uploaded to the user.

7. The SiPM-based PET detector front-end circuit online self-test device according to claim 1, characterized in that: If the time measurement frequency is basically consistent with the self-test signal generation frequency set by the user, it proves that the time measurement circuit works basically normally, otherwise an alarm data packet is generated and uploaded to the user.

8. The SiPM-based PET detector front-end circuit online self-test device as claimed in claim 1, characterized in that: The signal generated by the self-test circuit is used in combination with the code density method to complete the nonlinear correction of FPGA-TDC, and the correction result is stored in the internal memory of FPGA.

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