A driving method, circuit and chip for optimizing LED display screen coupling

Abstract

The present invention provides a driving method, circuit, and chip for optimizing LED display coupling. The method includes the following steps: receiving grayscale data to be displayed for each row of an LED display; configuring multiple register groups to set the total display duration and the display time of each segment; and displaying the grayscale data in segments based on the values of the register groups, with the display times of adjacent segments separated by a preset blanking clamping time. This method improves display coupling and improves display quality.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated electronic circuits, and in particular relates to a driving method, circuit and chip for optimizing the coupling of an LED display screen. Background Art

[0002] When LED displays display high-grayscale data, the large amount of data causes the line display time to be too long, resulting in coupling on the display, which affects the display quality. While existing technologies offer a method for optimizing the pulse duty cycle through hardware to address this issue, the optimized pulse duty cycle varies due to the wide variety of display models and specifications. This approach cannot be optimized for different displays, resulting in limited effectiveness in improving coupling. Summary of the Invention

[0003] In view of the defects in the prior art, the present invention provides a driving method, circuit and chip for optimizing the coupling of LED display screens, thereby improving the coupling phenomenon and display effect of the display screen.

[0004] In a first aspect, a driving method for optimizing coupling of an LED display screen comprises the following steps:

[0005] Receive the grayscale data to be displayed on each line of the LED display;

[0006] The total display duration and the display time of each segment can be set by configuring multiple register groups;

[0007] The grayscale data to be displayed is displayed in segments according to the value of the register group, wherein the display time of two adjacent segments is separated by a preset blanking clamping time.

[0008] Preferably, the register group includes a first register group and multiple second register groups, the first register group is used to configure the total display duration, and the second register group is used to configure the display time of each segment;

[0009] The segmented display of the grayscale data to be displayed according to the value of the register group specifically includes:

[0010] When a line feed signal is received, the counter is started to count the input clock;

[0011] Segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment;

[0012] When the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, the grayscale data of the next segment is displayed. During the display process, when the blanking clamp time is reached, the counter counting is paused.

[0013] Preferably, when the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, displaying the grayscale data of the next segment specifically includes:

[0014] Display the grayscale data of the first segment;

[0015] When the value of the counter is greater than the sum of the values of the i-th segment and all the second register groups corresponding to the segment before the i-th segment, the grayscale data of the i+1-th segment is displayed, where i≥1.

[0016] Preferably, when the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, displaying the grayscale data of the next segment specifically includes:

[0017] When the value of the counter is greater than n times the sum of the values of the second register group corresponding to one or more consecutive segments, the grayscale data of the next segment is displayed, where n≥1.

[0018] Preferably, segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment specifically includes:

[0019] The grayscale data to be displayed is divided into j+1 segments according to the values of the j second register groups, wherein the first j segments respectively correspond to one of the second register groups.

[0020] In a second aspect, a driving circuit for optimizing coupling of an LED display screen includes a serial-to-parallel data processing module, a storage module, a grouping register module, a grouping algorithm module, and a display output module;

[0021] The external serial input data is connected to the input end of the serial-to-parallel data processing module, the output end of the serial-to-parallel data processing module is connected to the input end of the display output module through the storage module, the output end of the serial-to-parallel data processing module is also connected to the input end of the display output module through the grouping register module and the grouping algorithm module in series, the control end of the display output module is connected to the control end of the grouping algorithm module, and the output end of the display output module outputs display data and transmits it to the LED display screen.

[0022] Preferably, the group register module includes a plurality of register groups, each register group is a k*8-bit register group consisting of k registers; the register group includes a first register group and a plurality of second register groups, the first register group is used to configure the total display duration, and the second register group is used to configure the display time of each segment;

[0023] The output ends of the registers in each register group form a register group bus, the clock end of the register is connected to the input clock; and the input end of the register receives external configuration data.

[0024] Preferably, the grouping algorithm module includes a counter and a plurality of operation modules; the input clock is connected to the input end of the counter; the control end of the counter serves as the control end of the grouping algorithm module;

[0025] The operation module is composed of a comparator; the output end of the counter is connected to one input end of the comparator, the output end of the register group in the group register module or the output end of the adder in any operation module is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module;

[0026] And / or, the operation module is composed of a comparator and an adder; the output ends of any two register groups in the grouped register module, or the output ends of the adders in any two operation modules, or the output end of any register group in the grouped register module and the output end of the adder in any operation module are respectively connected to the two input ends of the adder; the output end of the adder is connected to one input end of the comparator, the output end of the counter is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module.

[0027] Preferably, in the operation module composed of a comparator, the register group in the group register module connected to an input end of the comparator is the first register group or the second register group.

[0028] In a third aspect, a driver chip for optimizing the coupling of an LED display screen includes the above-mentioned driver circuit.

[0029] It can be seen from the above technical solution that the driving method, circuit and chip provided by the present invention, after the amount of grayscale data to be displayed is segmented, each displays the corresponding grayscale data in the corresponding segment. In this way, by segmenting the display time of the row display, the coupling phenomenon of the LED display screen is improved and the display effect is enhanced. The number of segments and the display time of each segment can be configured by the user using registers, which is more flexible to use and can be configured according to different LED display screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0031] Figure 1 This is a flowchart of a driving method provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a flowchart of the segmented display method provided in the second embodiment of the present invention.

[0033] Figure 3 This is the display principle of the LED display screen provided in the second embodiment of the present invention.

[0034] Figure 4 This is a schematic diagram of the control method provided in the second embodiment of the present invention.

[0035] Figure 5 for Figure 4 Schematic diagram of display control for each row in .

[0036] Figure 6 This is a module block diagram of the driving circuit provided in Example 3 of the present invention.

[0037] Figure 7 This is a timing diagram of a display example provided in the third embodiment of the present invention.

[0038] Figure 8 This is a circuit diagram of the group register module provided in the third embodiment of the present invention.

[0039] Figure 9 for Figure 8 Pin diagram for a single register in .

[0040] Figure 10 This is a module block diagram of the grouping algorithm module provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0041] The following embodiments of the technical solution of the present invention are described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore only examples and are not intended to limit the scope of protection of the present invention. It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0042] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0043] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0045] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0046] Example 1:

[0047] A driving method for optimizing LED display coupling, see Figure 1 , including the following steps:

[0048] S1: Receive the grayscale data to be displayed on each line of the LED display;

[0049] Specifically, the driving method is particularly suitable for displaying rows of grayscale data with high gray values.

[0050] S2: Set the total display duration and the display time of each segment by configuring multiple register groups;

[0051] Specifically, this driving method can configure the number of segments based on specific circumstances. The total display duration is the display time for the LED display's row display. This driving method is used to display grayscale data in segments during row display. Each segment can be configured with a register group to store the amount of grayscale data displayed in that segment.

[0052] S3: Displaying the grayscale data to be displayed in segments according to the value of the register group, wherein the display time of two adjacent segments is separated by a preset blanking clamping time.

[0053] Specifically, the shadow-clip time can be configured by software. During this time, the LED display screen turns off and does not perform any display operations. This driving method segments the grayscale data to be displayed, and each segment displays the corresponding grayscale data in the corresponding segment. This segmentation of the display time of the row display improves the coupling phenomenon of the LED display screen and enhances the display effect. The number of segments and the display time of each segment can be configured by the user using a register group, making it more flexible and configurable according to different LED displays.

[0054] Example 2:

[0055] The second embodiment is based on the first embodiment, and adds the following content:

[0056] The register group includes a first register group and multiple second register groups, the first register group is used to configure the total display duration, and the second register group is used to configure the display time of each segment;

[0057] Specifically, this method configures the total display duration and display time using two register sets. The number of second register sets can be determined based on the number of segments. Because the amount of grayscale data displayed after segmentation may exceed the maximum value of the register set, hardware configuration can be used to ensure that the amount of grayscale data that can be displayed after segmentation is n times the value in the register set, where n ≥ 1. For example, if the value in the register set is a, the display time for that segment is a*nT, where T is the period of the input clock.

[0058] See also Figure 2 The step of displaying the grayscale data to be displayed in segments according to the value of the register group specifically includes:

[0059] S11: When a line feed signal is received, the counter is started to count the input clock;

[0060] Specifically, when a line feed signal is received, the display of a new line in the LED display screen is restarted, and the counter is restarted to count the input clock, thereby determining the display time of the line display. Figure 3 , the number of rows and columns displayed can be increased or decreased according to user needs. Figure 3 in the row controller.

[0061] S12: Segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment;

[0062] S13: When the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, the grayscale data of the next segment is displayed. During the display process, when the blanking clamp time is reached, the counter is paused. Specifically, the steps include:

[0063] Display the grayscale data of the first segment;

[0064] When the value of the counter is greater than the sum of the values of the i-th segment and all the first register groups corresponding to the segment before the i-th segment, the grayscale data of the i+1-th segment is displayed, where i≥1.

[0065] Specifically, the control method of this method can be found in Figure 4 If the current line is displayed, it will start displaying again from the first line. Figure 5This is a display control diagram for each row. t1 is the display time period configured by the second register group for the first segment, t2 is the display time period configured by the second register group for the second segment, and t3 is the display time period configured by the second register group for the third segment. The display time periods for each subsequent segment are configured in this order.

[0066] In this way, when using this driving method to display a row on an LED display, if the display time of the first segment exceeds the amount of grayscale data to be displayed, the row display will only be displayed for the first segment. If the display time of the first segment cannot display all the grayscale data to be displayed, the remaining grayscale data will be displayed in the next segment until the display is complete.

[0067] Preferably, segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment specifically includes:

[0068] The grayscale data to be displayed is divided into j+1 segments according to the values of the j second register groups, wherein the first j segments respectively correspond to one of the second register groups.

[0069] Specifically, if the values of the register groups configured in all segments cannot display all the grayscale data to be displayed, a new segment is added, which is used to display all the remaining display time in the grayscale data to be displayed, for example Figure 5 In the fourth segment, when the first three segments cannot display all the grayscale data to be displayed, the grayscale data to be displayed except the first three segments is displayed in the fourth segment. The fourth segment does not need to specially configure the register group to set the display time, but determines the display time according to the value of the first register group.

[0070] The method provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference can be made to the corresponding content in the aforementioned embodiment.

[0071] Example 3:

[0072] A driving circuit for optimizing LED display coupling, see Figure 6 , including a serial-to-parallel data processing module, a storage module, a grouping register module, a grouping algorithm module and a display output module;

[0073] The external serial input data is connected to the input end of the serial-to-parallel data processing module, the output end of the serial-to-parallel data processing module is connected to the input end of the display output module through the storage module, the output end of the serial-to-parallel data processing module is also connected to the input end of the display output module through the grouping register module and the grouping algorithm module in series, the control end of the display output module is connected to the control end of the grouping algorithm module, and the output end of the display output module outputs display data and transmits it to the LED display screen.

[0074] Specifically, the driver circuit receives external serial input data via a serial interface. The serial-to-parallel data processing module converts the external serial input data into parallel data, which is then distributed to a storage module (e.g., an SRAM module) and a group register module. The group register module configures the display time for each segment and then sends the configuration data from the group register module to the group algorithm module for calculation. The calculation result is sent to the display output module, which then outputs the display data based on the grayscale data stored in the storage module and the calculation result, and transmits it to the LED display for display. The control terminal of the display output module is connected to the group algorithm module, which controls the group algorithm module to stop counting during the shadow clamping time.

[0075] Figure 7 The following is a timing diagram of a display example. CLK is the input clock, DISPLAY is the display signal, and ROW is the row break signal. The time period between every two pulses in ROW corresponds to the row display area. Figure 7 The middle bank display area is configured with three second register groups, which include four display time segments. Figure 7 In the example, n can be set to 4 through hardware configuration and the shadow clamping time can be set to 8 CLK clock cycles through software configuration. Assume that the data configured in the second register group corresponding to the first segment is 16, the data configured in the second register group corresponding to the second segment is 13, and the data configured in the second register group corresponding to the third segment is 30.

[0076] (1) The time period T1-T0 is the blanking and clamping time of the display signal configured in the column controller.

[0077] (2) If the amount of grayscale data to be displayed is 300, the display time of the first segment = T2-T1 = 16*4T clk, the display time of the second segment = T4-T3 = 13*4T clk, the display time of the third segment = T6-T5 = 30*4T clk, and the display time of the fourth segment = 300T clk-16*4T clk-13*4T clk-30*4T clk = 64T clk.

[0078] (3) If the amount of grayscale data to be displayed is 50, since 50<display time of the first segment 16*4=64, the display time of the first segment is 50T clk, and the second, third, and fourth segments are not displayed.

[0079] (4) If the amount of grayscale data to be displayed is 100, since 100-the display time of the first segment 16*4=36<the display time of the second segment 13*4=52, the display time of the first segment is 16*4T clk, the display time of the second segment is 36T clk, and the third and fourth segments are not displayed.

[0080] (5) If the amount of grayscale data to be displayed is 150, since 150-display time of the first segment 16*4-display time of the second segment 13*4=34<display time of the third segment 30*4, the display time of the first segment is 16*4Tclk; the display time of the second segment is 13*4Tclk; the display time of the third segment is 34Tclk, and the fourth segment is not displayed.

[0081] (6) T7-T6=T5-T4=T3-T2=preset shadow clamping time, for example, set to 8clk.

[0082] The circuit provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0083] Example 4:

[0084] Example 4 Based on the above example, the following contents are added:

[0085] See also Figure 8 The group register module includes several register groups, each register group is a k*8bit register group consisting of k registers; the register group includes a first register group and multiple second register groups, the first register group is used to configure the total display time, and the second register group is used to configure the display time of each segment;

[0086] The output ends of the registers in each register group form a register group bus, the clock end of the register is connected to the input clock; and the input end of the register receives external configuration data.

[0087] Specifically, Figure 8 The group register module in the contains four 8-bit register groups. REG1 is the first register group, used to configure the total display duration. REG2 is the second register group corresponding to the first segment. REG3 is the second register group corresponding to the second segment. REG4 is the second register group corresponding to the third segment.

[0088] Figure 9 This is the pinout diagram for a single register in the grouped register module. ck is the register's clock terminal, d is the register's input terminal, e is the data input terminal for verifying the register's data flow, si is the enable terminal for verifying the register's data flow, sn is the register's reset terminal (active low), and qb is the register's output terminal. The normal operation of a register is as follows: si is turned off, and the register is turned on for normal operation. During the non-rising edge of ck, the register stores the data at d. During the rising edge of ck, the value stored in d is output at qb.

[0089] Preferably, the grouping algorithm module includes a counter and a plurality of operation modules; the input clock is connected to the input end of the counter; the control end of the counter serves as the control end of the grouping algorithm module;

[0090] The operation module is composed of a comparator; the output end of the counter is connected to one input end of the comparator, the output end of the register group in the group register module or the output end of the adder in any operation module is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module;

[0091] And / or, the operation module is composed of a comparator and an adder; the output ends of any two register groups in the grouped register module, or the output ends of the adders in any two operation modules, or the output end of any register group in the grouped register module and the output end of the adder in any operation module are respectively connected to the two input ends of the adder; the output end of the adder is connected to one input end of the comparator, the output end of the counter is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module.

[0092] Preferably, in the operation module composed of a comparator, the register group in the group register module connected to an input end of the comparator is the first register group or the second register group.

[0093] See also Figure 10 The operation module 1 is composed of a comparator, one input end of which is connected to the output end REG2 of the register group corresponding to the first segment in the group register module, and is used to compare the output end of the counter with the output end of the register group corresponding to the first segment. If the data are the same, an enable signal is output to indicate that the first segment has been displayed.

[0094] Operation module 2 consists of a comparator and an adder. The output ends of the register groups corresponding to the first segment and the second segment in the grouped register module are respectively connected to the two input ends of the adder to add the output values of the two register groups. The output value of the adder (REG2+REG3) is then compared with the value of the counter. If the data are the same, an enable signal is output, indicating that the second segment has been displayed and completed.

[0095] The operation module 3 is composed of a comparator and an adder. The output end of the adder in the operation module 2 and the output end of the register group corresponding to the third segment in the group register module are respectively connected to the two input ends of the adder, so as to add the result of the adder in the operation module 2 and the value of the register group corresponding to the third segment, that is, to obtain the addition of the values of the register groups corresponding to the first three segments. Then, the output value of the adder (REG2+REG3+REG4) is compared with the value of the counter. If the data are the same, an enable signal is output, indicating that the display of the third segment has been completed.

[0096] The operation module 4 is composed of a comparator, one input end of which is connected to the output end of the first register group in the group register module, and is used to compare the output end of the counter with the output end REG1 of the first register group. If the data are the same, an enable signal is output to indicate that the fourth segment has been displayed.

[0097] The circuit provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0098] Embodiment 5:

[0099] A driver chip that optimizes LED display coupling,

[0100] Including the above-mentioned driving circuit.

[0101] The chip provided in the embodiment of the present invention is briefly described. For matters not mentioned in the embodiment part, reference may be made to the corresponding contents in the aforementioned embodiment.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and description of the present invention.

Claims

1. A driving method for optimizing LED display screen coupling, characterized in that: The following steps are involved: Receive the grayscale data to be displayed on each line of the LED display; The total display duration and the display time of each segment are set by configuring multiple register groups; the register groups include a first register group and multiple second register groups, the first register group is used to configure the total display duration, and the second register group is used to configure the display time of each segment; Displaying the grayscale data to be displayed in segments according to the value of the register group, wherein the display time of two adjacent segments is separated by a preset blanking clamping time; The segmented display of the grayscale data to be displayed according to the value of the register group specifically includes: when a line feed signal is received, starting a counter to count the input clock; segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment; when the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, displaying the grayscale data of the next segment, and during the display process, when the blanking clamp time is reached, pausing the counter counting.

2. The driving method for optimizing LED display coupling according to claim 1, characterized in that: When the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, displaying the grayscale data of the next segment specifically includes: Display the grayscale data of the first segment; When the value of the counter is greater than the sum of the values of the i-th segment and all the second register groups corresponding to the segment before the i-th segment, the grayscale data of the i+1-th segment is displayed, where i≥1.

3. The driving method for optimizing LED display coupling according to claim 1, characterized in that: When the value of the counter is greater than the sum of the values of the second register group corresponding to one or more consecutive segments, displaying the grayscale data of the next segment specifically includes: When the value of the counter is greater than n times the sum of the values of the second register group corresponding to one or more consecutive segments, the grayscale data of the next segment is displayed, where n≥1.

4. The driving method for optimizing LED display screen coupling according to claim 1, characterized in that: The step of segmenting the grayscale data to be displayed according to the value of the second register group to obtain grayscale data of each segment specifically includes: The grayscale data to be displayed is divided into j+1 segments according to the values of the j second register groups, wherein the first j segments respectively correspond to one of the second register groups.

5. A driving circuit for optimizing LED display screen coupling, characterized in that: The driving circuit adopts the driving method according to any one of claims 1 to 4, and the driving circuit includes a serial-to-parallel data processing module, a storage module, a grouping register module, a grouping algorithm module and a display output module; The external serial input data is connected to the input end of the serial-to-parallel data processing module, the output end of the serial-to-parallel data processing module is connected to the input end of the display output module through the storage module, the output end of the serial-to-parallel data processing module is further connected to the input end of the display output module by sequentially connecting the grouping register module and the grouping algorithm module in series, the control end of the display output module is connected to the control end of the grouping algorithm module, and the output end of the display output module outputs display data and transmits it to the LED display screen; The group register module includes a plurality of register groups, including a first register group and a plurality of second register groups, the first register group is used to configure the total display duration, and the second register group is used to configure the display time of each segment; The output ends of the registers in each register group form a register group bus, the clock end of the register is connected to the input clock; and the input end of the register receives external configuration data.

6. The driving circuit for optimizing LED display screen coupling according to claim 5, characterized in that: Each register group is a k*8bit register group consisting of k registers.

7. The driving circuit for optimizing LED display screen coupling according to claim 6, characterized in that: The grouping algorithm module includes a counter and a plurality of operation modules; the input clock is connected to the input end of the counter; the control end of the counter serves as the control end of the grouping algorithm module; The operation module is composed of a comparator; the output end of the counter is connected to one input end of the comparator, the output end of the register group in the group register module is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module; And / or, the operation module is composed of a comparator and an adder; the output ends of any two register groups in the grouped register module, or the output ends of the adders in any two operation modules, or the output end of any register group in the grouped register module and the output end of the adder in any operation module are respectively connected to the two input ends of the adder; the output end of the adder is connected to one input end of the comparator, the output end of the counter is connected to the other input end of the comparator, and the output end of the comparator is connected to the input end of the display output module.

8. The driving circuit for optimizing LED display screen coupling according to claim 7, characterized in that: In the operation module composed of a comparator, the register group in the group register module connected to an input terminal of the comparator is the first register group or the second register group.

9. A driver chip for optimizing LED display screen coupling, characterized in that: The driving circuit comprises the driving circuit according to any one of claims 5 to 8.

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