Capacitive structures for memory write assist

Abstract

A write assist circuit (106) facilitates increasing a voltage applied to a memory device (100) in changing a logic state of a memory cell (101) during a write operation. The write assist circuit includes a second capacitor line structure (116) or "metal cap" that selectively applies a voltage to one of a pair of bit lines (113, 114) in addition to a first capacitor line structure (115) coupled to one of a pair of bit lines (113, 114). The capacitor line structure provides increased write assist to the memory device. In some implementations, the second capacitor line is structurally positioned in a second orientation and is formed in a second metal layer of an integrated circuit relative to the first capacitor line. The additional capacitor line provides negative bit line assist by selectively driving its corresponding bit line negative during a write operation.

Description

Background Art

[0001] A bitline is a conductor or trace that couples a memory cell write driver to a memory cell. In static read access memory (SRAM) and other memories, a conventional negative bitline write assist (NBWA) circuit uses a pull-down voltage to provide a negative voltage supply or negative ground reference for a write driver on one of the bitlines. Such a technique is useful in writing a zero ("0") value into a memory cell that stores a one ("1") value at a first time and a zero ("0") value at a second time. Conventional NBWA circuits typically include a bias capacitor configured to provide a ground reference. However, because such bias capacitors consume a large amount of space, and because floorplan space on an integrated circuit is limited, it is typically not feasible to provide sufficient capacitance via such conventional bias capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] By referring to the accompanying drawings, the present disclosure may be better understood, and its numerous features and advantages may become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or equivalent items.

[0003] Figure 1 is a block diagram of an array of capacitive structures and memory cells according to some embodiments.

[0004] Figure 2 is a graph of voltages when a capacitive structure is coupled to a memory cell according to some implementations.

[0005] Figure 3 is a block diagram of a two-dimensional array of capacitive structures of memory cells according to some embodiments.

[0006] Figure 4 According to some embodiments, Figure 1 A block diagram of a cross-sectional view of line 1-1.

[0007] Figure 5 is a flow chart of a method of using a capacitive structure of a memory cell according to some embodiments. DETAILED DESCRIPTION

[0008] The ever-increasing demand for memory has led to the placement of a large number of memory cells on an integrated circuit (IC) or a system-on-chip (SOC). A memory device includes an array of memory cells arranged in columns and rows of silicon. For convenience, the physical columns of memory cells are usually grouped into logical columns of memory cells. Column circuits and row circuits facilitate access to a single memory cell. A column of memory cells or a row of memory cells represents a string of data bits. These memory cells include a structure configured to store one or more information bits. Memory cells are also referred to herein as bit cells. Many memory architectures implemented by such memory devices use bit line pairs, bit lines (BL) and their complementary bit lines ( / BL) to electrically couple each memory cell in a group (i.e., a column) of memory cells across bit line pairs in parallel to read and write memory cell contents. The write driver applies a voltage across the bit lines of the corresponding bit line pairs to write the corresponding value into the memory cell. In order to provide additional capacitance to the write driver, as further described herein, additional capacitor lines or "capacitor (cap)" lines are added to the memory architecture. According to some embodiments, the second capacitor line is substantially orthogonal to the first capacitor line.

[0009] Additional capacitor lines bring benefits to memory architectures and memory circuits. For large ICs and SOCs, relatively high statistical differences in "writability" will occur between memory cells on a processed silicon wafer because some memory cells are weaker and more difficult to write to than other memory cells for various reasons. If a memory cell is more difficult to write, it may not be possible to successfully write to the memory cell by a typical voltage Vdd applied to the bit line pair. Low power supply voltages may exacerbate this problem. The ability to write to a memory cell is improved by raising the applied voltage below the ground potential (negatively boosting the voltage applied to the bit line pair). In the described memory architecture, in order to improve the negative boost, one or more additional capacitor lines or capacitor line structures are coupled to one or both of the bit line and its bit line complement. The write driver selectively applies a capacitive boost from the additional capacitor line structure during a write operation. Although reference may be made to applying additional capacitance to the bit line, during a write operation, since the write data line is also typically electrically coupled to the memory cell while the bit line is coupled to the memory cell, the capacitance is also typically applied to the write data line.

[0010] Figure 11 is a block diagram of an array of capacitive structures and memory cells according to some embodiments. Memory device 100 includes columns and rows of memory cells 101. According to some embodiments, memory device 100 is implemented on an integrated circuit (IC) die. That is, according to some embodiments, memory device 100 is part of IC die 121. In various embodiments, memory cell 101 is implemented as one or more of the following: a static random access memory (SRAM) cell implemented using a field effect transistor (FET), a dynamic static random access memory (DRAM) cell implemented using a capacitor, or other types of memory cells known in the art.

[0011] Each memory cell 101 is accessed by a corresponding bit line 102 and word line 103. In a two-phase read or write operation, for each write operation, a row of memory cells 101 is first activated by a word line driver 104 through a corresponding word line 103, and then activated by a bit line write driver 106 through a bit line 102. In some embodiments, as part of a read operation, a bit line sense circuit 105 accesses each memory cell 101. For simplicity of illustration, a single bit line 102 is shown for each column of memory cell columns 101. As indicated by label 111, each bit line 102 is actually a bit line pair: a bit line 113 (a first bit line) and a bit line complement 114 (a second bit line), as further explained herein. The word line driver 104 is configured to selectively activate a row of memory cells 101 through a word line 103 for a particular operation. An activated bit line 102 can only access memory cells 101 in the activated row, because only one row is activated at a time for a write operation. The bit line 102 and word line 103 are conductive lines or traces configured to provide a low resistance path between the bit line write driver 106 and the word line driver 104 , respectively.

[0012] In label 111, more details of memory cell 101 and capacitive structures are shown. First bit line 113 is labeled "BL" and second bit line 114 is labeled " / BL. Second bit line 114 is the bit line complement of first bit line 113. A first capacitive line structure 115 labeled "CAP 1" is positioned in parallel with first bit line 113 and a first write data (WD1) line 117 labeled "WD1" on a first side of memory cell 112. A second capacitive line structure 116 labeled "CAP 2" is positioned in parallel with a second write data (WD2) line 118 on a second side of memory cell 112. Word line 103 is labeled "WL". WD2 line 118 is located on a third side of memory cell 112. According to some embodiments, and as Figure 1As shown, the second capacitive line structure 116 is coupled to the first capacitive line structure 115 through a conductive via 120. The via 120 is composed of a conductive material and is configured to provide a low resistance path between the first (column) capacitive line structure 115 and the second (row) capacitive line structure 116.

[0013] In reference 111, although the first bit line 113 is located between the first capacitor line structure 115 and the memory cell 112, in other embodiments, the first capacitor line structure 115 extends between the first bit line 113 and the first side of the memory cell 112. In other embodiments, the first capacitor line structure 115 extends parallel to the second bit line 114. According to some embodiments, a first capacitor line structure 115 is provided for each column of memory cells 101 in the memory device 100, and a second capacitor line structure 116 is provided for each word line 103 in the memory device 100. In such an embodiment, each memory cell 112 is provided with a pair of capacitor lines 115, 116.

[0014] According to some embodiments, in a write operation, word line 103 is activated with a memory write voltage source, and then first bit line 113 and second bit line 114 are activated by causing bit line write driver 106 to couple bit line 113 or bit line complement 114 to the memory write voltage source. According to some embodiments, during this write operation, word line 103 is disconnected from the memory write voltage. Then, first capacitor line structure 115 or second capacitor line structure 116 is coupled to one of first bit line 113 or bit line complement 114, such as through coupling transistor 119, to provide capacitive coupling or capacitive boosting to memory cell 112. Bit line write driver 106 performs capacitive coupling by activating coupling transistor 119. According to some embodiments, coupling transistor 119 is a component of bit line write driver 106, but alternatively, is a component of write data line driver 104. In annotation 111, when activated, bit line write assist is provided by a structure including a combination of first capacitor line structure 115 and second capacitor line structure 116.

[0015] According to some embodiments, the bit line write driver 106 includes a charge pump (not shown) coupled to the first capacitive line structure 115. The charge pump generates a negative voltage and continuously maintains a predetermined voltage level on the first capacitive line structure 115. During a phase of a write operation, the bit line write driver 106 provides a control signal that causes one of the bit lines 113, 114 to be first pulled to ground or some other predetermined reference voltage, and then pulled to a relatively negative voltage, for example, to negative 150 millivolts (mV) when a negative bit line write assist is provided to the memory cell 112.

[0016] For example, negative bit line write assist is used when writing a low value in a write operation when the memory cell 112 holds a high value. For example, when writing to the memory cell 112, a logic level high corresponds to, for example, but not limited to, a voltage in the range of 0.5 to 1 volt, 0.7 to 1.2 volts, 1 to 2 volts, 1 to 3 volts, 3 to 15 volts, or any of other voltages or other signal levels. A logic level low corresponds to, for example, but not limited to, a voltage in the range of 0 to 0.5 volts, -0.1 to 0.4 volts, -1.5 to 0 volts, or any of other voltages or other signal levels. Typically, according to some embodiments, one of the bit lines 113, 114 is coupled to a first capacitive line structure 115 to facilitate negative bit line write assist. A second capacitive line structure 116 provides increased capacity to store charge during a write operation to the memory cell 112.

[0017] According to other embodiments, when the memory cell 112 is a DRAM type memory cell, as is known in the art, the increased capacity of the second capacitive line structure 116 coupled to the first capacitive line structure 115 helps absorb negative charge when the memory cell 112 is charged to a "1" value. During a write operation, the activation of the coupling transistor 119 parasitically exposes the memory cell 112 to the combination of the first capacitive line structure 115 and the second capacitive line structure 116, which more effectively releases the stored charge from the memory cell 112 than using only the first capacitive line structure 115. Subsequently, the bit line write driver 106 applies a write voltage to one of the bit lines 113, 114. Therefore, the subsequently applied write voltage is more likely to successfully change the value stored in the memory cell 112.

[0018] The first capacitor line structure 115 is an example of a capacitor line structure for the memory device 100, which includes one or more metal lines or traces implemented at one or more metal layers of an IC die, the IC die 121 of the memory device 100 being fabricated with multiple metal layers interposed with insulating layers as is known in the art, the metal layers and insulating layers being the type of device layers used for the memory device 100. Figure 1In some embodiments, the first capacitor line structure 115 is located in a first metal layer of the memory device 100, and the second capacitor line structure 116 is located in a second metal layer of the memory device 100. In addition, the first capacitor line structure 115 is in a first orientation or first direction in the IC die 121, and the second capacitor line structure 116 is in a different second orientation or second direction in the memory device 100. In the case of limited space in the memory device 100, the available capacitance is increased by electrically coupling the column and row capacitor line structures 115, 116 so that they form a larger overall capacitive structure than is seen in conventional memory structures. In particular, the capacitance provided by the capacitive structure formed by the capacitor line structures 115, 116 is a function of the total length, width, and thickness of the capacitor line structures 115, 116 and each write data line 117, 118. In some implementations, by capacitively coupling the first bit line 113 to the first capacitive line structure 115 , which in turn is coupled to the second capacitive line structure 116 through the via 120 , the capacitive behavior of the memory device 100 is enhanced beyond conventional memory structures.

[0019] The capacitance present on one or more capacitive line structures, such as capacitive line structures 115, 116, at least in part, determines the maximum frequency at which memory cell 112 can operate. According to some embodiments, a higher capacitance in the combination of first capacitive line structure 115 and second capacitive line structure 116 corresponds to a higher resistance-capacitance (RC) time constant, which corresponds to a slower charging and discharging time of one or more of bit lines 113, 114. Thus, the total available capacitance defines the frequency at which data bits are transferred to memory cell 112 via bit lines 113, 114, thereby defining the speed of an operational write cycle of memory cell 112. Thus, capacitive line structures 115, 116 are designed and fabricated to have certain characteristics that enhance the efficiency and effectiveness of write operations of a memory device having a memory cell, such as memory device 100 having memory cell 112.

[0020] Figure 2200 is a graph of voltages when a capacitive structure is coupled to a memory cell according to some embodiments. During a write operation, a write signal ("write") changes from a first value 201 to a second value 202. In a write operation, a word line is activated and then a bit line and its bit line complement are activated. According to some embodiments, during this write operation, a bit line write driver performs a two-stage capacitive boost by coupling a first capacitive line structure to the bit line to provide a first capacitive boost, i.e., a first negative bit line write assist, to the memory cell and then coupling a second capacitive line structure to the bit line to provide a second capacitive boost. In other embodiments, during a write operation, both the first capacitive line structure and the second capacitive line structure are electrically coupled and then coupled to the bit line at a specified time.

[0021] Applying a two-stage capacitive boost, the bias capacitor voltage ("BIAS_CAP_OUT") at the memory cell changes from a first capacitance value 203 to a second capacitance value 204. The bit line write driver performs a first capacitive coupling by activating, for example, a first coupling transistor. According to another embodiment, during a write operation, the bit line write driver couples a second capacitive line structure to the bit line to provide a second capacitive boost, i.e., a second negative bit line write assist, to the memory cell. The bias capacitor voltage at the memory cell changes from the second capacitance value 204 to a third capacitance value 205. Figure 2 In , capacitive boosting is in addition to and occurs after writing a value to the memory cell.

[0022] Figure 3 is a block diagram of a circuit 300 including a two-dimensional array of capacitive structures of memory cells according to some embodiments. The circuit 300 includes a two-dimensional array of capacitive line structures for memory cells arranged in rows numbered 0 to N-1 and vertical columns 0 to M-1. For each row, a first capacitive line structure extending in a first orientation (e.g., in row [0]) is electrically coupled to a second capacitive line structure (e.g., in column [0]) through a conductive body. For clarity of illustration, the memory cells are omitted, but the bit lines and capacitive line structures are shown and are coupled to, for example, Figure 1 The annotation 111 and Figure 2, as is known in the art. The first column [0] corresponds to the first column of memory cells coupled to the word line and the column of available capacitive structures. In operation, the word line driver will be coupled to the rows [0] to [M-1] of the word lines and configured to identify one of the rows of memory cells for a write operation based on a row selector component that receives a row select signal. In addition, the bit line write driver will be coupled to the columns of the word lines and configured to identify one of the columns of memory cells for a write operation based on a column selector component that receives a column select signal. The bit line write driver will then be able to employ a capacitive line structure for a write operation, as further described herein.

[0023] The write data lines 302, 303 (labeled “WDT[0]” and “WDC[0]”) of the first row [0] are divided by a first capacitive line structure 304 labeled “capacitor.” In other embodiments, the first capacitive line structure 304 is positioned proximate to the first write data line WDT 302, the first write data line complement WDC 303, or both the first write data line WDT 302 and the first write data line complement WDC 303. The write data lines 312, 313 (labeled “WDT[1]” and “WDC[1]”) of the second row [1] are divided by a first capacitive line structure 314. In other embodiments, the first capacitive line structure 314 in the second row [1] is positioned proximate to the second write data line WDT 312, the second write data line complement WDC 313, or both the second write data line WDT 312 and the second write data line complement WDC 313 of the second row. The write data lines 322, 323 of the third row [N-1] (labeled as "WDT[N-1]" and "WDC[N-1]") are divided by a first capacitive line structure 324. In other embodiments, the first capacitive line structure 324 of the third row is positioned adjacent to the third write data line WDT 322, the third write data line complement WDC 323, or both the third write data line WDT 322 and the third write data line complement WDC 323 of the third row. The third row represents the Nth row, which shows that in a case such as Figure 3 An arbitrary number of rows of memory cells are arranged in the circuit of circuit 300 .

[0024] Intersecting the first write data lines 302, 303 is the first vertical column [0] of the write data lines 332, 333 and the first of the second capacitor line structures 334. Any number of columns such as rows 0, 1 and M-1 of the write data lines and the second capacitor line structures may intersect and couple with the first write data lines 302, 303, the second write data lines 312, 313 and the third write data lines 322, 323 and the corresponding first capacitor line structures 304, 314 and 324, respectively, as desired. For example, in the second column [1], the write data lines 342, 343 and the capacitor line structure 344 intersect with: (1) the first write data lines 302, 303 and the first capacitor line structure 304; (2) the second write data lines 312, 313 and the second capacitor line structure 314; and (3) the third write data lines 322, 323 and the third capacitor line structure 324.

[0025] In circuit 300, the first group of write data lines 332, 333 cross the second and third groups of write data lines 312, 313 and 322, 323, respectively, but are not electrically coupled to these second and third write data lines. Instead, only the first row of write data lines 302, 303 are electrically coupled to the first group of write data lines 332, 333 through conductive bodies 305, 307. Similarly, the second capacitor line structure 334 of the first column [0] is not electrically coupled to the second capacitor line structure 314 and the third capacitor line structure 324. Instead, only the first capacitor line structure 304 is electrically coupled to the first vertical "second" capacitor line structure 334 through conductive bodies 306, thereby providing increased capacitance for the write data lines 332, 333. The same scheme is applied to the second set of write data lines 342, 343 and second capacitor line structures 344 via vias 315, 316, 317, where these structures in the second column [1] are coupled only to corresponding structures in the second row of structures 312-314 and cross over with other columns of structures without electrical connection. The scheme is repeated for the last column of write data lines 352, 353 and second capacitor line structures 354, where these structures in the last column [M-1] are coupled only to corresponding structures in the last row [N-1] of structures 322-324 via vias 325, 326, 327 and cross over with other columns of structures without electrical connection. Only one set of vias is applied to the lines at each row / column combination, such as along Figure 3 In general, and according to the embodiments shown, a column of a set of structures is electrically coupled to only one row of a set of structures. According to some embodiments, the electrical structures of the columns are formed on a different layer than the electrical structures of the rows.

[0026] exist Figure 3In the embodiment of the present invention, the first capacitive line structures 304, 314 and 324 extend substantially the entirety of the first length along the first direction of the circuit 300, and the second capacitive line structures 334, 344 and 354 extend substantially the entirety of the second length along the second direction of the circuit 300. When activated by a write data line controller (not shown) and a bit line write controller (not shown), the plurality of second capacitive structures 334, 344, 354 of the plurality of rows 0 to M-1 provide increased capacitance to the circuit 300 to one or more corresponding memory cells coupled to the write data lines 302, 303, 312, 313, 323, 324 and the write data lines 332, 333, 342, 343, 352, 353. In operation, according to some embodiments, when the memory cells are activated, when the capacitive boost is turned on, the capacitive boost is applied to all columns. According to other embodiments, the capacitive boost is applied to a single column, such as at the first set of write data lines 332, 333.

[0027] The write data lines 332, 342, and 352 are arranged in a second orientation (e.g., a vertical orientation from top to bottom or from bottom to top) relative to the write data lines 302, 312, and 322. Similarly, the write data line complements 333, 343, and 353 are arranged in a second orientation (e.g., a vertical orientation from top to bottom or from bottom to top) relative to the write data line complements 303, 313, and 323. In addition, the second capacitive line structures 334, 344, and 354 are arranged in a second orientation (e.g., a vertical orientation from top to bottom or from bottom to top) relative to the first capacitive line structures 304, 314, and 324, and the first capacitive line structures are arranged in a first orientation (e.g., a horizontal orientation from left to right or from right to left).

[0028] According to some embodiments, the write data lines 332, 342, and 352, the write data line complements 333, 343, and 353, and the second capacitor line structures 334, 344, 354 are arranged in a substantially coplanar second layer, such as in a (WDT) second metal layer (e.g., metal 3 (M3), metal 4 (M4), metal 5 (M5)), as described with respect to Figure 4 According to some embodiments, the second capacitor line structures 334, 344, 354 are arranged substantially orthogonal or perpendicular to the first capacitor line structures 304, 314, 324. Figure 3, while the second capacitor line structures 334, 344, and 354 are shown as metal lines, in other embodiments, the second capacitor line structures 334, 344, and 354 are made of other materials and are part of another type of layer, as is known in the art. Although shown as lines, in other embodiments, the second capacitor line structures 334, 344, and 354 are formed and arranged in shapes other than lines, including rectangular plates, square areas, spiral traces, etc. For example, in some embodiments, the second capacitor line structures 334, 344, and 354 are arranged on multiple metal or conductive layers in the circuit 300, which is similar to the arrangement of elements of an n-channel MOSFET or a metal-insulator-metal capacitor (MIMcap) across multiple layers of the circuit.

[0029] Circuit 300 illustrates a write data line and a capacitive structure such as capacitor line structures 304, 314, 324, 334, 344, and 354 of memory device 321 according to an embodiment of the present disclosure. In general, the architecture for a memory device employing circuit 300 may include other structures as are known in the art. For example, although not shown, according to Figure 3 The device may also include: a row or write data driver, a column or bit line driver, and a memory cell. Figure 3 As shown, the memory cell lines are arranged into rows and columns, where each column or row represents a string of data bits, also called a word or byte.

[0030] Despite Figure 3 300, the first group of capacitor line structures 304, 314, 324 are shown as extending parallel to the write data lines, but in other embodiments, the first group of capacitor line structures are formed in the same direction as the second group of capacitor line structures parallel to the write data lines. That is, the capacitor line structures 304, 314, 324 are positioned parallel to the second group of capacitor line structures 334, 344, 345. In addition, in some embodiments, the capacitor line structures 304, 314, 324 are formed in the same or different metal layer as the capacitor line structures 334, 344, 345, depending on the specific design and application of the specific circuit 300.

[0031] Figure 4 According to some embodiments, Figure 11-1 of the circuit 400. The circuit 400 includes a base layer 401 on which other circuit layers are fabricated. Metal layers 402, 404, 406, 408, 410 are interlaced with insulating layers 403, 405, 407, 409 to form the circuit 400. Although five metal layers are shown, any number of metal and insulating layers can be fabricated together to form transistors, inverters, conductive bodies, capacitor line structures, and other elements as known in the art. The structure of the memory cell is fabricated in the lower layer 411 of the fifth metal layer 410 or in the layer above the upper surface 413 (not shown). The first capacitor line structure 115 marked as "CAP 1" is fabricated in the fourth metal layer 408. The bit line 113 and the bit line complement 114 are also fabricated in the fourth metal layer 408. The conductive body 120 is fabricated in, through, or in and through the fourth insulating layer 409. The second capacitor line structure 116 marked as "CAP 2" is fabricated in the fourth metal layer 410. Although in Figure 4 4, but the write data line will be parallel to the second capacitor line structure 116 in the fifth metal layer 410 and will be coupled to the write data line driver at the first edge 412 of the fifth metal layer 410 of the circuit 400. Figure 4 As shown, additional capacitance for capacitive boosting of bit line write assist is facilitated by the combination of first capacitive line structure 115 electrically coupled to second capacitive line structure 116 to improve capacitive boosting of memory cells coupled to bit line 113 and bit line complement 114 .

[0032] Figure 5 A method 500 for operating a memory cell of a memory device using a bit line or a write data line having a capacitive structure according to some embodiments is shown. Figure 1 Method 500 is described with reference to an exemplary embodiment of a memory device 100 of FIG. 501. At block 502, a memory voltage is disconnected from the memory cell by applying a memory voltage to a write data line, a bit line, or a combination of a write data line and a bit line. At block 503, a first capacitor line structure and a second capacitor line structure are coupled to a bit line, such as bit line 113, or to a memory cell, such as a memory cell. Figure 1 The first capacitor line structure is coupled to the second capacitor line structure, for example, through an interlayer conductive body. The first capacitor line structure and the second capacitor line structure provide a negative write assist voltage to the memory cell.

[0033] Although top, bottom, left, right, vertical, and horizontal are used herein, these directional terms are only for convenience in reference to the orientation shown in the corresponding figures, and are not necessarily with reference to a fixed reference system, such as with reference to gravity or the horizon. Unless otherwise specified, such reference terms to a component are only with reference to another component, especially with respect to describing one component with reference to another component in a particular figure. Columns of memory cells and rows of memory cells can be shown in a vertical orientation or a horizontal orientation relative to the corresponding figures. Similarly, rows of memory cells can be shown in a horizontal orientation or a vertical orientation relative to the corresponding figures.

[0034] It should be noted that not all activities or elements described above in the general description are required, a portion of a particular activity or device may not be required, and one or more other activities may be performed, or elements other than those described may be included. In addition, the order in which the activities are listed is not necessarily the order in which the activities are performed. In addition, concepts have been described with reference to specific embodiments. However, it will be appreciated by those of ordinary skill in the art that various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the appended claims. Therefore, this specification and the drawings will be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure.

[0035] The benefits, other advantages, and problem solutions have been described above with respect to specific embodiments. However, the benefits, advantages, problem solutions, and any features that may make any benefit, advantage, or problem solution appear or become more prominent should not be interpreted as being key, essential, or necessary features of any or all claims. In addition, the specific embodiments disclosed above are merely illustrative, because the disclosed subject matter may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings herein. Except as described in the appended claims, it is not intended to limit the details of the construction or design shown herein. Therefore, it is obvious that the specific embodiments disclosed above may be changed or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as stated in the appended claims.

Claims

1. A memory device, comprising: a set of memory cells; a first capacitive line structure in a first metal layer, the first capacitive line structure coupled to the group of memory cells, wherein the first capacitive line structure is linear in the first metal layer in a first direction and extends through a first plurality of memory cells; a second capacitive line structure of a second metal layer, the second capacitive line structure coupled to the group of memory cells, wherein the second capacitive line structure is linear in the second metal layer in a second direction and extends through a second plurality of memory cells, the second direction being perpendicular to the first direction; a conductive body electrically coupling the first capacitive line structure to the second capacitive line structure; as well as and a bit line write driver coupled to the group of memory cells and at least one of the first capacitor line structure and the second capacitor line structure, the bit line write driver being configured to selectively couple the first capacitor line structure and the second capacitor line structure to memory cells in the group of memory cells, thereby applying a write assist voltage to at least one memory cell in the group of memory cells during a write operation.

2. The memory device of claim 1, wherein the bit line write driver couples the first capacitive line structure to the memory cell before coupling the second capacitive line structure to the memory cell.

3. The memory device of claim 1, wherein the first metal layer is separated from the second metal layer by an insulating layer.

4. The memory device of claim 1 , wherein the bit line write driver is further configured to capacitively couple one or more of the first capacitor line structure and the second capacitor line structure to one of a plurality of physical bit lines during the write operation.

5. The memory device of claim 1 , further comprising: a first bit line and a first bit line complement in the first metal layer, wherein the first capacitive line structure or the second capacitive line structure is positioned adjacent to and in parallel with one of the first bit line and the first bit line complement; and A second bit line and a second bit line complement in the first metal layer, wherein the first capacitor line structure or the second capacitor line structure is adjacent to and positioned in parallel with one of the second bit line and the second bit line complement.

6. A memory device comprising: a bit cell including a structure for storing a bit value; a first pair of bit lines coupled to the bit cells, the first pair of bit lines being in a first metal layer; a pair of write data (WD) lines; a first capacitance line adjacent to one of the pair of write data lines, wherein the first capacitance line is linear in a first direction and extends through a first plurality of memory cells; a second capacitor line adjacent to the other of the pair of write data lines, wherein the second capacitor line is linear in a second direction perpendicular to the first direction and extends through a second plurality of memory cells; a first conductive body electrically coupling the first capacitance line to the second capacitance line; as well as A bit line write driver is coupled to the first pair of bit lines, the pair of write data lines, and at least one of the first capacitance line and the second capacitance line to apply a negative voltage to the first pair of bit lines during a negative write assist operation.

7. The memory device of claim 6, wherein the first capacitor line is in the first metal layer, and wherein at least one of the pair of write data lines is in a second metal layer different from the first metal layer.

8. The memory device of claim 6, wherein the first capacitor line is in a different metal layer than a metal layer of the second capacitor line.

9. The memory device of claim 6, further comprising: A write data driver is coupled to the first pair of bit lines to drive the first pair of bit lines in response to a state of a signal provided to the write data driver, the write data driver using the first capacitor line and the second capacitor line for a write assist operation on the bit cell.

10. A method of operating a memory cell of an integrated circuit die, the method comprising: disconnecting the memory unit from the write driver; as well as After disconnecting the memory cell from the write driver, a first capacitor line oriented in a first direction and extending through a first plurality of memory cells and a second capacitor line oriented in a second direction and extending through a second plurality of memory cells are simultaneously capacitively coupled to a bit line or a bit line complement of the memory cell to provide a negative write assist voltage to the memory cell.

11. The method of claim 10, further comprising: providing a negative write assist signal to provide the negative write assist voltage to the memory cell; as well as A zero or one value is written into the memory cell.

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