Display device

Abstract

A display device is disclosed. The display device includes a hole pattern of an upper conductive layer and a lower conductive layer that are arranged in a peripheral region of the display device and are asymmetric with respect to an opening of an insulating layer of the display device. A first one of the hole patterns may coincide with a second one of the hole patterns in a part of the peripheral region, while the first one of the hole patterns may intersect the second one of the hole patterns in another part of the peripheral region.

Description

Technical Field

[0001] The present disclosure generally relates to display devices, and more particularly, to configurations for preventing and reducing degradation of the quality of a displayed image caused by introduction of impurities and electrical interference in a region adjacent to a display region of a display device. Background Art

[0002] Recently, various types of display devices having a minimized thickness and thus a minimized weight have been developed. As a result, there are many different types of uses for such display devices and they are continuously evolving. In addition to flat panel display devices, some of these display devices also include foldable display devices or rollable display devices.

[0003] In these and other types of display devices, since the ability to interpret an image is fundamental to the desired use of a particular display device, it is desirable to avoid degradation of the quality of the displayed image. Summary of the Invention

[0004] Embodiments relate to a display device for preventing and reducing degradation of the quality of a displayed image caused by introduction of impurities and electrical interference in a region adjacent to a display region of a display device.

[0005] According to an embodiment, the display device includes a substrate, an insulating layer, a first conductive layer, and a second conductive layer. The substrate includes a display region and a peripheral region surrounding the periphery of the display region. The peripheral region includes a first peripheral region and a second peripheral region. The insulating layer includes a first insulating layer and a second insulating layer respectively disposed in the display region, the first peripheral region, and the second peripheral region, and a first opening penetrating the first insulating layer and the second insulating layer between the first peripheral region and the second peripheral region. The first conductive layer includes a first hole disposed in the first peripheral region and a second hole disposed in the second periphery. And the second conductive layer is disposed on the first conductive layer and includes a third hole disposed in the first peripheral region and a fourth hole disposed in the second peripheral region, wherein a part of the first hole and a part of the third hole overlap each other, and the second hole and the fourth hole are offset from each other.

[0006] The first conductive layer may be disposed on the first insulating layer, and the second conductive layer may be disposed on the second insulating layer.

[0007] The second conductive layer may be disposed above the first opening.

[0008] The display device may further include a first electrode, an emission layer, and a second electrode. The first electrode is disposed in the display region and on the second insulating layer. The emission layer is located on the first electrode, and the second electrode faces the first electrode.

[0009] The display device may further include a third insulating layer disposed on the second insulating layer and including a second opening and a third opening, a part of the first electrode being exposed through the second opening, and a part of the second conductive layer being exposed through the third opening.

[0010] The second electrode may be in contact with the second conductive layer in the third opening.

[0011] The third insulating layer may further include a fourth opening in which a first opening is disposed.

[0012] The second conductive layer and the first electrode may be disposed on the same layer.

[0013] The second electrode may be disposed above a part of the second peripheral region.

[0014] The display device may further include a contact portion in contact with the first conductive layer and the second conductive layer.

[0015] The display device may further include a first signal line and a second signal line. The first signal line is disposed between the substrate and the first conductive layer in the second peripheral region, and the second signal line is disposed on the second conductive layer in the second peripheral region.

[0016] A varying voltage may be applied to the first signal line and the second signal line.

[0017] The display device may further include a packaging layer disposed between the second signal line and the second conductive layer.

[0018] The display device may further include a power line in the second peripheral region disposed on the same layer as the first signal line, the power line being in contact with an edge of the first conductive layer.

[0019] The display device may further include a driving circuit disposed in the first peripheral region and below the first conductive layer.

[0020] The first hole and the third hole may overlap to coincide with each other and face each other.

[0021] The second hole and the fourth hole are offset to be spatially opposite in terms of positioning and sequence.

[0022] According to an embodiment, a display device includes a substrate, a first insulating layer, a second insulating layer, a first opening, a first conductive layer, and a second conductive layer. The substrate includes a display area and a peripheral area surrounding the periphery of the display area. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the first insulating layer, and each of the first insulating layer and the second insulating layer is disposed in the display area and the peripheral area. The first opening penetrates the first insulating area and the second insulating area in the peripheral area. The first conductive layer is disposed on the first insulating layer and has a first hole pattern. And the second conductive layer is disposed on the second insulating layer and has a second hole pattern, wherein the first hole pattern and the second hole pattern overlap each other in a region between the display area and the first opening, and the first hole pattern and the second hole pattern intersect each other in a region between the first opening and the edge of the substrate.

[0023] The display device may further include a first electrode, a third insulating layer, an emission layer, and a second electrode. The first electrode is disposed on the second insulating layer. The third insulating layer is disposed on the second insulating layer and includes a second opening and a third opening. A part of the first electrode is exposed through the second opening, and a part of the second conductive layer is exposed through the third opening. The emission layer is disposed on the second opening. And the second electrode faces the first electrode.

[0024] The second electrode may be in contact with the second conductive layer in the third opening.

[0025] The second conductive layer and the first electrode may be disposed on the same layer.

[0026] The display device may further include a contact portion in contact with the first conductive layer and the second conductive layer.

[0027] The first hole pattern and the second hole pattern may overlap each other in a region between the display area and the first opening to face each other.

[0028] The first hole pattern and the second hole pattern may intersect each other to be spatially opposite in terms of positioning and order in a region between the first opening and the edge of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] When considered in conjunction with the accompanying drawings, the following description according to an embodiment, these and / or other aspects will become apparent and easier to understand, in the drawings:

[0030] Figure 1 is a perspective view schematically showing a display device according to an embodiment;

[0031] Figure 2 is a plan view schematically showing a display panel according to an embodiment;

[0032] Figure 3 is an equivalent circuit diagram schematically showing a pixel of the display panel;

[0033] Figure 4 is a plan view schematically showing a peripheral region of a display panel according to an embodiment;

[0034] Figure 5 is schematically showing Figure 4 an enlarged plan view of a part of the display panel;

[0035] Figure 6 is a view omitting Figure 5 a part of the configuration;

[0036] Figure 7 is a cross-sectional view taken along line II-II' of Figure 6 ;

[0037] Figure 8 is a plan view schematically showing a peripheral region of a display panel according to another embodiment;

[0038] Figure 9 is schematically showing Figure 8 a plan view of a part of the display panel;

[0039] Figure 10 is along Figure 9 a cross-sectional view taken along line III-III' of;

[0040] Figure 11 is a plan view schematically showing an input sensing layer according to an embodiment;

[0041] Figure 12 is a plan view schematically showing a display panel and an input sensing layer of a display device according to an embodiment;

[0042] Figure 13 is schematically showing along Figure 12 a cross-sectional view of a part of a display area adjacent to a peripheral region taken along line III-III';

[0043] Figure 14 is schematically showing along Figure 12 a cross-sectional view of a part of a peripheral region adjacent to a display area taken along line IV-IV'; and

[0044] Figure 15 and Figure 16 is schematically showing according to another embodiment a cross-sectional view of a part of a display area and a peripheral region taken along line III-III' and line IV-IV' of Figure 12 . Detailed Description

[0045] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" after a list of elements modify the entire list of elements, rather than individual elements in the list.

[0046] Although the present disclosure may be modified in various ways and have additional embodiments, embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the present disclosure is not limited to the embodiments in the drawings and the specification, and should be construed to include all changes, equivalents, and substitutions included within the spirit and scope of the present disclosure.

[0047] The drawings and the description are considered illustrative only in nature and thus do not limit the embodiments described and claimed herein. Some parts in sections not relevant to the specification may not be provided to describe the embodiments of the present disclosure, and the same reference numerals indicate the same elements throughout the specification.

[0048] In the drawings, for better understanding and ease of description, the dimensions and thicknesses of each element are arbitrarily shown, however, the present disclosure is not limited thereto. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated. In the drawings, for better understanding and convenience of description, the thicknesses of some layers and regions may be exaggerated.

[0049] In the specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" after a list of elements modify the entire list of elements, rather than individual elements in the list. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms.

[0050] In addition, in the specification, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a sectional view" means when a cross-section obtained by vertically cutting the object portion is viewed from the side. Further, the terms "overlap" or "overlapped" mean that a first object may be located above or below a second object, and vice versa. When a layer, film, region, substrate, or area is referred to as being "on" another layer, film, region, substrate, or area, it may be directly on the other layer, film, region, substrate, or area, or there may be intervening layers, films, regions, substrates, or areas therebetween. In contrast, when a layer, film, region, substrate, or area is referred to as being "directly on" another layer, film, region, substrate, or area, there may be no intervening layers, films, regions, substrates, or areas therebetween. In addition, when a layer, film, region, substrate, or area is referred to as being "under" another layer, film, region, substrate, or area, it may be directly under the other layer, film, region, substrate, or area, or there may be intervening layers, films, regions, substrates, or areas therebetween. In contrast, when a layer, film, region, substrate, or area is referred to as being "directly under" another layer, film, region, substrate, or area, there may be no intervening layers, films, regions, substrates, or areas therebetween. Further, "above" or "on" may include being positioned above or below an object and does not necessarily imply a gravity-based direction.

[0051] Spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to facilitate describing the relationship between one element or component and another element or component, as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in the case where the device shown in the figures is flipped, a device positioned "below" or "beneath" another device may be placed "above" the other device. Accordingly, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, and thus, the spatial relative terms may be interpreted differently depending on the orientation.

[0052] Throughout the specification, when an element is referred to as being "connected" to another element, the element can be "directly connected" to the other element or "electrically connected" to the other element through one or more intermediate elements therebetween. It should also be understood that when the terms "comprise", "comprising", "include" and / or "including" are used in this specification, they or it may indicate the presence of the stated features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of other features, wholes, steps, operations, elements, components and / or any combination thereof.

[0053] It should be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or for the convenience of its description and explanation. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings herein.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that unless explicitly defined in this specification, terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0055] Figure 1 is a perspective view schematically showing a display device according to an embodiment.

[0056] Referring to Figure 1 , the display device 1 includes a light-emitting display area DA and a peripheral area PA surrounding the periphery of the display area DA. The peripheral area PA is a non-display area that does not emit light. The display device 1 can provide a specific image based on the light emitted from the pixels arranged in the display area DA.

[0057] Hereinafter, an organic light-emitting display device will be described as the display device 1 according to an embodiment. However, the display device according to an embodiment is not limited thereto. In another embodiment, various display devices such as an inorganic light-emitting display device, an inorganic electroluminescent (EL) display device, and a quantum dot light-emitting display device can be used. The display device 1 according to an embodiment can be a flexible display device such as a flat panel display device, a foldable display device, or a rollable display device.

[0058] The display device 1 may include a display panel 10 and an input sensing layer 40 positioned on the display panel 10. The display device 1 may be one of various electronic devices, such as a mobile phone, a laptop computer, and a smart watch or other smart devices.

[0059] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. The pixels may include display elements and pixel circuits connected to the display elements. The display elements may include organic light-emitting diodes, inorganic light-emitting diodes, or quantum dot light-emitting diodes, etc.

[0060] The input sensing layer 40 obtains coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and sensing signal lines connected to the sensing electrodes (or touch electrodes). The input sensing layer 40 may be positioned on the display panel 10.

[0061] The input sensing layer 40 may be directly formed on the display panel 10, or may be formed separately from the display panel 10 and then coupled to the display panel 10 via an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be continuously formed after the process of forming the display panel 10. Accordingly, the adhesive layer may not be positioned between the input sensing layer 40 and the display panel 10.

[0062] Although not shown, an optical function layer and a window may be sequentially positioned on the input sensing layer 40. In another embodiment, the input sensing layer 40 may be positioned on the optical function layer.

[0063] The optical function layer may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light (external light) incident on the display panel 10 from the outside via the window. The anti-reflection layer may include a retarder and a polarizer. The retarder may be of a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be of a film type or a liquid crystal coating type. The film type may include a stretched synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a specific arrangement. The retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or the protective film may be defined as a base layer of the anti-reflection layer.

[0064] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged considering the color of light emitted from each of the pixels of the display panel 10. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer arranged on different layers. The first reflected light and the second reflected light respectively reflected from the first reflective layer and the second reflective layer may be destructively interfered. Accordingly, the reflectance of external light may be reduced.

[0065] The optical functional layer may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or multiple layers having different refractive indices. The optical functional layer may include the above-mentioned antireflection layer and the lens layer or any one of them.

[0066] Figure 2 is a plan view schematically showing a display panel according to an embodiment, and Figure 3 is an equivalent circuit diagram schematically showing one pixel of the display panel.

[0067] Referring to Figure 2 , the display panel 10 includes a display area DA and a peripheral area PA. Figure 2 shows the appearance of the substrate 100 of the display panel 10. For example, it will be understood that the substrate 100 has a display area DA and a peripheral area PA.

[0068] The display panel 10 includes pixels P arranged in the display area DA. As Figure 3 shown, each of the pixels P includes a pixel circuit PC and an organic light-emitting display device (OLED) as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first transistor T1, a second transistor T2, and a capacitor Cst. Each pixel P may emit, for example, red light, green light, blue light, or white light through the OLED. The first transistor T1 and the second transistor T2 may be implemented with thin film transistors (TFTs).

[0069] The second transistor T2 may be a switching transistor connectable to a scan line SL and a data line DL, and may transmit a data signal input from the data line DL to the first transistor T1 according to a switching voltage input from the scan line SL. The capacitor Cst may be connected to the second transistor T2 and a power supply line PL, and may store a voltage corresponding to the difference between the voltage corresponding to the data signal transmitted from the second transistor T2 and the first power supply voltage ELVDD supplied to the power supply line PL.

[0070] The first transistor T1 may be a driving transistor, connectable to the power supply line PL and the capacitor Cst, and may control a driving current flowing through the OLED from the power supply line PL according to the voltage value stored in the capacitor Cst. Due to the driving current, the OLED may emit light with a certain brightness. The second electrode (e.g., cathode) of the OLED may receive a second power supply voltage ELVSS.

[0071] Figure 3 shows that the pixel circuit PC includes two transistors and one capacitor. However, the embodiment is not limited thereto. For example, various modifications may be made to the number of transistors and the number of capacitors according to the design of the pixel circuit PC.

[0072] Return reference Figure 2 The scan driver 1100 that supplies a scan signal to each pixel P, the data driver 1200 that supplies a data signal to each pixel P, supply lines (e.g., clock signal lines, carry signal lines, and driving voltage lines, etc.) that supply signal inputs to the scan driver 1100 and the data driver 1200, and main power supply lines for supplying a first power supply voltage ELVDD and a second power supply voltage ELVSS may be arranged in the peripheral area PA. Figure 2 It is shown that the data driver 1200 is adjacent to one side of the substrate 100. However, in another embodiment, the data driver 1200 may be positioned on a flexible printed circuit board (FPCB) and electrically connected to pads positioned on one side of the display panel 10.

[0073] Figure 4 is a plan view schematically showing a peripheral area of a display panel according to an embodiment, Figure 5 is schematically shown Figure 4 an enlarged plan view of a part of the display panel of Figure 6 is a view omitting Figure 5 a part of the configuration of Figure 7 is along Figure 6 a cross-sectional view taken along line II-II' of

[0074] Refer to Figures 4 to 7 According to an embodiment, the display panel 10A includes a substrate 100 having a display area DA and a peripheral area PA outside the display area DA.

[0075] The first conductive layer 150 and the second conductive layer 160 positioned on the first conductive layer 150 may be arranged in the peripheral area PA. The first conductive layer 150 may be positioned on the first insulating layer 115. The first insulating layer 115 may be positioned on the insulating surface 120. The insulating surface 120 may be the top surface of the substrate 100 or the top surface of at least one insulating layer above the substrate 100. The second insulating layer 116 may be positioned between the first conductive layer 150 and the second conductive layer 160.

[0076] A first insulating layer 115 and a second insulating layer 116 may have a first opening OP1 penetrating through the first insulating layer 115 and the second insulating layer 116. A width W1 of the first opening OP1 may be a width of an open surface in contact with the insulating surface 120. The first opening OP1 may surround a periphery of the display area DA. The first opening OP1 may form a closed loop completely surrounding the periphery of the display area DA. Accordingly, the first insulating layer 115 may include a first area 115a and a second area 115b separated from each other based on the first opening OP1. Similarly, the second insulating layer 116 may include a first area 116a and a second area 116b separated from each other based on the first opening OP1. Hereinafter, a peripheral area between the display area DA and the first opening OP1 is referred to as a first peripheral area PA1, and a peripheral area between the first opening OP1 and an edge of the substrate 100 is referred to as a second peripheral area PA2, and an area including the first opening OP1 between the first peripheral area PA1 and the second peripheral area PA2 is referred to as a third peripheral area PA3.

[0077] A first conductive layer 150 may surround a periphery of the display area DA. The first conductive layer 150 may include a first area 150a and a second area 150b separated from each other based on the first opening OP1. The first area 150a of the first conductive layer 150 may be located in the first peripheral area PA1, and the second area 150b of the first conductive layer 150 may be located in the second peripheral area PA2. The first conductive layer 150 may have a first hole pattern including first holes 150H1 arranged in a specific pattern in the first area 150a and second holes 150H2 arranged in a specific pattern in the second area 150b.

[0078] In Figure 6 order to Figure 5 more clearly show the above-described first hole pattern and second hole pattern, the second electrode 251 is omitted. The first holes 150H1 of the first conductive layer 150 may be spaced apart from each other by a certain distance in the x direction and the y direction so as not to overlap each other when arranged on a plane (which may be a plane parallel to the surface of the substrate 100). For example, the first holes 150H1 of the first conductive layer 150 may be adjacent to at least one vertex of four vertices of a virtual rectangle IS1. The second holes 150H2 of the first conductive layer 150 may be spaced apart from each other by a certain distance in the x direction and the y direction so as not to overlap each other on the plane. For example, the second holes 150H2 of the first conductive layer 150 may be adjacent to at least one of four vertices of a virtual rectangle IS2.

[0079] The second conductive layer 160 may surround the periphery of the display area DA. The second conductive layer 160 may be positioned on the first conductive layer 150 and may overlap with the first conductive layer 150. The second conductive layer 160 may cover (i.e., be disposed) above the first opening OP1. The second conductive layer 160 may include a first region 160a located in the first peripheral region PA1, a second region 160b located in the second peripheral region PA2, and a third region 160c located in the first opening OP1. The second conductive layer 160 may have a second hole pattern, which includes third holes 160H1 arranged in a specific pattern in the first region 160a and fourth holes 160H2 arranged in a specific pattern in the second region 160b.

[0080] Referring Figure 6 , the third holes 160H1 of the second conductive layer 160 may be spaced apart from each other at a certain distance in the x-direction and the y-direction, and may not overlap with each other on the plane. When disposed on the plane, the third holes 160H1 of the second conductive layer 160 may be arranged to overlap with the first holes 150H1 of the first conductive layer 150. For example, the third holes 160H1 may be adjacent to at least one of the four vertices of the virtual rectangle IS1. The fourth holes 160H2 of the second conductive layer 160 may be spaced apart from each other at a certain distance in the x-direction and the y-direction so as not to overlap with each other when disposed on the plane. For example, based on each of the fourth holes 160H2 of the second conductive layer 160, the fourth holes 160H2 of the second conductive layer 160 may be adjacent to at least one of the four vertices of the virtual rectangle IS3. When disposed on the plane, the fourth holes 160H2 of the second conductive layer 160 may be arranged not to overlap with the second holes 150H2 of the first conductive layer 150. For example, the second holes 150H2 of the first conductive layer 150 may be arranged adjacent to each other in the x-direction and / or the y-direction between the fourth holes 160H2 of the second conductive layer 160. The fourth holes 160H2 of the second conductive layer 160 may be arranged adjacent to each other in the x-direction and / or the y-direction between the second holes 150H2 of the first conductive layer 150.

[0081] Referring Figure 7, in the first peripheral region PA1, at least a portion of the first hole 150H1 of the first conductive layer 150 and at least a portion of the third hole 160H1 of the second conductive layer 160 may overlap with each other in the z-direction (vertical direction). In the second peripheral region PA2, the second hole 150H2 of the first conductive layer 150 and the fourth hole 160H2 of the second conductive layer 160 do not overlap with each other in the z-direction (i.e., the vertical direction) and may be arranged in a zigzag pattern so as to intersect each other when arranged on a plane. That is, as discussed above, in the first peripheral region PA1, the first hole pattern of the first conductive layer 150 including the first hole 150H1 and the second hole pattern of the second conductive layer 160 including the third hole 160H1 may coincide with each other, and in the second peripheral region PA2, the first hole pattern of the first conductive layer 150 including the second hole 150H2 and the second hole pattern of the second conductive layer 160 including the fourth hole 160H2 may intersect each other to arrange the holes respectively. Return reference Figure 4 and Figure 5 , the second electrode of the OLED (see Figure 13 and Figure 14 251) may be positioned on the first conductive layer 150 and the second conductive layer 160. The second electrode 251 of the OLED may cover the display region DA and may extend to cover a part of the peripheral region PA. The second electrode 251 of the OLED may cover the first peripheral region PA1 and the third peripheral region PA3. The second electrode 251 of the OLED may cover a part of the second peripheral region PA2 surrounding the first opening OP1.

[0082] Thus, as discussed above, an example arrangement of the first hole 150H1 and the second hole 150H2 of the first conductive layer 150 and the third hole 160H1 and the fourth hole 160H2 of the second conductive layer 160 has been provided.

[0083] Continuing to refer to Figures 4 to 7 , this example arrangement arranges the first hole 150H1 and the third hole 160H1 to overlap (i.e., coincide) with each other in the first peripheral region PA1 to face each other so that when observed in a plan view or a cross-sectional view, the first hole 150H1 and the third hole 160H1 are aligned to be aligned with each other. However, in the second peripheral region PA2, this example arrangement arranges the second hole 150H2 and the fourth hole 160H2 to intersect or not overlap with each other (i.e., not coincide) so that the second hole 150H2 and the fourth hole 160H2 are not aligned with each other in terms of their positioning and order in the x-direction or the y-direction, but are offset or spatially relative. Therefore, when observed in a plan view and a cross-sectional view, the second hole 150H2 is spaced apart from the fourth hole 160H2 and alternates with the fourth hole 160H2 in terms of positioning and order.

[0084] Figure 8is a plan view schematically showing a peripheral region of a display panel according to another embodiment,

[0085] Figure 9 is a plan view schematically showing Figure 8 a part of the display panel, and Figure 10 is a cross-sectional view taken along line Figure 9 III-III' of. In Figure 10 the second electrode 251 of Figure 9 is omitted.

[0086] In the embodiment of Figure 8 , the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other via a first contact portion CNT1 and a second contact portion CNT2 that can be added to the embodiment of Figure 4 . Hereinafter, a detailed description of a configuration identical to that of Figures 4 to 7 will be omitted.

[0087] Referring to Figures 8 to 10 , a display panel 10B according to an embodiment includes a substrate 100 having a display area DA and a peripheral area PA outside the display area DA. The peripheral area PA may include a first peripheral area PA1 located between the display area DA and a first opening OP1 and a second peripheral area PA2 located between the first opening OP1 and an edge of the substrate 100.

[0088] The first insulating layer 115 and the second insulating layer 116 may be arranged in the display area DA and the peripheral area PA, and a first opening OP1 penetrating the first insulating layer 115 and the second insulating layer 116 may be located in the peripheral area PA.

[0089] The first conductive layer 150 may include a first region 150a located in the first peripheral area PA1 and a second region 150b located in the second peripheral area PA2 that are separated from each other based on the first opening OP1. The first conductive layer 150 may include a first hole pattern including first holes 150H1 arranged in a specific pattern in the first region 150a and second holes 150H2 arranged in a specific pattern in the second region 150b. The second conductive layer 160 may include a first region 160a located in the first peripheral area PA1, a second region 160b located in the second peripheral area PA2, and a third region 160c located in the first opening OP1. The second conductive layer 160 may include a second hole pattern including third holes 160H1 arranged in a specific pattern in the first region 160a and fourth holes 160H2 arranged in a specific pattern in the second region 160b.

[0090] In a first peripheral region PA1, at least a portion of a first hole 150H1 of the first conductive layer 150 and at least a portion of a third hole 160H1 of the second conductive layer 160 may overlap in the z-direction (i.e., the vertical direction). In a second peripheral region PA2, a second hole 150H2 of the first conductive layer 150 and a fourth hole 160H2 of the second conductive layer 160 may not overlap in the z-direction, but may be arranged in a zigzag pattern so as to intersect each other when arranged on a plane.

[0091] In the first peripheral region PA1, the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other at a first contact portion CNT1. The second insulating layer 116 may include a contact hole located in the first contact portion CNT1, and the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other via the contact hole of the first contact portion CNT1. In the second peripheral region PA2, the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other at a second contact portion CNT2. The second insulating layer 116 may include a contact hole located in the second contact portion CNT2, and the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other via the contact hole in the second contact portion CNT2.

[0092] The second electrode 251 of the OLED may be positioned on the first conductive layer 150 and the second conductive layer 160. The second electrode 251 of the OLED may cover the display area DA and may extend to cover a portion of the peripheral area PA.

[0093] In an embodiment, a first opening OP1 is formed in the peripheral area PA such that the peripheral area PA may be separated from the display area DA. Accordingly, it is possible to prevent gas generated, for example, in the first insulating layer 115 and the second insulating layer 116 outside the first opening OP1, such as from the second peripheral region PA2 away from the display area DA, from reaching the inside of the display area DA.

[0094] In an embodiment, the hole patterns of the first conductive layer 150 and the second conductive layer 160 stacked in the peripheral area PA are asymmetric with respect to the first opening OP1 of the first insulating layer 115 and the second insulating layer 116. That is, such hole patterns may not be mirror images of each other so that they are arranged differently with respect to the first opening OP1.

[0095] Contrary to the embodiments described herein, in a case where the first hole 150H1 of the first conductive layer 150 and the third hole 160H1 of the second conductive layer 160 in the first peripheral region PA1 do not overlap and do not intersect with each other, the gas generated in the first insulating layer 115 is delayed by the first conductive layer 150 and is not easily discharged. Therefore, shrinkage may occur in the display device 1. However, in the disclosed embodiments, in the first peripheral region PA1, the first hole 150H1 of the first conductive layer 150 and the third hole 160H1 of the second conductive layer 160 overlap with each other. Thus, the gas in the first insulating layer 115 and the second insulating layer 116 can be easily discharged to the outside, so that shrinkage of the display device 1 can be prevented. That is, the gas generated by the first insulating layer 115 can pass through the first hole 150H1 and then enter the second insulating layer 116 to be discharged through the third hole 160H1 with or without the gas generated by the second insulating layer 116.

[0096] Moreover, in the embodiment, the second hole 150H2 of the first conductive layer 150 and the fourth hole 160H2 of the second conductive layer 160 intersect with each other in the second peripheral region PA2. Therefore, in the second peripheral region PA2, due to the arrangement of the second hole 150H2 and the fourth hole 160H2, the first conductive layer 150 and the second conductive layer 160 can prevent coupling between signal lines to which a varying voltage (i.e., a non-constant voltage) is applied when such signal lines are arranged below the first conductive layer 150 and above the second conductive layer 160. For example, in the second peripheral region PA2, the first conductive layer 150 and the second conductive layer 160 can prevent coupling between a signal line (e.g., a clock signal line of a driver) located below the first conductive layer 150 and a signal line (e.g., a sensing signal line of an input sensing layer) located above the second conductive layer 160.

[0097] Figure 4 and Figure 7 The shapes, sizes, and densities of the first hole 150H1 and the second hole 150H2 of the first conductive layer 150 and the third hole 160H1 and the fourth hole 160H2 of the second conductive layer 160 shown in and are exemplary. Therefore, the shapes of the first hole 150H1 and the second hole 150H2 of the first conductive layer 150 and the third hole 160H1 and the fourth hole 160H2 of the second conductive layer 160 can be rectangular, circular, elliptical, or polygonal other than rectangular, and can have other different shapes and sizes.

[0098] Figure 4 and Figure 8The first conductive layer 150 and the second conductive layer 160 shown in [Fig. 0] are positioned to completely surround the periphery of the display area DA along the four sides of the outer periphery of the substrate 100 and form a closed loop. However, the embodiments are not limited thereto. For example, the first conductive layer 150 and the second conductive layer 160 may be positioned at at least one side of the four sides of the substrate 100. In an embodiment, the first conductive layer 150 and the second conductive layer 160 may be positioned along the remaining three sides except the side where the data driver 1200 is positioned, and may have a "C" shape.

[0099] Figure 11 is a plan view schematically showing an input sensing layer according to an embodiment.

[0100] Referring to Figure 11 , the input sensing layer 40 may include a base layer BL, and the base layer BL includes a display area DA and a peripheral area PA. The base layer BL may correspond to the shape of the substrate 100 of the display panel 10, and may be set to have substantially the same shape as the substrate 100. In an embodiment, the base layer BL may be a part of the encapsulation layer of the display panel 10 (see Figure 13 and Figure 14 300), and for example, may be the second inorganic encapsulation layer 330 positioned on the outermost layer of the encapsulation layer 300. In another embodiment, the base layer BL may be an insulating substrate or an insulating film formed of an insulating material such as glass or a polymer resin, which is formed separately from the encapsulation layer 300.

[0101] The sensing electrode TSE may be positioned in the display area DA. The sensing signal lines connected to the sensing electrode TSE may be positioned in the peripheral area PA. The sensing electrode TSE may include a first sensing electrode 410 and a second sensing electrode 420. The sensing signal lines may include a first sensing signal line 450A and a second sensing signal line 450B. That is, the input sensing layer 40 may include a first sensing electrode 410, a first sensing signal line 450A connected to the first sensing electrode 410, a second sensing electrode 420, and a second sensing signal line 450B connected to the second sensing electrode 420. The input sensing layer 40 may sense an external input using a mutual capacitance method and / or a self-capacitance method.

[0102] The first sensing electrode 410 and the second sensing electrode 420 may have a substantially diamond shape. The first sensing electrode 410 and the second sensing electrode 420 may have a grid structure (or lattice structure) having holes therein. The line width of each of the lattice lines may be several micrometers. The holes of the first sensing electrode 410 and the second sensing electrode 420 may correspond to the emission regions of the OLED 200 (i.e., the regions where the emission layers are arranged).

[0103] The first sensing electrodes 410 may be arranged in the y direction, and the second sensing electrodes 420 may be arranged in the x direction intersecting the y direction. The first sensing electrodes 410 arranged in the y direction may be connected to each other via first connection electrodes between adjacent first sensing electrodes 410, and may form a first sensing line 410C. The second sensing electrodes 420 arranged in the x direction may be connected to each other via second connection electrodes between adjacent second sensing electrodes 420, and may form a second sensing line 420R. The first sensing line 410C and the second sensing line 420R may intersect each other. For example, the first sensing line 410C and the second sensing line 420R may be perpendicular to each other.

[0104] The first sensing line 410C and the second sensing line 420R may be arranged in the display area DA, and may be connected to the sensing signal pads 440 via a first sensing signal line 450A and a second sensing signal line 450B in the peripheral area PA. The first sensing line 410C may be connected to the first sensing signal line 450A, and the second sensing line 420R may be connected to the second sensing signal line 450B.

[0105] The first sensing electrodes 410 and the second sensing electrodes 420 may be formed on the same layer. The first sensing electrodes 410 may be connected to each other via connection electrodes formed on different layers. The second sensing electrodes 420 may be connected to each other via connection electrodes formed on the same layer. At least one insulating layer may be arranged between connection electrodes arranged on a layer different from the layer on which the first sensing electrodes 410 and the second sensing electrodes 420 are arranged.

[0106] The first sensing electrodes 410 and the second sensing electrodes 420 may include a metal. For example, the first sensing electrodes 410 and the second sensing electrodes 420 may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a multi-layer structure or a single-layer structure including the above materials. In an embodiment, the first sensing electrodes 410 and the second sensing electrodes 420 may have a multi-layer structure of Ti / Al / Ti.

[0107] Figure 12 is a plan view schematically showing a display panel and an input sensing layer of a display device according to an embodiment. Hereinafter, detailed descriptions identical to those of Figure 8 and Figure 11 will be omitted.

[0108] Referring to Figure 12 , a display device 1' according to an embodiment may include a display panel 10C and an input sensing layer 40'.

[0109] The display panel 10C includes a substrate 100 having a display area DA and a peripheral area PA located outside the display area DA. The peripheral area PA may include a first peripheral area PA1 located between the display area DA and the first opening OP1 and a second peripheral area PA2 located between the first opening OP1 and the edge of the substrate 100.

[0110] The first conductive layer 150 and the second conductive layer 160 may be arranged in the peripheral area PA.

[0111] The first conductive layer 150 may have a first hole pattern including a first hole 150H1 arranged in a specific pattern in the first peripheral area PA1 and a second hole 150H2 arranged in a specific pattern in the second peripheral area PA2, wherein the first peripheral area PA1 and the second peripheral area PA2 are separated from each other based on the first opening OP1. The second conductive layer 160 may have a second hole pattern including a third hole 160H1 arranged in a specific pattern in the first peripheral area PA1 and a fourth hole 160H2 arranged in a specific pattern in the second peripheral area PA2.

[0112] In the first peripheral area PA1, at least a part of the first hole 150H1 of the first conductive layer 150 and at least a part of the third hole 160H1 of the second conductive layer 160 may overlap each other when arranged on a plane. In the second peripheral area PA2, the second hole 150H2 of the first conductive layer 150 and the fourth hole 160H2 of the second conductive layer 160 may not overlap each other when arranged on a plane and may be arranged in a zigzag pattern so as to intersect each other. In the first peripheral area PA1, the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other at the first contact portion CNT1. In the second peripheral area PA2, the first conductive layer 150 and the second conductive layer 160 may be electrically connected to each other at the second contact portion CNT2.

[0113] The second electrode 251 of the OLED may be positioned on the first conductive layer 150 and the second conductive layer 160. The second electrode 251 of the OLED may cover the display area DA and may extend to cover a part of the peripheral area PA.

[0114] The input sensing layer 40' may be positioned on the display panel 10C. The input sensing layer 40' may include sensing electrodes TSE arranged in the display area DA of the base layer BL. The sensing electrodes TSE may include a first sensing electrode 410 and a second sensing electrode 420. Although not shown, a first sensing signal line (see Figure 11 450A) connected to the first sensing electrode 410 and a second sensing signal line (see Figure 11450B) can be positioned in the peripheral area PA of the base layer BL. The base layer BL can be a part of the encapsulation layer 300 of the display panel 10C, or can be an insulating substrate or insulating film formed separately from the encapsulation layer 300.

[0115] Therefore, in the above-described embodiments, there is an exemplary arrangement that arranges the first hole 150H1 and the third hole 160H1 to overlap (i.e., coincide) with each other in the first peripheral area PA1 to face each other, such that the first hole 150H1 and the third hole 160H1 are aligned with each other when observed in a plan view or a cross-sectional view. However, in the second peripheral area PA2, such an exemplary arrangement arranges the second hole 150H2 and the fourth hole 160H2 to intersect or not overlap (i.e., not coincide) with each other, such that the second hole 150H2 and the fourth hole 160H2 are not aligned with each other in terms of their positioning and order in the x direction or the y direction, but are offset or spatially relative. Therefore, when observed in a plan view and a cross-sectional view, the second hole 150H2 is spaced apart from the fourth hole 160H2 and alternates with the fourth hole 160H2 in terms of positioning and order.

[0116] Figure 13 is a schematic cross-sectional view showing a part of the display area adjacent to the peripheral area taken along Figure 12 line III-III', and Figure 14 is a schematic cross-sectional view showing a part of the peripheral area adjacent to the display area taken along Figure 12 line IV-IV'. Hereinafter, descriptions will be provided with reference to Figure 13 and Figure 14 for reference.

[0117] The buffer layer 111 can be positioned on the substrate 100 to prevent impurities from penetrating into the semiconductor layer of the TFT.

[0118] The substrate 100 can be formed of various materials such as glass, metal materials, or plastics. In an embodiment, the substrate 100 can be a flexible substrate. For example, the substrate 100 can include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0119] The buffer layer 111 can include an inorganic insulating material such as silicon nitride or silicon oxide, and can have a single-layer structure or a multi-layer structure.

[0120] The first TFT, TFT1, the capacitor Cst, and the OLED 200 electrically connected to the first TFT, TFT1, may be positioned in the display area DA of the substrate 100. The OLED 200 electrically connected to the first TFT, TFT1, may include a first electrode 211 electrically connected to the first TFT, TFT1. The first TFT, TFT1, may be Figure 3 the first transistor T1.

[0121] The first TFT, TFT1, may include a semiconductor layer 132, a gate electrode 134, a source electrode 136S, and a drain electrode 136D. The semiconductor layer 132 may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. For example, considering the adhesion to adjacent layers, the surface flatness of the stacked layers, and the processability, the gate electrode 134 may be formed of one or more materials selected from the group consisting of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer structure or a multi-layer structure.

[0122] In order to obtain an insulating property between the semiconductor layer 132 and the gate electrode 134, a gate insulating layer 112 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be interposed between the semiconductor layer 132 and the gate electrode 134. A first interlayer insulating layer 113 and a second interlayer insulating layer 114 including an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride may be positioned between the gate electrode 134 and the source electrode 136S and the drain electrode 136D. Each of the source electrode 136S and the drain electrode 136D may be electrically connected to the semiconductor layer 132 via contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0123] In order to provide conductivity, the source electrode 136S and the drain electrode 136D may be formed of one or more materials selected from the group consisting of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, and Cu, and may have a single-layer structure or a multi-layer structure.

[0124] The capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other with the first interlayer insulating layer 113 interposed therebetween. The capacitor Cst may overlap with the first TFT, TFT1. In this regard, Figure 11 it is shown that the gate electrode 134 of the first TFT, TFT1, is the lower electrode CE1 of the capacitor Cst. In another embodiment, the capacitor Cst may not overlap with the first TFT, TFT1. The capacitor Cst may be covered with the second interlayer insulating layer 114.

[0125] The pixel circuit including the first TFT TFT1 and the capacitor Cst can be covered with the first insulating layer 115 and the second insulating layer 116. The first insulating layer 115 and the second insulating layer 116 can be a planarizing insulating layer and an organic insulating layer. The first insulating layer 115 and the second insulating layer 116 can include an organic insulating material, for example, a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene polymer, a vinyl alcohol-based polymer, and mixtures thereof. In an embodiment, the first insulating layer 115 and the second insulating layer 116 can include polyimide.

[0126] The first insulating layer 115 and the second insulating layer 116 can be located in the display area DA and the peripheral area PA of the substrate 100, and can have a first opening OP1 located in the peripheral area PA. Based on the first opening OP1, the first insulating layer 115 and the second insulating layer 116 can be physically separated from each other into at least two parts. This is to prevent impurities introduced from the outside (for example, gas or moisture generated in the first insulating layer 115 and the second insulating layer 116 outside the first opening OP1) from reaching the inside of the display area DA through the inside of the first insulating layer 115 and the second insulating layer 116.

[0127] The display element (for example, the OLED 200) can be located on the second insulating layer 116. The OLED 200 can include a first electrode 211 as a pixel electrode, an intermediate layer 231, and a second electrode 251 as a counter electrode.

[0128] The first electrode 211 of the OLED 200 can be located on the second insulating layer 116, and can be connected to the first TFT TFT1 via a connection electrode 181 on the first insulating layer 115. Input signal lines 183 such as data lines DL and power lines PL can be located on the first insulating layer 115.

[0129] The first electrode 211 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the first electrode 211 can include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. In another embodiment, the first electrode 211 can further include a layer formed of ITO, IZO, ZnO, or In2O3 on / under the above layer.

[0130] The third insulating layer 117 may be positioned on the second insulating layer 116 in the display area DA and the peripheral area PA. The third insulating layer 117 may have openings (i.e., second openings OP2) corresponding to each of the pixels in the display area DA, and at least the center of the first electrode 211 is exposed through the openings, thereby defining the pixels. Moreover, the third insulating layer 117 may increase the distance between the edge of the first electrode 211 and the edge of the second electrode 251, thereby preventing the generation of an arc at the edge of the first electrode 211. The third insulating layer 117 may be formed of an organic material such as polyimide (PI) or hexamethyldisiloxane (HMDSO).

[0131] The third insulating layer 117 may include a third opening OP3, a fourth opening OP4, and a fifth opening OP5. The second conductive layer 160 is exposed through the third opening OP3 in the first peripheral area PA1, the second conductive layer 160 in the first opening OP1 is exposed through the fourth opening OP4 in the third peripheral area PA3, and the second conductive layer 160 is exposed through the fifth opening OP5 in the second peripheral area PA2. Similar to the first opening OP1, the fourth opening OP4 may prevent impurities introduced from the outside (e.g., gas or moisture generated in the third insulating layer 117 outside the first opening OP1) from reaching the inside of the display area DA through the inside of the third insulating layer 117. The second insulating layer 116 and the third insulating layer 117 may be formed of the same organic material. However, the embodiments are not limited thereto. The width W2 of the fourth opening OP4 included in the third insulating layer 117 may be greater than the width W1 of the first opening OP1 included in the first insulating layer 115 and the second insulating layer 116. Therefore, the third insulating layer 117 may not be positioned in the first opening OP1.

[0132] The intermediate layer 231 includes an emission layer. The emission layer may include a polymer or a small-molecular-weight organic material that emits light of a specific color. In an embodiment, the intermediate layer 231 may include a first functional layer below the emission layer and / or a second functional layer on the emission layer. The first functional layer and / or the second functional layer may include a layer formed integrally on the plurality of first electrodes 211 and may include a layer patterned to correspond to each of the plurality of first electrodes 211.

[0133] The first functional layer may have a single-layer structure or a multi-layer structure. For example, when the first functional layer includes a polymer material, the first functional layer, which is a hole transport layer (HTL) having a single-layer structure, may include poly(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PAIN). When the first functional layer includes a small-molecular-weight material, the first functional layer may include a hole injection layer (HIL) and an HTL.

[0134] The second functional layer may not always be provided. For example, when the first functional layer and the emission layer include polymer materials, the second functional layer may be formed so that the OLED can operate optimally. The second functional layer may have a single-layer structure or a multi-layer structure. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0135] The second electrode 251 is positioned to face the first electrode 211 with the intermediate layer 231 interposed therebetween. The second electrode 251 may include a conductive material having a small work function. For example, the second electrode 251 may include a (semi)transparent layer having Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. As another example, the second electrode 251 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer including the above materials.

[0136] The second electrode 251 may be positioned in the display area DA and the peripheral area PA, and may be positioned on the intermediate layer 231 and the third insulating layer 117. The second electrode 251 may be integrally formed in the plurality of OLEDs 200 in the display area DA, and thus may face the plurality of first electrodes 211. The second electrode 251 may be positioned inside the third opening OP3 and the fourth opening OP4 of the third insulating layer 117 in the peripheral area PA, and may be in direct contact with the second conductive layer 160. The second electrode 251 may completely cover the first opening OP1. That is, the second electrode 251 may completely cover all areas of the first opening OP1. Therefore, a path through which impurities (such as gas or moisture) introduced from an area outside the first opening OP1 and generated in an organic material (such as the third insulating layer 117) may penetrate into the display area DA can be prevented from being formed. The second electrode 251 may also be positioned inside some of the fifth openings OP5 of the third insulating layer 117 in the peripheral area PA.

[0137] The second TFT TFT2 may be positioned in the peripheral area PA of the substrate 100. The second TFT TFT2 may be positioned in the first peripheral area PA1 and / or the second peripheral area PA2. The second TFT TFT2 may be a part of a circuit unit for controlling an electrical signal applied to the display area DA, for example, a scan driver. The second TFT TFT2 may include a semiconductor layer 142, a gate electrode 144, a source electrode 146S, and a drain electrode 146D. The second TFT TFT2 may be formed by the same process as the first TFT TFT1. Therefore, a detailed description of the second TFT TFT2 may be omitted.

[0138] A control signal line IW for applying a control signal to a circuit unit including a second TFT TFT2 may be positioned in a second peripheral region PA2. The control signal line IW may include signal lines for applying a clock signal, an inverted clock signal, a carry signal, etc. In Figure 11 the control signal line IW is positioned on a second interlayer insulating layer 114 on the same layer as the layer on which an active electrode 146S and a drain electrode 146D are positioned. However, embodiments are not limited thereto. For example, the control signal line IW may be positioned on the same layer as the layer on which a semiconductor layer 142 or a gate electrode 144 is positioned, or may be positioned on the same layer as the layer on which an upper electrode CE2 of a capacitor Cst is positioned.

[0139] The second TFT TFT2 and the control signal line IW may be covered with a first insulating layer 115 and a second insulating layer 116. The first insulating layer 115 may include a first region 115a and a second region 115b separated from each other based on a first opening OP1. The second insulating layer 116 may include a first region 116a and a second region 116b separated from each other based on the first opening OP1.

[0140] A first conductive layer 150 may be positioned on the layer between the first insulating layer 115 and the second insulating layer 116. The first conductive layer 150 may be positioned on the same layer as the layer on which a connection electrode 181 and an input signal line 183 are positioned. The first conductive layer 150 may be physically separated from a first peripheral region PA1 and a second peripheral region PA2 based on the first opening OP1. The first conductive layer 150 may include a first hole 150H1 and a second hole 150H2 arranged adjacent to the periphery of the first opening OP1. The first conductive layer 150 may include the first hole 150H1 located in the first peripheral region PA1 and the second hole 150H2 located in the second peripheral region PA2.

[0141] A second conductive layer 160 may be positioned on the second insulating layer 116. The second conductive layer 160 may be positioned on the same layer as the layer on which a first electrode 211 of an OLED 200 is positioned. The second conductive layer 160 may be formed of the same material as the material used to form the first electrode 211 and may completely cover the first opening OP1. The second conductive layer 160 may include a third hole 160H1 and a fourth hole 160H2 arranged adjacent to the periphery of the first opening OP1. The second conductive layer 160 may include the third hole 160H1 located in the first peripheral region PA1 and the fourth hole 160H2 located in the second peripheral region PA2.

[0142] In the first peripheral region PA1, a first hole 150H1 of the first conductive layer 150 and a third hole 160H1 of the second conductive layer 160 may overlap with each other in the z direction. The first hole 150H1 and the third hole 160H1 can be used as paths for gas generated from the first insulating layer 115 and the second insulating layer 116, which may each include an organic material, arranged below the first conductive layer 150 and the second conductive layer 160, to be discharged to the outside. Accordingly, deterioration of the image quality achieved by the display device 1 due to gas generated from the first insulating layer 115 and the second insulating layer 116 and penetrating into the display area DA can be prevented or reduced.

[0143] In the second peripheral region PA2, a second hole 150H2 of the first conductive layer 150 and a fourth hole 160H2 of the second conductive layer 160 may not overlap with each other in the z direction and may intersect with each other in the x direction and the y direction (in a plane). That is, in the second peripheral region PA2, the fourth hole 160H2 of the second conductive layer 160 may overlap with a peripheral region of the first conductive layer 150 that extends beyond the second hole 150H2 of the first conductive layer 150, and a peripheral region of the second conductive layer 160 that extends beyond the fourth hole 160H2 of the second conductive layer 160 may overlap with the second hole 150H2 of the first conductive layer 150.

[0144] In the above-described embodiment, an example arrangement is provided in which the first hole 150H1 and the third hole 160H1 are arranged to overlap (i.e., coincide) with each other in the first peripheral region PA1 so as to face each other, such that the first hole 150H1 and the third hole 160H1 are aligned with each other when observed in a plan view or a cross-sectional view. However, in the second peripheral region PA2, this example arrangement arranges the second hole 150H2 and the fourth hole 160H2 to intersect or not overlap (i.e., not coincide) with each other, such that the second hole 150H2 and the fourth hole 160H2 are not aligned with each other in terms of their positions and orders in the x direction or the y direction, but are offset or spatially opposite. Accordingly, when observed in a plan view and a cross-sectional view, the second hole 150H2 is spaced apart from the fourth hole 160H2 and alternates with the fourth hole 160H2 in terms of position and order.

[0145] Accordingly, the first conductive layer 150 or the second conductive layer 160 may be positioned on a layer between the conductive layer on the display panel 10 and the control signal line IW and may cover the control signal line IW, such that signal interference between the conductive layer on the display panel 10 and the control signal line IW can be prevented. The conductive layer on the display panel 10 may be the first sensing signal line 450A and / or the second sensing signal line 450B of the input sensing layer 40.

[0146] As Figure 8As shown, the first conductive layer 150 and the second conductive layer 160 may be in contact with each other at the first contact portion CNT1 and the second contact portion CNT2 to be electrically connected to each other. The edge of the first conductive layer 150 may be in contact with the edge of the second conductive layer 160 at the third contact portion CNT3. The first conductive layer 150 and the second conductive layer 160 may be in contact with the main power line PL' on the second interlayer insulating layer 114 at the third contact portion CNT3. As described above, the main power line PL' may be a line in the peripheral area PA to supply the second power voltage ELVSS to each pixel P. That is, the first conductive layer 150 and the second conductive layer 160 may be connection lines for connecting the main power line PL' for supplying power to the second electrode 251 and the first electrode 211.

[0147] The third insulating layer 117 may be positioned on the second conductive layer 160. At least a part of the second conductive layer 160 may be exposed through the third opening OP3, the fourth opening OP4, and the fifth opening OP5 of the third insulating layer 117. The second conductive layer 160 may be in contact with the second electrode 251 in the third opening OP3 and the fourth opening OP4 of the third insulating layer 117. The second conductive layer 160 may be in contact with the second electrode 251 in the fifth opening OP5.

[0148] The encapsulation layer 300 may be positioned on the second electrode 251 so that the display device 1 can be protected from external foreign substances or moisture. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 13 and Figure 14 It is shown that the encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order may be changed.

[0149] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials selected from the group consisting of alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride, and may be formed by chemical vapor deposition (CVD). The organic encapsulation layer 320 may include polyterephthalic acid, polyethylene naphthalate, polycarbonate, polyimide, polyvinyl sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resins, such as polymethyl methacrylate, polyacrylic acid, or a certain composition.

[0150] The input sensing layer 40 is positioned on the encapsulation layer 300. Figure 13 and Figure 14Shows a sensing electrode TSE (i.e., the first sensing electrode 410 or the second sensing electrode 420) and sensing signal lines (i.e., the first sensing signal line 450A or the second sensing signal line 450B) positioned on the encapsulation layer 300. The sensing electrode TSE may be positioned in the display area DA, and the first sensing signal line 450A and the second sensing signal line 450B may be arranged in the peripheral area PA. At least a portion of the first sensing signal line 450A and at least a portion of the second sensing signal line 450B may overlap with the control signal line IW in the second peripheral area PA2. Due to the intersecting arrangement of the via patterns of the first conductive layer 150 and the second conductive layer 160, coupling between the first sensing signal line 450A, the second sensing signal line 450B, and the control signal line IW in the second peripheral area PA2 can be prevented.

[0151] Figure 13 and Figure 14 An embodiment of shows an example where the base layer BL of the input sensing layer 40 is the second inorganic encapsulation layer 330 positioned on the uppermost layer of the encapsulation layer 300. As Figure 15 and Figure 16 In another example shown in, the base layer BL of the input sensing layer 40 may be an insulating substrate or an insulating film positioned on the encapsulation layer 300. In display devices different from those discussed herein, impurities (such as gases or moisture) generated in the organic materials included in the display device may penetrate into the display elements, such that the quality of the images expected for the relevant manufacturing processes or relevant uses may deteriorate. However, according to the embodiments herein, such deterioration of image quality can be prevented or reduced.

[0152] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments.

[0153] Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the scope and spirit of the disclosure as defined in the appended claims.

Claims

1. A display device, comprising: a substrate, the substrate including a display area and a peripheral area surrounding the periphery of the display area, the peripheral area including a first peripheral area and a second peripheral area; an insulating layer, the insulating layer including: a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer being respectively disposed in the display area, the first peripheral area, and the second peripheral area; and a first opening, the first opening penetrating the first insulating layer and the second insulating layer between the first peripheral area and the second peripheral area; a first conductive layer, the first conductive layer including a first hole disposed in the first peripheral area and a second hole disposed in the second peripheral area; and a second conductive layer, the second conductive layer being disposed on the first conductive layer and including a third hole disposed in the first peripheral area and a fourth hole disposed in the second peripheral area, wherein a part of the first hole and a part of the third hole overlap each other, and the second hole and the fourth hole are offset from each other and do not overlap.

2. The display device according to claim 1, wherein, The first conductive layer is disposed on the first insulating layer, and the second conductive layer is disposed on the second insulating layer.

3. The display device according to claim 1, wherein, The second conductive layer is disposed above the first opening.

4. The display device according to claim 1, further comprising: a first electrode, the first electrode being disposed in the display area and on the second insulating layer; an emission layer, the emission layer being disposed on the first electrode; and a second electrode, the second electrode facing the first electrode.

5. The display device according to claim 4, further comprising: a third insulating layer, the third insulating layer being disposed on the second insulating layer and including: a second opening, a part of the first electrode being exposed through the second opening; and a third opening, a part of the second conductive layer being exposed through the third opening.

6. The display device according to claim 5, wherein, The second electrode is in contact with the second conductive layer in the third opening.

7. The display device according to claim 5, wherein, The third insulating layer further includes: a fourth opening, the first opening being disposed in the fourth opening.

8. The display device according to claim 4, wherein, The second conductive layer and the first electrode are located on the same layer.

9. The display device according to claim 4, wherein, The second electrode is disposed above a part of the second peripheral area.

10. The display device according to claim 1, further comprising: a contact portion, the contact portion being in contact with the first conductive layer and the second conductive layer.

11. The display device according to claim 1, further comprising: a first signal line, the first signal line being disposed between the substrate and the first conductive layer in the second peripheral area; and a second signal line, the second signal line being disposed on the second conductive layer in the second peripheral area.

12. The display device according to claim 11, wherein, A varying voltage is applied to the first signal line and the second signal line.

13. The display device according to claim 11, further comprising: a packaging layer, the packaging layer being disposed between the second signal line and the second conductive layer.

14. The display device according to claim 11, further comprising: A power supply line, the power supply line being disposed in the second peripheral region and on the same layer as the first signal line, the power supply line being in contact with an edge of the first conductive layer.

15. The display device according to claim 1, further comprising: A driving circuit, the driving circuit being disposed in the first peripheral region and below the first conductive layer.

16. The display device according to claim 1, wherein, The first hole and the third hole overlap to coincide with each other and face each other.

17. The display device according to claim 16, wherein, The second hole and the fourth hole are offset to be spatially relative in terms of positioning and sequence.

18. A display device, comprising: A substrate, the substrate including a display region and a peripheral region surrounding the periphery of the display region; A first insulating layer, the first insulating layer being disposed on the substrate; A second insulating layer, the second insulating layer being disposed on the first insulating layer, each of the first insulating layer and the second insulating layer being disposed in the display region and the peripheral region; A first opening, the first opening penetrating the first insulating layer and the second insulating layer in the peripheral region; A first conductive layer, the first conductive layer being disposed on the first insulating layer and having a first hole pattern; And A second conductive layer, the second conductive layer being disposed on the second insulating layer and having a second hole pattern, wherein the first hole pattern and the second hole pattern coincide with each other in a region between the display region and the first opening, and the first hole pattern and the second hole pattern intersect each other without overlapping in a region between the first opening and an edge of the substrate.

19. The display device according to claim 18, further comprising: A first electrode, the first electrode being disposed on the second insulating layer; A third insulating layer, the third insulating layer being disposed on the second insulating layer and including: A second opening, a part of the first electrode being exposed through the second opening; and A third opening, a part of the second conductive layer being exposed through the third opening; An emission layer, the emission layer being disposed on the second opening; and A second electrode, the second electrode facing the first electrode.

20. The display device according to claim 19, wherein, In the third opening, the second electrode is in contact with the second conductive layer.

21. The display device according to claim 19, wherein, The second conductive layer and the first electrode are disposed on the same layer.

22. The display device according to claim 19, further comprising: A contact portion, the contact portion being in contact with the first conductive layer and the second conductive layer.

23. The display device according to claim 18, wherein, The first hole pattern and the second hole pattern coincide with each other to face each other in the region between the display region and the first opening.

24. The display device according to claim 23, wherein, The first hole pattern and the second hole pattern intersect each other to be spatially relative in terms of positioning and sequence in the region between the first opening and the edge of the substrate.

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