A highly stable and programmable triangular wave generator circuit

Abstract

The present invention discloses a highly stable and adjustable triangular wave generator circuit. It includes a waveform comparison control loop, a waveform generation circuit, and a signal shaping and amplification loop; the waveform comparison control loop includes a comparator U3, the inverting input terminal of the comparator U3 is grounded, and the output terminal is connected to the base of the NPN transistor D2, the cathode of the Schottky diode D1, and one end of the resistor R1. The other end of the resistor R1 is connected to the collector of the transistor D2 and is connected to the positive power supply V+. The emitter of the transistor D2 and the anode of the Schottky diode D1 are connected in parallel to form a control output. The present invention has a brand-new idea for generating triangular carrier waves. Through reasonable design of the parameters of discrete devices, not only can the circuit change the frequency of the triangular wave, but also the amplitude can be adjusted. The most important thing is that the stability and reliability of its circuit system can be self-controlled, and the combined structure is simple and the debugging is very convenient.

Description

Technical Field

[0001] The present invention relates to a highly stable and adjustable triangular wave generator circuit, belonging to the technical field of power systems. Background Art

[0002] In the power system, for various application scenarios such as inversion, frequency conversion, and photovoltaic, a very reliable chopping technology is required. And the most core reference in the chopping technology is generally a triangular waveform, also known as a carrier wave. Therefore, the stability and fineness of its output waveform are very important. The conventional method is to directly purchase a waveform generator chip and externally configure a small number of resistor-capacitor components. However, due to the different technical capabilities of each manufacturer, the integration performance varies greatly. Especially for the requirement of reliable operation in various environments for a long time, the chip often malfunctions due to uneven heating or temperature and humidity problems. With the development of modern operational amplifier technology, it has been basically perfected. As long as it is a well-known manufacturer, its performance is very reliable and excellent.

[0003] In order to overcome the above defects, through the selection of basic components, reasonable configuration, and self-assembly using appropriate principles, the use effect is very obvious. Summary of the Invention

[0004] In view of this, the present invention provides a highly stable and adjustable triangular wave generator circuit, a brand-new idea for generating triangular carrier waves. Through reasonable design of discrete device parameters, not only can the circuit change the frequency of the triangular wave, but also the amplitude can be adjusted. The most important thing is that the stability and reliability of its circuit system can be self-controlled, and the combined structure is simple and the debugging is very convenient.

[0005] The present invention solves the above technical problems through the following technical means: a highly stable and adjustable triangular wave generator circuit, which includes a waveform comparison control loop, a waveform generation circuit, and a signal shaping and amplification loop;

[0006] The waveform comparison control loop includes a comparator U3. The inverting input terminal of the comparator U3 is grounded, and the output terminal is connected to the base of the NPN transistor D2, the cathode of the Schottky diode D1, and one end of the resistor R1. The other end of the resistor R1 is connected to the collector of the transistor D2 and is connected to the positive power supply V+. The emitter of the transistor D2 and the anode of the Schottky diode D1 are connected in parallel to form a control output;

[0007] The waveform generation circuit includes a resistor R2. The resistor R2 is connected in parallel with one end of the resistor R5 and finally connected to the output terminal of the waveform comparison control loop to form a network label N2. The other end of the resistor R5 is connected to one end of the integrating capacitor C1 and the inverting input terminal of the JFET operational amplifier U2 to form a network label N3; the other end of the integrating capacitor C1 is connected to the output terminal of the operational amplifier U2 and one end of the resistor R6 to form a network label N4; finally, the other end of the resistor R6 is connected in series with the resistor R5 for voltage division to form an operational amplifier closed-loop circuit as a whole. The network label N5 formed by the series voltage division of the resistors R5 and R6 is connected to the non-inverting input terminal of the comparator U3;

[0008] The signal shaping and amplifying circuit includes a DC-blocking capacitor C2. One end of the DC-blocking capacitor C2 is connected to the output terminal of the JFET operational amplifier U2, and the other end is connected to one end of the resistor R3 in the amplifying and shaping circuit. The other end of the R3 resistor is connected to one end of the R4 resistor and the inverting input terminal of the JFET operational amplifier U1. The non-inverting input terminal of the U1 operational amplifier is directly connected to the reference zero level. Finally, the output terminal of the U1 JFET operational amplifier and the other end of the R4 form a closed loop.

[0009] The U1 and U2 use JFET type operational amplifiers with low bias / offset current. Other resistors and capacitors use high-precision low-temperature drift coefficient specifications, and the diode D1 uses a Schottky diode with a low forward voltage drop.

[0010] The final output net label N2 of the waveform comparison control circuit generates a switching function of positive and negative levels based on the positive input terminal of the input reference terminal U3; if the reference level of the positive input terminal of U3 is higher than the reference zero level, the comparator drives the base and emitter of the triode through the pull-up resistor R1 to activate the NPN triode D2, thereby accelerating the rising edge of the N2 level; if it is lower than the reference zero level, the circuit finally makes the output of the net label N2 negative through the Schottky diode D1.

[0011] If the output of the net label N2 of the pre-stage circuit of the waveform generation circuit is V+, the circuit charges the C1 through the R2. When the potential of N3 exceeds the reference zero level of the operational amplifier U2, its output is negative and feedback integration is performed through the C1 capacitor. At this moment, N2 is at the V+ potential and N4 is a continuously decreasing negative level; when the series voltage-dividing resistors R5 and R6 take the set values and when N4 decreases to the set value of the voltage-dividing resistor, the potential of N5 is lower than the reference of the comparator U3. At this moment, the output N1 of the comparator is V-, the D2 triode fails, and the N2 is forced to the V- state through the Schottky diode D1. This process repeats continuously in a cycle to generate a triangular original waveform.

[0012] The triangular original waveform is output through the net label N4 and is connected to the amplifying circuit through a DC-blocking capacitor. By setting the values of R3 and R4, the amplitude of the final triangular output waveform F_out can be adjusted, thus finally completing the generation of the triangular waveform.

[0013] The present invention relates to the most core part in the field of power electronics system chopping technology, and solves the technical problem of providing a high-stability and high-reliability triangular carrier generator for ensuring the PWM chopping function.

[0014] The beneficial effects of the present invention are: the design idea is ingenious, the circuit structure is flexible, the heat dissipation is uniform when the devices are evenly distributed, the parameter calculation is convenient, it meets the requirements of mass production, can significantly improve the production and test efficiency and high reliability and high stability, and has wide application value. Description of the Drawings

[0015] Attached Figure 1 is the circuit diagram of the present invention. Specific Embodiment

[0016] The following further describes in detail the embodiments of the present invention in conjunction with the attached drawings. However, these embodiments do not limit the present invention. Any similar structures and their similar variations using the present invention should be included in the protection scope of the present invention. The commas in the present invention all represent the relationship of "and".

[0017] As Figure 1 shown, a highly stable and settable triangular wave generator circuit provided by an embodiment of the present invention includes a waveform comparison control loop, a waveform generation circuit, and a signal shaping and amplification loop;

[0018] The waveform comparison control loop includes a comparator U3. The inverting input terminal of the comparator U3 is grounded, and the output terminal is connected to the base of the NPN transistor D2, the cathode of the Schottky diode D1, and one end of the resistor R1. The other end of the resistor R1 is connected to the collector of the transistor D2 and is connected to the positive power supply V+. The emitter of the transistor D2 and the anode of the Schottky diode D1 are connected in parallel to form a control output.

[0019] The waveform generation circuit includes a resistor R2. The resistor R2 is connected in parallel with one end of the resistor R5 and finally connected to the output terminal of the waveform comparison control loop to form a network label N2. The other end of the resistor R5 is connected to one end of the integration capacitor C1 and the inverting input terminal of the JFET operational amplifier U2 to form a network label N3. The other end of the integration capacitor C1 is connected to the output terminal of the operational amplifier U2 and one end of the resistor R6 to form a network label N4. Finally, the other end of the resistor R6 is connected in series with the resistor R5 and then the whole forms an operational amplifier closed-loop circuit. The network label N5 formed by the series voltage division of the resistors R5 and R6 is connected to the non-inverting input terminal of the comparator U3.

[0020] The signal shaping and amplification loop includes a blocking capacitor C2. One end of the blocking capacitor C2 is connected to the output terminal of the JFET operational amplifier U2, and the other end is connected to one end of the resistor R3 in the amplification and shaping circuit. The other end of the resistor R3 is connected to one end of the resistor R4 and the inverting input terminal of the JFET operational amplifier U1. The non-inverting input terminal of the operational amplifier U1 is directly connected to the reference zero level. Finally, the output terminal of the JFET operational amplifier U1 and the other end of the resistor R4 form a closed loop.

[0021] The operational amplifiers U1 and U2 use JFET type operational amplifiers with low offset / offset current. Other resistors and capacitors use high-precision low-temperature drift coefficient specifications. The diode D1 uses a Schottky diode with a low forward voltage drop.

[0022] The final output network label N2 of the waveform comparison control circuit has the function of switching between positive and negative levels based on the positive input terminal of the input reference U3; if the reference level of the positive input terminal of U3 is higher than the reference zero level, the comparator drives the base and emitter of the triode through the pull-up resistor R1 to activate the NPN triode D2, thereby accelerating the rising edge of the N2 level; if it is lower than the reference zero level, the circuit finally makes the output of the network label N2 negative through the Schottky diode D1.

[0023] If the output of the network label N2 of the pre-stage circuit of the waveform generation circuit is V+, the circuit charges C1 through R2. When the potential of N3 exceeds the reference zero level of the operational amplifier U2, its output is negative and feedback integration is performed through the C1 capacitor. At this moment, N2 is at the V+ potential and N4 is a continuously decreasing negative level; when the series voltage-dividing resistors R5 and R6 take the set values and when N4 decreases to the set value of the voltage-dividing resistor, the potential of N5 is lower than the reference of the comparator U3. At this moment, the output N1 of the comparator is V-, the D2 triode fails, and the N2 is forced to the V- state through the Schottky diode D1. This process repeats continuously in a cycle to generate the original triangular waveform.

[0024] The original triangular waveform is output from the network label N4 and is connected to the amplification circuit through a DC-blocking capacitor. By setting the resistance values of R3 and R4, the amplitude of the final triangular output waveform F_out can be adjusted, thus finally completing the generation of the triangular waveform.

[0025] To ensure the high stability performance index of the circuit, U1 and U2 must use JFET type operational amplifiers with low offset / offset current, and other resistors and capacitors must use high-precision low-temperature drift coefficient specifications. The diode D1 uses a Schottky diode with a low forward voltage drop.

[0026] The comparator U3, the pull-up resistor R1, the Schottky diode D1, and the NPN triode D2 together form the waveform comparison control circuit. The reverse input terminal of U3 is connected to zero potential, and its non-inverting input terminal receives the loop signal from the voltage-dividing resistors R5 and R6 in the triangular wave generation circuit. The output terminal of the comparator is directly connected to the base of the triode D2, the cathode of the Schottky diode D1, and one end of the resistor R1; the emitter of the triode D2 is directly connected to the anode of the Schottky diode D1, and its collector is connected to the other end of the resistor R1 and is connected to the positive working power supply.

[0027] The resistor R2 is connected in parallel with one end of R5 and is connected to the output end of the waveform comparison control loop to form a network label N2, and the other end is connected to one end of the integrating capacitor C1 and the inverting input end of the JFET operational amplifier U2 to form a network label N3; the other end of the integrating capacitor C1 is connected to the output end of the U2 operational amplifier and one end of R6 to form a network label N4; finally, the other end of R6 is connected in series with R5 for voltage division and the whole forms a closed-loop operational amplifier circuit. The network label N5 formed by the series voltage division of R5 and R6 is connected to the non-inverting input end of the waveform comparator U3. The closed-loop connection is organized in this way to form a waveform generation circuit.

[0028] One end of the DC-blocking capacitor C2 is connected to the output end of the JFET operational amplifier U2, and the other end is connected to one end of the resistor R3 in the amplification and shaping circuit. The other end of the R3 resistor is connected to one end of the R4 resistor and the inverting input end of the JFET operational amplifier U1; the non-inverting input end of the U1 operational amplifier is directly connected to the reference zero level, and finally the output end of the U1 JFET operational amplifier and the other end of R4 form a closed loop to form an amplification and shaping circuit.

[0029] The working principle of the present invention is:

[0030] After the circuit is powered on, based on the inherent characteristics of the loop, the circuit quickly builds its own balance. If it is assumed that the reference level at the non-inverting input end of U3 is higher than the reference zero level, the comparator U3 drives the base-emitter of the triode through the pull-up resistor R1 to activate the NPN triode D2, and then accelerates the rising edge of the network label N2 level until it approaches the V+ potential at the highest; if it is lower than the reference zero level, the loop finally makes the output of the network label N2 a negative level through the Schottky diode D1.

[0031] The JFET operational amplifier U2, capacitor C1, resistors R2, R5, and R6 combine to form a triangular waveform generation circuit. If the output netlabel N2 of the previous-stage circuit is close to the V+ potential, it charges C1 through R2. When the potential of N3 exceeds the reference zero potential of the operational amplifier U2, its output netlabel N4 is at a negative level and performs feedback integration through the C1 capacitor. At this moment, N2 is at a high potential and N4 is a continuously decreasing negative level. When the series voltage-dividing resistors R5 and R6 take the set values, and when N4 decreases to the set value of the voltage-dividing resistor, the potential of N5 is lower than the reference of the comparator U3. At this moment, the comparator output N1 is V-, the D2 triode fails, and N2 is forced to the V- state through the Schottky diode D1. At this moment, N4 reaches the minimum negative potential (negative peak value, the magnitude is limited by the R4 and R5 parameters), N2 is at the V- potential, and due to the previous charging and integration relationship, the potential of N3 reaches the positive maximum value. The loop starts to discharge C1 through R2. After that, the potentials of N4 and N2 remain unchanged (through reasonable setting of the R2 and C1 parameters, the time is very short), and the potential of N3 gradually decreases. When it reaches slightly less than the reference zero potential, the output of the JFET operational amplifier U2 reverses. At this moment, the potential of N4 gradually rises from the negative peak value, N3 is slightly lower than the zero potential (considering the sensitivity relationship of the operational amplifier, N3 can be considered as the zero potential), N2 is at the V- potential, and the state of the comparator loop remains unchanged. With the feedback integration of U2 and C1, and the continuous discharge of N2 to N3 through R2, the potential of N3 gradually becomes less than the zero potential and has a decreasing trend, while the potential of N4 starts to gradually rise out of the negative trough. When it reaches the positive maximum set value, at this moment, N2 is still at the V- potential. Through the series relationship of R2 and C1, the potential of N3 reaches the negative minimum peak potential. Through the voltage-dividing relationship of the resistors R6 and R5 for N4 and N2, the potential of N5 reaches the reference condition higher than the zero reference. The comparator U3 loop starts to reverse the potential, making N2 at the positive peak potential. At this moment, N4 is at the positive set peak potential, N2 is close to the V+ potential, and N3 is at the negative minimum potential state. N2 starts to charge C1 through the resistor R2. When the potential at the N3 terminal gradually rises above the zero potential reference, the output polarity of the operational amplifier U2 starts to reverse again, and feedback integration is performed through C1... This process repeats continuously, thus generating the original triangular waveform.

[0032] The JFET operational amplifier U1, resistors R3, R4, and capacitor C2 form a waveform shaping and amplification loop. The original triangular waveform output netlabel N4 is connected to the amplification loop through a DC-blocking capacitor for high-pass filtering. By setting the values of R3 and R4, the amplitude of the final triangular output waveform F_out can be adjusted, thus finally completing the generation of the triangular waveform.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A highly stable and adjustable triangular wave generator circuit, characterized in that: it includes a waveform comparison control loop, a waveform generation circuit, and a signal shaping and amplification loop; The waveform comparison control loop includes a comparator U3. The inverting input terminal of the comparator U3 is grounded, and the output terminal is connected to the base of the NPN transistor D2, the cathode of the Schottky diode D1, and one end of the resistor R1. The other end of the resistor R1 is connected to the collector of the transistor D2 and is connected to the positive power supply V+. The emitter of the transistor D2 and the anode of the Schottky diode D1 are connected in parallel to form a control output; The waveform generation circuit includes a resistor R2. One end of the resistor R2 is connected in parallel with one end of the resistor R5 and finally connected to the output terminal of the waveform comparison control loop to form a network label N2. The other end of the resistor R5 is connected to one end of the integrating capacitor C1 and the inverting input terminal of the JFET operational amplifier U2 to form a network label N3; The other end of the integrating capacitor C1 is connected to the output terminal of the operational amplifier U2 and one end of the resistor R6 to form a network label N4; Finally, the other end of the resistor R6 is connected in series with the resistor R5 for voltage division to form an overall operational amplifier closed-loop circuit. The network label N5 formed by the series voltage division of the resistor R5 and the resistor R6 is connected to the non-inverting input terminal of the comparator U3; The signal shaping and amplification loop includes a blocking capacitor C2. One end of the blocking capacitor C2 is connected to the output terminal of the JFET operational amplifier U2, and the other end is connected to one end of the resistor R3 in the amplification and shaping circuit. The other end of the resistor R3 is connected to one end of the resistor R4 and the inverting input terminal of the JFET operational amplifier U1. The non-inverting input terminal of the operational amplifier U1 is directly connected to the reference zero level. Finally, the output terminal of the U1 JFET operational amplifier and the other end of the resistor R4 form a closed loop.

2. A highly stable and adjustable triangular wave generator circuit as described in claim 1, characterized in that: the operational amplifiers U1 and U2 are of the JFET type with low bias / offset current, other resistors and capacitors are of high-precision low-temperature drift coefficient specifications, and the diode D1 is a Schottky diode with a low forward voltage drop.

3. A highly stable and adjustable triangular wave generator circuit as described in claim 2, characterized in that: The final output network label N2 of the waveform comparison control loop has a function of switching between positive and negative levels based on the input reference terminal, the non-inverting input terminal of U3; If the reference level at the non-inverting input terminal of U3 is higher than the reference zero level, the comparator drives the BE pole of the transistor through the pull-up resistor R1 to activate the NPN transistor D2, thereby accelerating the rising edge of the N2 level; If it is lower than the reference zero level, the loop finally makes the output of the network label N2 negative through the Schottky diode D1.

4. A highly stable and adjustable triangular wave generator circuit as described in claim 3, characterized in that: If the output of the pre-stage circuit of the waveform generation circuit, the net label N2, is V+, then the loop charges the capacitor C1 through R2. When the potential of N3 exceeds the reference zero level of the operational amplifier U2, its output is a negative level and performs feedback integration through the capacitor C1. At this moment, N2 is at the V+ potential and N4 is a continuously decreasing negative level. When the series voltage-dividing resistors R5 and R6 take the set values and when N4 decreases to the set value of the voltage-dividing resistor, the potential of N5 is lower than the reference of the comparator U3. At this moment, the output N1 of the comparator is V-, the triode D2 fails, and the net label N2 is forced to the V- state through the Schottky diode D1. This process repeats continuously in a cycle to generate the original triangular waveform.

5. A highly stable and adjustable triangular wave generator circuit as described in claim 4, characterized in that: The original triangular waveform output net label N4 is connected to the amplification loop through a DC-blocking capacitor. By setting the resistance values of R3 and R4, the amplitude of the final triangular output waveform F_out can be adjusted, thus finally completing the generation of the triangular waveform.

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